Method and apparatus for reducing errors in operational amplifiers - Patents.com

Abstract

An example device (105) includes a switch circuit element (106A) configured to connect a first switch input to a first switch output and a second switch input to a second switch output in a first state (202) based on a control signal (118) and to connect the first switch input to the second switch output and the second switch input to the first switch output in a second state (204) based on the control signal; an operational amplifier (110) configured to generate a first voltage (V1, 112) based on a gain and a connection in the first state in response to the control signal and to generate a second voltage (V2, 112) based on the gain and a connection in the second state in response to the control signal; and an analog-to-digital converter (ADC) (116) configured to convert the first voltage (V1, 112) and the second voltage (V2, 112) to a digital value (504) based on a multiplication of an input voltage and the gain.

Description

[Technical field]

[0001] This description relates generally to operational amplifiers (op amps), and more particularly to methods and apparatus for reducing errors in operational amplifiers. [Background technology]

[0002] Operational amplifiers are often used in analog circuitry to generate an output voltage that is amplified relative to an input voltage. In some instances, the ratio of the output voltage of an operational amplifier to the input voltage of the operational amplifier is referred to as the gain of the operational amplifier. In some configurations, such as negative feedback loops, the gain of the operational amplifier can be configured by external components. Summary of the Invention

[0003] Regarding a method and apparatus for reducing errors in an operational amplifier, an example device includes switch circuitry configured to connect a first switch input to a first switch output and a second switch input to a second switch output in a first state based on a control signal, and to connect the first switch input to the second switch output and the second switch input to the first switch output in a second state based on the control signal; an operational amplifier configured to generate a first voltage based on a gain and a connection in the first state in response to the control signal, and to generate a second voltage based on the gain and a connection in the second state in response to the control signal; and an analog-to-digital converter (ADC) configured to convert a third voltage and a fourth voltage to digital values ​​based on a multiplication of an input voltage and the gain. [Brief description of the drawings]

[0004] [Figure 1] FIG. 1 is an example block diagram of a computer system.

[0005] [Diagram 2] 2 illustrates an example block diagram of the example offset controller circuitry of FIG. 1.

[0006] [Diagram 3] 2 is an example circuit diagram of the switch circuitry and operational amplifier of FIG. 1;

[0007] [Figure 4] FIG. 2 is an example block diagram of an analog-to-digital converter (ADC) circuit element of FIG. 1.

[0008] [Diagram 5] 5 shows a timing diagram illustrating the operational output signal, chop control signal, and ADC output signal of FIG. 1, and the ADC start of conversion (SOC) signal and sample output signal of FIG.

[0009] [Figure 6] 2 is a histogram describing the error of the offset controller circuitry of FIG. 1;

[0010] In the drawings, the same reference numbers or other reference designators are used to denote the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The drawings are not necessarily drawn to scale. Generally, like reference numbers in the drawings and this application refer to the same or similar parts. Although the drawings show regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may be unobservable, blended, and / or irregular.

[0012] Operational amplifiers are used in a wide variety of applications, including signal processing, sensing, and control systems. In many applications, operational amplifiers are used as the initial computation in a system that uses the output of the operational amplifier to perform additional computations. In such applications, the performance of the operational amplifier can have a significant impact on the performance of the system as a whole. As such, electronics manufacturers may strive to continually improve the performance and accuracy of operational amplifiers.

[0013] One way to characterize the performance of an operational amplifier is the offset voltage. Offset voltage refers to the error by which the voltage generated by an operational amplifier differs from the expected voltage. For example, an operational amplifier with a gain of 10 may output 10.2 millivolts (mV) in response to a 1 mV signal, where 0.2 mV is due to the offset voltage. The offset voltage may arise due to the difference between the voltages received at the input stages of the transistors in the operational amplifier. The magnitude of the offset voltage is also affected by the temperature of the operational amplifier. Temperature drift is a metric that quantifies how much the offset voltage changes in response to temperature changes and may also be used to characterize the performance of an operational amplifier.

[0014] In some instances, electronics manufacturers may mitigate offset voltages using chopping techniques. With chopping techniques, the output of an operational amplifier may be characterized as a square wave that alternates between a maximum value of G×(input voltage+offset voltage) and a minimum value of G×(input voltage−offset voltage), where G refers to the gain of the operational amplifier. Previous solutions that utilize chopping techniques may mitigate offset voltages by implementing a frequency filter to average the maximum and minimum voltages, thereby eliminating offset voltage swings. However, previous solutions that utilize chopping may require additional space on an integrated circuit to implement both the operational amplifier and the frequency filter, leading to increased manufacturing costs.

[0015] The exemplary methods, systems, and devices described herein describe an exemplary operational amplifier implemented in an integrated circuit (such as a microprocessor) that includes an exemplary analog-to-digital converter (ADC). Advantageously, offset swings caused by using chopping techniques are removed when the exemplary ADC samples the output of the operational amplifier. Thus, the examples herein describe techniques for removing offset voltage without using circuit elements outside the microprocessor, such as frequency filters. Additionally, the exemplary operational amplifier alternates between G×(input voltage+offset voltage) and G×(input voltage−offset voltage) at a rate determined by the exemplary ADC. As a result, the exemplary operational amplifier may exhibit smaller offset voltage and lower temperature drift than previous solutions.

[0016] 1 is an example block diagram of an example computer system 100. The example computer system 100 includes an example voltage source 102, an example input voltage 104, an example offset controller circuitry 105, an example ADC output signal 120, an example memory 122, and an example processor circuitry 124. The example offset controller circuitry 105 includes an example switch circuitry 106A, an example offset voltage 108, an example operational amplifier 110, an example opamp output signal (OPAOUT) 112, an example voltage divider 114, an example ADC 116, and an example chop control signal 118.

[0017] The example voltage source 102 generates an input voltage 104. The example voltage source 102 may be implemented as any type of device and may generate the input voltage 104 for any purpose. For example, the voltage source 102 may be sensor circuitry that generates the input voltage 104 to perform a measurement. In another example, the voltage source 102 may be transceiver circuitry that generates the input voltage 104 in response to receiving data over a transmission medium (e.g., a cell network, a cable, etc.). In some examples, the input voltage 104 may change over time.

[0018] The example offset controller circuitry 105 receives an input voltage 104 from a voltage source 102 and generates a digital value (i.e., “0” bits and “1” bits) that represents the input voltage. The digital value may be referred to as an example ADC output signal 120. The components within the example offset controller circuitry 105 may be implemented together on an integrated circuit. In some examples, one or more of the example voltage source 102, the example memory 122, and the example processor circuitry 124 may be implemented on the same integrated circuit as the example offset controller circuitry 105. In other examples, one or more of the example voltage source 102, the example memory 122, and the example processor circuitry 124 may be implemented separately from the example offset controller circuitry 105.

[0019] Within the example offset controller circuitry 105, the example switch circuitry 106A includes a plurality of switches. The example switch circuitry 106A has two inputs and two outputs. The example switch circuitry 106A transitions between a first state and a second state based on the chop control signal 118. In the first state, in each of the example switch circuitry 106A, the first input is connected to the first output and the second input is connected to the second output. In the second state, in each of the example switch circuitry 106A, the first input is connected to the second output and the second input is connected to the first output. The example switch circuitry 106A is further described in conjunction with FIG. 2.

[0020] Within the example offset controller circuitry 105, the example offset voltage 108 represents an internal error in the operational amplifier 110. In the example shown in FIG. 1, the example offset voltage 108 is represented outside the operational amplifier 110 to visually indicate the error and to functionally describe the operational amplifier 110 as an ideal op-amp. An ideal op-amp is a hypothetical model of an operational amplifier that has infinite input impedance, no output impedance, and produces no error. The example offset voltage 108 may be any value. In some examples, the example offset voltage 108 may change over time due to changes in ambient temperature.

[0021] Within the example offset controller circuitry 105, the example operational amplifier 110 receives a differential input from the switch circuitry 106A in the form of two input voltages. The example operational amplifier 110 generates an output voltage that is an op-amp output signal 112 that is amplified with respect to the input voltage across the differential input pair. The gain of the operational amplifier 110 may be any value. In the examples used herein, the gain of the operational amplifier 110 may be generalized as a variable G. The example operational amplifier 110 is represented in FIG. 1 as an ideal op-amp. An actual implementation of the example operational amplifier 110 is further described in conjunction with FIG. 3.

[0022] Within the example offset controller circuitry 105, the example voltage divider 114 is implemented with two or more resistors in series coupled to the op amp output signal 112 at a first node and coupled to ground at a second node. The example voltage divider 114 also includes one or more intermediate nodes between the series connected resistors. Each intermediate node exhibits an intermediate voltage less than the op amp output signal 112 but greater than ground (e.g., 0 volts (V)). The voltage at any intermediate node in the voltage divider 114 is TIFF2025510380000002.tif520, where OPAOUT 112 is the voltage from the op amp output signal 112, and R 1 is the total resistance between the intermediate node and the first node, and R2 is the total resistance between the intermediate node and ground. In Figure 1, the manufacturer has chosen to design the circuit so that one of the intermediate nodes is at a voltage (OPAOUT 112 The resistor values ​​in the example voltage divider 114 may be predetermined to have a gain G (G / R). This node is connected to the second input of the switch circuit element 106A. The resistor values ​​used in the voltage divider 114 may be predetermined by the manufacturer and may be based on the gain G.

[0023] Within the example offset controller circuitry 105, the example ADC 116 converts the op amp output signal 112, which is an analog voltage, to digital bits. The example ADC 116 generates an ADC output signal 120 that includes a high supply voltage for a logic [1] bit and a low supply voltage for a logic [0] bit. The example ADC 116 also generates a chop control signal 118. The example chop control signal 118 is further described in conjunction with FIGS. 2 and 4.

[0024] The example memory 122 stores the digital bits encoded in the ADC output signal 120. The example memory 122 may be implemented as any type of memory. For example, the example memory 122 may be a volatile memory or a non-volatile memory. The volatile memory may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory may be implemented by Flash memory and / or any other desired type of memory device.

[0025] The example processor circuitry 124 may retrieve digital bits from memory 122 and perform an operation based on the digital bits. For example, the digital bits may represent a sensor reading and the processor circuitry 124 may perform an operation by presenting the reading to a user on a display. In another example, the digital bits may represent a message from an external device and the processor circuitry 124 may perform an operation by sending a response message to the external device. The example processor circuitry 124 may be implemented by any type of processor device. Examples of processor devices include a programmable microprocessor, a field programmable gate array (FPGA) that may instantiate instructions, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), or an integrated circuit such as a microcontroller or an application specific integrated circuit (ASIC).

[0026] Advantageously, the components of the example offset controller circuitry 105 may be implemented together on a single integrated circuit, such as a microprocessor. Because an ADC is a common component used in a variety of applications, manufacturers may design microprocessors to include an ADC by default. Thus, using the example ADC 116 to correct for offset voltages generated in the op amp output signal 112 does not require additional die space on the integrated circuit as the frequency filters of previous solutions.

[0027] The example switch circuit element 106A changes between a first state and a second state based on the chop control signal 118. By doing so, the example computer system 100 ensures that the op amp output signal 112 is equal to G×(V IN104 +V OFF108 ) and G×(V IN104 -V OFF108 ) is implemented. As used above and herein, V IN104 refers to an example input voltage 104, and V IN108refers to an example offset voltage 108. Advantageously, using the example ADC 116 to correct for the offset voltage and to determine when the value of the op amp output signal 112 changes via the chop control signal 118 results in a smaller magnitude of offset voltage and temperature drift than previous solutions.

[0028] Figure 2 shows an example block diagram of the example offset controller circuitry 105 of Figure 1. Figure 2 includes example configurations 202, 204. The example configurations 202, 204 show the example switch circuitry 106A in two different states. In Figure 2, the offset voltage 108 is shown as being external to the example operational amplifier 110, which is represented as an ideal op-amp.

[0029] The switch circuit element 106A includes two inputs. In the example switch circuit element 106A, the first input is connected to the input voltage 104 and the second input is connected to the intermediate node of the voltage divider 114. The switch circuit element 106A also includes two outputs. In the example configurations 202, 204, the switch circuit element 106A may be implemented by four single-pole, single-throw (SPST) switches, which may be implemented using transistors or other suitable switching circuit elements. In such an example, within the switch circuit element 106A, a first SPST switch connects the first input to the first output, a second SPST switch connects the first input to the second output, a third SPST switch connects the second input to the first output, and a fourth SPST switch connects the second input to the second output. In other examples, a different number of different switches may be used to implement the switch circuit element 106A. For example, two single-pole double-throw (SPDT) switches may be implemented, where a given SPDT switch connects one of the inputs to both the first and second outputs.

[0030] The example configuration 202 shows the example switch circuit element 106A in a first state. In the first state, the switch circuit element 106A connects the input voltage 104 to a first output and the op amp output signal 112 to a second output. The first output of the switch circuit element 106A is then connected in series with an offset voltage 108, shown externally. Thus, the voltage seen by the positive input terminal of the example operational amplifier 110 in the example configuration 202 is (V IN104 +V OFF108 ) and the characteristic of an ideal op-amp is that the output voltage increases, and therefore the feedback input, until the voltage difference between the input terminals is 0V. Therefore, the voltage seen by the negative input terminal of the example operational amplifier 110 in the steady-state example configuration 202 is also (V IN104 +V OFF108 ). These voltages are amplified by G in the example operational amplifier 110. Thus, when the switch circuit element 106A is in a first state, the op amp output signal 112 is G×(V IN104 +V OFF108 ) becomes.

[0031] The example configuration 204 shows the example switch circuitry 106A in a second state. In the second state, the switch circuitry 106A connects the input voltage 104 directly to the negative terminal of the operational amplifier 110 via its second output. Also, because the example operational amplifier 110 is represented as an ideal op-amp, both terminals of the example operational amplifier 110 receive the input voltage 104. However, the positive input terminal of the operational amplifier 110 remains connected in series with the offset voltage 108. As such, the voltage received by the positive input terminal is the sum of the offset voltage 108 and the voltage at the first output of the switch circuitry 106A. Thus, for the positive terminal of the operational amplifier 110 to receive the input voltage 104, the voltage at the first output of the switch circuitry 106A must be greater than V IN104 -V OFF108In the example configuration 204, a first output of the switch circuit element 106A is connected in series with a second input of the switch circuit element 106A, and the second input of the switch circuit element 106A is connected in series with an output of the example voltage divider 114. The example voltage divider 114 is designed to output a voltage having a smaller amplitude than the example op-amp output signal 112. Specifically, the output of the example voltage divider 114 has an amplitude of G of the example op-amp output signal 112. Thus, when the voltage at the first output of the switch circuit element 106A is V IN104 -V OFF108 An example of the op amp output signal 112 when the switch circuit element 106A is in the second state is G×(V IN104 -V OFF108 ) becomes.

[0032] 2 illustrates how example switch circuitry 106A is used to alternate the value of opamp output signal 112 within example offset controller circuitry 105. For example, when chop control signal 118 indicates that switch circuitry 106A is in a first state, example offset controller circuitry 105 alternates the value of opamp output signal 112. 112 = G × (V IN104 +V OFF108 ) in example configuration 202. Additionally, when chop control signal 118 indicates that switch circuitry 106A is in a second state, example offset controller circuitry 105 operates such that op amp output signal 112 = G × (V IN104 -V OFF108) in the example configuration 204. Advantageously, the example chop control signal 118 is generated by the example ADC 116. As a result, the frequency at which the chop control signal 118 transitions between two values ​​of the op amp output signal 112 is synchronous with the rate at which the example ADC 116 samples the op amp output signal 112 to convert the analog voltage to a digital value. The synchronous implementation of the example chop control signal 118 via the example ADC 116 may reduce the magnitude of the offset voltage and temperature drift of the example operational amplifier 110 as compared to previous solutions.

[0033] Figure 3 is a circuit diagram of the switch circuit 106A and an example operational amplifier 110 of Figure 1. Figure 3 includes the switch circuit element 106A, an example operational amplifier 110, and an example voltage divider 114. The example operational amplifier 110 includes example positive metal-oxide semiconductor (PMOS) transistors 302, 304, 306, 308, 310, 312, 314, example negative metal-oxide semiconductor (NMOS) transistors 316, 318, 320, 322, and example switch circuit elements 106B, 106C.

[0034] The illustrative PMOS transistors 302, 304, 306 are configured to form an input stage of an operational amplifier. In the input stage, the current flowing through the drain gates of the PMOS transistors 302, 304 is proportional to the input voltage 104 and the voltage provided by the voltage divider 114. The two voltages provided by the switch circuit element 106A are ideally equal in magnitude, but in practice may differ. The difference in magnitude of the voltages measured at 302 and 304 is the offset voltage 108.

[0035] The exemplary PMOS transistors 308, 310, 312, 314 and the exemplary NMOS transistors 316, 318, 320, 322 collectively form a folded cascode amplifier. The gain of the operational amplifier 110 is a measure of the amplification of the voltage between the NMOS transistors 318 and 322 and is based on the transconductance of the transistors in the folded cascode amplifier.

[0036] In practice, the example operational amplifier 110 may include an implementation of three example switch circuit elements 106A, 106B, 106C as described in FIG. 3. The example switch elements 106B, 106C may be implemented similarly to the example switch element 106A described above. Thus, the example switch circuit elements 106B, 106C each have two inputs and two outputs. The example switch circuit elements 106B, 106C each transition between a first state and a second state based on the chop control signal 118. Also, the example switch circuit elements 106A, 106B, 106C may be configured such that at any given time, all three switch circuit elements 106A, 106B, 106C are in the first state or all in the second state. The example switch circuit elements 106B, 106C are each implemented with four SPST switches, which may be implemented using transistors or other suitable switching circuit elements. 1 and 2, the example switch circuitry 106B, 106C was not required to describe the example operational amplifier 110 as an ideal op-amp, but in reality, the example operational amplifier 110 switches G×(V IN104 +V OFF108 ) in the second state, G×(V IN104 -V OFF108 ), each of the example switch circuit elements 106A, 106B, 106C may be included to output a corresponding one of the signal lines 106A, 106B, 106C.

[0037] The example switch circuit element 106B has two inputs and two outputs. The two inputs of the example switch circuit element 106B are coupled to the drain gates of the example PMOS transistors 308 and 310. The two outputs of the example switch circuit element 106B are coupled to the source gates of the example PMOS transistors 312 and 314. When the example switch circuit element 106B is in a first state, the drain gate of the example PMOS transistor 308 is coupled to the source gate of the example PMOS transistor 312, and the drain gate of the example PMOS transistor 310 is coupled to the source gate of the example PMOS transistor 314. When the example switch circuit element 106B is in a second state, the drain gate of the example PMOS transistor 308 is coupled to the source gate of the example PMOS transistor 314, and the drain gate of the example PMOS transistor 310 is coupled to the source gate of the example PMOS transistor 312.

[0038] The example switch circuit element 106C has two inputs and two outputs. The two inputs of the example switch circuit element 106C are coupled to the source gates of the example NMOS transistors 316 and 318. The two outputs of the example switch circuit element 106C are coupled to the drain gates of the example NMOS transistors 320 and 322. When the example switch circuit element 106C is in a first state, the source gate of the example NMOS transistor 316 is coupled to the drain gate of the example NMOS transistor 320, and the source gate of the example NMOS transistor 318 is coupled to the source gate of the example NMOS transistor 322. When the example switch circuit element 106C is in a second state, the source gate of the example NMOS transistor 316 is coupled to the drain gate of the example NMOS transistor 322, and the source gate of the example NMOS transistor 318 is coupled to the source gate of the example NMOS transistor 320.

[0039] FIG. 3 illustrates how an operational amplifier 110 can be designed at the transistor level to amplify the input voltage 104 and implement the chopping technique. Advantageously, the operational amplifier 110 includes switch circuit elements 106B, 106C controlled by the example ADC 116 via a chop control signal 118. As a result, the example ADC 116 can generate digital bits that do not represent the offset voltage 108, eliminating the need for additional die space to remove the offset voltage using circuit elements such as frequency filters. Also, using the example ADC 116 to remove the offset voltage 108 reduces the magnitude of the offset voltage, thereby removing the offset, since the output of the operational amplifier can be sampled and averaged by the chop control signal 118. Also, since the example ADC 116 can implement the chopping technique at multiple temperatures, the temperature drift of the example operational amplifier 110 can be lower than previous solutions.

[0040] Figure 4 is an example block diagram of the analog-to-digital converter (ADC) circuitry of Figure 1. The example ADC 116 includes an example chop controller circuitry 402, an example sample-and-hold circuitry 404, an example averager circuitry 406, and an example converter circuitry 408. Figure 4 also includes an example opamp output signal 112, an example chop control signal 118, an example ADC output signal 120, an example ADC SOC signal 410, and an example sample output signal 412.

[0041] The example chop controller circuitry 402 implements the chopping technique in accordance with the teachings of the present application. For example, the example chop controller circuitry 402 receives the example ADC SOC signal 410 from the example sample and hold circuitry 404 and generates the example chop control signal 118 in synchronization therewith. The example chop controller circuitry 402 also sends the chop control signal 118 to the example switch circuitry 106A, 106B, 106C to indicate when the switches are in a first state and when the switches are in a second state, as previously described in FIG. 2. The example chop control signal 118 and the example ADC SOC signal 410 are further described in connection with FIG. 5. The example chop controller circuitry 402 also provides instructions to the example averager circuitry 406 to indicate when to calculate the average voltage.

[0042] The example sample and hold circuit element 404 receives the opamp output signal 112 generated by the example operational amplifier 110. The example sample and hold circuit element 404 uses a clock circuit to record a voltage from the opamp output signal 112 and output the recorded voltage for an amount of time. In some examples, the recorded voltage may be referred to as a sample or a conversion. The example sample and hold circuit element 404 sends an ADC SOC signal 410 to indicate that a new conversion has begun. Similarly, the amount of time that the example sample and hold circuit element 404 outputs a given recorded voltage may be referred to as a hold time. The example sample and hold circuit element 404 provides a sample output signal 412, which is the recorded voltage, to the example averager circuit element 406. The example opamp output signal 112 is further described in connection with FIG. 5.

[0043] The example averager circuitry 406 receives multiple voltages in the example sample output signal 412 over time. For example, the example averager circuitry 406 may receive a first recorded voltage for a first hold time, followed by a second recorded voltage for a second hold time, etc. Upon receiving a command from the example chop controller circuitry 402, the example averager circuitry 406 calculates the average of the previous two recorded voltages in the example sample output signal 412. The example averager circuitry 406 provides the calculated average voltage to the converter circuitry 408.

[0044] The example converter circuitry 408 converts the calculated average voltage to a digital value. The digital value may include any number of bits. The example converter circuitry 408 may generate the digital value using any analog-to-digital conversion technique. For example, the example converter circuitry 408 may implement a look-up table that describes what corresponding digital bit should be generated for any calculated average voltage within a range of values. In such an example, the look-up table may be pre-programmed into the converter circuitry 408 or may be provided to the example converter circuitry 408 by the processor circuitry 124. The digital value generated by the example converter circuitry 408 is referred to as the example ADC output signal 120.

[0045] Advantageously, the example ADC 116 includes example chop controller circuitry 402 for synchronizing the chop control signal 118, the ADC SOC signal 410, and when the averager circuitry 406 calculates the average. The example chop controller circuitry 402 synchronizes the chop control signal 118, the ADC SOC signal 410, and when the averager circuitry 406 calculates the average. The example chop controller circuitry 402 synchronizes the chop control signal 118, the ADC SOC signal 410, and when the averager circuitry 406 calculates the average. IN104 +V OFF108 ) and the other voltage used as an input to the averaging circuitry 406 is G×(V IN104 -V OFF108) so that the digital bits generated by converter element 408 are equal to the calculated average voltage G×V IN104 Additionally, using the example ADC circuitry 116 to remove the offset reduces implementation area compared to previous solutions that required external filters to achieve the same thing.

[0046] FIG. 5 shows a timing diagram 502 illustrating an example opamp output signal 112, an example chop control signal 118, an example ADC SOC signal 410, an example sample output signal 412, and an example ADC output signal 120.

[0047] The example timing diagram 502 shows how the opamp output signal 112 varies over time. Ideally, the opamp output signal 112 varies over time as a function of G×V IN104 When the example switch circuit elements 106A, 106B, 106C are in a first state, the example op-amp output signal 112 is represented in FIG. 1 The voltage is written as G×V IN104 G×V is greater than OFF108 Similarly, when the example switch circuit elements 106A, 106B, 106C are in a second state, the example op amp output signal 112 is V 2 The voltage is written as G×V IN104 G×V smaller than OFF108 It's a bolt.

[0048] An ideal square wave includes instantaneous transitions between voltages. In practice, the example operational amplifier 110 generates a square wave with a voltage of V 1 and V 2 In some examples, the example operational amplifier 110 may also or alternatively determine the target voltage (V 1 Or V 2The output of the operational amplifier 110 may overshoot or undershoot the output of the operational amplifier 110 (either the output of the operational amplifier 110 or the output of the operational amplifier 110) and may take a certain amount of time to return to the target voltage. In some examples, the amount of time required for the example operational amplifier 110 to return to the target voltage after a transition occurs is referred to as the settle time.

[0049] The example timing diagram 502 shows the aforementioned signals over 2.5 periods of the chopping frequency. During one period of the chopping frequency, the op amp output signal 112 is G×(V IN104 +V OFF108 ) and G×(V IN104 -V OFF108 ) and during one period of the chopping frequency, the example ADC 116 produces one digital value.

[0050] The example chop control signal 118 includes a high supply voltage and a low supply voltage. When the example chop control signal 118 indicates a low supply voltage, the example switch circuit elements 106A, 106B, 106C are in a first state as previously described. Similarly, when the example chop control signal indicates a high supply voltage, the example switch circuit elements 106A, 106B, 106C are in a second state as previously described.

[0051] The example ADC SOC signal 410 describes when the example sample and hold circuit 404 samples the opamp output signal 112. The example sample and hold circuit 404 begins sampling the example opamp output signal 112 when the ADC SOC signal 410 transitions from a lower supply voltage to a higher supply voltage. Similarly, the example sample and hold circuit 404 stops sampling when the ADC SOC signal 410 transitions from a higher supply voltage to a lower supply voltage. The example ADC SOC signal 410 is generated by the example chop controller circuitry 402.

[0052] The example sample output signal 412 represents the voltage that the ADC records during each sample. While the example input voltage 104 may vary over time, the example chop control signal 118 synchronizes the example chop control signal 118 with the example ADC SOC signal 410 such that the voltage recorded during any ADC sample period may be represented by one of two values. 1 The sample marked with is the voltage G × (V IN104 +V OFF108 ) and V 2 The sample marked with is the voltage G × (V IN104 -V OFF108 During one period of the chopping frequency, the example sample output signal 412 has a frequency of V 1 One sample labeled as V 2 To filter the offset voltage, the example converter circuitry 408 generates a digital bit based on the average of the voltages recorded during one period of the chopping frequency (i.e., the voltages from two consecutive samples). TIFF2025510380000003.tif12112 where V Convert is the analog voltage generated by averager circuitry 406 and provided to converter circuitry 408.

[0053] The example ADC output signal output 120 includes one new digital value for each period of the chopping frequency. In the example timing diagram of FIG. 5, the example ADC output signal 120 is generated when the converter circuit 408 outputs V Convert After two additional samples of the example op amp output signal 112, the example converter circuit 408 generates an example digital value 504 based on the first value of V. Convert The example digital values ​​504, 506 may include any amount of data. For example, the example digital values ​​504, 506 may include one or more bits, bytes, words, etc. of data.

[0054] Advantageously, the chop control signal 118 (which determines the value of the op amp output signal 112) is based on the ADC SOC signal 410 sent from the sample and hold circuitry 404 to the example chop controller circuitry 402. Thus, the example ADC 116 generates the chop control signal 118 and the ADC SOC signal 410 synchronously in the sense that subsequent sampling of the op amp output signal 112 does not begin until sufficient time has passed for the op amp output signal 112 to settle after a transition in the chop control signal 118 has occurred. In particular, the instantaneous voltage of the op amp output signal 112 and the desired target voltage (V 1 Or V 2 The op amp output signal 112 may be considered to have settled when the difference between the voltages (either the voltage at the output of the op amp or the voltage at the output of the op amp) is less than or equal to the error threshold. Doing so ensures that Code 1 and Code 2 of the example sample output signal 412 are based on the desired target voltage of the op amp output signal 112 and not on the overshoot or undershoot voltages that the example operational amplifier 110 generates during the settle time.

[0055] Figure 6 includes histograms describing the errors of the operational amplifier of Figure 1. Figure 6 includes example histograms 602, 604.

[0056] The example histogram 602 illustrates the offset of the example operational amplifier 110 across multiple simulations of the example computer system 100 operating. In some examples, the offset of the example operational amplifier 110 may be calculated as the difference between the measured voltage of the op amp output signal 112 and the expected output voltage of the operational amplifier 110. In other examples, the offset of the example operational amplifier 110 may be calculated as the difference between the measured voltage of the ADC output signal 120 and the expected output voltage of the ADC 116.

[0057] The x-axis of the example histogram 602 shows the offset in volts, and the y-axis of the example histogram 602 shows the number of simulations for which the offset was calculated between two particular voltages (i.e., the number of simulations that fall into a particular bin of the histogram). The example histogram 602 shows that across all example simulations, the example operational amplifier 110 exhibited an offset of less than or equal to 202 microvolts (μV).

[0058] The example histogram 602 illustrates the temperature drift of the example operational amplifier 110 across multiple simulations of the example computer system 100 operating. To calculate a single temperature drift value, the example computer system 100 is simulated multiple times operating at multiple ambient temperatures and an offset is calculated for each unique temperature simulation. The temperature drift is then calculated as T drift = TIFF2025510380000004.tif518, where T drift is the temperature drift, and Offset max is the maximum recorded offset voltage, and Offset min is the smallest recorded offset voltage, and T max is the maximum operating temperature, T min is the minimum operating temperature.

[0059] The x-axis of the example histogram 604 shows temperature drift in microvolts per degree Celsius (μV / °C), and the y-axis of the example histogram 604 shows the number of simulations for which the temperature drift was calculated between two particular values ​​(i.e., the number of simulations that fall into a particular interval of the histogram). The example histogram 604 shows that across all example simulations, the example operational amplifier 110 exhibited a temperature drift of less than or equal to 1.18 μV / °C.

[0060] In this description, the term "and / or" (when used in the form A, B, and / or C, etc.) refers to any combination or subset of A, B, and C, such as (a) A only, (b) B only, (c) C only, (d) A and B, (e) A and C, (f) B and C, (g) A, B and C. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to an implementation that includes any of (a) at least one A, (b) at least one B, and (c) at least one A and at least one B.

[0061] The exemplary methods, apparatus, and products described herein improve the performance of the operational amplifier and reduce the amount of die space required to remove errors from the operational amplifier. The output of the exemplary operational amplifier 110 is provided directly to the exemplary ADC 116 for offset removal. Both the exemplary operational amplifier 110 and the exemplary ADC 116 are implemented on the same integrated circuit, eliminating the need to use additional die space on another circuit to remove the offset. Additionally, the exemplary ADC 116 controls both when the output of the operational amplifier changes and when the output of the operational amplifier is sampled to form a digital value. As a result, the magnitude of offset and temperature drift of the exemplary operational amplifier 110 may be smaller than previous solutions.

[0062] The term "couple" is used throughout this specification. This term may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B if device A provides a signal to control device B to perform an action, or in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal provided by device A, where the intervening component C does not substantially change the functional relationship between device A and device B.

[0063] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) to perform that function by a manufacturer at the time of manufacture and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuring may be accomplished through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or through a combination of these.

[0064] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless otherwise noted, these terms are used generally to refer to interconnections between device elements, circuit elements, integrated circuits, devices or other electronic or semiconductor components.

[0065] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, either during or after manufacture, e.g., by an end user and / or a third party.

[0066] Although particular transistors are described herein for use, other transistors (or equivalent devices) may be substituted. For example, a p-type metal oxide silicon FET (MOSFET) may be substituted for an n-type MOSFET with little or no modification to the circuit. Also, other types of transistors, such as bipolar junction transistors (BJTs), may be used.

[0067] The circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to that available prior to the replacement of the components. Components illustrated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the illustrated resistor, unless otherwise noted. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0068] Use of the term "ground" in the above description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of the present application. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means ±10 percent of the stated value.

[0069] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. It is a device, An operational amplifier having a positive input, a negative input, and an output, An analog-to-digital converter (ADC), A sample-and-hold circuit coupled to the output of the operational amplifier, A control circuit element coupled to the sample-and-hold circuit, configured to provide a control signal that identifies either a first state or a second state based on the sample-and-hold circuit, The ADC includes, A first switch circuit element having a first switch input configured to receive an input voltage, a first switch output coupled to the positive input of the operational amplifier, a second switch input coupled to the output of the operational amplifier, and a second switch output coupled to the negative input of the operational amplifier, In the first state described above, the first switch input is electrically coupled to the first switch output, and the second switch input is electrically coupled to the second switch output. In the second state described above, the first switch input is electrically coupled to the second switch output, and the second switch input is electrically coupled to the first switch output. The first switch circuit element is configured as follows: Includes, The operational amplifier is configured to generate a first voltage using the first switch circuit element in the first state, and to generate a second voltage using the first switch circuit element in the second state. A device in which the ADC is configured to convert the first voltage and the second voltage into digital values.

2. The device according to claim 1, A device in which the operational amplifier, the ADC, and the first switch circuit element are all mounted together on an integrated circuit.

3. The device according to claim 1, The operational amplifier, A second switch circuit element, Based on the control signal, a first set of electrical connections is created in the first state. Based on the aforementioned control signal, a second set of electrical connections is created in the second state. A device comprising the second switch circuit element configured as described above.

4. The device according to claim 1, A device in which the control circuit element is further configured to cause the control signal to alternate between identifying a first state and identifying a second state at a rate based on the sampling rate of the sample-and-hold circuit.

5. The device according to claim 1, The ADC further comprises an averaging circuit element coupled to the sample-and-hold circuit, the averaging circuit element configured to average the first voltage and the second voltage.

6. The device according to claim 5, The ADC further includes a conversion circuit element coupled to the averaging circuit element, the conversion circuit element configured to provide the digital value based on the average of the first voltage and the second voltage.

7. The device according to claim 1, A first resistor coupled between the output of the operational amplifier and the second switch input of the first switch circuit element, A second resistor is coupled between the first resistor and ground, Devices that further include the following.

8. The device according to claim 3, The operational amplifier, A first transistor having a source coupled to a voltage supply, a drain coupled to the second switch circuit element, and a gate, A second transistor having a source coupled to the voltage supply, a drain coupled to the second switch circuit element, and a gate coupled to the gate of the first transistor, A third transistor having a source coupled to the second switch circuit element, a drain coupled to the gate of the second transistor, and a gate, A fourth transistor having a source coupled to the second switch circuit element, a drain coupled to the output of the operational amplifier, and a gate coupled to the gate of the third transistor, Devices that further include the following.

9. The device according to claim 8, The operational amplifier, A third switch circuit element, A fifth transistor having a source coupled to the third switch circuit element, a drain coupled to the drain of the third transistor, and a gate, A sixth transistor having a source connected to the third switch circuit element, a drain connected to the drain of the fourth transistor, and a gate connected to the gate of the fifth transistor, A seventh transistor having a source connected to ground, a drain connected to the third switch circuit element, and a gate, An eighth transistor having a source connected to the ground, a drain connected to the third switch circuit element, and a gate connected to the gate of the seventh transistor, Devices that further include the following.

10. It is a device, A processor circuit element having an input connected to memory, An operational amplifier having a positive input, a negative input, and an output, An analog-to-digital converter (ADC) having an input coupled to the operational amplifier, a first output coupled to the memory, and a second output configured to output a control signal, A switch circuit element coupled to the second output of the ADC, comprising: a first switch input coupled to receive an input voltage; a first switch output coupled to the positive input of the operational amplifier; a second switch input coupled to the output of the operational amplifier; and a second switch output coupled to the negative input terminal of the operational amplifier. In the first state based on the control signal, the first switch input is electrically connected to the first switch output, and the second switch input is electrically connected to the second switch output. In the second state based on the control signal, the first switch input is electrically connected to the second switch output, and the second switch input is electrically connected to the first switch output. The switch circuit element is configured as follows: Includes, The operational amplifier is configured to generate a first voltage in response to the control signal and a second voltage in response to the control signal. The ADC is configured to convert the first voltage and the second voltage into digital values, store the digital values ​​in the memory, and alternate the signal control between indicating a first state and indicating a second state at a frequency determined by the ADC. A device in which the processor circuit element is configured to perform a certain action based on the digital value.

11. The device according to claim 10, The conversion of the first voltage and the second voltage to the digital value is the first conversion. The ADC is further configured to perform multiple conversions of the first voltage and the second voltage into multiple digital values, A device in which the rate at which the control signal alternates between indicating a first state and indicating a second state is based on the conversion rate of the output of the operational amplifier.

12. The device according to claim 10, A device in which the processor circuit element, the operational amplifier, the ADC, the memory, and the switch circuit element are all implemented together in a microprocessor.

13. The device according to claim 10, In order to convert the first voltage and the second voltage into digital values, the ADC, The output of the operational amplifier is sampled over a first period during which the operational amplifier generates the first voltage. The output of the operational amplifier is sampled over a second period during which the operational amplifier generates the second voltage. The digital value is calculated based on the average of the samples from the first period and the samples from the second period. A device further configured in this way.

14. The device according to claim 10, A first resistor coupled between the output of the operational amplifier and the second switch input of the switch circuit element, A second resistor is coupled between the first resistor and ground, Devices that further include the following.

15. It is a method, In the first state, The first switch is used to electrically couple the input voltage to the positive input of the operational amplifier, The first switch is used to electrically couple the output of the operational amplifier to the negative input of the operational amplifier, Using the operational amplifier, a first voltage is generated based on the input voltage, The first voltage is sampled using an analog-to-digital converter (ADC), To generate a control signal that identifies a second state based on the sampling of the first voltage, In the second state described above, The input voltage is electrically coupled to the negative input of the operational amplifier using the first switch, The first switch is used to electrically couple the output of the operational amplifier to the positive input of the operational amplifier, Using the operational amplifier, a second voltage is generated based on the input voltage, The second voltage is sampled using the ADC, Using the ADC, the first voltage and the second voltage are converted into digital values, Methods that include...

16. The method according to claim 15, The first conversion is the conversion of the first voltage and the second voltage into digital values. The method described above is The ADC further includes performing multiple conversions of the first voltage and the second voltage into multiple digital values, A method wherein the rate at which the first state and the second state alternate is based on the conversion rate of the output of the operational amplifier.

17. The method according to claim 15, A method in which the first switch, the operational amplifier, and the ADC are all mounted on an integrated circuit.

18. The method according to claim 15, A method for converting the first voltage and the second voltage into digital values, comprising calculating the digital values ​​based on the average of the first voltage and the second voltage.

19. The method according to claim 15, Using the second switch in the operational amplifier, the input of the second switch circuit element is connected to the output of the second switch circuit element in the first configuration in the first state based on the control signal, Using the second switch, the input of the second switch circuit element is connected to the output of the second switch circuit element in the second configuration in the second state based on the control signal, Methods that further include the above.

20. The method according to claim 15, A method further comprising generating the control signal that identifies the first state based on a sampling of the second voltage in the second state.

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