Integrated circuit with circuit for matching voltage supplied to gate of power transistor - Patent 733636

Abstract

The invention relates to an integrated circuit, comprising an enhancement mode power transistor (P2) and a circuit for adapting the voltage supplied to the gate of said enhancement mode power transistor, said circuit comprising at least one branch (101) connected between an input terminal (INPUT) and a second terminal (SOURCE), said branch comprising a depletion mode head transistor (M1), a depletion mode tail transistor (M2) connected to a first dipole (R1), a connecting quadrupole (10) and an enhancement mode base transistor whose source is connected to the second terminal (SOURCE) and whose gate is connected to its drain, said drain being connected to a second dipole (15), said control circuit being connected to the gate of the power transistor (P2) by the source of the head transistor (M1).

Description

[Technical field]

[0001] The present invention relates to the field of power electronics.

[0002] The invention particularly relates to a circuit for adapting the voltage supplied to the gate of a power transistor. [Background technology]

[0003] The invention advantageously allows the gate of a power transistor to be controlled at higher voltage levels than in the prior art without damaging the power transistor. The invention further proposes an adaptive circuit that is more robust and smaller than the circuits of the prior art.

[0004] Power electronics is a branch of electronic circuits dedicated to high-power energy transfer, where the key is to minimize energy losses. Power electronics is mainly based on the use of controlled power switches. For this purpose, a large number of silicon technology switches (IGBT, MOSFET) can be used, as well as wide bandgap semiconductor components (SiC, GaN). The transistors can be controlled by a control circuit called a "driver". The purpose of this control circuit is to control the charging and / or discharging of the gate of the power component in order to allow the change of state of the power transistor.

[0005] Generally, the gate of a transistor is limited in the voltage that can be applied to it without it being damaged. Typically, according to GaN transistor models, this voltage can be a maximum of 3, 6, or 9 V.

[0006] The driver itself can supply a voltage between 6 and 20 V. To adapt the voltage supplied by the driver, an adaptation circuit can be inserted between the driver and the gate of the power transistor.

[0007] For this purpose, it is possible to use a circuit made from discrete components such as that shown in FIG.

[0008] Typically, the prior art adaptation circuit 200 receives as input INPUT a pulse width modulated signal, also called a PWM signal, which alternates between high and low states. The input INPUT is connected to a first interconnection point A1 of the three branches of the adaptation circuit 200.

[0009] The first branch comprises a resistor R4 connected in series with the cathode of a Schottky diode D4, the anode of which is connected to the second interconnection point A2.

[0010] A second branch implemented in parallel with the first branch comprises a resistor R3.

[0011] The third branch comprises, among other things, two Schottky diodes D2, D3. The first Schottky diode D2 is connected by its cathode to the first interconnection point A1, while the second diode D3 is connected by its anode to the first interconnection point A1. The cathode of the second Schottky diode D3 is connected on the one hand to the capacitor C1 and on the other hand to the cathode of the Zener diode D1, the capacitor C1 and the Zener diode D1 being connected in parallel. The anode of the first diode D2 is connected to a resistor R2, the other terminal of which is connected on the one hand to ground and on the other hand to the anode of the Zener diode D1 and the second terminal of the capacitor C1.

[0012] The adaptation circuit 200 supplies power to the gate of the power transistor P2.

[0013] Such circuits have the disadvantage that they comprise a large number of components and therefore occupy a large surface area, which makes it impossible to integrate the circuits in a small space.

[0014] Another prior art solution consists in using an integrated circuit such as the integrated circuit of US Patent Application Publication No. 2020 / 0357906 shown in FIG. 2.

[0015] The integrated circuit 300 also receives a pulse width modulated signal as an input. The input is connected to the drain of a transistor T1. The gate of the transistor T1 is connected to the cathode of a Zener diode D7, the anode of which is connected to ground. A resistor R7 is connected between the drain and gate of the transistor T1. The source of the transistor T1 is connected to the gate of the power transistor whose voltage is to be regulated.

[0016] This circuit is generally called a "clamp circuit", in which the voltage supplied to the gate of the power transistor, connected to a point not shown in the diagram but called the "clamp signal", can be limited by the presence of a Zener diode D7.

[0017] This circuit is more compact than that of Figure 1, but is highly sensitive to variations in temperature and in the manufacturing parameters of the transistors, also known as "process corners." [Prior art documents] [Patent documents]

[0018] [Patent Document 1] US Patent Application Publication No. 2020 / 0357906 Summary of the Invention [Problem to be solved by the invention]

[0019] The problem which the invention proposes to solve is that of providing an adaptive circuit which is more compact than the circuits of the prior art and which has limited sensitivity to variations in temperature and in the manufacturing parameters of the transistors. [Means for solving the problem]

[0020] In order to solve this problem, the applicant has disclosed an integrated circuit comprising: an enhancement mode power transistor having a drain connected to a first terminal of the integrated circuit and a source connected to a second terminal of the integrated circuit; an adaptation circuit for adapting a voltage supplied to a gate of an enhanced mode power transistor, the adaptation circuit comprising at least one branch connected between an input adapted to receive a signal capable of adopting a low state and a high state and a second terminal; The present invention relates to an integrated circuit having a

[0021] This branch is a depletion-mode head transistor, the drain of which is connected to the input; a depletion-mode tail transistor having a source connected to a terminal of the first dipole and a gate connected to a second terminal of the first dipole; a connecting quadrupole having a first terminal connected to the gate of the head transistor, a second terminal connected to the source of the head transistor, a third terminal connected to the source of the tail transistor, a third terminal connected to the source of the tail transistor, and a fourth terminal connected to the drain of the tail transistor; an enhanced mode base (or feet) transistor having a source connected to a second terminal and a gate connected to a drain, the drain being connected to a second terminal of a second dipole having a first terminal connected to a second terminal of the first dipole; Equipped with.

[0022] The adaptation circuit is connected by the source of the head transistor to the gate of the power transistor.

[0023] According to the invention, a signal capable of adopting low and high states is, for example, a pulse width modulated signal.

[0024] Such an adaptation circuit has fewer components compared to the prior art of FIG. 1. It is therefore easier to implement in an integrated circuit. In addition, due to the limited number of components, interferences related to the interaction between components do not appear as much on the control signal of the power transistor. Furthermore, the circuit can be considered as quasi-passive in the sense that it has only one input connected to the driver and one output connected to the gate of the power transistor, and in the sense that it does not require any energy source other than the one provided by the driver to adapt the voltage.

[0025] In addition, it is known that depletion mode transistors have a negative threshold voltage and enhancement mode transistors have a positive threshold voltage.

[0026] By observing the threshold voltages of enhancement and depletion mode transistors as manufacturing parameters vary, it is possible in some cases to compensate for the effect that these variations have on the performance of the circuitry that uses the transistors.

[0027] Thus, in the circuit of the present invention, when the lower and upper parts of the circuit are combined, an enhancement mode transistor can compensate for a pair of depletion mode transistors.

[0028] As a direct consequence, variations associated with temperature variations and variations in the method for manufacturing a given transistor are compensated for by the presence of other transistors in the circuit.

[0029] Therefore, the circuit is more robust than prior art circuits.

[0030] According to the first embodiment, the above-mentioned connecting quadrupole is composed of two shorts connecting the first terminal with the third terminal, and the second terminal with the fourth terminal, respectively.

[0031] It is therefore advantageous if the second dipole is short circuited.

[0032] This embodiment is the simplest: the circuit only comprises two depletion mode transistors, one enhancement mode transistor and one dipole, i.e. four components in total. Such a circuit is therefore particularly easy to implement and to integrate in an integrated circuit.

[0033] The number of enhancement mode transistors and the number of depletion mode transistors are selected according to the maximum voltage value that is desired to be applied to the gates of the enhancement mode power transistors.

[0034] The adaptation circuit of this first embodiment therefore provides a maximum voltage of 3V.

[0035] According to a second embodiment, the connecting quadrupole comprises two depletion mode transistors, i.e. a high-order transistor and a low-order transistor, the source of the high-order transistor is connected to the drain of the low-order transistor and to a first terminal of the connecting quadrupole, the drain of the high-order transistor is connected to a second terminal of the connecting quadrupole, the gate of the low-order transistor is connected to a third terminal of the connecting quadrupole, and the gate of the high-order transistor and the source of the low-order transistor are connected to a fourth terminal of the connecting quadrupole.

[0036] It is therefore advantageous if the second dipole comprises an enhancement mode transistor having a source connected to the second terminal of the second dipole and a gate connected to a drain, said drain being connected to the first terminal of the second dipole.

[0037] In this embodiment, the circuit therefore comprises two enhancement mode transistors, the threshold voltages of which are compensated by means of two pairs of depletion mode transistors.

[0038] The adaptation circuit of this second embodiment therefore provides a maximum voltage of 6V.

[0039] According to a third embodiment, the connecting quadrupole is composed of n elementary quadrupoles, n>1, each elementary quadrupole comprises two depletion mode transistors, namely a high transistor and a low transistor, the source of the high transistor is connected to the drain of the low transistor and to a first terminal of the elementary quadrupole, the drain of the high transistor is connected to a second terminal of the elementary quadrupole, the gate of the low transistor is connected to a third terminal of the elementary quadrupole, the gate of the high transistor and the source of the low transistor are connected to the third terminal of the elementary quadrupole, The element quadrapole is connected to the fourth terminal of the element quadrapole, and each element quadrapole is connected in series, where two successive element quadrapoles are connected such that the first terminal of the element quadrapole is connected to the third terminal of the element quadrapole and the second terminal of the element quadrapole is connected to the fourth terminal of the element quadrapole, and the first and second terminals of the element quadrapole form the first and second terminals of the connecting quadrapole, and the third and fourth terminals of the element quadrapole form the third and fourth terminals.

[0040] It is therefore advantageous if the second dipole comprises n enhancement mode transistors, each of which has its gate connected to its drain, said transistors being connected in series, two successive transistors being connected by the source of one and the drain of the other, the drain of the first transistor forming a first terminal of the second dipole and the source of the last transistor forming a second terminal of the second dipole.

[0041] According to these embodiments, the first dipole can be, for example, an enhanced mode transistor whose gate is connected to the drain. The transistor therefore behaves like a diode. Preferably, the first dipole is a resistor, which allows better compensation of variations in the circuit. The sizing of the transistor or the value of the resistor in principle does not have a significant effect on the value of the voltage reference. However, the sizing of these components can be adapted in order to limit the energy consumption of the adaptation circuit.

[0042] Therefore, the adaptation circuit of this third embodiment provides a maximum voltage that is the product of 3V multiplied by n.

[0043] To increase the value of the current delivered to the power transistor, it is possible to connect several branches such as those described above in parallel.

[0044] The adaptation circuit thus comprises m branches connected in parallel, each connected by the source of its head transistor to the gate of a power transistor, so that the current available at the output is increased by a factor m while maintaining the performance of the original branch.

[0045] The manner in which the invention is achieved as well as the advantages arising therefrom will become apparent from the following description of an embodiment with the aid of the attached figures. [Brief description of the drawings]

[0046] [Figure 1] FIG. 1 is an electrical schematic diagram of a prior art adaptive circuit with discrete components. [Diagram 2] FIG. 2 is an electrical schematic diagram of another prior art adaptive circuit that can be achieved in integrated circuit form. [Diagram 3] FIG. 2 is an electrical circuit diagram of an adaptation circuit according to a first embodiment of the present invention. [Figure 4] FIG. 4 is an electrical schematic diagram of a variation of the embodiment of FIG. 3. [Diagram 5] FIG. 4 is an electrical circuit diagram of an adaptation circuit according to a second embodiment of the present invention. [Figure 6] FIG. 5 is an electrical circuit diagram of an adaptation circuit according to a third embodiment of the present invention. [Figure 7] FIG. 11 is an electrical circuit diagram of an adaptation circuit according to a fourth embodiment of the present invention. [Figure 8] FIG. 10 is an electrical circuit diagram of an adaptation circuit according to a fifth embodiment of the present invention. [Figure 9] FIG. 10 is an electrical circuit diagram of an adaptation circuit according to a sixth embodiment of the present invention. [Figure 10] 4 is a comparison graph between the input and output signals of the circuit of the present invention for various transistors having variations in their manufacturing process; [Figure 11] 1 is a graph showing the behavior of the amplitude of a signal supplied to a gate of a power transistor according to an input voltage under three process corner conditions. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] The integrated circuit of the invention as shown in Figures 3 to 9 comprises an adaptation circuit connected to the gates of the enhanced mode power transistors P2 to P8. The integrated circuit has three terminals: an input terminal INPUT, a first terminal DRAIN connected to the drains of the enhanced mode power transistors P2 to P8, and a second terminal SOURCE connected to the sources of the enhanced mode power transistors P2 to P8.

[0048] The adaptation circuit comprises at least one branch 101-108. Each branch comprises a head transistor M1, M11, M21, M31, M41, M51, M61, M71, the drain of which is connected to an input terminal INPUT intended to receive a pulse-width modulated signal alternating between a high and a low state. This signal is provided, for example, by a control circuit or "driver". The input signal INPUT can have a high state, for example between 8 and 12 V, and a low state equal to 0 V.

[0049] The sources of the head transistors M1, M11, M21, M31, M41, M51, M61, and M71 are connected to the gates of the enhancement mode power transistors P2 to P8.

[0050] Each branch 101 to 108 of the adaptation circuit of the invention also comprises a tail transistor M2, M14, M26, M36, M44, M54, M64, M74.

[0051] The two head transistors M1, M11, M21, M31, M41, M51, M61, M71 and the tail transistors M2, M14, M26, M36, M44, M54, M64, M74 are connected to each other by connecting quadrapoles 10, 20, 30, 40.

[0052] In the first embodiment of Figures 3 and 4, the connecting quadrupole 10 accommodates two short circuits: a first short circuit connects the terminals Q1 and Q3 of the connecting quadrupole 10, and a second short circuit connects the terminals Q2 and Q4 of the connecting quadrupole 10.

[0053] Thus, head transistor M1 is connected by its source to the drain of tail transistor M2 via a short circuit connecting terminals Q2 and Q4, and in addition the source of tail transistor M2 is connected to the gate of head transistor M1 via a short circuit connecting terminals Q1 and Q3.

[0054] In the second embodiment of FIG. 5, the connecting quadrupole 20 comprises two depletion mode transistors M12, M13 in series, namely the high transistor M12 and the low transistor M13. The source of the high transistor M12 is connected to the drain of the low transistor M13 and to the first terminal Q1 of the connecting quadrupole 20. The first terminal Q1 is also connected to the gate of the head transistor M11. The drain of the high transistor M12 is connected to the second terminal Q2 of the connecting quadrupole 20. The second terminal Q2 is also connected to the source of the head transistor M11. The gate of the low transistor M13 is connected to the third terminal Q3 of the connecting quadrupole 20. The third terminal Q3 is also connected to the source of the tail transistor M14. Finally, the gate of the high-order transistor M12 and the source of the low-order transistor M13 are connected to a fourth terminal Q4 of the connecting quadrupole 20, which is also connected to the drain of the tail transistor M14.

[0055] 7, the connection quadrupole 30 is composed of two element quadrupoles QEi, QEi+1 connected in series, that is, the third terminal QEi-3 of the first element quadrupole QEi is connected to the first terminal QEi+1-1 of the second element quadrupole QEi+1, and the fourth terminal QEi-4 of the first element quadrupole QEi is connected to the second terminal QEi+1-2 of the second element quadrupole QEi+1. Each element quadrupole QEi, QEi+1 includes two depletion mode transistors M32-M35, that is, high-order transistors M32, M34 and low-order transistors M33, M35. The source of each high-order transistor M32, M34 is connected to the drain of each low-order transistor M33, M35 and the first terminal QEi-1, QEi+1-1 of each element quadra-pole QEi, QEi+1. The drain of each high-order transistor M32, M34 is connected to the second terminal QEi-2, QEi+1-2 of each element quadra-pole QEi, QEi+1. The gate of each low-order transistor M33, M35 is connected to the third terminal QEi-3, QEi+1-3 of each element quadra-pole QEi, QEi+1. The gate of each high-order transistor M32, M34 and the source of each low-order transistor M33, M35 are connected to the fourth terminal QEi-4, QEi+1-4 of each element quadra-pole QEi, QEi+1. The terminals QEi-1 and QEi-2 respectively form the terminals Q1 and Q2 of the connecting quadrupole 30, and the terminals QEi+1-3 and QEi+1-4 respectively form the terminals Q3 and Q4 of the connecting quadrupole 30.

[0056] In the third embodiment of Fig. 6, the connecting quadrupole 40 is composed of n element quadrupoles QE1 to QEn, n>1. Each element quadrupole comprises two depletion mode transistors, i.e. high-order transistors M22, M24 and low-order transistors M23, M25, connected in the same way as the element quadrupoles QEi, QEi+1 described with reference to Fig. 7. Each element quadrupole QE1 to QEn is connected in series, where two consecutive element quadrupoles QEi, QEi+1 are connected such that the first terminal QEi+1-1 of the element quadrupole QEi+1 is connected to the third terminal QEi-3 of the element quadrupole QEi and the second terminal QEi+1-2 of the element quadrupole QEi+1 is connected to the fourth terminal QEi-4 of the element quadrupole QEi. The first and second terminals QE1-1, QE1-2 of the element quadrupole QE1 form the first and second terminals Q1, Q2 of the connecting quadrupole 40, and the third and fourth terminals QEn-3, QEn-4 of the element quadrupole QEn form the third and fourth terminals Q3, Q4 of the connecting quadrupole 40.

[0057] The head and tail transistors are depletion mode transistors. They can belong to the category of GaN transistors or MOS transistors.

[0058] The tail transistors M2, M14, M26, M36, M44, M54, M64, M74 are connected by their sources to a terminal of the first dipole. The gates of the tail transistors M2, M14, M26, M36, M44, M54, M64, M74 are connected to a second terminal of the first dipole. The first dipole can be, for example, a resistor R1, R11, R21, R31, R41, R51, R61, R71 as shown in Fig. 3 and Figs. 5 to 9, or can be a diode. For example, the first dipole is an enhancement mode transistor M4 implemented as a diode, i.e. with its gate connected to its drain, as shown in Fig. 4.

[0059] The second terminal of the first dipole is connected in series with the second dipole 15, 25, 35, 45.

[0060] In the first embodiment of figures 3 and 4, the second dipole 15 corresponds to a short circuit.

[0061] 5, the second dipole 25 comprises an enhancement mode transistor M15 having a source connected to the second terminal of the second dipole 25 and a gate connected to a drain which is also connected to the first terminal of the second dipole 25.

[0062] In the fourth embodiment of Fig. 7, the second dipole 35 comprises two enhanced mode transistors M37, M38. Each transistor M37, M38 has its gate connected to its drain. The transistors M37, M38 are connected in series, i.e. the source of the first transistor M37 is connected to the drain of the second transistor M38. Thus, the drain of the first transistor M37 forms the first terminal A3 of the second dipole 45, and the source of the second transistor M38 forms the second terminal A4 of the second dipole 45.

[0063] In the third embodiment of Fig. 6, the second dipole 35 comprises n enhanced mode transistors M27, M28. Each transistor M27, M28 has its gate connected to its drain. The transistors M27, M28 are connected in series, i.e. two successive transistors M27, M28 are connected by one source and the other drain. Thus, the drain of the first transistor M27 forms the first terminal A3 of the second dipole 35, and the source of the last transistor M28 forms the second terminal A4 of the second dipole 35.

[0064] The second terminals of the second dipoles 15, 25, 35, 45 are connected to non-linear components. In fact, the non-linear components are the base transistors M3, M16, M29, M39. The base transistors M3, M29, M39 are advantageously enhancement mode transistors with their gates connected to their drains. The base transistors M3, M29, M39, M46, M56, M66, M76 are connected to the second terminal SOURCE and are themselves generally connected by their sources to ground.

[0065] The maximum voltage value supplied to the gates of the power transistors P2 to P8 is determined by the number of enhancement mode transistors M3, M15, M16, M27 to M29, M37 to M39, M45, M46, M55, and M56 in this circuit.

[0066] Thus, a first embodiment includes only one enhancement mode transistor M3 and can limit the voltage supplied to the gate of power transistor P2 to a value substantially equal to 3V. A second embodiment includes two enhancement mode transistors M15, M16 and can limit the voltage supplied to the gate of power transistor P4 to a value substantially equal to 6V. A fourth embodiment includes three enhancement mode transistors M37-M39 and can limit the voltage supplied to the gate of power transistor P6 to a value substantially equal to 9V. A third embodiment includes n enhancement mode transistors M37-M39 and can limit the voltage supplied to the gate of power transistor P5 to a value substantially equal to n times 3V.

[0067] According to the fifth and sixth embodiments shown in figures 8 and 9, it is possible to implement two identical branches 101-108 in parallel in order to increase the current of the signals supplied to the gates of the power transistors P2-P8 while maintaining the same voltage. The fifth and sixth embodiments thus comprise two branches 105-108 each comprising two enhancement mode transistors M45, M46, M65, M66, making it possible to limit the voltage supplied to the gates of the power transistors P7, P8 to a value substantially equal to 6V.

[0068] Therefore, for a circuit with only one branch, the current flowing through the circuit from the input INPUT to the gates of the enhanced mode power transistors P2-P8 is approximately 1A.

[0069] When several branches are connected in parallel, the current can reach several amperes. Thus, the invention is well adapted to a wide range of power transistors.

[0070] 8, branches 105 and 106 are connected in parallel between the input INPUT and the second terminal SOURCE. The branch 105 is connected to the branch 106 by the source of its head transistor M41, which is connected to the source of the head transistor M51 of the branch 106. Thus, the sources of the two head transistors M41 and M51 are connected to the gate of the power transistor P7.

[0071] In one variant, as shown in Fig. 9, it is possible to share the lower part of the adaptation circuit with the enhancement mode transistors M75, M76. Thus, branches 105 and 106 are connected in parallel between the input INPUT and the second terminal of the first dipole R71.

[0072] The resulting adaptive circuit is therefore less susceptible to supply voltage variations, temperature variations, and variations in transistor manufacturing process variations.

[0073] In fact, the applicant has carried out digital simulations, the results of which are shown in Figures 10 and 11. Thus, for an input signal 120 having a high state equal to 12V and a low state equal to 0V, the signals fed to the gates of the power transistors P2 to P8 have little variation depending on the transistor manufacturing process. In the worst case, i.e. for slow-slow (SS) transistors, there is a slight delay increase in the signal 140, but it remains completely satisfactory. For all other combinations of transistors, the signal 130 is faithfully reproduced, having a low state of 0V and a high state of 6V.

[0074] 11 shows the behavior of a signal (referenced V(V)) supplied to the gate of a power transistor as a function of an input voltage INPUT (referenced VDC), obtained through a process corner conventionally used in digital simulations to study the behavior of a circuit taking into account the variations related to the manufacturing method. The curves FF and SS thus correspond to a simulation at the two extreme "corners" of the "process corner", namely fast-fast and slow-slow, respectively, and the curve TT corresponds to a simulation for nominal or typical conditions. It will thus be noted that the voltage V(V) remains substantially constant under the conditions in question. [Explanation of symbols]

[0075] 10 Connection Quadra-pole 15 Second Dipole 100 Branch A3 1st terminal A4 Second Terminal DRAIN 1st terminal INPUT Input terminal, input signal, input voltage M1 Depletion mode head transistor M2 Depletion mode tail transistor M3 Enhancement mode base transistor P2 Enhanced mode power transistor Q1 1st terminal Q2 Second Terminal Q3 3rd terminal Q4 4th terminal R1 Resistor, first dipole SOURCE 2nd terminal

Claims

1. 1. An integrated circuit comprising: enhancement mode power transistors (P2-P8) having drains connected to a first terminal (DRAIN) of the integrated circuit and sources connected to a second terminal (SOURCE) of the integrated circuit; an adaptation circuit for adapting the voltage supplied to the gates of the enhancement mode power transistors (P2-P8); Equipped with The adaptation circuit comprises at least one branch (100-108) connected between an input terminal (INPUT) adapted to receive a signal capable of adopting a low-level state and a high-level state and the second terminal (SOURCE), the at least one branch (100-108) comprising: depletion mode head transistors (M1, M11, M21, M31, M41, M51, M61, M71) whose drains are connected to the input terminal (INPUT); a depletion mode tail transistor (M2, M14, M24, M34, M46, M56) having a source connected to a terminal of a first dipole (R1, R11, R21, M4) and a gate connected to a second terminal of the first dipole (R1, R11, R21, R31, R41, R51, R61, R71, M4); a connecting quadrupole (10, 20, 30, 40) having a first terminal (Q1) connected to the gates of the head transistors (M1, M11, M21, M31, M41, M51, M61, M71), a second terminal (Q2) connected to the sources of the head transistors (M1, M11, M21, M31, M41, M51, M61, M71), a third terminal (Q3) connected to the sources of the tail transistors (M2, M14, M26, M36, M44, M54, M64, M74), and a fourth terminal (Q4) connected to the drains of the tail transistors (M2, M14, M26, M36, M44, M54, M64, M74); an enhancement mode base transistor (M3, M16, M29, M39, M46, M56, M76) having a source connected to the second terminal (SOURCE) and a gate connected to a drain, the drain being connected to a second terminal (A4) of a second dipole (15, 25, 35) having a first terminal (A3) connected to the second terminal of the first dipole (R1, R11, R21, R31, R41, R51, R61, R71, M4); Equipped with the adaptive circuit is connected to the gates of the power transistors (P2 to P8) by the sources of the head transistors (M1, M11, M21, M31, M41, M51, M61, M71); Integrated circuits.

2. 2. The integrated circuit according to claim 1, characterized in that the connecting quadrupole (10) consists of two shorts connecting the first terminal (Q1) to the third terminal (Q3) and the second terminal (Q2) to the fourth terminal (Q4), respectively.

3. The connecting quadrupole (20) comprises two depletion mode transistors (M12, M13, M42, M52, M43, M53, M62, M63, M72, M73), i.e., a high-order transistor (M12, M42, M52, M62, M72) and a low-order transistor (M13, M43, M53, M63, M73), the sources of the high-order transistors (M12, M42, M52, M62, M72) being connected to the drains of the low-order transistors (M13, M43, M53, M63, M73) and to the first terminal (Q1) of the connecting quadrupole (20), and the high-order transistors (M13, M43, M53, M63, M73) are connected to the drains of the low-order transistors (M13, M43, M53, M63, M73) and to the first terminal (Q1) of the connecting quadrupole (20), 2. The integrated circuit according to claim 1, characterized in that the drains of the (M12, M42, M52, M62, M72) are connected to the second terminal (Q2) of the connecting quadrupole (20), the gates of the low-order transistors (M13, M43, M53, M63, M73) are connected to the third terminal (Q3) of the connecting quadrupole (20), and the gates of the high-order transistors (M12, M42, M52, M62, M72) and the sources of the low-order transistors (M13, M43, M53, M63, M73) are connected to the fourth terminal (Q4) of the connecting quadrupole (20).

4. The connecting quadrupole (40) is composed of n element quadrupoles (QE1, QEi, QEi+1, QEn), n>1, and each element quadrupole (QEi) has two depletion mode transistors, i.e., high-order transistors (M42, M52, M44, M54) and low-order transistors (M23, M33, M25, M35), and the sources of the high-order transistors (M22, M24) are connected to the drains of the low-order transistors (M23, M25) and the element quadrupoles (M22, M24). The drains of the high-order transistors (M22, M24) are connected to the second terminal (QEi-2) of the element quadrupole (QEi), the gates of the low-order transistors (M23, M25) are connected to the third terminal (QEi-3) of the element quadrupole (QEi), and the gates of the high-order transistors (M22, M24) and the sources of the low-order transistors (M23, M25) are connected to the first terminal (QEi-1) of the element quadrupole (QEi). The element quadrupoles are connected in series, and two consecutive element quadrupoles (QEi, QEi+1) are connected in series such that the first terminal (QEi+1-1) of the element quadrupole (QEi+1) is connected to the third terminal (QEi-3) of the element quadrupole (QEi) and the second terminal (QEi+1-2) of the element quadrupole (QEi+1) is connected to the fourth terminal (QEi-4) of the element quadrupole (QEi).

2. The integrated circuit according to claim 1, wherein a first terminal (QE1-1) and a second terminal (QE1-2) of the element quadrupole (QE1) form the first terminal (Q1) and the second terminal (Q2) of the connecting quadrupole (40), and a third terminal (QEn-3) and a fourth terminal (QEn-4) of the element quadrupole (QEn) form the third terminal (Q3) and the fourth terminal (Q4) of the connecting quadrupole (40).

5. 2. The integrated circuit of claim 1, wherein the depletion mode transistors (M1, M2, M11-M14, M21-M26, M31-M36, M41-M46, M51-M54, M61-M64, M71-M74) and the enhancement mode transistors (M3, M15, M27-M29, M37-M39, M45, M46, M55, M56, M75, M76) are GaN transistors or MOS transistors.

6. 2. The integrated circuit of claim 1, wherein the first dipoles are resistors (R1, R11, R21, R31, R41, R51, R61, R71).

7. 2. The integrated circuit of claim 1, wherein the first dipole is an enhancement mode transistor (M4) having a gate connected to a drain.

8. 3. The integrated circuit according to claim 2, characterized in that the second dipole (15) is a short circuit.

9. 4. The integrated circuit of claim 3, wherein the second dipole (25) comprises an enhancement mode transistor (M15) having a source connected to the second terminal of the second dipole (25) and a gate connected to a drain, the drain being connected to the first terminal (A3) of the second dipole (25).

10. 5. The integrated circuit according to claim 4, characterized in that the second dipole (35) comprises n enhancement mode transistors (M27, M28), each of which has its gate connected to its drain, the transistors (M27, M28) being connected in series, and two successive transistors (M27, M28) being connected by their source one and their drain the other, the drain of a first transistor (M27) forming the first terminal (A3) of the second dipole (35) and the source of a last transistor (M28) forming the second terminal (A4) of the second dipole (35).

11. 2. The integrated circuit according to claim 1, comprising n branches (101 to 108) connected in parallel, each branch being connected to the gate of said power transistors (P2 to P8) by the source of a respective head transistor (M1, M11, M21, M31, M41, M51, M61, M71).

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