Semiconductor device and method for manufacturing the same

Abstract

According to an embodiment of the present invention, a method for manufacturing a semiconductor device may include growing a stack layer by alternately stacking a sacrificial layer and a channel region on a substrate, forming a sacrificial poly gate on the stack layer, forming an inner spacer and a side spacer on a side of the sacrificial layer and a side of the sacrificial poly gate, and performing a heat treatment on the inner spacer or the side spacer in a chamber set to a predetermined process pressure and a predetermined process temperature.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Semiconductor devices are components that are primarily used in electronic circuits and similar devices that utilize the electrical conductivity properties of semiconductors. Semiconductors can be classified into memory semiconductors and non-memory semiconductors. Memory semiconductors can be classified into volatile memories such as DRAM and SRAM, and non-volatile memories such as Mask ROM, EP ROM, EEP ROM, and flash memory.

[0003] New processes and semiconductor devices with new structures are being developed to miniaturize semiconductor devices. A typical example is the Gate-All-Around (GAA) process. With the Gate-All-Around process, the gate and channel are in contact on four sides, allowing precise control of current flow and overcoming the limitations of existing semiconductor devices.

[0004] In recent years, a new structure called MBCFET (Multi-Bridge Channel Field Effect Transistor) has been disclosed to solve the shortcomings of the gate-all-around structure. In the MBCFET structure, the channel region is formed in a nanosheet shape, so the effective area where the gate and channel contact increases, and therefore the amount of current flowing between the gate and channel also increases. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to improve the film quality performance of inner spacers or side spacers included in semiconductor elements that include nanosheets.

[0006] The object of the present specification is not limited to the object mentioned above, and other objects and advantages of the present specification not mentioned can be more clearly understood from the examples of the present specification described below. In addition, the object and advantages of the present specification can be realized by the elements and combinations thereof described in the claims. [Means for solving the problem]

[0007] In one embodiment, a method for manufacturing a semiconductor device may include growing a stack layer by alternately stacking sacrificial layers and channel regions on a substrate, forming a sacrificial poly gate on the stack layer, forming inner spacers and side spacers on sides of the sacrificial layer and sides of the sacrificial poly gate, and performing a heat treatment on the inner spacers or the side spacers in a chamber set to a predetermined process pressure and a predetermined process temperature.

[0008] According to one embodiment, a semiconductor device includes a substrate, a channel region including a plurality of nanosheets stacked on the substrate, a gate electrode arranged to contact at least one surface of the channel region, a source region and a drain region arranged on both sides of the channel region, respectively, a side spacer arranged on a side of the gate electrode, and an inner spacer arranged on a side of the gate electrode, and an oxide layer may be formed on an outer surface of the side spacer or the inner spacer by a heat treatment performed in a chamber set to a predetermined process pressure and a predetermined process temperature. Effect of the Invention

[0009] According to the method for manufacturing a semiconductor device according to the embodiment, the film quality performance of the inner spacer or the side spacer of the semiconductor device can be improved. That is, the thickness of the inner spacer or the side spacer becomes uniform and the stability is improved, so that the insulation property of the inner spacer or the side spacer can be improved. As a result, the parasitic capacitance between the gate electrode and the source and drain regions can be reduced, so that the electrical characteristics and reliability of the semiconductor device can be improved. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device according to an embodiment; [Figure 2a] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 2b] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 2c] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 2d] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 2e] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 2f] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 2g] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Diagram 3] 1 is a flow chart illustrating a method of manufacturing a semiconductor device according to an embodiment. [Figure 4a] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 4b] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 4c] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 4d] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 4e] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to another embodiment. [Diagram 5] 11 is a flow chart illustrating a method of manufacturing a semiconductor device according to another embodiment. [Figure 6] 1 is a graph showing leakage current values ​​measured when a voltage is applied to a semiconductor device manufactured according to the prior art and a semiconductor device manufactured according to an embodiment of the present specification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The above-mentioned objects, features and advantages will be described in detail below with reference to the accompanying drawings, so that those skilled in the art to which the present specification pertains can easily implement the embodiments of the present specification. In describing the present specification, if a detailed description of a known technology related to the present specification is deemed to obscure the gist of the present specification, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present specification will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings indicate the same or similar components.

[0012] As used herein, a "nanosheet" refers to a conductive structure having a cross-section that is substantially perpendicular to the direction of current flow through the nanosheet. In addition, one of the Cartesian cross-sectional dimensions within the nanosheet is significantly smaller than the other dimensions. For example, a nanosheet may include a conductive structure having a cross-sectional area in one of the Cartesian cross-sectional dimensions ranging from a few nm to about 20 nm, and in another Cartesian cross-sectional dimension ranging from about 15 nm to about 70 nm.

[0013] FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to an embodiment.

[0014] Referring to FIG. 1, a semiconductor device 10 according to one embodiment may include substrates 110 and 120, a source region 210, a drain region 220, a gate electrode 370, channel regions 150 and 160, a side spacer 180, and an inner spacer 190.

[0015] The base substrate layer 110 may be a single crystal substrate. The base substrate layer 110 may include a single crystal semiconductor layer on at least one surface. The single crystal semiconductor layer may be made of any of, but is not limited to, Si, Ge, SiGe, GeSn, InSb, GaAs, GaP, InAlAs, InGaAs, GaSbP, GaAsSb, and InP.

[0016] The buffer substrate layer 120 can be formed by epitaxial growth on the base substrate layer 110. The buffer substrate layer 120 can be formed by doping the base substrate layer 110 with an impurity of a material different from that of the base substrate layer 110.

[0017] The buffer substrate layer 120 may have a different lattice constant than the base substrate layer 110 to minimize lattice stress. In some embodiments, the lattice constant and crystal structure of the buffer substrate layer 120 may be substantially the same as the lattice constant and crystal structure of the base substrate layer 110.

[0018] The lattice constant of the buffer substrate layer 120 may be different for each layer level. For example, the lattice constant of the buffer substrate layer 120 may be larger from a lower layer level to a higher layer level.

[0019] The source region 210 and the drain region 220 may be disposed on either side of the channel regions 150, 160, respectively.

[0020] The gate electrodes 340 and 370 can control the flow of current through the channel regions 150 and 160. The gate electrodes 340 and 370 may be disposed between the source region 210 and the drain region 220. The gate electrodes 340 and 370 may be disposed to surround the channel regions 150 and 160, i.e., the upper, lower and side surfaces of the basal nanosheet 150 and the nanosheet 160, in other words, to be in contact with the upper, lower and side surfaces of the basal nanosheet 150 and the nanosheet 160, respectively.

[0021] The base gate insulating film 130 can prevent parasitic coupling of the substrates 110 and 120 due to the gate electrodes 340 and 370. The base gate insulating film 130 can prevent undesirable conductive channels from being formed in the substrates 110 and 120 when the semiconductor device 10 is conductive. In FIG. 1, the base gate insulating film 130 may be disposed below the gate electrode 340 that is disposed at the bottom. Depending on the embodiment, the base gate insulating film 130 may be omitted.

[0022] The channel region 150, 160 may include a base nanosheet 150 disposed on the bottom surface and at least one nanosheet 160 stacked on top of the base nanosheet 150. In one embodiment, the channel regions 150, 160 may be stacked vertically spaced apart from each other and side by side with the gate electrodes 340, 370. The channel regions 150, 160 may be disposed between the source region 210 and the drain region 220. The number of nanosheets 160 included in the channel region 150, 160 may vary depending on the embodiment.

[0023] The channel regions 150, 160 may be defined as conductive structures having a cross section perpendicular to the direction of current flow. The base nanosheet 150 and the nanosheet 160 may be made of a material doped with conductive impurities. For example, the base nanosheet 150 and the nanosheet 160 may include Si and III-IV semiconductor materials such as SiGe, Ge, and InGaAs.

[0024] The base nanosheet 150 and the nanosheet 160 may be spaced apart from each other in the vertical direction. The base nanosheet 150 and the nanosheet 160 may have a plate-like shape, and the horizontal length may be relatively greater than the vertical thickness.

[0025] The inner spacer 190 can reduce the parasitic capacitance between the gate electrode 340 and the source and drain regions 210 and 220 .

[0026] The inner spacers 190 may be disposed on the sides of the gate electrode 340. This may separate the source region 210 and the drain region 220 from the gate electrode 340. The inner spacers 190 may contact the channel regions 150, 160.

[0027] An oxide layer 191 may be formed on an outer surface of the inner spacer 190. In one embodiment, a heat treatment is performed on the outer surface of the inner spacer 190, so that the outer surface of the inner spacer 190 is oxidized to form the oxide layer 191. The oxide layer 191 may improve the film quality performance of the inner spacer 190. The formation of the oxide layer 191 may reduce defects in the inner spacer 190, thereby improving the quality of the inner spacer 190.

[0028] The side spacers 180 may be formed to surround some or all of the sides of the gate electrode 370. The side spacers 180 may separate the source region 210 and the drain region 220 from the gate electrode 370. In one embodiment, a heat treatment may be performed on the side spacers 180 to form an oxide layer on the outer surface of the side spacers 180. The oxide layer may improve the film quality performance of the side spacers 180. The formation of the oxide layer may reduce defects in the side spacers 180 and improve the quality of the side spacers 180.

[0029] 2a to 2g show a process for manufacturing a semiconductor device according to an embodiment, and Fig. 3 is a flow chart showing a method for manufacturing a semiconductor device according to an embodiment.

[0030] 3, the method for manufacturing a semiconductor device according to an embodiment may include a step of growing a stack layer (a1), a step of forming a sacrificial poly gate and a side spacer (b1), a step of forming a side recess (c1), a step of forming an inner spacer (d1), and a step of forming an oxide layer (e1). In addition, the method for manufacturing a semiconductor device according to an embodiment may further include a step of growing a source region and a drain region (f1), and a step of forming an interface film (g1).

[0031] 2a, in the step (a1) of growing the stack layer, a base gate insulating film 130 may be first stacked on the substrates 110 and 120. In some embodiments, the stack layer may be omitted. Then, the stack layer, i.e., the sacrificial layer 140 and the channel regions 150 and 160 may be alternately stacked on the base gate insulating film 130. The sacrificial layer 140 and the channel regions 150 and 160 may be formed epitaxially.

[0032] In one embodiment, the sacrificial layer 140 may include SiGe and the channel regions 150, 160 may include Si.

[0033] Referring to FIG. 2b, in a sacrificial poly gate and side spacer formation step (b1), a sacrificial poly gate 170 and side spacers 180 may be formed on top of the stack layers, ie, the sacrificial layer 140 and the channel regions 150 and 160, respectively.

[0034] The sacrificial poly gate 170 may comprise silicon, e.g., Poly-Si. The side spacers 180 may comprise a dielectric material, e.g., silicon nitride. The side spacers 180 may comprise a low-dielectric material (or low-k material).

[0035] 2c, in the side recess forming step (c1), the side recess may be formed by selectively removing a portion of the sacrificial layer 140 and the base gate insulating film 130. In the side recess forming step (c1), the sacrificial layer 140 and the portion of the base gate insulating film 130 may be removed by wet etching or dry etching, or may be removed by selective etching.

[0036] The sacrificial layer 140 and the base gate insulating layer 130 may have a relatively high selective etch ratio with respect to the channel regions 150 and 160. Thus, when the sacrificial layer 140 and the base gate insulating layer 130 are removed, the channel regions 150 and 160 may not be removed.

[0037] If the step of depositing the base gate insulating film 130 is omitted in the step of growing the stack layer (a1), only a portion of the sacrificial layer 140 can be selectively removed in the step of forming the side recess (c1).

[0038] 2d, in the forming of the inner spacer (d1), the inner spacer 190 may be formed in the side recess formed in the forming of the side recess (c1). In one embodiment, the inner spacer 190 may be formed by atomic layer deposition (ALD). The inner spacer 190 may include a low dielectric material (or low-k material).

[0039] Referring to FIG. 2e, in the oxide layer formation step (e1), the inner spacer 190 may be subjected to a heat treatment.

[0040] More specifically, in the oxide layer forming step (e1), the heat treatment of the inner spacer 190 may be performed in a chamber set to a predetermined process pressure and a predetermined process temperature. In one embodiment, the predetermined process pressure may be set to within a range of 2 atm to 100 atm. In one embodiment, the predetermined process temperature may be set to within a range of 200°C to 600°C.

[0041] When the heat treatment is performed in the oxide layer formation step (e1), an ambient gas may be supplied into the chamber. In one embodiment, the ambient gas may be O2 or H2O. In one embodiment, the concentration of the ambient gas in the chamber may be 100%.

[0042] In one embodiment, the heat treatment carried out in the oxide layer formation step (e1) can be carried out in either a wet, dry or supercritical environment.

[0043] 2f, in the source and drain region growth step (f1), a source region 210 and a drain region 220 may be formed on both sides of the stack layer, i.e., the sacrificial layer 140 and the channel regions 150 and 160. Also, in the source and drain region growth step (f1), the sacrificial layer 140 and the sacrificial poly gate 170 may be removed by selective etching.

[0044] 2g, in the interface film forming step (g1), gate electrodes 340 and 370 each including a metal component may be formed in the area where the sacrificial layer 140 and the sacrificial poly gate 170 have been removed. An interface film including an oxide may be formed on the outer surfaces of the gate electrodes 340 and 370.

[0045] In some embodiments, the source region 210 and drain region 220 may be formed after the sacrificial layer 140 and sacrificial poly gate 170 are removed and the gate electrodes 340, 370 are formed.

[0046] 4a to 4e show a process for manufacturing a semiconductor device according to another embodiment, and Fig. 5 is a flow chart showing a method for manufacturing a semiconductor device according to another embodiment.

[0047] 5, the method for manufacturing a semiconductor device according to another embodiment may include a step of growing a stack layer (a2), a step of forming a sacrificial poly gate (b2), a step of forming a mask (c2), a step of forming a recess (d2), a step of forming a spacer material layer (e2), a step of forming side spacers and inner spacers (f2), and a step of forming an oxide layer (g2). Furthermore, the method for manufacturing a semiconductor device according to another embodiment may further include a step of growing a source region and a drain region (h2), and a step of forming an interface film (i2).

[0048] 4a, in the step (a2) of growing the stack layer, a base gate insulating film 130 may be first stacked on the substrates 110 and 120. In some embodiments, the stack layer may be omitted. Then, the stack layer, i.e., the sacrificial layer 140 and the channel regions 150 and 160, may be alternately stacked on the base gate insulating film 130. The sacrificial layer 140 and the channel regions 150 and 160 may be formed epitaxially.

[0049] In one embodiment, the sacrificial layer 140 may include SiGe and the channel regions 150, 160 may include Si.

[0050] 4a, in the sacrificial poly gate formation step (b2), a sacrificial poly gate 170 may be formed on the stack layer, i.e., the sacrificial layer 140 and the channel regions 150 and 160. The sacrificial poly gates 170 may be formed to be spaced apart from each other. The sacrificial poly gates 170 may include silicon, for example, Poly-Si.

[0051] Referring to FIG. 4 a , in a mask formation step ( c 2 ), a mask 171 may be formed on top of the sacrificial poly gate 170 .

[0052] 4b, in the recess forming step (d2), the recess may be formed by selectively removing a portion of the sacrificial layer 140 and the base gate insulating film 130. In the recess forming step (d2), the sacrificial layer 140 and the portion of the base gate insulating film 130 may be removed by wet etching or dry etching, or may be removed by selective etching.

[0053] The sacrificial layer 140 and the base gate insulating layer 130 may have a relatively high selective etch ratio with respect to the channel regions 150 and 160. Thus, when the sacrificial layer 140 and the base gate insulating layer 130 are removed, the channel regions 150 and 160 may not be removed.

[0054] If the lamination process of the base gate insulating film 130 is omitted in the step (a2) of growing the stack layer, only a portion of the sacrificial layer 140 can be selectively removed in the step (d2) of forming the recess.

[0055] Referring to FIG. 4c, in the spacer material layer forming step (e2), a spacer material layer 280 may be formed on the recess formed in the recess forming step (d2) and on the side of the sacrificial poly gate 170. In the spacer material layer forming step (e2), the sacrificial poly gate 170 may be used as a support structure and a mask. In one embodiment, the spacer material layer 280 may be formed by atomic layer deposition (ALD). The spacer material layer 280 may include a low dielectric material (or low-k material).

[0056] 4d, in the step (f2) of forming side spacers and inner spacers, a portion of the channel regions 150 and 160 and a portion of the spacer material layer 280 are etched to form side spacers 180 and inner spacers 190. In the step (f2) of forming side spacers and inner spacers, the side spacers 180 and the inner spacers 190 may be formed simultaneously.

[0057] Referring to FIG. 4e, in the oxide layer forming step (g2), the inner spacer 190 may be subjected to a heat treatment.

[0058] More specifically, in the oxide layer forming step (g2), the heat treatment of the inner spacer 190 may be performed in a chamber set to a predetermined process pressure and a predetermined process temperature. In one embodiment, the predetermined process pressure may be set to within a range of 2 atm to 100 atm. In one embodiment, the predetermined process temperature may be set to within a range of 200°C to 600°C.

[0059] When the heat treatment is performed in the oxide layer forming step (g2), an ambient gas may be supplied into the chamber. In one embodiment, the ambient gas may be O2 or H2O. In one embodiment, the concentration of the ambient gas in the chamber may be 100%.

[0060] In one embodiment, the heat treatment performed in the oxide layer formation step (g2) can be performed in a wet, dry or supercritical environment.

[0061] In some embodiments, in the oxide layer forming step (g2), a heat treatment may be performed on the side spacer 180. As a result, an oxide layer may be formed on the outer surface of the side spacer 180.

[0062] Although not shown, in the source and drain region growth step (h2), the source region 210 and the drain region 220 can be formed on both sides of the stack layers, i.e., the sacrificial layer 140 and the channel regions 150, 160, respectively. Also, in the source and drain region growth step (h2), the sacrificial layer 140 and the sacrificial poly gate 170 can be removed by selective etching, respectively.

[0063] Although not shown, in the interface film formation step (i2), gate electrodes 340 and 370 each including a metal component may be formed in the area where the sacrificial layer 140 and the sacrificial poly gate 170 have been removed. An interface film including an oxide may be formed on the outer surfaces of the gate electrodes 340 and 370.

[0064] In some embodiments, the source region 210 and drain region 220 may be formed after the sacrificial layer 140 and sacrificial poly gate 170 are removed and the gate electrodes 340, 370 are formed.

[0065] FIG. 6 is a graph showing leakage current values ​​measured when a voltage is applied to a semiconductor device manufactured according to the prior art and a semiconductor device manufactured according to an embodiment of the present specification.

[0066] In FIG. 6, M0 denotes a semiconductor device manufactured according to the conventional technology, and M1 to M3 denote semiconductor devices manufactured according to an embodiment of the present specification.

[0067] M0 is a semiconductor element manufactured according to the same process as in the embodiment of this specification, but the inner spacer is not subjected to heat treatment.

[0068] M1 is a semiconductor element manufactured according to a process similar to that of one embodiment of this specification, in which a heat treatment was performed on the inner spacer in a chamber in which the process temperature was set to 400° C. and the process pressure was set to 2 atmospheres.

[0069] M2 is a semiconductor element manufactured according to a process similar to that of one embodiment of this specification, in which a heat treatment was performed on the inner spacer in a chamber in which the process temperature was set to 400° C. and the process pressure was set to 5 atmospheres.

[0070] M3 is a semiconductor element manufactured according to a process similar to that of one embodiment of this specification, in which a heat treatment was performed on the inner spacer in a chamber in which the process temperature was set to 400° C. and the process pressure was set to 10 atmospheres.

[0071] 6, the leakage current of the semiconductor elements (M1, M2, M3) in which the heat treatment is performed on the inner spacer according to the embodiment is smaller than the leakage current of the semiconductor element (M0) in which the heat treatment is not performed on the inner spacer. In particular, it is confirmed that the leakage current of the semiconductor elements (M1, M2, M3) in which the heat treatment is performed on the inner spacer according to the embodiment is maintained at 3.5 mA or less. Therefore, when the heat treatment is performed on the inner spacer, the electrical characteristics of the semiconductor elements can be improved.

[0072] As described above, the present specification has been described with reference to the exemplary drawings, but the present specification is not limited to the embodiments and drawings disclosed in the present specification, and various modifications may be made by those skilled in the art. Furthermore, even if the effects of the configurations of the present specification are not explicitly described and explained in the above-mentioned embodiments of the present specification, the effects that can be predicted by the configurations should also be recognized.

Claims

1. growing a stack of layers on a substrate by alternating sacrificial layers and channel regions; forming a sacrificial poly gate on the stack layer; forming inner spacers and side spacers on sides of the sacrificial layer and sides of the sacrificial poly gate; performing a heat treatment on the inner spacer or the side spacer in a chamber set to a predetermined process pressure and a predetermined process temperature; Including, A method for manufacturing a semiconductor device.

2. The predetermined process pressure is Determined within 2 atm to 100 atm. The method for manufacturing a semiconductor device according to claim 1 .

3. The predetermined process temperature is Determined at 200°C to 600°C; The method for manufacturing a semiconductor device according to claim 1 .

4. An ambient gas is provided in the chamber, The atmospheric gas is O ２ Or H ２ It is O. The method for manufacturing a semiconductor device according to claim 1 .

5. The concentration of the atmospheric gas is 100%. The method for manufacturing a semiconductor device according to claim 4 .

6. The heat treatment is This can be done in wet, dry or supercritical environments. The method for manufacturing a semiconductor device according to claim 1 .

7. The step of forming the inner spacer and the side spacer comprises: forming the side spacers on the stack layer; The method for manufacturing a semiconductor device according to claim 1 .

8. The step of forming the inner spacer and the side spacer comprises: removing a portion of the sacrificial layer to form a side recess; forming an inner spacer in the side recess; Including, The method for manufacturing a semiconductor device according to claim 1 .

9. The step of forming the inner spacer and the side spacer comprises: removing a portion of the sacrificial layer to form a recess; forming a spacer material layer on sides of the recess and the sacrificial poly gate; removing a portion of the channel region and a portion of the spacer material layer to form the inner spacers and side spacers; Including, The method for manufacturing a semiconductor device according to claim 1 .

10. forming source and drain regions; removing the sacrificial layer and the sacrificial poly gate; forming a gate electrode; Further comprising: The method for manufacturing a semiconductor device according to claim 1 .

11. removing the sacrificial layer and the sacrificial poly gate; forming a gate electrode; forming source and drain regions; Further comprising: The method for manufacturing a semiconductor device according to claim 1 .

12. A substrate; a channel region including a number of nanosheets deposited on the substrate; a gate electrode disposed in contact with at least one surface of the channel region; a source region and a drain region disposed on either side of the channel region, a side spacer disposed on a side surface of the gate electrode; an inner spacer disposed on a side surface of the gate electrode; Including, An oxide film layer is formed on an outer surface of the side spacer or the inner spacer by a heat treatment performed in a chamber set to a predetermined process pressure and a predetermined process temperature. Semiconductor element.

13. The predetermined process pressure is determined within a range of 2 atm to 100 atm. The semiconductor device of claim 12.

14. The predetermined process temperature is Determined at 200°C to 600°C; The semiconductor device of claim 12.

15. An ambient gas is provided in the chamber, The atmospheric gas is O ２ Or H ２ It is O. The semiconductor device of claim 12.

16. The concentration of the atmospheric gas is 100%. The semiconductor device of claim 15.

17. The heat treatment is This can be done in wet, dry or supercritical environments. The semiconductor device of claim 12.

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