CAPACITOR AND METHOD FOR MANUFACTURING A CAPACITOR - Patent application

Abstract

An embodiment of the present disclosure provides a capacitor and a method for manufacturing the capacitor. The capacitor includes a substrate having a first surface and a second surface opposite to the first surface, the substrate being provided with a via extending through the first surface to the second surface; a first electrode plate coupled to the first surface of the substrate; a first conductive portion disposed on the second surface of the substrate; a second conductive portion disposed on a side of the first electrode plate and opposite to the via; and a third conductive portion disposed on an inner wall of the via to couple the first conductive portion and the second conductive portion. According to this solution, the first surface and the second surface of the substrate are short-circuited by the conductive portion. In this way, an effective bypass effect can be formed for the substrate, and as a result, the dielectric loss of the capacitor under high frequency operating conditions can be significantly reduced and the performance of the capacitor can be improved.

Description

[Technical field]

[0001] The present disclosure relates to the field of capacitors, and more specifically to capacitors having ultra-low losses at high frequencies and methods of making the capacitors. [Background technology]

[0002] In the application field of radio frequency signals, the amplification and transmission of signals under radio frequency operating conditions are usually related. In the conventional packaging structure of radio frequency devices, a capacitor in the form of a metal-oxide-semiconductor field-effect transistor (MOSFET) can be introduced at the input end to match the input impedance to maximize the performance of the radio frequency device. The radio frequency losses of the capacitor at the input end are likely to occur under high frequency operating conditions due to the limitations of the physical properties of the electrode material of the substrate. As the operating frequency band of the capacitor increases, these radio frequency losses will further increase. Therefore, how to reduce the radio frequency losses of the capacitor is a challenge for designers. Summary of the Invention

[0003] In consideration of the aforementioned problems, the embodiments of the present disclosure relate to a technical solution for a capacitor, in particular to provide a capacitor and a method for manufacturing a capacitor, to reduce the loss of the capacitor at high frequencies.

[0004] According to a first aspect of the present disclosure, a capacitor is provided, the capacitor comprising: a substrate having a first surface and a second surface opposite to the first surface, the substrate being provided with a via extending through the first surface to the second surface; a first electrode plate coupled to the first surface of the substrate; a first conductive portion disposed on the second surface of the substrate; a second conductive portion disposed on a side of the first electrode plate facing the via; and a third conductive portion disposed on an inner wall of the via to couple the first conductive portion to the second conductive portion.

[0005] According to this embodiment of the present disclosure, the first and second sides of the substrate are short-circuited by the conductive part, in this way, an effective bypass effect can be formed for the substrate, so that the dielectric loss of the capacitor in high frequency operating conditions can be significantly reduced and the performance of the capacitor can be improved.

[0006] In some implementations, the first electrode plate has a first portion and a second portion, and the capacitor further comprises: a first dielectric layer located on and coupled to the first portion of the first electrode plate; and a second electrode plate located on and coupled to the first dielectric layer by the first dielectric layer. In this way, a stable operation of the capacitor can be ensured.

[0007] In some implementations, the capacitor further comprises a second dielectric layer disposed on the second portion of the first plate and at least a portion of the second plate, In this manner, capacitor components can be protected from water and shock.

[0008] In some implementations, the first dielectric layer is made of the following materials: silicon nitride, silicon oxide, silicon oxynitride. ,acid In this manner, multiple materials can be used to manufacture the first media layer, resulting in greater flexibility in the manufacture of the first media layer.

[0009] In some implementations, the second electrode plate comprises at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride. In this manner, multiple materials may be used to manufacture the second electrode plate as well, resulting in greater flexibility in the manufacture of the second electrode plate.

[0010] In some implementations, the second dielectric layer is made of the following materials: silicon nitride, silicon oxide, silicon oxynitride. ,acidThe second dielectric layer may include at least one of aluminum oxide, titanium oxide, and titanium dioxide. In this way, a suitable material may be selected from a variety of materials based on the actual design requirements to manufacture the second dielectric layer.

[0011] In some implementations, the first conductive portion, the second conductive portion, and the third conductive portion are integrally formed. In this manner, the conductive portions can be conveniently and quickly formed.

[0012] In some implementations, when the via is viewed in a direction perpendicular to the first surface, the cross section of the via is circular, elliptical, long strip-like, or polygonal. In this manner, expected vias can be obtained based on various design requirements.

[0013] In some implementations, the first conductive portion, the second conductive portion, and the third conductive portion comprise at least one of the following materials: nickel, titanium, aluminum, lead, platinum, gold, titanium nitride, tantalum nitride, and copper. In this way, the short-circuit effect of the first and second sides of the substrate can be ensured by the conductive properties of the conductive portions to ensure the performance of the capacitor.

[0014] In some implementations, the first electrode plate has at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride. In this way, a suitable material can be flexibly selected from various materials to manufacture the first electrode plate based on actual design requirements.

[0015] According to a second aspect of the present disclosure, there is provided a method of manufacturing a capacitor, the method comprising: providing a substrate, the substrate having a first surface and a second surface opposite to the first surface; providing a via on the substrate extending through the first surface to the second surface; providing a first electrode plate on the substrate, the first electrode plate being bonded to the first surface of the substrate; providing a first conductive portion on the second surface of the substrate; providing a second conductive portion on a side of the first electrode plate facing the via; and providing a third conductive portion on an inner wall of the via to bond the first conductive portion to the second conductive portion.

[0016] In some implementations, the first electrode plate has a first portion and a second portion, and the method further includes: providing a dielectric material on the first electrode plate; and removing a portion of the dielectric material that is bonded to the second portion to form a first dielectric layer.

[0017] In some implementations, the method further comprises: providing a second electrode plate on the first dielectric layer, wherein the second electrode plate is coupled to the first electrode plate by the first dielectric layer.

[0018] In some implementations, the method further includes: providing a wrapping material over the second portion of the first electrode plate and the second electrode plate; and removing a portion of the wrapping material that is over the second electrode plate to form a second dielectric layer.

[0019] In some implementations, the first dielectric layer is made of the following materials: silicon nitride, silicon oxide, silicon oxynitride. ,acid The material contains at least one of aluminum oxide, titanium oxide, and aluminum carbide.

[0020] In some implementations, the second electrode plate comprises at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride.

[0021] In some implementations, the second dielectric layer is made of the following materials: silicon nitride, silicon oxide, silicon oxynitride. ,acid The material contains at least one of aluminum oxide, titanium oxide, and aluminum carbide.

[0022] In some implementations, the first conductive portion, the second conductive portion, and the third conductive portion are integrally formed.

[0023] In some implementations, when the via is viewed in a direction perpendicular to the first surface, the cross section of the via is circular, elliptical, elongated strip-like, or polygonal.

[0024] In some implementations, the first conductive portion, the second conductive portion, and the third conductive portion comprise at least one of the following materials: nickel, titanium, aluminum, lead, platinum, gold, titanium nitride, tantalum nitride, and copper.

[0025] In some implementations, the first electrode plate comprises at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride.

[0026] It should be understood that the contents described in the summary are not intended to limit the key or important features of the implementation of the present disclosure or to limit the scope of the present disclosure. Other features of the present disclosure will be readily understood by the following description. [Brief description of the drawings]

[0027] The foregoing and other features, advantages, and aspects of the disclosed embodiments will become more apparent with reference to the accompanying drawings and the following detailed description, in which like or similar reference numbers indicate like or similar elements.

[0028] [Figure 1] FIG. 1 is a cross-sectional view of an existing capacitor structure.

[0029] [Diagram 2] FIG. 2 is a schematic diagram of an equivalent circuit of the capacitor in FIG.

[0030] [Diagram 3] FIG. 2 is a cross-sectional view of a capacitor structure according to an example embodiment of the present disclosure.

[0031] [Figure 4] FIG. 4 is a schematic diagram of an equivalent circuit of the capacitor in FIG.

[0032] [Figure 5A] 4 illustrates example stages for forming a capacitor according to an embodiment of the present disclosure. [Figure 5B] 4 illustrates example stages for forming a capacitor according to an embodiment of the present disclosure. [Figure 5C] 4 illustrates example stages for forming a capacitor according to an embodiment of the present disclosure. [Figure 5D] 4 illustrates example stages for forming a capacitor according to an embodiment of the present disclosure. [Figure 5E] 4 illustrates example stages for forming a capacitor according to an embodiment of the present disclosure. [Figure 5F] 4 illustrates example stages for forming a capacitor according to an embodiment of the present disclosure. [Figure 5G] 4 illustrates example stages for forming a capacitor according to an embodiment of the present disclosure. [Figure 5H] 4 illustrates example stages for forming a capacitor according to an embodiment of the present disclosure. [Figure 5I] 4 illustrates example stages for forming a capacitor according to an embodiment of the present disclosure.

[0033] [Figure 6] 1 illustrates a method of manufacturing a capacitor according to an example embodiment of the present disclosure.

[0034] [Figure 7A] FIG. 2 is a top view of a capacitor according to an example embodiment of the present disclosure. [Figure 7B] FIG. 2 is a top view of a capacitor according to an example embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] Hereinafter, the embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided for a fuller and more complete understanding of the present disclosure. It should be understood that the accompanying drawings and embodiments of the present disclosure are merely used as examples and are not intended to limit the protection scope of the present disclosure.

[0036] In describing embodiments of the present disclosure, the term "include" and similar terms should be understood as a non-exclusive inclusion, i.e., "including but not limited to." The term "based on" should be understood as "based at least in part on." The term "an embodiment" or "this embodiment" should be understood as "at least one embodiment." Terms such as "first" and "second" may refer to different objects or the same object. The term "and / or" refers to at least one of the two items associated with the term. For example, "A and / or B" refers to A, B, or A and B. The following may further include other explicit and implied definitions.

[0037] It should be understood that in the technical solutions provided in the embodiments of the present disclosure, some repeated parts may not be described again in the following descriptions of specific embodiments, but these specific embodiments should be regarded as being mutually referenced and can be combined with each other.

[0038] As mentioned above, the industry is eager to find a capacitor that can reduce radio frequency losses. Figure 1 is a cross-sectional view of a structure of a capacitor 100' in the prior art. As shown in Figure 1, the capacitor 100' generally includes a substrate 110', a dielectric layer 140', and an electrode plate 150' arranged in sequence in a laminated structure. The dielectric layer 140' is located above the substrate 110'. The electrode plate 150' is located above the dielectric layer 140'.

[0039] As the operating frequency of the capacitor increases, radio frequency losses exist in both the dielectric layer 140' and the electrode plate 150'. Thus, the transmission speed of the signal slows down and the high-speed transmission of the signal is greatly regulated. To reduce this radio frequency loss of the capacitor 100', several solutions have been proposed in the prior art.

[0040] FIG. 2 is a schematic diagram of an equivalent circuit of the capacitor 100' in FIG. 1. Since the substrate 110' introduces a resistor resistance value to the entire capacitor 100', the equivalent capacitor 200' in FIG. 2 is equivalent to equivalently connecting a resistor R' in series with the dielectric layer 240' and the electrode plate 250' in the capacitor 200'. Since there is a proportional relationship between the equivalent resistance R' introduced by the substrate 110' and the thickness d' of the substrate 110', in some conventional solutions, the thickness d' of the substrate 110' can be reduced. This method is intended to reduce the high frequency loss of the capacitor 100' by reducing the resistance value of the resistor R' introduced by the substrate 110' in the entire capacitor 100' by thinning the substrate 110'. However, due to the limitation of the manufacturing process, there is a bottleneck restriction on thinning the substrate 110'. For example, it is difficult to reduce the thickness d' of the substrate 110' to less than 50 μm. Therefore, the degree of loss reduction is limited. More unsatisfactorily, since the substrate 110' has unavoidable high frequency losses, there will still be non-negligible losses in the capacitor 100' regardless of the thickness d' of the substrate 110'. Since the substrate 110' is non-negligible, there must be a resistor R', whose resistance causes high frequency losses.

[0041] To address at least the aforementioned problems, embodiments of the present disclosure provide a capacitor, and a method for manufacturing the capacitor, that can have ultra-low losses at high frequencies.

[0042] According to a first aspect, a capacitor according to an embodiment of the present disclosure is provided. FIG. 3 is a cross-sectional view of a capacitor 300. As shown in FIG. 3, the capacitor 300 generally includes a substrate 310, a first electrode plate 320, a first dielectric layer 340, and a second electrode plate 350 in a laminated structure. The substrate 310 has a first surface 311 and a second surface 312 facing the first surface 311. The first electrode plate 320 is bonded to the first surface 311 of the substrate 310, and the first dielectric layer 340 and the second electrode plate 350 are sequentially disposed above the first electrode plate 320. In addition, as shown in FIG. 3, the substrate 310 provides a via 315 extending through the first surface 311 to the second surface 312. A portion of the first electrode plate 320 is exposed by the via 315. Capacitor 300 further has a plurality of conductive portions including a first conductive portion 331 disposed on second surface 312 of substrate 310, a second conductive portion 332 disposed on a side of first electrode plate 320 facing via 315 (i.e., a portion that is a part of first electrode plate 320 and exposed by via 315), and a third conductive portion 333 disposed on an inner wall 316 of via 315. First conductive portion 331 is coupled to second conductive portion 332 by third conductive portion 333, so that the conductive portions of capacitor 300 may be formed as a whole.

[0043] According to this embodiment of the present disclosure, the first electrode plate 320 is disposed on the first surface 311 of the substrate 310, a backside via process is applied to the second surface 312 of the substrate 310, and a conductive part is applied to the second surface 312 of the substrate 310 and inside the via 315, so that the first surface 311 and the second surface 312 of the substrate 310 can be shorted by the conductive part. In this way, an effective bypass effect can be formed for the substrate 310.

[0044] FIG. 4 is a schematic diagram of an equivalent circuit of the capacitor 300 in FIG. 3. As shown in FIG. 4, the first electrode plate 320 and the substrate 310 are shorted by the first electrode plate 320, the via 315 extending through the substrate 310, and the conductive portion of the capacitor 300 in FIG. 3. In this way, the resistor introduced by the first electrode plate 320 and the substrate 310 can be neglected. Compared with the circuit structure in the existing solution shown in FIG. 2, the equivalent capacitor 400 in FIG. 4 does not have high-frequency loss caused by the resistor R'. Therefore, the first dielectric layer 440 and the second electrode plate 450 in the equivalent capacitor 400 can be regarded as not being connected in series with the equivalent resistance R'. In this way, the dielectric loss of the capacitor 300 in high-frequency operating conditions can be significantly reduced.

[0045] Referring back to Figure 3. In some embodiments, the first conductive portion 331, the second conductive portion 332, and the third conductive portion 333 may have at least one of the following materials: nickel, titanium, aluminum, lead, platinum, gold, titanium nitride, tantalum nitride, and copper. In other embodiments, the conductive portions may be made of any combination of these materials. In this way, the first electrode plate 320 disposed on the first surface 311 of the substrate 310 and the second surface 312 of the substrate 310 may be short-circuited by the conductive effect of these conductive portions to ensure a reduction in high frequency loss. It should be understood that the materials listed herein are merely exemplary and not comprehensive. The first conductive portion 331, the second conductive portion 332, and the third conductive portion 333 may also be made of other conductive materials currently available or developed in the future, as long as such conductive materials can implement the expected short-circuit effect.

[0046] In the following, an example of a process for forming a capacitor 500 according to an embodiment of the present disclosure will be described with reference to the steps shown in Figures 5A to 5I. It should be understood that these illustrated steps are merely examples, are not exhaustive, and are not intended to limit the scope of protection of the present disclosure. There may be any other suitable transformation methods for forming the capacitor 500. Details are not described herein.

[0047] As shown in FIG. 5A, a substrate 510 having a first side 511 and a second side 512 is provided. The substrate 510 may be made of a semiconductor wafer known in the industry or developed in the future. In some embodiments, such a semiconductor wafer may be made of one or more of materials such as silicon, silicon carbide, gallium nitride, and aluminum nitride. It should be understood that the materials listed herein are merely exemplary and not all-inclusive. In some other embodiments, such a semiconductor wafer may be a conductive wafer, a semi-insulating wafer, or an insulating wafer. In other words, the conductivity of the semiconductor wafer is not limited in this embodiment of the disclosure. It should be noted that although the drawings show the first side 511 and the second side 512 of the substrate 510 as being parallel, this is not required. There may be a certain non-zero included angle between the first side 511 and the second side 512.

[0048] Further, see FIG. 5B. The first electrode plate 520 is provided above the first surface 511 of the substrate 510. The first electrode plate 520 is also referred to as a lower electrode plate. In some embodiments, the first electrode plate 520 may be made of a metal, such as, for example, one or more of gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, and tantalum. In some other embodiments, the first electrode plate 520 may alternatively be made of an alloy material, such as, for example, one or more of titanium nitride, tungsten silicide, and tantalum nitride. It should be understood that the materials listed herein are merely exemplary and not limiting. Those skilled in the art may consider other materials for manufacturing the first electrode plate 520. In some embodiments, a layer of metal may be deposited by electron beam evaporation, magnetron sputtering, or the like to form the first electrode plate 520. It should be noted that the deposition manner described herein is merely illustrative and not limiting. To provide a first electrode plate 520 above the first surface 511 of the substrate 510, material may be deposited by any known or future developed deposition technique.

[0049] Further, see FIG. 5C. A first dielectric layer 540 is deposited above the first electrode plate 520. In some embodiments, the thickness of the first dielectric layer 540 may range from 20 nm to 500 nm. Note that the values ​​herein are merely exemplary and not limiting. In some other embodiments, the first dielectric layer 540 is made of the following materials: silicon nitride, silicon oxide, silicon oxynitride. ,acid The first dielectric layer 540 may have at least one of aluminum oxide, titanium oxide, and aluminum carbide. The first dielectric layer 540 may be of a single layer structure or a multi-layer stack structure. The specific structure of the first dielectric layer 540 is not limited in this embodiment of the present disclosure.

[0050] Further, see FIG. 5D. A first portion 521 and a second portion 522 different from the first portion 521 can be determined in the first electrode plate 520. The portion that is part of the first dielectric layer 540 and is bonded to the second portion 522 can be removed by an etching process, and the portion that is part of the first dielectric layer 540 and is bonded to the first portion 521 can be maintained, thereby forming the final first dielectric layer 540. In other words, the unnecessary portion can be etched by a suitable process, and a portion of the dielectric material can be maintained, thereby forming the first dielectric layer 540. Since the designed capacitance of the capacitor 500 is proportional to the area of ​​the first dielectric layer 540, the area of ​​the first dielectric layer 540 that needs to be maintained can be calculated based on the required capacitance of the final capacitor 500 that needs to be obtained. The specific calculation method is not limited in this embodiment of the present disclosure.

[0051] It should be noted that the technique for obtaining the first dielectric layer 540 is not limited in this embodiment of the present disclosure. For example, in some embodiments, the final first dielectric layer 540 may be obtained by various wet or dry etching processes.

[0052] Further, see FIG. 5E. The second electrode plate 550 is provided above the first dielectric layer 540. The second electrode plate 550 is also referred to as the upper electrode plate. In some embodiments, the second electrode plate 550 may be made of a metal material, such as one or more of gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, and tantalum. In some other embodiments, the second electrode plate 550 may be made of an alloy material, such as one or more of titanium nitride, tungsten silicide, and tantalum nitride. The second electrode plate 550 may be made of the same material as that of the first electrode plate 520, or may be made of a different material than that of the first electrode plate 520. If the second electrode plate 550 is metal, the metal graphics of the second electrode plate 550 may be determined by using a lithography process. In some other embodiments, the graphics may alternatively be obtained by a metal evaporation process or a metal dry etching process. It should be understood that the processes mentioned herein are merely exemplary.

[0053] Also see FIG. 5F. A second dielectric layer 560 may be formed above the second electrode plate 550. In some embodiments, the thickness of the second dielectric layer 560 may range from 20 nm to 2000 nm. Note that the values ​​herein are merely exemplary and not limiting. In some other embodiments, the second dielectric layer 560 may be made of the following materials: silicon nitride, silicon oxide, silicon oxynitride. ,acidThe second dielectric layer 560 may have at least one of aluminum oxide, titanium oxide, and titanium dioxide. It should be understood that the materials listed herein are merely exemplary and not limiting. A person skilled in the art may consider other materials for manufacturing the second dielectric layer 560. In some embodiments, the second dielectric layer 560 may be made of the same material as that of the first dielectric layer 540. In some other embodiments, the second dielectric layer 560 may alternatively be made of a material different from that of the first dielectric layer 540. The second dielectric layer 560 may be of a single layer structure or may be of a multi-layer stack structure. The specific structure of the second dielectric layer 560 is not limited in this embodiment of the present disclosure.

[0054] Further, see FIG. 5G. A portion of the second dielectric layer 560 may be removed from the second electrode plate 550 by an etching process, and the remaining portion of the second dielectric layer 560 may be maintained, thereby forming the final second dielectric layer 560. In other words, the unnecessary portion may be etched by a suitable process, and a portion of the dielectric material may be maintained, thereby forming the second dielectric layer 560. The second dielectric layer 560 may be referred to as a wrapping layer, and is configured to protect other components of the capacitor 500 from being affected by moisture, impact, etc.

[0055] It should be noted that, similar to the first dielectric layer 540, the technique for obtaining the second dielectric layer 560 is not limited in this embodiment of the present disclosure. For example, in some embodiments, the final second dielectric layer 560 may be obtained by various wet or dry etching processes. The second dielectric layer 560 may be obtained by the same process as that of the first dielectric layer 540, or may be obtained by a process different from that of the first dielectric layer 540.

[0056] Further, please refer to FIG. 5H. As shown in the drawing, a deep via etch is performed on the second surface 512 of the substrate 510 to obtain the vias 515 shown in the drawing. The vias 515 are etched, so that a part of the first electrode plate 520 is exposed, and the inner wall 516 of the vias 515 is also exposed. Although two vias 515 are shown in the drawing, this is not limiting. The number of vias 515 can be determined based on the actual process requirements. In addition, the two vias 515 shown in FIG. 5H extend parallel to each other. In this way, a part of the vias 515 and a part of the first electrode plate 520 can be exposed. It should be understood that the parallelism in this specification is merely exemplary and does not require absolute parallelism in the strict sense, and a certain degree of non-parallelism between the multiple vias 515 is allowed. In addition, in the embodiment of FIG. 5A to FIG. 5I, the depth direction of these vias 515 is substantially perpendicular to the second surface 512 of the substrate 510. It should be understood that this is merely exemplary. The via 515 and the second surface 512 of the substrate 510 may form other angles, such as, for example, 85 degrees, 80 degrees, or 75 degrees, etc. The specific angle is not limited to this embodiment of the disclosure.

[0057] Finally, see FIG. 5I. A metal laminate material is deposited on the second surface 512 of the substrate 510. Such a metal laminate material may be deposited on the second surface 512 of the substrate 510. Second 5I, the first conductive portion 531 is coupled to the second conductive portion 532 by the third conductive portion 533, so that a conductive portion is formed as a whole. In some embodiments, the thickness of the first conductive portion 531, the second conductive portion 532, and the third conductive portion 533 may range from 20 nm to 1500 nm. Note that the values ​​herein are merely exemplary and not limiting. In some other embodiments, the first conductive portion 531, the second conductive portion 532, and the third conductive portion 533 may comprise at least one of the following materials: nickel, titanium, aluminum, lead, platinum, gold, titanium nitride, tantalum nitride, and copper. It should be understood that the materials listed herein are merely exemplary and not limiting. Other materials for fabricating these conductive portions may be considered by those skilled in the art.

[0058] Since the first conductive portion 531 is located on the second surface 512 of the substrate 510 and the second conductive portion 532 is located on the exposed portion of the first electrode plate 520, the second surface 512 of the substrate 510 and the first electrode plate 520 can be short-circuited by the conductive portion which is coupled to each other and has an approximately square wave shape. In this way, an effective bypass effect can be formed for the substrate 510 and the first electrode plate 520, ensuring a reduction in high frequency loss.

[0059] 5A to 5I show examples of steps for manufacturing the capacitor 500, it should be understood that the steps do not have to be performed strictly in the order shown in the drawings, and some steps may be interchanged. For example, as shown in FIGS. 5D and 5E, the graphic of the first dielectric layer 540 is formed first, and then the second electrode plate 550 is provided above the graphic-defined first dielectric layer 540. However, in other embodiments, the first dielectric layer 540 and the second electrode plate 550 may alternatively be graphically defined after the first dielectric layer 540 and the second electrode plate 550 are formed above the entire surface of the first electrode plate 520. Such steps should be considered to be included in the embodiments of the present disclosure. For another example, in the illustrated embodiment, the via 515 is formed after the first dielectric layer 540, the second electrode plate 550, and the second dielectric layer 560 are formed. However, it may be understood that the via 515 may alternatively be formed before the first dielectric layer 540, the second electrode plate 550, and the second dielectric layer 560 are formed, or may be formed synchronously with the first dielectric layer 540, the second electrode plate 550, and the second dielectric layer 560. Such steps should also be considered to be included in the embodiments of the present disclosure. Additionally, the components in the figures are not drawn to scale, and the size relationships between these components are merely exemplary.

[0060] FIG. 6 illustrates, in block diagram form, a manufacturing method 600 according to a second aspect of the present disclosure for manufacturing the above-mentioned semiconductor device 500. As illustrated in FIG. 6, in block 602, a substrate 510 having a first side 511 and a second side 512 is provided. The substrate 510 may be, for example, a wafer as commonly referred to in the art. Then, in block 604, the substrate 510 is provided with vias 515 extending through the first side 511 to the second side 512. This may be implemented in any suitable manner. After the vias 515 are formed, in block 606, a first electrode plate 520 is provided on the first side 511 of the substrate 510, such that the first electrode plate 520 is bonded to the first side 511. Then, in block 608, a first conductive portion 531 is provided on the second side 512 of the substrate 510. As shown in blocks 610 and 612, respectively, second conductive portion 532 is formed on a surface exposed by via 515 and on a side of first electrode plate 520 facing via 515, and third conductive portion 533 is formed on an inner wall 516 of via 515. Second conductive portion 532 is coupled to first conductive portion 531 by third conductive portion 533.

[0061] 7A and 7B are top views of a capacitor 700 according to an embodiment of the present disclosure. Several examples of the structure and layout of the via 715 and the positional relationship between the via 715 and the second electrode plate 750 can be seen. In some embodiments, as shown in FIG. 7A, the cross section of the via 715 can be approximately elliptical when the via 715 is observed in a direction perpendicular to the surface of the substrate in FIGS. 5A to 5I. In the embodiment shown in FIG. 7B, the via 715 can alternatively be in the shape of a long strip. However, those skilled in the art can understand that various other graphics can be conceived, such as a circle, a semicircle, a triangle, a rectangle, a rectangle with rounded corners, or another polygon. The specific shape is not limited in this embodiment of the present disclosure.

[0062] Although the subject matter has been described in language specific to structural features and / or methodological operations, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or operations described above. On the contrary, the specific features and operations described above are merely example forms for implementing the claims. (Other possible items) (Item 1) a substrate (10) having a first surface (11) and a second surface (12) opposite said first surface (11), said substrate (10) being provided with vias (15) extending through said first surface (11) to said second surface (12); a first electrode plate (20) bonded to the first surface (11) of the substrate (10); a first conductive portion (31) disposed on the second surface (12) of the substrate (10); a second conductive portion (32) disposed on the side of the first electrode plate (20) facing the via (15); and a third conductive portion (33) disposed on an inner wall (16) of the via (15) to couple the first conductive portion (31) to the second conductive portion (32); A capacitor (1). (Item 2) The first electrode plate (20) has a first portion (21) and a second portion (22), and the capacitor (1) further comprises: a first dielectric layer (40) located on and bonded to the first portion (21) of the first electrode plate (20); and a second electrode plate (50) located on the first dielectric layer (40) and coupled to the first electrode plate (20) by the first dielectric layer (40); The capacitor (1) according to item 1, comprising: (Item 3) 3. The capacitor (1) of claim 2, further comprising a second dielectric layer (60) positioned on the second portion (22) of the first electrode plate (20) and at least a portion of the second electrode plate (50). (Item 4) 4. The capacitor (1) according to item 2 or 3, wherein the first dielectric layer (40) comprises at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, and titanium oxide. (Item 5) 5. The capacitor (1) of any one of items 2 to 4, wherein the second electrode plate (50) comprises at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride. (Item 6) 4. The capacitor (1) of claim 3, wherein the second dielectric layer (60) comprises at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, and titanium oxide. (Item 7) 7. The capacitor (1) of any one of items 1 to 6, wherein the first conductive portion (31), the second conductive portion (32), and the third conductive portion (33) are integrally formed. (Item 8) 8. The capacitor (1) of any one of items 1 to 7, wherein when the via (15) is observed in a direction perpendicular to the first surface (11), the cross section of the via (15) is circular, elliptical, elongated strip-like, or polygonal. (Item 9) 9. The capacitor (1) according to any one of claims 1 to 8, wherein the first conductive portion (31), the second conductive portion (32), and the third conductive portion (33) have at least one of the following materials: nickel, titanium, aluminum, lead, platinum, gold, titanium nitride, tantalum nitride, and copper. (Item 10) 10. The capacitor (1) of any one of items 1 to 9, wherein the first electrode plate (20) comprises at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride. (Item 11) A method for manufacturing a capacitor (1), comprising the steps of: providing a substrate (10), said substrate (10) having a first surface (11) and a second surface (12) opposite said first surface (11); providing a via (15) on said substrate (10) extending through said first side (11) to said second side (12); providing a first electrode plate (20) on the substrate (10), wherein the first electrode plate (20) is bonded to the first surface (11) of the substrate (10); providing a first conductive portion (31) on the second surface (12) of the substrate (10); providing a second conductive portion (32) on a side of the first electrode plate (20) facing the via (15); and providing a third conductive portion (33) on an inner wall (16) of the via (15) to couple the first conductive portion (31) to the second conductive portion (32); A method comprising: (Item 12) The first electrode plate (20) has a first portion (21) and a second portion (22), and the method further comprises: providing a dielectric material on the first electrode plate (20); and Item 12. The method of item 11, comprising removing a portion of the dielectric material that is bonded to the second portion (22) to form a first dielectric layer (40). (Item 13) The method further comprises: Item 13. The method of item 12, comprising providing a second electrode plate (50) on the first dielectric layer (40), wherein the second electrode plate (50) is bonded to the first electrode plate (20) by the first dielectric layer (40). (Item 14) providing a wrapping material on the second portion (22) of the first electrode plate (20) and on the second electrode plate (50); and removing a portion of the wrapping material that is above the second electrode plate (50) to form a second dielectric layer (60); Item 14. The method of item 13, further comprising: (Item 15) 15. The method according to any one of items 12 to 14, wherein the first dielectric layer (40) comprises at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, and titanium oxide. (Item 16) 15. The method according to claim 13 or 14, wherein the second electrode plate (50) comprises at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride. (Item 17) Item 15. The method according to item 14, wherein the second dielectric layer (60) comprises at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, and titanium oxide. (Item 18) Item 18. The method according to any one of items 11 to 17, wherein the first conductive portion (31), the second conductive portion (32), and the third conductive portion (33) are integrally formed. (Item 19) 19. The method according to any one of items 11 to 18, wherein the cross-section of the via (15) is circular, elliptical, elongated strip-like, or polygonal when the via (15) is observed in a direction perpendicular to the first face (11). (Item 20) 20. The method according to any one of items 11 to 19, wherein the first conductive portion (31), the second conductive portion (32) and the third conductive portion (33) comprise at least one of the following materials: nickel, titanium, aluminum, lead, platinum, gold, titanium nitride, tantalum nitride and copper. (Item 21) 21. The method according to any one of items 11 to 20, wherein the first electrode plate (20) comprises at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride.

Claims

1. a substrate (10) having a first surface (11) and a second surface (12) opposite said first surface (11), said substrate (10) being provided with vias (15) extending through said first surface (11) to said second surface (12); a first electrode plate (20) bonded to the first surface (11) of the substrate (10); A first conductive portion (31) disposed on the second surface (12) of the substrate (10); A second conductive portion (32) disposed on the side of the first electrode plate (20) facing the via (15); and a third conductive portion (33) disposed on an inner wall (16) of the via (15) to couple the first conductive portion (31) to the second conductive portion (32); A capacitor (1).

2. The first electrode plate (20) has a first portion (21) and a second portion (22), and the capacitor (1) further comprises: a first dielectric layer (40) located on and bonded to the first portion (21) of the first electrode plate (20); and a second electrode plate (50) located on the first dielectric layer (40) and bonded to the first electrode plate (20) by the first dielectric layer (40); The capacitor (1) according to claim 1, comprising:

3. The capacitor (1) of claim 2, further comprising a second dielectric layer (60) located on the second portion (22) of the first electrode plate (20) and on at least a portion of the second electrode plate (50).

4. The capacitor (1) according to claim 2 or 3, wherein the first dielectric layer (40) comprises at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon oxide, aluminium oxide and titanium oxide.

5. 5. The capacitor (1) of claim 2, wherein the second electrode plate (50) comprises at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride.

6. The capacitor (1) of claim 3, wherein the second dielectric layer (60) comprises at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

7. The capacitor (1) according to any one of claims 1 to 6, wherein the first conductive portion (31), the second conductive portion (32), and the third conductive portion (33) are integrally formed.

8. 8. The capacitor (1) of claim 1, wherein the cross section of the via (15) is circular, elliptical, elongated strip-like, or polygonal when the via (15) is observed in a direction perpendicular to the first surface (11).

9. 9. The capacitor (1) of claim 1, wherein the first conductive portion (31), the second conductive portion (32), and the third conductive portion (33) comprise at least one of the following materials: nickel, titanium, aluminum, lead, platinum, gold, titanium nitride, tantalum nitride, and copper.

10. 10. The capacitor (1) of any one of claims 1 to 9, wherein the first electrode plate (20) comprises at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride.

11. A method for manufacturing a capacitor (1), comprising the steps of: providing a substrate (10), said substrate (10) having a first surface (11) and a second surface (12) opposite said first surface (11); providing a via (15) on said substrate (10) that extends through said first surface (11) to said second surface (12); providing a first electrode plate (20) on said substrate (10), wherein said first electrode plate (20) is bonded to said first surface (11) of said substrate (10); providing a first conductive portion (31) on the second side (12) of the substrate (10); providing a second conductive portion (32) on a side of the first electrode plate (20) facing the via (15); and providing a third conductive portion (33) on an inner wall (16) of the via (15) for coupling the first conductive portion (31) to the second conductive portion (32). A method comprising:

12. The first electrode plate (20) has a first portion (21) and a second portion (22), and the method further comprises: providing a dielectric material on the first electrode plate (20); and 12. The method of claim 11, comprising removing a portion of the dielectric material that is bonded to the second portion (22) to form a first dielectric layer (40).

13. The method further comprises:

13. The method of claim 12, comprising providing a second electrode plate (50) on the first dielectric layer (40), wherein the second electrode plate (50) is bonded to the first electrode plate (20) by the first dielectric layer (40).

14. providing a wrapping material on the second portion (22) of the first electrode plate (20) and on the second electrode plate (50); and removing a portion of said wrapping material and above said second electrode plate (50) to form a second dielectric layer (60); The method of claim 13 further comprising:

15. 15. The method of any one of claims 12 to 14, wherein the first dielectric layer (40) comprises at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

16. 15. The method of claim 13 or 14, wherein the second electrode plate (50) comprises at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride.

17. 15. The method of claim 14, wherein the second dielectric layer (60) comprises at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

18. 18. The method according to any one of claims 11 to 17, wherein the first conductive portion (31), the second conductive portion (32), and the third conductive portion (33) are integrally formed.

19. 19. The method according to any one of claims 11 to 18, wherein the cross-section of the via (15) is circular, elliptical, elongated strip-like, or polygonal when the via (15) is observed in a direction perpendicular to the first face (11).

20. 20. The method according to any one of claims 11 to 19, wherein the first conductive portion (31), the second conductive portion (32), and the third conductive portion (33) comprise at least one of the following materials: nickel, titanium, aluminum, lead, platinum, gold, titanium nitride, tantalum nitride, and copper.

21. 21. The method of any one of claims 11 to 20, wherein the first electrode plate (20) comprises at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride.

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