Phase change memory material, its preparation method, phase change memory chip, and device

Abstract

The present application relates to the field of data storage technology, in particular to a phase change memory material, its preparation method, phase change memory chip, and device. The phase change memory material is Ti a Sb b Te c D d where a represents the atomic percentage of Ti, b represents the atomic percentage of Sb, c represents the atomic percentage of Te, and d represents the atomic percentage of element D, where a+b+c+d=1, 3%≦a≦45%, and 0.5≦(b:c)≦3, and D is a doping element, where 0≦d≦15%. The phase change memory material has low operating power consumption and low operating delay.

Description

[Technical field]

[0001] This application claims priority to Chinese Patent Application No. 202210356787.X, entitled “PHASE-CHANGE MEMORY MATERIAL, PREPARATION METHOD THEREOF, PHASE-CHANGE MEMORY CHIP, AND DEVICE,” filed with the State Intellectual Property Office of the People's Republic of China on April 6, 2022, the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the field of data storage technology, in particular to phase change memory materials, their preparation methods, phase change memory chips and devices. [Background technology]

[0003] With the development of information technology, memories are required to have low latency and large capacity. Low latency helps to increase data processing speed. Large capacity helps to improve storage density and save the cost of manufacturing memories.

[0004] As a non-volatile memory, phase-change memory (PCM) has high-density data storage capability and fast erase and write speeds, and is used in embedded memory, etc. However, current phase-change memory cannot balance low power consumption and low operation delay, and as a result, it has poor performance. Summary of the Invention

[0005] SUMMARY OF THE DISCLOSURE The embodiments of the present application provide a phase change memory material, its preparation method, phase change memory chip, and device, which reduce the power consumption and operation delay of the phase change memory chip and device.

[0006] According to a first aspect, there is provided a phase change memory material, wherein the phase change memory material comprises a material represented by formula (1): Ti a Sb b Tec D d (1) where a represents the atomic percentage of Ti, b represents the atomic percentage of Sb, c represents the atomic percentage of Te, d represents the atomic percentage of element D, and a+b+c+d=1, 3%≦a≦45%, and 0.5≦(b:c)≦3, D is a doping element, and 0≦d≦15%.

[0007] The phase change memory material provided in this embodiment of the present application is a new Sb-Te based phase change memory material. When SbTe is crystallized, i.e., in a crystalline state, the phase change memory material is in a low resistance state, or when SbTe is amorphous, i.e., in an amorphous state, the phase change memory material is in a high resistance state. Different resistance states of the phase change memory material can represent different information and realize information storage. In addition, information can be read out by measuring the resistance state of the phase change memory material.

[0008] The phase change memory material includes element Ti, and Ti and Te form TiTe nucleation centers. Specifically, the bond strength between TiTe is greater than that between SbTe. During the transformation of SbTe between a crystalline state (i.e., a low resistance state) and an amorphous state (i.e., a high resistance state), the TiTe nucleation centers can maintain a stable structure. When SbTe transforms from a crystalline state (i.e., a low resistance state) to an amorphous state (i.e., a high resistance state), TiTe as a nucleation center can accelerate the transformation of SbTe from a crystalline state to an amorphous state, so that the operation delay can be reduced. Therefore, when the phase change memory material is used in a storage class memory, the storage class memory can have a low delay.

[0009] In addition, the lattice mismatch between the TiTe lattice and the SbTe lattice is 12%, and the phase change memory material contains Ti, which can cause lattice distortion or lattice defects in the phase change memory material, so that the phase change memory material is more easily converted from a crystalline state to an amorphous state, and therefore the power consumption required for converting from a crystalline state to an amorphous state can be reduced.

[0010] In addition, the Ti contained in the phase change memory material can reduce the grain size of the phase change memory material, so that the grain size distribution is more uniform (this can be understood as the smaller the grain size, the smaller the grain size distribution range, and therefore the more uniform the grain size distribution). Therefore, the fatigue life of the phase change memory material can be improved.

[0011] In a possible implementation, the value range of the atomic percentage a of Ti may be 5%≦a≦40%, 10%≦a≦38%, 15%≦a≦30%, or 20%≦a≦35%, etc. More specifically, in one example, a may be specifically 5%. In one example, a may be specifically 8%. In one example, a may be specifically 10%. In one example, a may be specifically 13%. In one example, a may be specifically 15%. In one example, a may be specifically 18%. In one example, a may be specifically 20%. In one example, a may be specifically 25%. In one example, a may be specifically 28%. In one example, a may be specifically 30%. In one example, a may be specifically 32%. In one example, a may be specifically 35%. In one example, a may be specifically 37%. In one example, a may specifically be 40%. In one example, a may specifically be 45%.

[0012] When the value range of the atomic percentage a of Ti is 20%≦a≦35%, the phase change memory material has better performance in operation delay, power consumption, thermal stability, fatigue life, etc.

[0013] In possible implementations, the ratio of the atomic percentage b of Sb to the atomic percentage c of Te can be 0.5≦(b:c)≦1, 0.5≦(b:c)≦2, 1≦(b:c)≦3, or 2≦(b:c)≦3, etc. More specifically, in one example, (b:c) can be specifically 0.5, (2:3), 1, 2, or 3, etc.

[0014] When (b:c) is (2:3), the phase change memory material has better performance in operation delay, power consumption, thermal stability, fatigue life, etc.

[0015] In a possible implementation, the value range of the atomic percentage a of Ti is 20%≦a≦35%, and the ratio of the atomic percentage b of Sb to the atomic percentage c of Te is 2:3.

[0016] In this implementation, the phase change memory material has less operational delay, lower power consumption, higher thermal stability, and higher fatigue life.

[0017] In possible implementations, the atomic percentage d of the doping element D can be 0%≦d≦10%, 0%≦d≦8%, 3%≦d≦10%, or 3%≦d≦8%. More specifically, in one example, the atomic percentage d of the doping element D is 0, i.e., the phase change memory material does not include the doping element D. In one example, d is 1%. In one example, d is 3%. In one example, d is 5%. In one example, d is 8%. In one example, d is 10%. In one example, d is 15%.

[0018] When 3%≦d≦8%, the phase change memory material has less operating delay and higher fatigue life.

[0019] In a possible implementation, the doping element includes one or a combination of at least two of a first non-metallic element, a first metallic element, and a telluride of a first metallic element, where the first non-metallic element is one or a combination of at least two of C, O, N, and Si, and the first metallic element is one or a combination of at least two of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn.

[0020] In this implementation, the doping element is doped into the phase change memory material, so that the thermal stability and fatigue life of the phase change memory material can be improved, and the crystallization speed (specifically, the speed of transformation from a high resistance state to a low resistance state) of the phase change memory material can be further increased, and therefore the operation delay can be reduced.

[0021] According to a second aspect, a method for preparing a phase change memory material is provided, where the method can be used to prepare the phase change memory material provided in the first aspect. The method includes preparing a phase change memory material by a first deposition manner according to the element ratio shown by formula (1), and the first deposition manner belongs to one of chemical vapor deposition CVD, physical vapor deposition PVD, and atomic layer deposition ALD. Ti a Sb b Te c D d (1) It is. a represents the atomic percentage of Ti, b represents the atomic percentage of Sb, c represents the atomic percentage of Te, and d represents the atomic percentage of element D, where a+b+c+d=1, 3%≦a≦45%, and 0.5≦(b:c)≦3, and D is a doping element, where 0≦d≦15%.

[0022] This method can efficiently prepare phase change memory materials, is easy to operate, and is easy to implement industrially.

[0023] In a possible implementation, the first deposition method is a sputtering method in physical vapor deposition, and the step of preparing a phase change memory material in the first deposition method according to the element ratio indicated by formula (1) includes the steps of preparing a first target material according to the atomic percentage indicated by formula (1) and performing sputtering on the first target material to obtain a phase change memory material.

[0024] In this implementation, the alloy target material may be prepared first, and then sputtering is carried out on the alloy target material to obtain phase change memory material. This method is simpler and easier to implement, saves preparation time, and is easy to implement industrially.

[0025] In a possible implementation, the first deposition manner is a sputtering manner in physical vapor deposition, and the step of preparing a phase change memory material in the first deposition manner according to the element ratio indicated by formula (1) includes performing co-sputtering on a Ti single element target material and a SbTe alloy target material to obtain a phase change memory material, and the sputtering powers of the different single element target materials are adjusted according to the atomic percentage indicated by formula (1) in the co-sputtering process.

[0026] In this implementation, simultaneous sputtering may be performed on single element target material and alloy target material to obtain phase change memory material. This method is simple and easy to implement, saves preparation time, and is easy to implement industrially.

[0027] According to a third aspect, there is provided a phase change memory chip including a plurality of memory cells forming a memory cell array, each memory cell including a phase change layer, an electrode provided on one side of the phase change layer, and an electrode provided on the other side of the phase change layer, the phase change layer being made of the phase change memory material provided in the first aspect.

[0028] Phase change memory chips have the advantages of low operation delay, low power consumption, high thermal stability, and high fatigue life.

[0029] In a possible implementation, each memory cell further includes a buffer layer in contact with the phase change layer, the buffer layer being made of one of carbon, a third metal, a nitride of the third metal, and a telluride of a fourth metal, the third metal being one or a combination of at least two of W, Ta, and Ti, and the fourth metal being one or a combination of at least two of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, and Sn.

[0030] In this implementation, a buffer layer is introduced in contact with the phase change layer, so that the performance of the phase change layer and the memory chip can be further improved. Specifically, when the material of the buffer layer is carbon, the buffer layer can improve the thermal insulation effect of the phase change layer, reduce the operation power consumption of the phase change memory chip, prevent element diffusion in the phase change layer, and improve the adhesion effect between the phase change layer and the electrode. When the material of the buffer layer is a telluride of a fourth metal, such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn, the buffer layer can be used as a crystallization template of the phase change memory material, so that the speed of the transformation of the phase change memory material from an amorphous state to a crystalline state can be accelerated. Thus, the operation delay of the phase change memory chip can be reduced, the heating efficiency of the phase change memory chip can be improved, and the operation power consumption of the phase change memory chip can be reduced. When the material of the buffer layer is a third metal such as W, Ta, or Ti, the buffer layer can prevent element diffusion in the phase change memory material, and can also improve the adhesion effect between the phase change layer and the electrode. When the material of the buffer layer is a nitride of a third metal, the buffer layer can improve the adhesion effect between the phase change layer and the electrode, improve the heating efficiency of the phase change memory material, reduce the resistance drift, repair the voids at the interface of the phase change memory material, improve the adhesion effect between the phase change layer and the electrode, etc.

[0031] In a possible implementation, a buffer layer is provided between the phase change layer and the electrode. 、The phase change layer has a groove and the buffer layer is disposed within the groove of the phase change layer, or the buffer layer has a groove and the phase change layer is disposed within the groove of the buffer layer.

[0032] In this implementation, the phase change layer and the buffer layer may be contacted in multiple ways, so that the phase change memory chip can be flexibly implemented and is easy to prepare.

[0033] In a possible implementation, each memory cell further includes at least one phase change layer and at least one chalcogenide layer, both of which are disposed between a first electrode and a second electrode, and the at least one phase change layer and the at least one chalcogenide layer are stacked alternately.

[0034] In this implementation, the phase change layer and the chalcogenide layer are alternately stacked, so that more interfaces can be introduced into the phase change memory material in the phase change memory chip, and the interfaces can reduce heat conduction. Therefore, the operating power consumption of the phase change memory chip is reduced, and the fatigue life of the phase change memory chip is improved. In addition, the chalcogenide has good thermal insulation performance, which can reduce the operating power consumption of the phase change memory chip and improve the fatigue life of the phase change memory chip.

[0035] In a possible implementation, the lattice coefficient of the chalcogenide layer is smaller than the lattice coefficient of SbTe.

[0036] In this implementation, a material with a lattice coefficient smaller than that of SbTe, such as TiTe2, can be used as the material of the chalcogenide layer 115. This can prevent element diffusion in the phase change layer and improve the fatigue life of the phase change layer, in other words, improve the fatigue life of the phase change memory chip.

[0037] According to a fourth aspect, there is provided a storage device, comprising a controller and a phase change memory chip as provided in the third aspect, the phase change memory chip configured to store data, and the controller configured to write data to or read data from the memory chip.

[0038] According to a fifth aspect, there is provided an electronic device comprising a processor and a storage device as provided in the fourth aspect, wherein the storage device is configured to store data and the processor is configured to write data to or read data from the storage device.

[0039] The phase change memory material and the phase change memory chip provided in the embodiments of the present application have low operation delay. When the phase change memory material and the phase change memory chip are used in a storage class memory, the storage class memory has low delay, so that the operation delay of the storage device and the electronic device in which the phase change memory material and the phase change memory chip are provided can be further reduced. In addition, the phase change memory material and the phase change memory chip further have low operation power consumption, so that the power consumption of the storage device and the electronic device in which the phase change memory material and the phase change memory chip are provided can be reduced. Furthermore, the phase change memory material and the phase change memory chip have a high fatigue life, so that the service life of the storage device and the electronic device in which the phase change memory material and the phase change memory chip are provided can be improved. [Brief description of the drawings]

[0040] [Figure 1A] 1 is a diagram of a structure of a phase change memory cell according to an embodiment of the present application. [Figure 1B] FIG. 2 is a diagram of another phase change memory cell structure according to an embodiment of the present application. [Diagram 2]1 is a diagram of a structure of a phase change memory cell array according to one embodiment of the present application. [Figure 3A] FIG. 2 is a diagram of the low resistance state of a germanium-antimony-tellurium based phase change memory material. [Figure 3B] FIG. 2 is a diagram of the high resistance state of a germanium-antimony-tellurium based phase change memory material. [Figure 4A] FIG. 2 is a diagram of a low resistance state of a phase change memory material according to an embodiment of the present application. [Figure 4B] FIG. 2 is a diagram of a high resistance state of a phase change memory material according to an embodiment of the present application. [Figure 5A] FIG. 2 is a representation of grain size of a phase change memory material according to an embodiment of the present application. [Figure 5B] FIG. 2 is a representation of grain size of a phase change memory material according to an embodiment of the present application. [Figure 6] FIG. 2 is a representation of a resistance-temperature curve of a phase change memory material according to an embodiment of the present application. [Figure 7A] 1 is a diagram of a structure of a phase change memory cell array according to one embodiment of the present application. [Figure 7B] 1 is a diagram of a structure of a phase change memory cell array according to one embodiment of the present application. [Figure 7C] 1 is a diagram of a structure of a phase change memory cell array according to one embodiment of the present application. [Figure 7D] 1 is a diagram of a structure of a phase change memory cell array according to one embodiment of the present application. [Figure 7E] 1 is a diagram of a structure of a phase change memory cell array according to one embodiment of the present application. [Figure 8A] 1 is a diagram of a structure of a phase change memory cell array according to one embodiment of the present application. [Figure 8B] 1 is a diagram of a structure of a phase change memory cell array according to one embodiment of the present application. [Figure 8C] 1 is a diagram of a structure of a phase change memory cell array according to one embodiment of the present application. [Figure 8D] 1 is a diagram of a structure of a phase change memory cell array according to one embodiment of the present application. [Figure 9] FIG. 2 is a diagram of the structure of a storage device according to one embodiment of the present application. [Figure 10] FIG. 1 is a diagram of a structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] The following describes the technical solutions in the embodiments of the present application with reference to the accompanying drawings. It is obvious that the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0042] In this specification, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0043] In describing the embodiments of the present application, it can be understood that words such as "example," "for example," or "exemplary" are used to denote giving an example, illustration, or explanation. Any embodiment or way of design described in the embodiments of the present application as "example," "for example," or "exemplary" should not be construed as being preferred or having more advantages over another embodiment or way of design. Rather, the use of words such as "example," "for example," or "exemplary" is intended to present the relevant concept in a concrete manner.

[0044] The term "and / or" in the description of the embodiments of the present application describes only the relational relationship between related objects and indicates that there are three possible relations. For example, A and / or B may indicate the following three cases: only A is present, only B is present, and both A and B are present. Also, unless otherwise indicated, the term "plurality" means two or more. For example, a plurality of systems means two or more systems, and a plurality of terminals means two or more terminals.

[0045] A phase change memory chip is a chip that stores data by using the difference in conductivity exhibited by a phase change memory material during the transformation of the phase change memory material between a crystalline state and an amorphous state. Specifically, in the crystalline state, the atoms in the phase change memory material are arranged in an orderly manner, so that the phase change memory material has long-distance atomic energy levels and a high free electron density, and therefore the phase change memory material has a low resistivity. Thus, the crystalline state may be referred to as a low resistance state. In the amorphous state, the atoms in the phase change memory material are arranged in a disordered manner, so that the phase change memory material has short-distance atomic energy levels and a low free electron density, and therefore the phase change memory material has a high resistivity. Thus, the amorphous state may be referred to as a high resistance state. The phase change memory material in the low resistance state may be set to correspond to one of "0" and "1", and the phase change memory material in the high resistance state may be set to correspond to the other of "0" and "1".

[0046] When a certain pulse voltage is applied to the phase change memory material, the phase change memory material can be converted between a high resistance state and a low resistance state. Specifically, a high and narrow electric pulse (which can be called a reset pulse) can be applied to the phase change memory chip, so that the phase change memory material is converted from a low resistance state to a high resistance state. A low and wide electric pulse (which can be called a set pulse) can be applied to the phase change memory chip, so that the phase change memory material is converted from a high resistance state to a low resistance state. Thus, a write operation to the phase change memory material can be realized.

[0047] In addition, the high and low resistance states of the phase change memory material correspond to different bit values, respectively. In this way, a low read voltage (a voltage that cannot cause the phase change memory material to convert between the high and low resistance states) can be applied to the phase change memory material to read the resistance value of the phase change memory material and achieve a read operation.

[0048] FIG. 1A illustrates an implementation of a phase change memory cell 110 and a corresponding selector 120. A phase change memory cell is a memory cell that is in a phase change memory chip and is configured to store one bit value ("0" or "1"). As shown in FIG. 1A, the phase change memory cell 110 may include an electrode 111, an electrode 112, and a phase change layer 113 disposed between the electrodes 111 and 112. The phase change layer 113 is made of a phase change memory material. A voltage or current is applied to the phase change layer 113 through the electrodes 111 and 112 to achieve a write operation or a read operation.

[0049] During writing, a current or voltage is applied to the word line 130, so that the word line 130 is at a high potential and the transistor 120 is conductive. Then, a current or voltage is applied to the bit line 140, so that the phase change layer of the phase change memory cell is converted between a high resistance state and a low resistance state to perform the write operation. During reading, the column selection circuit applies a small preset potential to the bit line 140 (where the preset potential does not change the resistance state of the phase change memory cell). As explained above, the word line 130 is at a high potential. This affects the potential on the bit line 140, and the magnitude of the effect is related to the magnitude of the resistance of the phase change memory cell. The effect of the word line 130 on the potential on the bit line 140 is equivalent to the phase change memory cell outputting a signal, and the result of the effect (the potential on the bit line 140 after being affected by the word line 130) is equivalent to the output signal. The result of the effect is compared to a reference potential to determine the resistance state of the phase change memory cell and, based on the resistance state, to determine the data stored in the phase change memory cell. The column selection circuitry is described below and will not be described in detail here.

[0050] 1B shows another implementation of a phase change memory cell 110. The phase change memory cell 110 may include, in sequence adjacent to each other, an electrode 111, a phase change layer 113, an electrode 112, a selection layer 116 (selection layer 116 may also be referred to as a selection tube 116), and an electrode 117. The phase change layer 113 may include a phase change memory material. A voltage or current may be applied to the phase change layer 113 between the electrodes 111 and 112 to achieve a write or read operation.

[0051] Specifically, the electrode 112 may be connected to the word line 130 via the selective layer 116 and the electrode 117. The voltage difference across the selective layer 116 is the threshold switching voltage V th , the selection layer 116 is made conductive and the voltage across the selection layer 116 decreases, so that more voltage is applied across the phase-change layer 113. Thus, a write or read operation can be realized.

[0052] In some embodiments, the material of the selective layer 116 is an ovonic threshold switching (OTS) material that includes Ge, Se, and As. The OTS material forming the selective layer 116 may be doped with at least one of Si, N, and S. In some embodiments, the material of the selective layer 116 is a GeAsSe alloy. In some embodiments, the material of the selective layer 116 is a GeAsSe alloy doped with at least one of Si, N, C, As, Se, etc.

[0053] In addition, materials of phase change layer 113, electrode 111, electrode 112, electrode 116, and electrode 117 are described below. In the following description, when no particular distinction is made, electrode 111, electrode 112, electrode 116, and electrode 117 may be referred to as electrodes for short. FIG. 2 shows a phase change memory chip including a phase change memory cell array and peripheral circuits. The phase change memory cell array includes a plurality of phase change memory cells arranged in a cross manner to form a high-density memory array. Phase change memory cell 110 may be one phase change memory cell in the phase change memory cell array. Phase change memory cell 110 may use the structure shown in FIG. 1A or the structure shown in FIG. 1B. In addition, when the phase change memory cell in the phase change memory cell array is specifically the structure shown in FIG. 1A, the phase change memory cell array further includes a selection transistor (not shown in FIG. 2) of the phase change memory cell. For a phase change memory cell, when the bit line and the word line are selected simultaneously and the selector is in a conductive state, the phase change memory cell is in a selected state, otherwise the phase change memory cell is in a non-selected state. A processor (not shown) may select the word line 130 through a row selection circuit, select the bit line 140 through a column selection circuit, and control the selection transistor 120 to be conductive to select the phase change memory cell 110. A read / write (R / W) circuit may receive instructions from the processor and control the row selection circuit and the column selection circuit based on the instructions to apply voltages to the phase change memory cell 110 through the word line 130 and the bit line 140 to perform a read operation or a write operation. A drive circuit VS1 may apply a voltage to the phase change memory cell 110 through the word line 130 under the control of the row selection circuit, and a drive circuit VS2 may apply a voltage to the phase change memory cell 110 through the bit line 140 under the control of the column selection circuit.

[0054] The above examples describe the structures of the phase change memory chip and the phase change memory cell provided in the embodiments of the present application. The following describes the phase change memory material.

[0055] The performance of phase change memory materials, such as phase change power consumption (specifically, the energy consumption required for conversion between high and low resistance states), fatigue life, phase change speed (the time required for conversion between high and low resistance states), and thermal stability, have an important impact on the operation delay, life, and reliability of phase change memory chips. Conventional germanium-antimony-tellurium (GeSbTe, GST)-based phase change memory materials have good thermal stability and good fatigue life. However, as shown in FIG. 3A and FIG. 3B, the conversion between high and low resistance states involves the breaking and recombination of GeTe bonds, which delays the phase change process (specifically, the speed of conversion between high and low resistance states is low). As a result, the operation delay is high (100 ns level). This cannot fully meet the requirements for low delay of storage-class memory (SCM). Therefore, even if phase change memory materials are used in storage-class memory, the delay of storage-class memory is large.

[0056] One embodiment of the present application provides a Ti-doped SbTe phase change memory material. Ti doping improves the thermal stability of the SbTe phase change system, reduces the phase change power consumption, and improves the fatigue life. In addition, the presence of TiTe nucleation centers can accelerate the crystallization and thus reduce the operation delay. The chemical general formula of the Ti-doped SbTe phase change memory material is Ti a Sb b Te c D da represents the atomic percentage of the chemical element titanium Ti. Specifically, a represents the proportion of the chemical element titanium Ti in the total amount of all atoms in the phase change memory material. b represents the atomic percentage of the chemical element antimony Sb. Specifically, b represents the proportion of the chemical element antimony Sb in the total amount of all atoms in the phase change memory material. c represents the atomic percentage of the chemical element tellurium Te. Specifically, c represents the proportion of the chemical element tellurium Te in the total amount of all atoms in the phase change memory material. d represents the atomic percentage of the doping element D. Specifically, d represents the proportion of the doping element D in the total amount of all atoms in the phase change memory material. In short, a+b+c+d=1.

[0057] In the phase change memory material provided in this embodiment of the present application, 3%≦a≦45%. Specifically, the proportion of Ti in the total amount of all atoms in the phase change memory material is 3% or more and 45% or less. In addition, 0.5≦(b:c)≦3. Specifically, in the phase change memory material, the ratio of the atomic weight of Sb to the atomic weight of Te is 0.5 or more and 3 or less. 0≦d≦15%. Specifically, the proportion of the doping element D in the total amount of all atoms in the phase change memory material is 15% or less. In other words, the phase change memory material may not contain a doping element or may contain a doping element, and the atomic percentage of the doping element does not exceed 15%.

[0058] The phase change memory material provided in this embodiment of the present application is a new Sb-Te based phase change memory material. When SbTe is crystallized, i.e., in a crystalline state, the phase change memory material is in a low resistance state, or when SbTe is amorphous, i.e., in an amorphous state, the phase change memory material is in a high resistance state. Different resistance states of the phase change memory material can represent different information and realize information storage. In addition, information can be read out by measuring the resistance state of the phase change memory material.

[0059] Please refer to FIG. 4A and FIG. 4B. In the phase change memory material provided in one embodiment of the present application, Ti and Te form TiTe nucleation centers, and TiTe has stronger bond strength than SbTe. When SbTe is transformed from a crystalline state (i.e., a low resistance state) to an amorphous state (i.e., a high resistance state), the TiTe nucleation centers can maintain a stable structure. Therefore, TiTe nucleation centers exist in both the low resistance state and the high resistance state of the phase change memory material. When the phase change memory material is transformed from a high resistance state (i.e., an amorphous state) to a low resistance state (i.e., a crystalline state), the TiTe nucleation centers as nucleation centers for recrystallization can increase the crystallization speed of SbTe, so that the operation delay is reduced. Crystallization is a process in which the atomic structure in the material is changed from disorder to an ordered arrangement, that is, the process of transforming the amorphous state to a crystalline state.

[0060] In addition, the lattice mismatch between the lattice of TiTe and the lattice of SbTe is 12%, and Ti is introduced into the phase change memory material provided in this embodiment of the present application, which can cause lattice distortion or lattice defects of TiSbTe, so that the phase change memory material can be more easily converted from a crystalline state to an amorphous state, and therefore the power consumption required for the conversion from a crystalline state to an amorphous state can be reduced.

[0061] In addition, based on experimental tests, the Ti contained in the phase change memory material provided in this embodiment of the present application can reduce the grain size and therefore improve the fatigue life.

[0062] In addition, based on experimental tests, the Ti contained in the phase change memory material provided in this embodiment of the present application can improve the thermal stability of the phase change memory material in the low resistance state and the high resistance state.

[0063] In some embodiments, the value range of Ti atomic percentage a can be 5%≦a≦40%, 10%≦a≦38%, 15%≦a≦30%, or 20%≦a≦35%, etc. Details are not listed here one by one. When the value range of Ti atomic percentage a is 20%≦a≦35%, the phase change memory material has better performance in operation delay, power consumption, thermal stability, fatigue life, etc.

[0064] In one example, a may specifically be 5%. In one example, a may specifically be 8%. In one example, a may specifically be 10%. In one example, a may specifically be 13%. In one example, a may specifically be 15%. In one example, a may specifically be 18%. In one example, a may specifically be 20%. In one example, a may specifically be 25%. In one example, a may specifically be 28%. In one example, a may specifically be 30%. In one example, a may specifically be 32%. In one example, a may specifically be 35%. In one example, a may specifically be 37%. In one example, a may specifically be 40%. In one example, a may specifically be 45%.

[0065] In some embodiments, the ratio of the atomic percentage b of Sb to the atomic percentage c of Te, i.e., (b:c), can be 0.5≦(b:c)≦1, 0.5≦(b:c)≦2, 1≦(b:c)≦3, or 2≦(b:c)≦3, etc. The details will not be recited here one by one.

[0066] In one example, (b:c) can be specifically 0.5, (2:3), 1, 2 or 3, etc. Details are not listed here one by one. When (b:c) is (2:3), the phase change memory material has better performance in operation delay, power consumption, thermal stability, fatigue life, etc.

[0067] In some embodiments, the value range of the atomic percentage a of Ti is 20%≦a≦35%, and the ratio of the atomic percentage b of Sb to the atomic percentage c of Te is (2:3), in which case the phase change memory material has less operation delay, lower power consumption, higher thermal stability, and higher fatigue life.

[0068] In some embodiments, the doping element D may be one or a combination of at least two of non-metallic elements, specifically C, O, N, and Si. In some embodiments, the doping element D may be one or a combination of at least two of metallic elements, specifically Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn. In some embodiments, the doping element D may be one or a combination of at least two of tellurides of metallic elements, specifically Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn. In some embodiments, the doping element D may be one or a combination of at least two of non-metallic elements, specifically C, O, N, and Si, metallic elements, specifically Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn, and tellurides of metallic elements.

[0069] Doping element D is added to phase change memory material, so that the thermal stability and fatigue life of phase change memory material can be improved, and the crystallization speed (specifically, the speed of transformation from high resistance state to low resistance state) of phase change memory material can be further increased. Therefore, the operation delay is reduced.

[0070] In some embodiments, the atomic percentage d of the doping element D can be 0%≦d≦10%, 0%≦d≦8%, 3%≦d≦10%, or 3%≦d≦8%. When 3%≦d≦8%, the phase change memory material has less operational delay and higher fatigue life.

[0071] In one example, the atomic percentage d of the doping element D is 0, i.e., the phase change memory material does not contain the doping element D. In one example, d is 1%. In one example, d is 3%. In one example, d is 5%. In one example, d is 8%. In one example, d is 10%. In one example, d is 15%.

[0072] The above examples describe the composition of the phase change memory material. Hereinafter, the preparation solution of the phase change memory material will be described using examples.

[0073] In an embodiment of the present application, the phase change memory material is Ti in a material deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). a Sb b Te c D d The substrate may be an electrode. 、 It may be a buffer layer, as described below, a chalcogenide layer, as described below, or another particular substrate, not described in detail here.

[0074] In some embodiments, the phase change memory material is prepared on the substrate by using Ti single element target material and SbTe alloy target material. In the sputtering process, different deposition rates can be obtained by controlling the power of different target materials, and phase change memory materials with corresponding composition distribution ratios can be obtained.

[0075] In some embodiments, the phase change memory material can be prepared on the substrate by sputtering a single target material in a sputtering manner (e.g., magnetron sputtering) in physical vapor deposition. Specifically, when the doping element D is not included or when the doping element D1 is not N and / or O, the sputtering can be performed using a Ti single element target material, a Sb single element target material, a Te single element target material, and a doping element D (when the phase change material includes the doping element D) single element target material to prepare the phase change memory material on the substrate. When the doping element D1 is N, the sputtering can be performed using a titanium nitride alloy target material, a Sb single element target material, and a Te single element target material to prepare the phase change memory material on the substrate. When the doping element D1 is O, the sputtering can be performed using a titanium oxide alloy target material, a Sb single element target material, and a Te single element target material to prepare the phase change memory material on the substrate. In the sputtering process, different deposition rates can be obtained by controlling the power of different target materials to obtain phase change memory materials with corresponding composition distribution ratios.

[0076] In some embodiments, first, Ti a Sb b Te c D d The alloy can be prepared (e.g., smelted). Then, sputtering is performed to remove Ti a Sb b Te c D d An alloy is used to prepare a phase change memory material on the substrate.

[0077] The preparation process of the phase change memory material in a specific embodiment is described below.

[0078] EMBODIMENT 1 The elemental composition is Ti8Sb 36.8 Te 55.2 A phase change memory material is prepared as follows.

[0079] A Ti single element target material and an SbTe alloy target material, each having an atomic percentage purity of 99.99% or more, are placed at different target material positions in the sputtering cavity. The ratio of Sb atoms to Te atoms in the SbTe alloy is 2:3. A substrate is placed on a sample stage in the sputtering cavity. Sputtering power is applied to the Ti single element target material and the SbTe alloy target material to generate a sputtering glow. The sputtering power applied to the Ti single element target material is 10 W, and the sputtering power applied to the SbTe alloy target material is 7 W. The argon flow rate is 35 sccm in the sputtering process. In this way, a Ti8Sb 36.8 Te 55.2 A phase change memory material, which is

[0080] EMBODIMENT 2 The elemental composition is Ti 22 Sb 31.2 Te 46.8 A phase change memory material is prepared as follows.

[0081] A Ti single element target material and an SbTe alloy target material, each having an atomic percentage purity of 99.99% or more, are placed at different target material positions in the sputtering cavity. The ratio of Sb atoms to Te atoms in the SbTe alloy is 2:3. A substrate is placed on a sample stage in the sputtering cavity. Sputtering power is applied to the Ti single element target material and the SbTe alloy target material to generate a sputtering glow. The sputtering power applied to the Ti single element target material is 30 W, and the sputtering power applied to the SbTe alloy target material is 7 W. The argon flow rate is 35 sccm in the sputtering process. In this way, a Ti single element target material having an elemental composition of 10 ... 22 Sb 31.2 Te 46.8A phase change memory material, which is

[0082] EMBODIMENT 3 The elemental composition is Ti 28 Sb 28.8 Te 43.2 A phase change memory material is prepared as follows.

[0083] A Ti single element target material and an SbTe alloy target material, each having an atomic percentage purity of 99.99% or more, are placed at different target material positions in the sputtering cavity. The ratio of Sb atoms to Te atoms in the SbTe alloy is 2:3. A substrate is placed on a sample stage in the sputtering cavity. Sputtering power is applied to the Ti single element target material and the SbTe alloy target material to generate a sputtering glow. The sputtering power applied to the Ti single element target material is 40 W, and the sputtering power applied to the SbTe alloy target material is 7 W. The argon flow rate is 35 sccm in the sputtering process. In this way, a Ti single element target material having an elemental composition of 10 ... 22 Sb 31.2 Te 46.8 A phase change memory material, which is

[0084] EMBODIMENT 4 The elemental composition is Ti3Sb 38.8 Te 58.2 A phase change memory material is prepared, which is: For specific preparation process, please refer to the description in embodiment 1. Details are not described again here.

[0085] EMBODIMENT 5 The elemental composition is Ti 45 Sb 18.8 Te 36.2 A phase change memory material is prepared, which is: For specific preparation process, please refer to the description in embodiment 1. Details are not described again here.

[0086] EMBODIMENT 6 The elemental composition is Ti 40 Sb 23.8 Te 36.2 A phase change memory material is prepared, which is: For specific preparation process, please refer to the description in embodiment 1. Details are not described again here.

[0087] EMBODIMENT 7 The elemental composition is Ti 21 Sb 29.6 Te 44.4 A phase change memory material is prepared, which is C5. The elemental composition is Ti 21 Sb 29.6 Te 44.4 The alloy is refined to be C5. 21 Sb 29.6 Te 44.4 The C5 alloy is placed at the target material position in the sputtering cavity. The substrate is placed on the sample stage in the sputtering cavity. The sputtering power is set to Ti 21 Sb 29.6 Te 44.4 C5 alloy to generate a sputtering glow. 21 Sb 29.6 Te 44.4 The C5 alloy was sputtered onto the substrate, and Ti 21 Sb 29.6 Te 44.4 Prepare C5 phase change memory material.

[0088] EMBODIMENT 8 The elemental composition is Ti 25.7 Sb 27.7 Te 41.6 A phase change memory material is prepared, which is C5. The elemental composition is Ti 25.7 Sb 27.7 Te 41.6 The alloy is refined to be C5. 25.7 Sb 27.7 Te 41.6 The C5 alloy is placed at the target material position in the sputtering cavity. The substrate is placed on the sample stage in the sputtering cavity. The sputtering power is set to Ti 25.7 Sb 27.7 Te41.6 C5 alloy to generate a sputtering glow. 25.7 Sb 27.7 Te 41.6 The C5 alloy was sputtered onto the substrate, and Ti 25.7 Sb 27.7 Te 41.6 Prepare C5 phase change memory material.

[0089] EMBODIMENT 9 The elemental composition is Ti 17 Sb 31.2 Te 46.8 A phase change memory material with elemental composition of TiO5 is prepared. 17 Sb 31.2 Te 46.8 The alloy is refined to be O5. 17 Sb 31.2 Te 46.8 The O5 alloy is placed at the target material position in the sputtering cavity. The substrate is placed on the sample stage in the sputtering cavity. The sputtering power is set to Ti 17 Sb 31.2 Te 46.8 O5 alloy to produce a sputtering glow. 17 Sb 31.2 Te 46.8 The O5 alloy was sputtered onto the substrate, 17 Sb 31.2 Te 46.8 Prepare O5 phase change memory material.

[0090] EMBODIMENT 10 The elemental composition is Ti 14 Sb 31.2 Te 46.8 A phase change memory material is prepared, which is Si8. The elemental composition is Ti 14 Sb 31.2 Te 46.8 The alloy is refined to be Si8. 14 Sb 31.2 Te 46.8 The Si8 alloy is placed at the target material position in the sputtering cavity. The substrate is placed on the sample stage in the sputtering cavity. The sputtering power is set to Ti14 Sb 31.2 Te 46.8 The Si alloy is applied to generate a sputtering glow. 14 Sb 31.2 Te 46.8 The Si8 alloy is sputtered onto the substrate, and Ti 14 Sb 31.2 Te 46.8 Prepare Si8 phase change memory material.

[0091] The above examples describe the preparation solutions of the phase change memory materials provided in the embodiments of the present application. The following describes data related to the fatigue life and thermal stability of the phase change memory materials provided in the embodiments of the present application.

[0092] The phase change memory material prepared in embodiment 1 and the phase change memory material prepared in embodiment 2 are observed separately using a transmission electron microscope, and the results are shown in FIG. 5A and FIG. 5B, respectively. It can be seen that when the atomic percentage of Ti in the phase change memory material is 8%, some grain sizes are tens of nanometers. When the atomic percentage of Ti in the phase change memory material increases to 28%, the grain size can be reduced to less than 10 nm. It shows that Ti can reduce the grain size in the phase change memory material, so that the grain size distribution is more uniform (this can be seen as the smaller the grain size, the smaller the grain size distribution range, and the more uniform the grain size distribution). Therefore, the short fatigue life of the phase change memory material caused by the non-uniform grain size can be reduced or prevented. That is, when the atomic percentage of Ti in the phase change memory material is high (for example, 28%), the fatigue life of the phase change memory material is high.

[0093] The resistance of the phase change material prepared in embodiment 1 is measured at different temperatures. The results are shown by curves 601a and 601b in Figure 6. Curve 601a is the temperature increase curve, and curve 601b is the temperature decrease curve.

[0094] The resistance of the phase change material prepared in embodiment 2 is measured at different temperatures. The results are shown by curve 602a and curve 602b in Figure 6. Curve 602a is the temperature increase curve, and curve 602b is the temperature decrease curve.

[0095] The resistance of the phase change material prepared in embodiment 3 is measured at different temperatures. The results are shown by curve 603a and curve 603b in Figure 6. Curve 603a is the temperature increase curve, and curve 603b is the temperature decrease curve.

[0096] The temperature drop curve shows the change in resistance during the temperature drop process. The temperature rise curve shows the change in resistance during the temperature rise process. As shown in Fig. 6, in the temperature rise process of the phase change memory material prepared in the embodiment of the present application, the decrease in resistance indicates that the phase change memory material is crystallizing. In the temperature drop process of the phase change memory material, the resistance of the phase change memory material is basically unchanged, indicating that the crystallization is completed.

[0097] In addition, it can be seen from FIG. 6 that when Ti concentration increases, the initial resistance of phase change memory material decreases and the crystallization temperature increases. The abscissa of the position where the resistance decreases the fastest is the crystallization temperature. Specifically, the crystallization temperature of the phase change material prepared in embodiment 1 is about 210° C., the crystallization temperature of the phase change material prepared in embodiment 2 is about 240° C., and the crystallization temperature of the phase change material prepared in embodiment 3 is about 260° C. In addition, the initial resistance is the resistance corresponding to the minimum temperature on each curve in FIG. 6.

[0098] It can be learned from Figure 6 that in the embodiment of the present application, Ti is added to the phase change memory material, so that the crystallization temperature of the phase change memory material is increased, that is, the thermal stability of the phase change memory material is improved.

[0099] The above describes the element composition, preparation method and performance of the phase change memory material provided in the embodiment of the present application.The following describes the phase change memory chip formed by the phase change memory material provided in the embodiment of the present application.

[0100] The phase change memory chip provided in this embodiment of the present application can include a phase change memory cell memory array and a peripheral circuit. For details, please refer to the above description of the embodiment shown in Figure 2. For details, they will not be described again here.

[0101] The phase change memory cell array may include a plurality of phase change memory cells. In some embodiments, the structure of the phase change memory cell may be implemented with respect to the structure shown in FIG. 1A. In some embodiments, the structure of the phase change memory cell may be implemented with respect to the structure shown in FIG. 1B. Please refer to FIG. 1A or FIG. 1B again. The phase change layer 113 in the phase change memory cell 110 may be a phase change memory material provided in the embodiment of the present application. The material of the electrode may be a metal material, a non-metal material, a metal nitride, etc. More specifically, the material of the electrode 1 may be one or a combination of at least two of tungsten (W), carbon (C), tantalum Ta, titanium nitride (TiN), tantalum nitride (TaN), etc. The material of the electrode is not specifically limited in this embodiment of the present application.

[0102] In embodiment a, the phase change memory cell 110 may further include a buffer layer 114. The buffer layer 114 is in contact with the phase change layer 113 and is disposed between the electrode 111 and the electrode 112. In an embodiment, the material of the buffer layer 114 may be a non-metal, such as carbon (C). 。In an embodiment, the material of the buffer layer 114 can be a metal, such as W, Ta, or Ti. In an embodiment, the material of the buffer layer 114 can be a metal nitride, such as TiN or TaN. In an embodiment, the material of the buffer layer 114 can be a telluride of a metal, such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn.

[0103] A buffer layer 114 contacting the phase change layer 113 is introduced into the phase change memory cell 110, so that the performance of the phase change layer 113 can be further improved. Specifically, when the material of the buffer layer 114 is a nonmetal such as carbon (C), the buffer layer 114 can improve the thermal insulation effect of the phase change layer 113, reduce the operation power consumption of the phase change memory cell, prevent element diffusion in the phase change layer 113, and improve the adhesion effect between the phase change layer and the electrode. When the material of the buffer layer 114 is a metal telluride such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn, the buffer layer 114 can be used as a crystallization template of the phase change memory material, so that the conversion speed of the phase change memory material from an amorphous state to a crystalline state can be accelerated. Therefore, the operation delay of the phase change memory operating cell 110 can be reduced, the heating efficiency of the phase change memory cell 110 can be improved, and the operation power consumption of the phase change memory cell 110 can be reduced. When the material of the buffer layer 114 is a metal such as W or Ta, the buffer layer 114 can prevent element diffusion in the phase change memory material, and can also improve the adhesion effect between the phase change layer and the electrode. When the material of the buffer layer 114 is a metal nitride, the buffer layer 114 can improve the adhesion effect between the phase change layer and the electrode, improve the heating efficiency of the phase change memory material, reduce the resistance drift, repair the voids at the interface of the phase change memory material, improve the adhesion effect between the phase change layer and the electrode, etc.

[0104] The above describes the material and function of the buffer layer 114. Hereinafter, the positional relationship between the buffer layer 114 and the phase-change layer 113 will be described using an example.

[0105] In an example of embodiment a, referring to FIG. 7A, the buffer layer 114 contacts the phase change layer 113, and the buffer layer 114 is disposed between the phase change layer 113 and the electrode 111.

[0106] In another example of embodiment a, referring to FIG. 7B, the buffer layer 114 contacts the phase change layer 113, and the buffer layer 114 is disposed between the phase change layer 113 and the electrode 112.

[0107] In another example of embodiment a, referring to FIG. 7C, a phase change memory cell 110 includes two buffer layers 114, each of which contacts a phase change layer 113. One buffer layer 114 is provided between the phase change layer 113 and the electrode 111, and the other buffer layer 114 is provided between the phase change layer 113 and the electrode 112. The materials of the two buffer layers 114 may be the same or different. For example, the materials of the two buffer layers 114 are both nonmetals such as carbon (C), metals such as W or Ta, metal nitrides such as TiN or TaN, or metal tellurides such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn. For example, one material of the two buffer layers 114 is a non-metal, such as carbon (C), the other material of the buffer layer 114 is a non-metal, such as carbon (C), the one material of the buffer layer 114 is a metal nitride, such as TiN or TaN, the other material of the buffer layer 114 is a metal telluride, such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn. Details are not listed here one by one. The materials of the two buffer layers 114 are different, so that the phase change memory cell 110 can have the advantages corresponding to the two materials.

[0108] In another example of embodiment a, referring to FIG. 7D, phase change layer 113 has a groove, and buffer layer 114 is disposed in the groove of phase change layer 113 and contacts phase change layer 113. That is, phase change layer 113 surrounds buffer layer 114.

[0109] In another example of embodiment a, referring to FIG. 7E, the buffer layer 114 has a groove, and the phase change layer 113 is disposed in the groove of the buffer layer 114 and contacts the buffer layer 114. That is, the buffer layer 114 surrounds the phase change layer 113.

[0110] Although the above describes the positional relationship between the phase change layer 113 and the buffer layer 114 using the structures shown in Figures 7A to 7E as examples, the examples are not exhaustive. In other embodiments, the phase change layer 113 and the buffer layer 114 may alternatively have other positional relationships. The details are not listed here one by one.

[0111] In embodiment b, the phase change memory cell 110 may further include at least one chalcogenide layer 115 and at least one phase change layer 113. The at least one phase change layer 113 and the at least one chalcogenide layer 115 are alternately stacked and disposed together between the electrode 111 and the electrode 112.

[0112] In an example of embodiment b, the material of the chalcogenide layer 115 is a metal sulfide, for example, GeS. x It is possible.

[0113] In another example of embodiment b, the material of the chalcogenide layer 115 is a metal Te compound, for example, TiTe2, Hf x Te y , or Zr x Te y It is possible.

[0114] In another example of embodiment b, the material of the chalcogenide layer 115 is alternatively a phase change memory material, for example Sb x Te y , Ge x Sb y Te z , Ge x Te y , Bi x Te y , and In x Te yIn the above chemical formula, the subscripts x, y, and z each represent the proportion of the corresponding atoms.

[0115] The phase change layer 113 and the chalcogenide layer 115 are stacked alternately. It is not difficult to understand that there is an interface between one phase change layer 113 and one adjacent chalcogenide layer 115. In this way, the alternate stacking of the phase change layer 113 and the chalcogenide layer 115 can introduce more interfaces for the phase change memory material, and the interfaces can reduce the thermal conduction. Therefore, the operating power consumption of the phase change memory cell 110 is reduced, and the fatigue life of the phase change memory cell 110 is improved. In addition, the chalcogenide has good thermal insulation performance. This can reduce the operating power consumption of the phase change memory cell 110 and improve the fatigue life of the phase change memory cell 110. In addition, when the material of the chalcogenide layer 115 is TiTe2, etc., the lattice coefficient of the chalcogenide layer 115 is smaller than the lattice coefficient of the phase change memory material provided in the embodiments of the present application, so that element diffusion in the phase change layer 113 can be prevented, and the fatigue life of the phase change layer 113 is improved, in other words, the fatigue life of the phase change memory cell 110 is improved.

[0116] 8A, in another example of embodiment b, at least one chalcogenide layer 115 and at least one phase change layer 113 may be alternately stacked or periodically arranged in a direction from electrode 111 to electrode 112 to form n periodic repeated stacks starting from phase change layer 113 and ending with chalcogenide layer 115, where n is an integer equal to or greater than 1.

[0117] In another example of embodiment b, referring to FIG. 8B, at least one chalcogenide layer 115 and at least one phase change layer 113 may be alternately stacked or periodically arranged in a direction from electrode 111 to electrode 112 to form n periodic repeated stacks starting from chalcogenide layer 115 and ending with phase change layer 113, where n is an integer equal to or greater than 1. 。

[0118] In another illustrative example of embodiment b, referring to FIG. 8C, in the direction from electrode 111 to electrode 112, at least one chalcogenide layer 115 and at least one phase change layer 113 are alternately stacked or periodically arranged. It can start with phase change layer 113 and end with phase change layer 113. Between phase change layer 113 at the start position and phase change layer 113 at the end position, there are n periodically and repeatedly stacked chalcogenide layers 115 and phase change layers 113. In addition, in phase change memory cell 110, at least one chalcogenide layer 115 is between two phase change layers 113, and at least one phase change layer is between two chalcogenide layers 115, where n is an integer equal to or greater than 1. 。

[0119] In another example of embodiment b, referring to FIG. 8D, at least one chalcogenide layer 115 and at least one phase change layer 113 are alternately stacked or periodically arranged in the direction from electrode 111 to electrode 112. This can start with chalcogenide layer 115 and end with chalcogenide layer 115. Between chalcogenide layer 115 at the start position and chalcogenide layer 115 at the end position, there are n periodically and repeatedly stacked phase change layers 113 and chalcogenide layers 115. In addition, the phase change memory cell 110 In the above, at least one chalcogenide layer 115 is between two phase change layers 113, and at least one phase change layer is between two chalcogenide layers 115. n is an integer equal to or greater than 1. 。

[0120] Although the above describes the positional relationship between the phase change layer 113 and the chalcogenide layer 115 using the structures shown in Figures 8A to 8D as examples, the examples are not exhaustive. In other embodiments, the phase change layer 113 and the chalcogenide layer 115 may alternatively have other positional relationships. The details are not listed here one by one.

[0121] Please refer to Fig. 9. An embodiment of the present application provides a storage device 900 including a phase change memory chip 910 and a controller 920. The phase change memory chip 910 may be configured to store data, and the controller 920 may be configured to write data to or read data from the phase change memory chip 910. The phase change memory chip 910 may include a plurality of phase change memory cells 110, and the plurality of phase change memory cells 110 form a memory cell array in the storage device 900.

[0122] In some embodiments, the phase change memory chip 910 may be implemented with reference to the above description of the embodiment shown in Figure 2. The controller 920 may be a device having data processing capabilities and configured to control the peripheral circuits of the phase change memory chip 910 to write data to or read data from the phase change memory chip 910.

[0123] Please refer to FIG. 10. An embodiment of the present application provides an electronic device 1000. The electronic device 1000 may include a processor 1010 and a storage device 900. The storage device 900 may be configured to store data, for example, applications and setting files of the electronic device 1000. The storage device 900 may provide a data storage space for the processor 1010, so that the processor 1010 can write data to the data storage space. The data stored in the storage device 900 may be read or accessed by the processor 1010. The processor 1010 is configured to write data to the storage device 900 or read data from the storage device 900. Specifically, the processor 1010 may write data to the phase change memory chip 910 or read data from the phase change memory chip 910 via the controller 920. For example, the processor 1010 may access data in the storage device 900 to realize a corresponding function of the electronic device 1000.

[0124] In some embodiments, the storage device 900 may be used as a memory of the electronic device 1000. In some embodiments, the storage device 900 may be used as an external memory of the electronic device 1000. In some embodiments, the processor 1010 may be a neural-network processing unit (NPU). In some embodiments, the storage device 900 may alternatively be another form of equipment having data storage capabilities and within the electronic device 1000. The implementation of the storage device 900 is not specifically limited in this application.

[0125] In some embodiments, the processor 1010 may be a central processing unit (CPU). In some embodiments, the processor 1010 may be a graphics processing unit (GPU). In some embodiments, the processor 1010 may be an application-specific integrated circuit (ASIC). In some embodiments, the processor 1010 may be a neural-network processing unit (NPU). In some embodiments, the processor 1010 may alternatively be an electronic device having data processing capabilities. 1000 The implementation of the processor 1010 is not specifically limited in this application.

[0126] In some embodiments, the electronic device 1000 may be a server, a mobile terminal (e.g., a mobile phone, a tablet computer, or a notebook computer), or an in-vehicle terminal, etc. The implementation of the electronic device in which the processor 1010 and the storage device 900 are provided is not specifically limited in this embodiment of the present application.

[0127] It can be understood that the above embodiments are only for describing the technical solutions of the present application, and are not for limiting the present application. Although the present application has been described in detail with reference to the above embodiments, modifications to the technical solutions recorded in the above embodiments, or equivalent replacements to some technical features thereof may still be made, and those skilled in the art should understand that these modifications or replacements do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions in the embodiments of the present application.

[0128] The above description is merely a specific implementation of the present application, and is not intended to limit the scope of protection of the present application. Any variation or replacement that is easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should fall within the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the scope of protection of the claims.

Claims

1. A phase change memory material, comprising a material represented by formula (1): Today ａ Sb ｂ Te ｃ D ｄ (1) wherein a represents the atomic percentage of Ti, b represents the atomic percentage of Sb, c represents the atomic percentage of Te, and d represents the atomic percentage of element D, a+b+c+d=1, 3%≦a≦45%, and 0.5≦(b:c)≦3, and D is a doping element, and 0≦d≦15%.

2. The value range of the atomic percentage a of Ti is 20%≦a≦35%. The phase change memory material of claim 1 .

3. The ratio of the atomic percentage b of Sb to the atomic percentage c of Te is 2:3; 3. A phase change memory material according to claim 1 or 2.

4. the atomic percentage d of the doping element D is 3%≦d≦8%; The phase change memory material according to any one of claims 1 to 3.

5. The doping element comprises one or a combination of at least two of a first non-metallic element, a first metallic element, and a telluride of the first metallic element; The first nonmetallic element is one or a combination of at least two of C, O, N, and Si; The first metal element is one or a combination of at least two of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn; The phase change memory material according to any one of claims 1 to 4.

6. A method for preparing a phase change memory material, said method being used for preparing a phase change memory material according to any one of claims 1 to 5, said method comprising the steps of: Preparing the phase change memory material by a first deposition manner according to the element ratio shown by formula (1), the first deposition manner belonging to one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD); Today ａ Sb ｂ Te ｃ D ｄ (1) wherein a represents the atomic percentage of Ti, b represents the atomic percentage of Sb, c represents the atomic percentage of Te, and d represents the atomic percentage of element D, a+b+c+d=1, 3%≦a≦45%, and 0.5≦(b:c)≦3, and D is a doping element, and 0≦d≦15%.

7. A phase change memory chip comprising a plurality of memory cells, the plurality of memory cells forming a memory cell array, each memory cell comprising a phase change layer, a first electrode provided on one side of the phase change layer, and a second electrode provided on the other side of the phase change layer, the phase change layer being made of the phase change memory material according to any one of claims 1 to 5. Phase change memory chip.

8. Each memory cell further comprises a buffer layer in contact with the phase change layer, the buffer layer being made of one of carbon, a third metal, a nitride of the third metal, and a telluride of a fourth metal, the third metal being one or a combination of at least two of W, Ta, and Ti, and the fourth metal being one or a combination of at least two of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, and Sn.

8. The phase change memory chip of claim 7.

9. Each memory cell further comprises at least one phase change layer and at least one chalcogenide layer, both of which are disposed between the first electrode and the second electrode, and the at least one phase change layer and the at least one chalcogenide layer are stacked in an alternating manner.

9. The phase change memory chip according to claim 7 or 8.

10. the lattice coefficient of the chalcogenide layer is smaller than the lattice coefficient of SbTe; 10. The phase change memory chip of claim 9.

11. A storage device comprising a controller and a phase change memory chip according to claim 9 or 10, the phase change memory chip being configured to store data, and the controller being configured to write data to the phase change memory chip or read data from the phase change memory chip.

12. 12. An electronic device comprising a processor and a storage device according to claim 11, the storage device being configured to store data, the processor being configured to write data to the storage device or read data from the storage device.

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