Selective Inhibition for Selective Metal Deposition

Abstract

A method for processing a substrate includes treating the substrate with a small molecule inhibitor (SMI), the substrate including a recess formed in a dielectric layer and a first metal layer within the recess, the SMI covering a surface of the first metal layer. The method further includes treating the substrate with a large molecule inhibitor (LMI) after treating the substrate with the SMI, the LMI covering a sidewall of the dielectric layer within the recess. The method further includes heating the substrate to remove the SMI from the first metal layer and expose the first metal layer within the recess, the LMI remaining on the sidewall after removing the SMI from the first metal layer. The method further includes depositing a second metal on the first metal layer within the recess, the LMI covering the sidewall preventing deposition of the second metal on the dielectric layer.

Description

[Technical field]

[0001] Cross-references to related patents and applications This application claims priority to and the benefit of the filing dates of U.S. Provisional Patent Application No. 63 / 315,062, filed February 28, 2022, and U.S. Nonprovisional Patent Application No. 18 / 156,142, filed January 18, 2023, which are incorporated by reference in their entireties herein.

[0002] The present invention relates generally to methods of processing substrates and, in particular embodiments, to selective inhibition for selective metal deposition. [Background technology]

[0003] Generally, semiconductor devices such as integrated circuits (ICs) are fabricated by sequentially depositing and patterning layers of dielectric, conductive, and semiconducting materials on a substrate to form a network of electronic components and interconnect elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias) integrated in a monolithic structure. Scaling efforts to increase the number of interconnect elements per unit area face greater challenges as scaling enters nanometer-scale semiconductor device manufacturing nodes. Thus, there is a demand for three-dimensional (3D) semiconductor devices in which transistors are stacked on top of each other.

[0004] As device structures become denser and more vertically developed, there is a stronger demand for precise material processing, for example during deposition and patterning, which calls for further innovation in various deposition techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), among others, to provide sufficient deposition rate, profile control, film conformality, and film quality. Summary of the Invention [Means for solving the problem]

[0005] According to one embodiment of the present invention, a method for processing a substrate includes treating the substrate with a small molecule inhibitor (SMI), the substrate including a recess formed in a dielectric layer and a first metal layer within the recess, the SMI covering a surface of the first metal layer. The method further includes treating the substrate with a large molecule inhibitor (LMI) after treating the substrate with the SMI, the LMI covering a sidewall of the dielectric layer within the recess. The method further includes heating the substrate to remove the SMI from the first metal layer and expose the first metal layer within the recess, the LMI remaining on the sidewall after removing the SMI from the first metal layer. The method further includes depositing a second metal on the first metal layer within the recess, the LMI covering the sidewall preventing deposition of the second metal on the dielectric layer.

[0006] According to one embodiment of the present invention, a method for processing a substrate includes performing a cyclic chemical vapor deposition (CVD) process, the substrate includes a dielectric layer having a recess and a first metal layer at the bottom of the recess. According to the method, one cycle of the cyclic CVD process includes treating the substrate with a small molecule inhibitor (SMI), where the SMI covers a surface of a second metal formed on the first metal layer, and treating the substrate with a large molecule inhibitor (LMI) after treating the substrate with the SMI, where the LMI covers a sidewall of the dielectric layer in the recess. According to the method, one cycle of the cyclic CVD process includes heating the substrate to remove the SMI from above the second metal and expose the second metal layer, where the LMI remains on the sidewall, and depositing the second metal on the first metal layer in the recess, where the LMI covering the sidewall prevents deposition of the second metal on the dielectric layer.

[0007] According to one embodiment of the present invention, a method for treating a substrate includes exposing the substrate to a first vapor including a small molecule inhibitor (SMI), the substrate including a dielectric surface and a first metal surface, the SMI selectively adsorbing to the first metal surface compared to the dielectric surface. The method includes exposing the substrate to a second vapor including a large molecule inhibitor (LMI), the LMI selectively adsorbing to the dielectric surface, the adsorbed SMI preventing the LMI from adsorbing to the first metal surface. The method includes removing the SMI from the first metal surface without removing the LMI from the dielectric surface, and depositing a second metal on the first metal surface by chemical vapor deposition (CVD), the deposition rate on the first metal surface being at least 100 times higher than the deposition rate on the dielectric surface.

[0008] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0009] [Figure 1A] 1A and 1B are schematic diagrams illustrating the impurity interface problem caused by conventional chemical vapor deposition (CVD) processes for metal deposition: FIG 1A shows a cross-sectional view of an exemplary substrate during a conventional CVD process, and FIG 1B shows a cross-sectional view of the substrate after a cycle of the conventional CVD process. [Figure 1B] 1A and 1B are schematic diagrams illustrating the impurity interface problem caused by conventional chemical vapor deposition (CVD) processes for metal deposition: FIG 1A shows a cross-sectional view of an exemplary substrate during a conventional CVD process, and FIG 1B shows a cross-sectional view of the substrate after a cycle of the conventional CVD process. [Figure 2A]2A-2H are cross-sectional views of a substrate at various stages of a metal deposition process according to various embodiments. FIG. 2A shows an incoming substrate with a first metal layer and a dielectric layer having recess features, FIG. 2B shows the substrate after pretreatment to expose the first metal layer, FIG. 2C shows the substrate after selective treatment with a small molecule inhibitor (SMI), FIG. 2D shows the substrate after selective treatment with a large molecule inhibitor (LMI), FIG. 2E shows the substrate after removing the SMI, FIG. 2F shows the substrate after depositing a second metal, FIG. 2G shows the substrate after a metal core removal etch, and FIG. 2H shows the substrate after cycles of a metal deposition process to fill the recesses with the second metal. [Figure 2B] 2A-2H are cross-sectional views of a substrate at various stages of a metal deposition process according to various embodiments. FIG. 2A shows an incoming substrate with a first metal layer and a dielectric layer having recess features, FIG. 2B shows the substrate after pretreatment to expose the first metal layer, FIG. 2C shows the substrate after selective treatment with a small molecule inhibitor (SMI), FIG. 2D shows the substrate after selective treatment with a large molecule inhibitor (LMI), FIG. 2E shows the substrate after removing the SMI, FIG. 2F shows the substrate after depositing a second metal, FIG. 2G shows the substrate after a metal core removal etch, and FIG. 2H shows the substrate after cycles of a metal deposition process to fill the recesses with the second metal. [Figure 2C] 2A-2H are cross-sectional views of a substrate at various stages of a metal deposition process according to various embodiments. FIG. 2A shows an incoming substrate with a first metal layer and a dielectric layer having recess features, FIG. 2B shows the substrate after pretreatment to expose the first metal layer, FIG. 2C shows the substrate after selective treatment with a small molecule inhibitor (SMI), FIG. 2D shows the substrate after selective treatment with a large molecule inhibitor (LMI), FIG. 2E shows the substrate after removing the SMI, FIG. 2F shows the substrate after depositing a second metal, FIG. 2G shows the substrate after a metal core removal etch, and FIG. 2H shows the substrate after cycles of a metal deposition process to fill the recesses with the second metal. [Figure 2D]2A-2H are cross-sectional views of a substrate at various stages of a metal deposition process according to various embodiments. FIG. 2A shows an incoming substrate with a first metal layer and a dielectric layer having recess features, FIG. 2B shows the substrate after pretreatment to expose the first metal layer, FIG. 2C shows the substrate after selective treatment with a small molecule inhibitor (SMI), FIG. 2D shows the substrate after selective treatment with a large molecule inhibitor (LMI), FIG. 2E shows the substrate after removing the SMI, FIG. 2F shows the substrate after depositing a second metal, FIG. 2G shows the substrate after a metal core removal etch, and FIG. 2H shows the substrate after cycles of a metal deposition process to fill the recesses with the second metal. [Figure 2E] 2A-2H are cross-sectional views of a substrate at various stages of a metal deposition process according to various embodiments. FIG. 2A shows an incoming substrate with a first metal layer and a dielectric layer having recess features, FIG. 2B shows the substrate after pretreatment to expose the first metal layer, FIG. 2C shows the substrate after selective treatment with a small molecule inhibitor (SMI), FIG. 2D shows the substrate after selective treatment with a large molecule inhibitor (LMI), FIG. 2E shows the substrate after removing the SMI, FIG. 2F shows the substrate after depositing a second metal, FIG. 2G shows the substrate after a metal core removal etch, and FIG. 2H shows the substrate after cycles of a metal deposition process to fill the recesses with the second metal. [Figure 2F] 2A-2H are cross-sectional views of a substrate at various stages of a metal deposition process according to various embodiments. FIG. 2A shows an incoming substrate with a first metal layer and a dielectric layer having recess features, FIG. 2B shows the substrate after pretreatment to expose the first metal layer, FIG. 2C shows the substrate after selective treatment with a small molecule inhibitor (SMI), FIG. 2D shows the substrate after selective treatment with a large molecule inhibitor (LMI), FIG. 2E shows the substrate after removing the SMI, FIG. 2F shows the substrate after depositing a second metal, FIG. 2G shows the substrate after a metal core removal etch, and FIG. 2H shows the substrate after cycles of a metal deposition process to fill the recesses with the second metal. [Figure 2G]2A-2H are cross-sectional views of a substrate at various stages of a metal deposition process according to various embodiments. FIG. 2A shows an incoming substrate with a first metal layer and a dielectric layer having recess features, FIG. 2B shows the substrate after pretreatment to expose the first metal layer, FIG. 2C shows the substrate after selective treatment with a small molecule inhibitor (SMI), FIG. 2D shows the substrate after selective treatment with a large molecule inhibitor (LMI), FIG. 2E shows the substrate after removing the SMI, FIG. 2F shows the substrate after depositing a second metal, FIG. 2G shows the substrate after a metal core removal etch, and FIG. 2H shows the substrate after cycles of a metal deposition process to fill the recesses with the second metal. [Figure 2H] 2A-2H are cross-sectional views of a substrate at various stages of a metal deposition process according to various embodiments. FIG. 2A shows an incoming substrate with a first metal layer and a dielectric layer having recess features, FIG. 2B shows the substrate after pretreatment to expose the first metal layer, FIG. 2C shows the substrate after selective treatment with a small molecule inhibitor (SMI), FIG. 2D shows the substrate after selective treatment with a large molecule inhibitor (LMI), FIG. 2E shows the substrate after removing the SMI, FIG. 2F shows the substrate after depositing a second metal, FIG. 2G shows the substrate after a metal core removal etch, and FIG. 2H shows the substrate after cycles of a metal deposition process to fill the recesses with the second metal. [Figure 3A] 3A-3D are schematic diagrams illustrating step-by-step area-selective surface modification of a metal deposition process according to one embodiment: Figure 3A shows selective adsorption of a small molecule inhibitor (SMI) on a metal, Figure 3B shows selective adsorption of a large molecule inhibitor (LMI) on a silicon oxide, Figure 3C shows selective removal of SMI by H2 treatment, and Figure 3D shows selective metal deposition on a metal. [Figure 3B] 3A-3D are schematic diagrams illustrating step-by-step area-selective surface modification of a metal deposition process according to one embodiment: Figure 3A shows selective adsorption of a small molecule inhibitor (SMI) on a metal, Figure 3B shows selective adsorption of a large molecule inhibitor (LMI) on a silicon oxide, Figure 3C shows selective removal of SMI by H2 treatment, and Figure 3D shows selective metal deposition on a metal. [Figure 3C] 3A-3D are schematic diagrams illustrating step-by-step area-selective surface modification of a metal deposition process according to one embodiment: Figure 3A shows selective adsorption of a small molecule inhibitor (SMI) on a metal, Figure 3B shows selective adsorption of a large molecule inhibitor (LMI) on a silicon oxide, Figure 3C shows selective removal of SMI by H2 treatment, and Figure 3D shows selective metal deposition on a metal. [Figure 3D] 3A-3D are schematic diagrams illustrating step-by-step area-selective surface modification of a metal deposition process according to one embodiment: Figure 3A shows selective adsorption of a small molecule inhibitor (SMI) on a metal, Figure 3B shows selective adsorption of a large molecule inhibitor (LMI) on a silicon oxide, Figure 3C shows selective removal of SMI by H2 treatment, and Figure 3D shows selective metal deposition on a metal. [Figure 4A] 4A-4C are process flow diagrams of methods of metal deposition processes according to various embodiments, with FIG 4A showing one embodiment, FIG 4B showing another embodiment, and FIG 4C showing yet another embodiment. [Figure 4B] 4A-4C are process flow diagrams of methods of metal deposition processes according to various embodiments, with FIG 4A showing one embodiment, FIG 4B showing another embodiment, and FIG 4C showing yet another embodiment. [Figure 4C] 4A-4C are process flow diagrams of methods of metal deposition processes according to various embodiments, with FIG 4A showing one embodiment, FIG 4B showing another embodiment, and FIG 4C showing yet another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] This application relates to a method for treating a substrate, and more specifically, to selective metal deposition using two types of molecular inhibitors. Generally, conductive materials are used in semiconductor devices to enable electrical connections between various components. Although copper (Cu) has been used for interconnects in integrated circuits (ICs) for decades, new conductive materials with lower electrical resistivity (e.g., Ru, Mo, Co, and W) are being tested as good candidates for applications such as sub-10 nm node middle-of-line (MOL) and back-end-of-line (BEOL) logic interconnects. In addition, some of these new conductive materials, unlike Cu, may not require a diffusion barrier layer, which advantageously simplifies the fabrication process. However, it has been difficult to deposit and pattern these metal materials with sufficient selectivity for high aspect ratio (HAR) features at small scales. To fill high HAR recesses with metal without voids or pinch-off issues, bottom-up selective metal deposition is desired. One solution is to use molecular inhibitors during the deposition process, which can preferentially deposit metal on metal surfaces compared to, for example, inhibitor-covered dielectric surfaces. However, inhibitors can also adsorb to the metal surface, causing impurity problems and slowing down the metal deposition rate. Therefore, new methods for selective metal deposition would be desirable.

[0011] The embodiments of the present application disclose a method of selective metal deposition using two different molecular inhibitors. One of the molecular inhibitors is for the metal surface and the other is for the dielectric surface. In various embodiments, the metal surface may be first treated with a first molecular inhibitor (e.g., a small molecule inhibitor, SMI) to passivate it. The dielectric surface may then be treated with a second molecular inhibitor (e.g., a large molecule inhibitor, LMI) to passivate it, where the presence of SMI can prevent undesired LMI adsorption on the metal surface. After passivation of the dielectric surface with LMI, the SMI may be removed from the metal surface, so that a subsequent metal deposition process (e.g., CVD) can be preferentially performed on the exposed metal surface while the LMI prevents metal deposition on the dielectric. These methods may be applied as a cyclic process to fill high aspect ratio (HAR) recesses.

[0012] The methods described in this disclosure can advantageously improve the selectivity of various metal deposition methods. The improved selectivity allows these metal deposition methods to overcome the problem of impurities at the metal-metal interface. These methods can be particularly advantageous for manufacturing processes for sub-10 nm node middle-of-line (MOL) and back-end-of-line (BEOL) logic interconnects and can also enable the use of new metal materials such as Ru, Mo, Co, and W for these applications. In this disclosure, various embodiments of the methods are primarily described as CVD, but the use of the two molecular inhibitors can also be applied to other methods such as atomic layer deposition (ALD) and wet processes.

[0013] In the following, the impurity interface problem of conventional CVD methods is first described with reference to Figures 1A-1B. Then, the steps of a CVD method using two molecular inhibitors according to various embodiments are described with reference to Figures 2A-2H and 3A-3D. An exemplary process flow diagram is shown in Figures 4A-4D. All figures in this disclosure are drawn for illustrative purposes only and are not to scale, including aspect ratios of features.

[0014] 1A-1B illustrate diagrammatically the impurity interface problem caused by conventional chemical vapor deposition (CVD) processes for metal deposition.

[0015] FIG. 1A shows a cross-sectional view of an exemplary substrate having a recess during a conventional CVD process using a molecular inhibitor, where the conventional CVD process selectively deposits a second metal 104 on a first metal 102 to fill the recess. The molecular inhibitor may prevent metal deposition on the sidewalls and may form an impurity layer 106 (e.g., containing Si) at the interface between the first metal 102 and the second metal 104. When the conventional CVD process is performed in cycles (FIG. 1B), the impurity layer 106 may form at each intermetal interface. The impurity layer 106 often adversely affects the quality of the metal interconnects and may also reduce the metal deposition rate during the CVD process. The inventors of the present application have determined that this impurity problem is caused by the undesired passivation of the metal surface by the molecular inhibitor. As further described below with reference to Figures 2A-2H and 3A-3D, the methods of metal deposition described in the present disclosure can advantageously solve this impurity problem by pre-passivating the metal surface with a separate molecular inhibitor that can be easily removed in a subsequent step.

[0016] Figures 2A-2H show cross-sectional views of a substrate 100 at various stages of a metal deposition process according to various embodiments. The selective surface modification of the metal deposition process is further illustrated generally in Figures 3A-3D, which are discussed in conjunction with Figures 2C-2F, respectively.

[0017] 2A shows a cross-sectional view of an incoming substrate 100. In various embodiments, the substrate 100 may be part of or include a semiconductor device, e.g., may have undergone several processing steps following conventional processing. Thus, the substrate 100 may have layers of semiconductors useful in various microelectronics. For example, a semiconductor structure may have the substrate 100 on which various device regions are formed.

[0018] In one or more embodiments, the substrate 100 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In certain embodiments, the substrate 100 may include a silicon germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, or other compound semiconductors. In other embodiments, the substrate 100 comprises a heterogeneous layer, such as silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, as well as a layer of silicon on silicon or an SOI substrate. In various embodiments, the substrate 100 is patterned or embedded with other components of a semiconductor device.

[0019] 2A, the substrate 100 may have a recess 115 formed in the dielectric layer 110. In certain embodiments, the substrate 100 may further have an etch stop layer (ESL) 120 as a bottom layer of the dielectric layer 110 and a first metal layer 130 at the bottom of the recess 115. As shown in FIG. 2A, in one or more embodiments, a surface oxide layer 135 may be present on the surface of the first metal layer 130.

[0020] In various embodiments, the dielectric layer 110 may be any other suitable dielectric material, including silicon oxide, low-k materials such as fluorinated silicon glass (FSG), carbon-doped oxides, polymers, SiCOH-containing low-k materials, non-porous low-k materials, porous low-k materials, CVD low-k materials, spin-on dielectric (SOD) low-k materials, or high-k materials. In certain embodiments, the critical dimension (CD) of the recess 115 may be between about 10 nm and about 65 nm for via-based structures, or in other embodiments, between about 10 nm and about 100 nm for trench-based structures. In one or more embodiments, the depth of the recess 115 may be between about 40 nm and about 80 nm for single damascene structures, or between about 80 nm and about 150 nm for dual damascene structures. In various embodiments, the recesses 115 may have an aspect ratio between about 4 and about 8 for single damascene, or between about 6 and about 10 for dual damascene.

[0021] The first metal layer 130 may include a low resistivity metal such as copper (Cu), ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tungsten (W). Although not shown in FIG. 2A, in certain embodiments, the first metal layer 130 may include two or more stacked conductive layers. Examples of stacked conductive layers include Co metal on Cu metal (Co / Cu) and Ru metal on Cu metal (Ru / Cu).

[0022] ESL 120 may include a dielectric material such as silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride. ESL 120 may be deposited using deposition techniques such as vapor deposition, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes, such as plasma enhanced chemical vapor deposition (PECVD), sputtering, and other processes. In certain embodiments, the thickness of ESL 120 may be between 2 nm and 5 nm.

[0023] FIG. 2B shows a cross-sectional view of the substrate 100 after pre-treatment to expose the first metal layer 130.

[0024] In various embodiments, prior to treatment with a molecular inhibitor for selective metal deposition, a pretreatment may be performed to remove the surface oxide layer 135 and expose the first metal layer 130. The pretreatment may include, for example, treating the surface oxide layer 135 with a plasma containing dihydrogen (H2). In other embodiments, the pretreatment may be omitted if the substrate 100 does not already have a surface oxide present.

[0025] FIG. 2C shows a cross-sectional view of the substrate after selective treatment with a small molecule inhibitor (SMI).

[0026] FIG. 3A illustrates the selective adsorption of SMI to metals according to one embodiment.

[0027] In FIG. 2C, the substrate 100 may be treated with a small molecule inhibitor (SMI) to selectively cover the exposed surface of the first metal layer 130, resulting in a passivated first metal surface 140. In one embodiment, as shown in FIG. 3A, the SMI may selectively adsorb metal only on dielectric surfaces such as silicon oxide. With the SMI passivating the first metal layer 130, a subsequent step with another molecular inhibitor may advantageously selectively adsorb on the dielectric layer 110. In various embodiments, the SMI may be vaporized and delivered to the substrate 100 as a vapor diluted in a carrier gas (e.g., N2), and a substrate temperature of about room temperature may be maintained. In one embodiment, this exposure to the SMI may be performed for 1-120 seconds using a heating stage or temperature ramping technique.

[0028] In various embodiments, the SMI may include a nitrogen-containing compound, and in certain embodiments, the nitrogen-containing compound includes NH, N, or an aromatic compound. Examples of nitrogen-aromatic SMIs include pyridine, pyrimidine, pyrazine, pyrrole, imidazole, pyrazole, aniline, and benzotriazole (BTA). In other embodiments, the SMI is R-POH, R-COOH, R-SH, or R-SO. x In various embodiments, any suitable molecular inhibitor can be used that meets the following criteria: the SMI selectively adsorbs to the metal layer (e.g., first metal layer 130) relative to other layers (e.g., dielectric layer 110); the metal layer can be regenerated by a subsequent removal step of the SMI. In one or more embodiments, the SMI can be oxygen-free to prevent oxygen from interacting with the metal and potentially causing impurity issues.

[0029] FIG. 2D shows the substrate 100 after selective treatment with a large molecule inhibitor (LMI).

[0030] FIG. 3B shows the selective adsorption of LMI onto a silicon oxide surface.

[0031] In FIG. 2D, the substrate 100 may be treated with a large molecule inhibitor (LMI). The LMI may selectively cover the exposed surface, both sidewalls, and top horizontal surfaces of the dielectric layer 110, resulting in a passivated dielectric surface 150. The presence of SMI may prevent unwanted LMI adsorption onto the first metal layer 130. This is further illustrated in FIG. 3B, where LMI is adsorbed only onto the silicon oxide surface. Without wishing to be limited to any theory, treatment with LMI may make the surface of the dielectric layer 110 more hydrophobic, which may be beneficial in reducing deposition of metal precursors during the metal deposition step. In various embodiments, the LMI may be vaporized and delivered to the substrate 100 as a vapor diluted in a carrier gas (e.g., N2). In certain embodiments, the treatment may be performed without plasma excitation, at a substrate temperature between about 80° C. and about 250° C., a process chamber pressure of about 1-10 Torr, and an exposure time of 1-120 seconds.

[0032] In various embodiments, the LMI comprises an alkyl silane, an alkoxy silane, an alkyl alkoxy silane, an alkyl siloxane, an alkoxy siloxane, an alkyl alkoxy siloxane, an aryl silane, an acyl silane, an aryl siloxane, an acyl siloxane, a silazane, dimethylsilane dimethylamine (DMSDMA), trimethylsilane dimethylamine (TMSDMA), bis(dimethylamino)dimethylsilane (BDMADMS), N,O-bistrimethylsilyltrifluoroacetamide (BSTFA), or trimethylsilylpyrrole (TMS-pyrrole).

[0033] In this disclosure, a first molecular inhibitor used to passivate a metal surface (e.g., Figures 2C and 3A) is referred to as a small molecule inhibitor (SMI), and a second molecular inhibitor used to passivate a dielectric surface (e.g., Figures 2D and 3B) is referred to as a large molecule inhibitor (LMI), generally due to the relative molecular size of the molecular inhibitors. In one embodiment, the LMI may have a larger molecular weight than the SMI. In another embodiment, the LMI may have a larger molecular volume or surface area than the SMI. However, in various embodiments, molecular inhibitors of any molecular size may be used, so long as they allow for sufficiently selective passivation of the respective surfaces.

[0034] FIG. 2E illustrates a cross-sectional view of substrate 100 after the SMI has been removed.

[0035] FIG. 3C shows the selective removal of SMI by H2 treatment.

[0036] After the two molecular inhibitor treatment steps (e.g., FIGS. 2C and 2D), an SMI removal step may be performed. In various embodiments, the SMI removal step may be an annealing process at a temperature below 400° C. under an inert gas flow or a reducing environment (e.g., H2). The reducing environment for the annealing process may advantageously minimize undesired reactions of the metal in the first metal layer 130, such as nitridation or oxidation. In certain embodiments, the annealing temperature may be between 250° C. and 400° C., such that the annealing process does not exceed the thermal budget for the target semiconductor device fabrication. As shown in FIGS. 2E and 3D, the annealing process may selectively remove the SMI from the metal surface (e.g., the first metal layer 130) while preserving the LMI on the dielectric surface (e.g., the dielectric layer 110). This selective SMI removal restores the metal surface and allows it to be processed in a subsequent metal deposition step.

[0037] FIG. 2F shows a cross-sectional view of the substrate 100 after depositing a second metal 160 .

[0038] FIG. 3D shows selective metal-on-metal deposition.

[0039] In various embodiments, the metal deposition step can be performed using chemical vapor deposition (CVD), although other techniques, including wet processes, can be used in other embodiments. The second metal 160 can include a low-resistivity metal, such as Cu, Ru, Co, W, etc. The second metal 160 may or may not be the same material used for the first metal layer 130. Although not shown in FIG. 2F, in certain embodiments, multiple metals may be deposited to form an alloy or stacked conductive layer. Since the sidewalls and top surface of the dielectric layer 110 are still passivated by LMI, the second metal 160 can be selectively deposited and grown bottom-up on the first metal layer 130.

[0040] In certain embodiments, Ru metal may be deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) using a Ru-containing precursor. An example of a Ru-containing precursor is Ru(CO). 12 , (2,4-dimethylpentadienyl)(ethylcyclopentadienyl)ruthenium (Ru(DMPD)(EtCp)), bis(2,4-dimethylpentadienyl)ruthenium (Ru(DMPD)2), 4-dimethylpentadienyl)(methylcyclopentadienyl)ruthenium (Ru(DMPD)(MeCp)), and bis(ethylcyclopentadienyl)ruthenium (Ru(EtCp)2), as well as combinations of these with other precursors. In one embodiment, the process conditions for the Ru metal CVD process include Ru(CO) without plasma excitation. 12 and CO (e.g., a gas flow ratio of about 1:100), a substrate temperature of between about 100° C. and about 250° C., a process chamber pressure of between about 1 mTorr and about 500 mTorr, and an exposure time of 400 seconds, depositing between about 10 nm and 20 nm of Ru metal on the metal surface.

[0041] In various embodiments, as further shown in FIG. 2F, the metal deposition step can fill a portion of the recess 115, for example, about one-quarter of the initial depth of the recess 115. In other embodiments, the recess 115 can be completely filled in one metal deposition step. In certain embodiments, the metal deposition step can be terminated at a certain height to avoid excessive formation of metal nuclei 165 on the dielectric layer 110. These metal nuclei 165 can be formed by adsorption of the metal precursor on the LMI or incomplete passivation of the dielectric layer 110 by the LMI. The metal nuclei 165 on the dielectric layer 110, especially on the sidewalls, can cause lateral growth of the second metal 160, which can create voids in the second metal 160 and cause pinch-off problems. Thus, in various embodiments, the metal deposition step is performed as a cyclic process including a metal nuclei removal etch as described below (FIG. 2G), and the recess 115 can be filled in cycles of the metal deposition process.

[0042] FIG. 2G shows a cross-sectional view of the substrate 100 after the metal core removal etch.

[0043] To minimize undesired lateral metal growth, a metal nucleus removal etch may be performed after the metal deposition step to clean the sidewalls and top surface of the dielectric layer 110. It may be preferable to remove the metal nuclei 165 before they become too large and difficult to remove efficiently. As shown in FIG. 2G, after the metal nucleus removal etch, the LIM may also be removed from the dielectric layer 110. In certain embodiments, the metal nucleus removal etch may be performed using reactive ion etching (RIE), for example using plasma excited O2 gas, optionally with the addition of a halogen-containing gas (e.g., Cl2). In one embodiment, process conditions for O2-Cl2 RIE for metal nucleus removal etch may include an etch including O2 and Cl2 (e.g., gas flow ratio of about 100:1), a substrate temperature between about room temperature and about 370°C, plasma excitation using a capacitively coupled plasma (CCP) source (about 1200 W RF power applied to the top electrode and between about 0 W and about 300 W RF power applied to the bottom electrode), a process chamber pressure of about 5 mTorr, and an exposure time of 40 seconds, removing the equivalent of about 5 nm of metal nuclei. In a particular embodiment, the metal nucleus removal etch may be performed using chemical vapor etching (CVE). In another embodiment, treatment with ozone (O3) gas may also be used for the metal nucleus removal etch. Ozone for ozone treatment can be generated from dioxygen (O2) gas by ultraviolet excitation under the following exemplary process conditions: process temperature between about 50°C and 200°C; pressure range between about 500mT and 10 Torr diluted with Ar gas; ozone exposure time between 1 second and 60 seconds; and 100 g / m 3 ~300g / m 3 Ozone density between 0.01 and 0.05 nm. Ozone treatment can be applied to BEOL metallization without causing damage to low-k dielectrics, which may be advantageous over O2 plasma-based RIE.

[0044] In other embodiments, not shown, metal deposition (FIG. 2F) may be achieved without metal nuclei (e.g., metal nuclei 165 in FIG. 2F) on the sidewalls of the dielectric layer 110, and in these cases the metal nuclei removal etch may be omitted. In certain embodiments, LMI may not completely stop metal deposition on the dielectric layer 110, but may slow the deposition rate substantially. In one example, the deposition rate on the first metal layer 130 may be at least 100 times the deposition rate on the dielectric layer 110.

[0045] FIG. 2H shows a cross-sectional view of the substrate 100 after a cycle of a metal deposition process to fill the recess 115 with a second metal 160.

[0046] In various embodiments, the method of selective metal deposition process may be implemented as a cyclic process by repeating the steps of selective SMI treatment (e.g., FIGS. 2C and 3A), selective LMI treatment (e.g., FIGS. 2D and 3B), selective SMI removal (e.g., FIGS. 2E and 3C), metal deposition (e.g., FIGS. 2F and 3D), and metal core removal etch (e.g., FIG. 2G). Each cycle of the selective metal deposition process may fill a portion of the recess 115 with the second metal 160, and may be repeated until the recess 115 is completely filled. As shown in FIG. 2H, the filled recess may be free of impurities, unlike the conventional method shown in FIGS. 1A and 1B. In one embodiment, the impurity level (e.g., Si) in the filled recess may be below the detection limit (e.g., ±0.1 atomic %) of common techniques such as elemental analysis and X-ray photoelectron spectroscopy (XPS). Furthermore, the filled recess may be free of voids. In one embodiment, the recess 115 may be completely filled by four cycles of the selective metal deposition process, although in other embodiments, any number of cycles may be performed. In certain embodiments, the process conditions for the selective metal deposition process steps may be adjusted for each cycle to account for the aspect ratio of the remaining recess. For example, the exposure time for metal deposition for the first cycle may be shorter than the exposure time for subsequent cycles, since the surface area may be larger and therefore the likelihood of metal nucleation on the sidewalls may be higher. In certain embodiments, the selective metal deposition process cycles may use multiple deposition techniques, since the use of two molecular inhibitors in the method is not limited to any particular deposition technique. In various embodiments, each step of the selective metal deposition process (e.g., FIGS. 2A-2H) may be performed within the thermal budget for the target semiconductor device fabrication, such as, for example, below 400° C.

[0047] 4A-4C show process flow diagrams of methods of metal deposition processes according to various embodiments. The process flow can follow the diagrams discussed above (FIGS. 2C-2G) and therefore will not be described again.

[0048] In FIG. 4A, process flow 40 begins with treating a substrate with a small molecule inhibitor (SMI), where the substrate comprises a recess formed in a dielectric layer and a first metal layer within the recess (block 410, FIG. 2C). The surface of the first metal layer may be selectively covered with SMI. After treating the substrate with SMI, the substrate may be treated with a large molecule inhibitor (LMI) to cover the sidewalls of the dielectric layer within the recess (block 420, FIG. 2D). The substrate may then be heated to remove the SMI from the first metal layer and expose the first metal layer within the recess, with the LMI remaining on the sidewalls (block 430, FIG. 2E). A second metal may then be selectively deposited on the first metal layer within the recess, with the LMI covering the sidewalls preventing deposition of the second metal on the dielectric layer (block 440, FIG. 2F).

[0049] In FIG. 4B, a cyclic chemical vapor deposition (CVD) process 42 begins with treating a substrate with SMI to cover a metal surface (e.g., a first metal layer in a first cycle of the cyclic CVD process, and a second metal surface in a subsequent cycle) (block 412, FIG. 2C). The substrate may have a dielectric layer with a recess and a first metal layer exposed at the bottom of the recess. After treating the substrate with SMI, the substrate may be treated with LMI to cover a sidewall of the dielectric layer in the recess (block 422, FIG. 2D). The substrate may then be heated to remove the SMI from the first metal layer and expose the first metal layer in the recess, with the LMI remaining on the sidewall (block 432, FIG. 2E). A second metal may then be selectively deposited on the first metal layer in the recess, with the LMI covering the sidewall preventing deposition of the second metal on the dielectric layer (block 442, FIG. 2F). These steps (blocks 412, 422, 432, and 442) may be repeated in a cyclical manner in certain embodiments. In other embodiments, the deposition of the second metal may deposit second metal nuclei on portions of the sidewall, and an additional etch may be inserted into one or more of the cycles of the cyclic CVD process to remove the second metal nuclei from the portions of the sidewall (block 452, FIG. 2G).

[0050] In FIG. 4C, another process flow 44 begins with exposing a substrate to a first vapor including SMI, where the substrate includes a recess formed in a dielectric layer and a first metal layer within the recess (block 414, FIG. 2C). The SMI selectively adsorbs to the first metal layer relative to the sidewalls of the dielectric layer within the recess. The substrate may then be exposed to a second vapor including LMI (block 424, FIG. 2D), where the LMI selectively adsorbs to the sidewalls and the adsorbed SMI prevents the LMI from adsorbing to the first metal layer. The SMI may then be removed from the first metal layer without removing the LMI from the sidewalls (block 434, FIG. 2E). A second metal may then be selectively deposited by CVD on the first metal layer within the recess, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer (block 444, FIG. 2F).

[0051] The selective metal deposition using two molecular inhibitors in various embodiments can advantageously eliminate or minimize impurity problems due to inhibitor contamination. These methods are particularly useful for vapor phase metal deposition to fill high aspect ratio (HAR) recesses in applications such as sub-10 nm node middle-of-line (MOL) and back-end-of-line (BEOL) logic interconnects, where even very low levels of impurities can reduce electrical conductivity and thereby device performance. Although the present disclosure primarily describes embodiments related to chemical vapor deposition of low resistivity metals (e.g., Cu, Ru, Co, and W), the methods can also be applied to atomic layer deposition (ALD) or other deposition techniques. Furthermore, in certain embodiments, these methods can be used to deposit metal compounds (e.g., metal oxides and metal nitrides), and the selective metal deposition step may be followed by additional processing to convert the deposited metal to the metal compound.

[0052]

[0023] Exemplary embodiments of the present invention are summarized herein. Other embodiments can be seen throughout this specification and the claims.

[0053] Example 1. A method for treating a substrate includes treating the substrate with a small molecule inhibitor (SMI), the substrate including a recess formed in a dielectric layer and a first metal layer within the recess, the SMI covering a surface of the first metal layer. The method further includes treating the substrate with a large molecule inhibitor (LMI) after treating the substrate with the SMI, the LMI covering a sidewall of the dielectric layer within the recess. The method further includes heating the substrate to remove the SMI from the first metal layer and expose the first metal layer within the recess, the LMI remaining on the sidewall after removing the SMI from the first metal layer. The method further includes depositing a second metal on the first metal layer within the recess, the LMI covering the sidewall preventing deposition of the second metal on the dielectric layer.

[0054] Example 2. The method of Example 1, wherein the substrate further comprises a surface oxide layer over the first metal layer, and the method further comprises removing the surface oxide layer to expose the first metal layer in the recess prior to treating the substrate with the SMI.

[0055] Example 3. The method of example 1 or 2, wherein the deposition of the second metal deposits second metal nuclei on a portion of the sidewall, and the method further comprises removing the second metal nuclei.

[0056] Example 4. The method of any one of Examples 1-3, wherein deposition of the second metal is achieved bottom-up from the first metal layer, and the second metal does not grow out of the dielectric layer.

[0057] Example 5. The method of any one of Examples 1-4, wherein heating the substrate comprises heating the substrate to a temperature between 250°C and 400°C.

[0058] Example 6. The method of any one of Examples 1-5, wherein heating the substrate comprises exposing the substrate to a gas comprising dihydrogen (H2).

[0059] Example 7. The method of any one of Examples 1-6, wherein the SMI comprises a nitrogen-containing compound.

[0060] Example 8. The method of any one of Examples 1-7, wherein the nitrogen-containing compound comprises NH3, N2H4, or an aromatic compound.

[0061] Example 9. The method of any one of Examples 1-8, wherein the SMI comprises R-PO3H, R-COOH, R-SH, or R-SOx.

[0062] Example 10. The method of any one of Examples 1-9, wherein the LMI comprises an alkyl silane, an alkoxy silane, an alkyl alkoxy silane, an alkyl siloxane, an alkoxy siloxane, an alkyl alkoxy siloxane, an aryl silane, an acyl silane, an aryl siloxane, an acyl siloxane, a silazane, dimethylsilane dimethylamine (DMSDMA), trimethylsilane dimethylamine (TMSDMA), bis(dimethylamino)dimethylsilane (BDMADMS), N,O-bistrimethylsilyltrifluoroacetamide (BSTFA), or trimethylsilylpyrrole (TMS-pyrrole).

[0063] Example 11. The method of any one of Examples 1-10, wherein the first metal layer comprises Ru, Co, or W, and the second metal comprises Cu, Ru, Co, or W.

[0064] Example 12. A method for treating a substrate includes performing a cyclic chemical vapor deposition (CVD) process, the substrate includes a dielectric layer having a recess and a first metal layer at the bottom of the recess. According to the method, one cycle of the cyclic CVD process includes treating the substrate with a small molecule inhibitor (SMI), where the SMI covers a surface of a second metal formed on the first metal layer, and treating the substrate with a large molecule inhibitor (LMI) after treating the substrate with the SMI, where the LMI covers the sidewalls of the dielectric layer in the recess. According to the method, one cycle of the cyclic CVD process includes heating the substrate to remove the SMI from above the second metal and expose the second metal layer, where the LMI remains on the sidewalls, and depositing the second metal on the first metal layer in the recess, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer.

[0065] Example 13. The method of Example 12, wherein the deposition of the second metal deposits second metal nuclei on a portion of the sidewall, and wherein one of the cyclic CVD processes further comprises removing the second metal nuclei from said portion of the sidewall.

[0066] Example 14. The method of example 12 or 13, wherein the cyclic CVD process fills the recesses without forming voids.

[0067] Example 15. The method of any one of Examples 12-14, wherein the LMI comprises silane and the second metal filling the recess does not contain detectable silicon or silane impurities.

[0068] Example 16. A method for treating a substrate includes exposing the substrate to a first vapor containing a small molecule inhibitor (SMI), the substrate including a dielectric surface and a first metal surface, the SMI selectively adsorbing to the first metal surface compared to the dielectric surface. The method includes exposing the substrate to a second vapor containing a large molecule inhibitor (LMI), the LMI selectively adsorbing to the dielectric surface, the adsorbed SMI preventing the LMI from adsorbing to the first metal surface. The method includes removing the SMI from the first metal surface without removing the LMI from the dielectric surface, and depositing a second metal on the first metal surface by chemical vapor deposition (CVD), the deposition rate on the first metal surface being at least 100 times that on the dielectric surface.

[0069] Example 17. The method of Example 16, wherein the removing step includes treating the substrate with a gas comprising dihydrogen (H2) at a substrate temperature between 250°C and 400°C.

[0070] Example 18. The method of example 16 or 17, wherein the first metal layer comprises Ru, Co, Mo, or W, and the second metal comprises Cu, Ru, Co, Mo, or W.

[0071] Example 19. The method of any one of Examples 16-18, wherein the SMI does not contain silicon and the LMI contains silicon.

[0072] Example 20. The method of any one of Examples 16-19, wherein the substrate comprises a recess, the recess having a dielectric surface as a sidewall and a first metal surface as a bottom surface, the recess having a critical dimension (CD) between 10 nm and 650 nm.

[0073] Although the present invention has been described with reference to exemplary embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present invention, will be apparent to those skilled in the art upon reference to the above description. It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims

1. 1. A method for processing a substrate, the method comprising: treating the substrate with a small molecule inhibitor (SMI), the substrate having a recess formed in a dielectric layer and a first metal layer within the recess, the SMI selectively adsorbing onto the first metal layer and coating a surface of the first metal layer; After treating the substrate with the SMI, treating the substrate with a large molecule inhibitor (LMI), wherein the LMI is selectively adsorbed onto the dielectric layer and coats the sidewalls of the dielectric layer in the recess, and the LMI has a larger molecular weight or volume than the SMI; heating the substrate to remove the SMI from the first metal layer and expose the first metal layer in the recess, the LMI remaining on the sidewall after removing the SMI from the first metal layer; depositing a second metal on the first metal layer in the recess, wherein the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer, and the deposition rate of the second metal on the first metal layer is at least 100 times that of the second metal on the dielectric layer; A method comprising:

2. the substrate further comprises a surface oxide layer on the first metal layer; 2. The method of claim 1, further comprising removing the surface oxide layer to expose the first metal layer in the recess before treating the substrate with SMI.

3. the step of depositing the second metal deposits second metal nuclei on a portion of the sidewall; The method of claim 1 , further comprising removing the second metal nuclei.

4. 2. The method of claim 1, wherein the step of depositing the second metal is performed bottom-up from the first metal layer, and the second metal does not grow out of the dielectric layer.

5. The method of claim 1 , wherein heating the substrate comprises heating the substrate to a temperature between 250° C. and 400° C.

6. The step of heating the substrate may include heating dihydrogen (H ２ 10. The method of claim 1, further comprising exposing the substrate to a gas containing:

7. The method of claim 1 , wherein the SMI comprises a nitrogen-containing compound.

8. The nitrogen-containing compound is NH ３ , N ２ H ４ or an aromatic compound.

9. The SMI is R-PO ３ H, R—COOH, R—SH, or R—SO ｘ The method of claim 1 , comprising:

10. 2. The method of claim 1, wherein the LMI comprises an alkylsilane, an alkoxysilane, an alkylalkoxysilane, an alkylsiloxane, an alkoxysiloxane, an alkylalkoxysiloxane, an arylsilane, an acylsilane, an arylsiloxane, an acylsiloxane, a silazane, dimethylsilane dimethylamine (DMSDMA), trimethylsilane dimethylamine (TMSDMA), bis(dimethylamino)dimethylsilane (BDMADMS), N,O-bistrimethylsilyltrifluoroacetamide (BSTFA), or trimethylsilylpyrrole (TMS-pyrrole).

11. The method of claim 1 , wherein the first metal layer comprises Ru, Co, or W, and the second metal comprises Cu, Ru, Co, or W.

12. 1. A method for processing a substrate, the method comprising: performing a cyclic chemical vapor deposition (CVD) process, the substrate having a dielectric layer with a recess and a first metal layer at the bottom of the recess; and One cycle of the cyclic CVD process comprises: treating the substrate with a small molecule inhibitor (SMI), wherein the SMI selectively adsorbs onto the first metal layer and coats the surface of a second metal formed on the first metal layer; After the step of treating the substrate with the SMI, treating the substrate with a large molecule inhibitor (LMI), wherein the LMI is selectively adsorbed onto the dielectric layer and coats the sidewalls of the dielectric layer in the recess, and the LMI has a larger molecular weight or volume than the SMI; heating the substrate to remove the SMI from over the second metal and expose the second metal, with the LMI remaining on the sidewalls; depositing the second metal on the first metal layer in the recess, the LMI covering the sidewalls preventing deposition of the second metal on the dielectric layer; A method comprising:

13. the step of depositing the second metal deposits second metal nuclei on a portion of the sidewall; 13. The method of claim 12, wherein one of the cyclic CVD processes further comprises removing the second metal nuclei from the portion of the sidewall.

14. The method of claim 12 , wherein the cyclic CVD process fills the recess without forming voids.

15. 13. The method of claim 12, wherein the LMI comprises silane, and the second metal filling the recess does not contain detectable silicon or silane impurities.

16. 1. A method for processing a substrate, the method comprising: exposing the substrate to a first vapor containing a small molecule inhibitor (SMI), the substrate having a dielectric surface and a first metal surface, the SMI selectively adsorbing to the first metal surface relative to the dielectric surface; exposing the substrate to a second vapor containing a large molecule inhibitor (LMI), wherein the LMI selectively adsorbs onto the dielectric surface and the adsorbed SMI prevents the LMI from adsorbing onto the first metal surface; removing the SMI from the first metal surface without removing the LMI from the dielectric surface; depositing a second metal on the first metal surface by chemical vapor deposition (CVD), the deposition rate on the first metal surface being at least 100 times that on the dielectric surface; A method comprising:

17. The removing step is carried out at a substrate temperature between 250° C. and 400° C. using dihydrogen (H ２ 17. The method of claim 16, further comprising treating the substrate with a gas comprising:

18. 17. The method of claim 16, wherein the first metal surface comprises Ru, Co, Mo, or W and the second metal comprises Cu, Ru, Co, Mo, or W.

19. The method of claim 16 , wherein the SMI does not include silicon and the LMI includes silicon.

20. the substrate has a recess, the recess having the dielectric surface as a sidewall and the first metal surface as a bottom; 17. The method of claim 16, wherein the recess has a critical dimension (CD) between 10 nm and 65 nm.

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