Integrated circuits employing multi-pattern metallization to optimize metal interconnect spacing and related manufacturing methods - Patents.com

Abstract

An integrated circuit (IC) includes transistors formed in a diffusion region. In each transistor, a source and a drain extend in a first direction, and a gate is disposed on the diffusion region between the source and drain. To reduce a connection resistance through at least one of the source and drain metal lines connected to the source and drain of the transistor, one of the source and drain metal lines extends further in the first direction than the other to provide an additional via landing area to support an interconnect via having a reduced resistance without increasing the side-to-side capacitance between the source and drain metal lines. Increasing the via landing area reduces the connection resistance to the source and / or drain. By providing an extending source and / or drain metal line, the via landing area can be shifted in the first direction to reduce the via capacitance.

Description

[Technical field]

[0001] Priority Application This application claims priority to U.S. patent application Ser. No. 17 / 659,214, filed April 14, 2022, entitled “INTEGRATED CIRCUITS (ICS) EMPLOYING MULTI-PATTERN METALLIZATION TO OPTIMIZE METAL INTERCONNECT SPACING FOR IMPROVED PERFORMANCE AND RELATED FABRICATION METHODS,” which is incorporated by reference in its entirety. [Background technology]

[0002] I. Field of Disclosure The technology of this disclosure relates generally to integrated circuits, and more particularly to metal interconnects formed in metal layers using multi-pattern metallization.

[0003] II. Background Meeting market demands for smaller electronic devices that consume less power while providing higher levels of functionality (i.e., more functionality at higher levels of performance) drives the continued development of new generations of integrated circuits and the semiconductor circuits therein. Semiconductor circuits include transistors formed in semiconductor materials in and / or on a substrate, and the transistors are electrically connected to the circuit by metal interconnects formed in layers above the substrate. With each new generation of semiconductor technology, the transistors become smaller and the metal interconnects connecting the transistors in the circuit become smaller and closer together. The narrow metal interconnects that provide signals or power to the transistors cause high connection resistance in the electrical circuit, which increases power consumption and / or reduces performance. Placing metal interconnects close to each other can increase circuit capacitance, which can also slow circuit performance. Thus, there is a need for a method to achieve better electrical circuit performance using existing manufacturing techniques. Summary of the Invention

[0004] Embodiments disclosed in the detailed description include integrated circuits (ICs) employing multi-pattern metallization to optimize metal interconnect spacing for improved performance. Related methods of manufacturing ICs with optimized metal interconnect spacing are also disclosed. The IC includes one or more transistors formed in a diffusion region. The IC includes metal lines in a metal layer coupled to respective sources and drains of the transistors to provide signal routing and / or power to the transistors. In each transistor, the source and drain extend in a first direction, and a gate is disposed on the diffusion region between the source and drain. The metal lines include, in each transistor, a source metal line coupled to the source and a drain metal line coupled to the drain to provide connectivity to the source and drain of the transistor. In an exemplary embodiment, one of the source metal line and the drain metal line extends farther in the first direction than the other of the source metal line and the drain metal line to reduce a connection resistance through at least one of the source metal line and the drain metal line connected to the source and drain, respectively, of the transistor. In this way, additional via landing areas are provided to support increased area interconnect vias for reduced resistance without increasing side-to-side capacitance between the source and drain metal lines. Increasing the area of ​​the vias reduces the connection resistance to the source and / or drain. Providing an extending source and / or drain metal line also allows the via landing area to be moved farther in a first direction to reduce via-to-via capacitance. In some examples, one of the source and drain metal lines extends farther in a first direction and the other of the drain and source metal lines extends farther in the opposite direction to reduce the interconnect resistance. In some examples, the source and drain metal lines are formed in the same metal layer with different metallization patterns.

[0005] Exemplary aspects disclosed herein include an integrated circuit (IC) comprising a semiconductor including a diffusion region and a transistor including a source and a drain each disposed within the diffusion region. The IC further comprises a metal layer comprising a source metal line coupled to the source and extending in a first direction and a drain metal line coupled to the drain and extending in the first direction. A first one of the source and drain metal lines extends further in the first direction than a second one of the source and drain metal lines.

[0006] In another exemplary aspect, a method of manufacturing an integrated circuit is disclosed. The method includes forming a transistor including a source and a drain in a semiconductor diffusion region. The method further includes forming a metal layer including forming a source metal line coupled to the source and extending in a first direction. The forming metal layer further includes forming a drain metal line coupled to the drain and extending in the first direction. A first one of the source and drain metal lines is formed to extend farther in the first direction than a second one of the source and drain metal lines.

[0007] In another exemplary aspect, a transistor circuit is disclosed. The transistor circuit includes a diffusion region and a source and a drain each disposed within the diffusion region. The transistor circuit further includes a metal layer including a source metal line coupled to the source and extending in a first direction and a drain metal line coupled to the drain and extending in the first direction. A first one of the source metal line and the drain metal line extends farther in the first direction than a second one of the source metal line and the drain metal line. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 1 illustrates a top view of an integrated circuit (IC) including source and drain metal lines in a metal layer coupled to the source and drain of a transistor in a semiconductor diffusion region. [Figure 1B]1B is a diagram illustrating a top view of the source and drain metal lines in the IC of FIG. 1A, showing via landing areas for the vias on the top surface of the source and drain metal lines. [Figure 1C] FIG. 1C illustrates a top view of the source and drain metal lines of FIG. 1B showing via landing areas for the vias on the bottom surfaces of the source and drain metal lines. [Diagram 2] 1 is a flowchart of an exemplary method of manufacturing an IC that includes one of the source and drain metal lines extending farther in one direction to increase a via landing area for reduced interconnect resistance. [Figure 3A] FIG. 1 illustrates a top view of an example IC in which one of the source and drain metal lines of a transistor extends farther in one direction than the other metal line to increase the via landing area for reduced interconnect resistance. [Figure 3B] FIG. 3B is a diagram showing a top view of the source and drain metal lines of a transistor in the IC of FIG. 3A, showing an increased via landing area for a via on the top surface of one of the source and drain metal lines to which it extends. [Figure 3C] FIG. 3B illustrates a top view of the source and drain metal lines of a transistor in the IC of FIG. 3A, showing a shifted via landing area for a via on the bottom surface of one of the source and drain metal lines extending therethrough for reduced via capacitance. [Figure 4] FIG. 1 illustrates a top view of an example IC in which either the source or drain metal lines of a transistor are extended various distances farther in a first direction to increase and shift the via landing area of ​​at least one via. [Figure 5A] FIG. 1 illustrates a top view of an example IC in which either the drain or source metal lines of a transistor are extended farther in a second direction to increase and shift the via landing area of ​​at least one via. [Figure 5B]FIG. 5B illustrates a top view of the drain and source metal lines of a transistor in the IC of FIG. 5A, showing an increased via landing area for a via on the top surface of one of the drain and source metal lines extending therethrough. [Figure 5C] FIG. 5B illustrates a top view of the drain and source metal lines of a transistor in the IC of FIG. 5A, showing a via landing area shifted in a second direction for a via on the bottom surface of one of the drain and source metal lines to which it extends for reduced via capacitance. [Figure 6] FIG. 2 illustrates a top view of an example IC in which drain metal lines of transistors extend farther in a first direction than source metal lines by a different distance to increase the via landing area of ​​the via. [Figure 7] FIG. 1 is a top view of an exemplary IC in which a drain metal line of a transistor extends farther in a first direction than a source metal line of the transistor, and the source metal line extends farther in a second direction than the drain metal line, in order to increase the via landing area size to reduce resistance without increasing capacitance, and to shift the via landing area to reduce capacitance. [Figure 8] FIG. 8 is a block diagram of an exemplary wireless communication device including a radio frequency integrated circuit (RFIC) including an exemplary IC, the IC of FIGS. 3A-7, in which at least one of the source and drain metal lines of a transistor extends farther in one direction than the other metal lines to increase the via landing area for reduced interconnect resistance. [Figure 9] FIG. 8 is a block diagram of an example processor-based system that may include an RFIC including an example IC including the ICs of FIGS. 3A-7, in which at least one of the source and drain metal lines of a transistor extends farther in one direction than the other metal lines to increase via landing area for reduced interconnect resistance. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Some exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0010] Embodiments disclosed in the detailed description include integrated circuits (ICs) employing multi-pattern metallization to optimize metal interconnect spacing for improved performance. Related methods of manufacturing ICs with optimized metal interconnect spacing are also disclosed. The IC includes one or more transistors formed in a diffusion region. The IC includes metal lines in a metal layer coupled to respective sources and drains of the transistors to provide signal routing and / or power to the transistors. In each transistor, the source and drain extend in a first direction, and a gate is disposed on the diffusion region between the source and drain. The metal lines include, in each transistor, a source metal line coupled to the source and a drain metal line coupled to the drain to provide connectivity to the source and drain of the transistor. In an exemplary embodiment, one of the source metal line and the drain metal line extends farther in the first direction than the other of the source metal line and the drain metal line to reduce a connection resistance through at least one of the source metal line and the drain metal line connected to the source and drain, respectively, of the transistor. In this way, additional via landing areas are provided to support increased area interconnect vias for reduced resistance without increasing side-to-side capacitance between the source and drain metal lines. Increasing the area of ​​the vias reduces the connection resistance to the source and / or drain. Providing an extending source and / or drain metal line also allows the via landing area to be moved farther in a first direction to reduce via-to-via capacitance. In some examples, one of the source and drain metal lines extends farther in a first direction and the other of the drain and source metal lines extends farther in the opposite direction to reduce the interconnect resistance. In some examples, the source and drain metal lines are formed in the same metal layer with different metallization patterns.

[0011] Before describing, beginning with FIG. 2, an example IC in which at least one of a transistor's source and drain metal lines extends farther in one direction than the other metal lines to increase via landing area for reduced interconnect resistance, a conventional IC 100 will first be described with reference to FIGS. 1A-1C.

[0012] 1A is a diagram illustrating a top view of an IC 100 including a source metal line 102 and a drain metal line 104 in a metal layer 106. The top view of FIG. 1A is provided to illustrate features of the metal layer 106. The source metal line 102 and the drain metal line 104 each provide a connection to a source 108 and a drain 110, respectively, of a transistor 112 in a diffusion region 114 of a semiconductor 116. The source metal line 102 and the drain metal line 104 are part of a metal interconnect that may connect the transistors 112 to each other and / or to an external circuit (not shown). The diffusion region 114 may include additional transistors 112 not shown in FIG. 1A, and the semiconductor 116 may include additional diffusion regions 114.

[0013] To increase the number of transistors 112 that can fit within an IC 100, the dimensions of the transistors 112 and the metal features of the metal interconnects, including the source metal line 102 and the drain metal line 104, are reduced with each technology generation. However, such reduction is limited by the physical limitations of the technology. For example, the metal layer 106, including the source metal line 102 and the drain metal line 104, may be formed in a photolithography process using a metallization pattern, as known in the art. The limitations of this method, including optical limitations, limit how small the dimensions of the metal features can be to be reliably formed with the metallization pattern. These dimensions may include the minimum width of the metal features (e.g., metal lines) as well as the minimum allowable spacing or separation distance between the metal features. One example of such a minimum spacing limitation is the side-to-side distance D between the source metal line 102 and the drain metal line 104. SS-MLOne technique used to overcome the limitations of metallization patterns is to use a first metallization pattern to form some of the features in metal layer 106 and a second metallization pattern to form other features in metal layer 106. Features formed by different metallization patterns do not have the same minimum distance as features in the same metallization pattern. Using different metallization patterns, features can be placed closer together than the minimum allowable separation distance of a single metallization pattern. Other examples of spacing limitations are discussed below in the detailed description of the features of IC 100 of FIG. 1A.

[0014] As described above, each of the transistors 112 includes one of the sources 108 and one of the drains 110 that are portions of the diffusion region 114 that extend in the +Y-axis (positive Y-axis) direction across the diffusion region 114. Each of the transistors 112 also includes a gate 118 disposed on the diffusion region 114. The gate 118 also extends in the +Y-axis direction over a channel 120 in the diffusion region 114 between the source 108 and the drain 110. A gate voltage V GATE is the current I 112 is provided to gate 118 to control whether a current I flows through channel 120. 112 is the source voltage V supplied to the source 108 by the metal interconnect including the source metal line 102. SRC Based on the drain voltage V DRN is supplied to the drain metal line 104 by a metal interconnect that includes the drain metal line 104. The gate voltage V GATE 1A and may be coupled to each of the gates 118 as described below. The gate metal lines 122 may also be within the metal layer 106 and coupled to the gates 118 by vias 124.

[0015] The gate metal line 122 may be formed with the same metallization pattern as the source metal line 102 and / or the drain metal line 104. In FIG. 1A, the gate metal line 122 is formed with the same metallization pattern as the drain metal line 104. As a result, the side S 122 and the first end 128 of the drain metal line 104 in the +Y-axis direction. SE In FIG. 1A, the source metal line 102 may be formed by the same metallization pattern as the drain metal line 104 and the gate metal line 122, and may have at least a minimum side-to-side spacing distance D between the source metal line 102 and the drain metal line 104. SS-ML , and the side S of the gate metal line 122 122 to the first end 126 of the source metal line 102. SE Alternatively, one of the source metal line 102 or the drain metal line 104 may be formed with a separate metallization pattern.

[0016] As shown in FIG. 1A, the gates 118 of all of the transistors 112 are coupled to a gate metal line 122. Thus, the transistors 112 of FIG. 1A each have a respective current I 112 The gate voltage V GATE This may be done, for example, to provide a greater drive strength than can be driven by one of the transistors 112 due to its small size. The IC 100 also controls the source voltage V SRC or drain voltage V DRN The signal metal line 130 may be coupled to at least one of the source metal line 102 and the drain metal line 104 to provide a side S 130 is the distance D between the second end 132 of the source metal line 102 and the second end 134 of the drain metal line 104. ESThe IC 100 also includes alternate gates 136 between the transistors. The alternate gates 136 may be inactive, non-conductive features (e.g., dummy gates). In some examples, the alternate gates 136 may be used to interconnect transistors on the IC 100. In some examples, the alternate gates 136 may be additional gates 118 for controlling channels on each side of the drain metal line 104 and / or the source metal line 102. In such examples, the additional gates 118 are coupled to the gate metal line 122 by vias 124. In this regard, it should also be noted that each of the source 108 and drain 110 may function as either a source or a drain of the transistor 112 depending on the polarity of the voltage applied between the source 108 and drain 110.

[0017] FIG. 1B is a diagram illustrating a top view of the source metal line 102 and the drain metal line 104 of one of the transistors 112 of FIG. 1A. FIG. 1B also includes a gate 118, a gate metal line 122, and a signal metal line 130. FIG. 1B is provided to show a via landing area 140 for a via 142 disposed on a top surface 144 of the source metal line 102 and the drain metal line 104. Here, the via landing area 140 on the source metal line 102 is the same size as the via landing area 140 on the drain metal line 104. Via Landing Area A 140 1 shows a cross-sectional area of ​​a via landing area 140 that couples metal layer 106 to a higher level of metal (not shown). For example, metal layer 106 may be a first metal layer M1, and via 142 may be coupled to a second metal layer M2 or a higher metal layer (e.g., M3 or M4). The resistance of via landing area 140 is expressed as a function of the cross-sectional via landing area A. 140 Therefore, the cross-sectional via landing area A of the via 142 is inversely proportional to 140Increasing the resistance of the metal interconnect to transistor 112 reduces the resistance in the metal interconnect to transistor 112. Reducing the resistance in the metal interconnect to transistor 112 can reduce power consumption and improve circuit performance. However, there are limitations to via formation, which may include limitations on via-to-via separation distance in the +Y axis direction, which may limit the number of vias used, and / or limitations on side-to-side via overlap to minimize via-to-via capacitance.

[0018] 1C is a diagram illustrating another top view of the source metal line 102 and the drain metal line 104 of the transistor 112 of FIG. 1B. FIG. 1C is provided to illustrate the via landing area 150 for the via 152 disposed on the bottom surface 154 of the source metal line 102 and the drain metal line 104. The via landing area 150 on the source metal line 102 is the same size as the via landing area 150 on the drain metal line 104. Cross-section Via Landing Area A of the Via Landing Area 150 150 is the cross-sectional area of ​​a via (not shown) that couples the metal layer 106 to a lower level metal or diffusion region 114. For example, via landing area 150 is the cross-sectional via landing area A of a via 152 that couples the source metal line 102 to the source 108 and the drain metal line 104 to the drain 110. 150 Shows.

[0019] 1B and 1C are also provided to show that the vias 142, 152 on the source metal line 102 face off against the vias 142, 152 on the drain metal line 104 (i.e., on either side of the gate 118). Capacitance between metal interconnects can increase the delay of the transistor 112. The metal interconnects to the transistor 112 include the source metal line 102, the drain metal line 104, and the vias 142, 152. Thus, capacitance between such features can impair the performance of a circuit including the transistor 112.

[0020] Specifically, there is a capacitance C1 between the source metal line 102 and the drain metal line 104 that depends on the side-to-side distance D1. The capacitance C1 also depends on the length L1 over which the source metal line 102 and the drain metal line 104 face each other. The source metal line 102 in Figures 1A-1C is the same length as the drain metal line 104, and they face each other over their entire length. Thus, the length of the source metal line 102 is the length L1 that creates the capacitance C1.

[0021] There is also a capacitance C2 between the vias 142 on the top surface 144 of the source metal line 102 and the drain metal line 104, and there is a capacitance C3 between the vias 152 on the bottom surface 154 of the source metal line 102 and the drain metal line 104. The capacitance C2 depends on the length L2 that the vias 142 are parallel to each other and the distance D2 between them. The capacitance C3 depends on the length L3 that the vias 152 are parallel to each other and the distance D3 between them.

[0022] Another example of a manufacturing limitation that may be imposed on metal features within a single metallization pattern is the +Y-axis distance D between the vias 142 in FIG. 142 and the distance D in the +Y-axis direction between the vias 152 in FIG. 152 Distance D 142 and D. 152 limits the number of vias 142, 152 that can be coupled to the source metal line 102 and the drain metal line 104 within the length L1. One way to reduce the resistance between the source 108 and the source metal line 102 is to increase the area of ​​the vias 152, such as by increasing the number of vias 152. An alternative to increasing the number of vias 152 would be to increase the cross-sectional area of ​​the existing vias 152. However, both of these methods increase the distance D between the vias 152. 152 , and the distance from the via 152 to the first ends 126, 128 of the source metal line 102 and the drain metal line 104, and the distance from the via 152 to the second ends 132, 134, all of which must fit within the length L1.

[0023] FIG. 2 is a flow chart of an example method 200 for fabricating the example IC 300 of FIGS. 3A-3C, which illustrates the side-to-side capacitance C between a source metal line 302 and a drain metal line 304. SS-ML 3B and 3C ) for reduced interconnect resistance without increasing the resistance of the via landing area 306. The method 200 includes forming transistors 312 each having a source 314 and a drain 316 in a diffusion region 308 of a semiconductor 310 (block 202), forming a metal layer 318 (block 204), including forming a source metal line 302 coupled to the source 314 and extending in a first direction (the +Y direction) (block 206), and forming a drain metal line 304 coupled to the drain 316 and extending in the first direction (the +Y direction) (block 208). In the method 200, a first metal line of the source metal line 302 and the drain metal line 304 is formed to extend farther in a first direction (the +Y-axis direction) than a second metal line of the source metal line 302 and the drain metal line 304 (block 210).

[0024] 3A illustrates a top view of an example IC 300 in which a first one of the source and drain metal lines 302 and 304 (e.g., the first metal line) of a transistor 312 extends further in a first direction (e.g., in the +Y-axis direction) than a second one of the source and drain metal lines 302 and 304 (e.g., the second metal line). Extending the first metal line in this manner provides additional length in the +Y-axis direction to increase the via landing area 306 (see FIG. 3B) for reduced interconnect resistance while still maintaining the minimum via-to-via distance constraint. Because the drain metal line 304 does not extend in the same direction in the +Y-axis direction to correspond to the source metal line 302, the side-to-side capacitance C between the source and drain metal lines 302 and 304 increases. SS-MLdoes not increase. It should be noted that the various terms used herein for the minimum distance allowed for the metallization patterns can include minimum separation distances and minimum spacing distances, among other variations that refer to the design rules used in the manufacture of features of the metal layer having the metallization patterns.

[0025] The source 314 and the drain 316 are disposed within a diffusion region 308. The diffusion region 308 is a region of a semiconductor 310 (e.g., silicon) doped with at least one of an N-type dopant and a P-type dopant (i.e., a pentavalent or trivalent material). A source metal line 302 is coupled to the source 314 and extends in a first direction, which is the +Y-axis direction in FIG. 3A. A drain metal line 304 is coupled to the drain 316 and also extends in the first direction. Each of the transistors 312 in the IC 300 includes a gate 324 disposed on the diffusion region 308 between the source metal line 302 and the drain metal line 304. The IC 300 also includes a gate metal line 326 that extends in a second direction, which is the X-axis direction in the example of FIG. 1A. The gate metal line 326 is coupled to the gate 324 of the transistor 312 by a via 327. A voltage V on the gate metal line 326 is connected to the gate 324 of the transistor 312 by a via 327. GATEis provided to each of the gates 324 to activate the transistors 312. In this way, the transistors 312 in this example are coupled in parallel to provide a larger drive current capability. However, the IC 300 is only an example, and the exemplary aspects disclosed herein are not limited to ICs with multiple transistors 312 coupled in parallel. In addition, the IC 300 includes an alternate gate 325, which may be an inactive non-conductive feature (e.g., a dummy gate). In some examples, the alternate gate 325 may be used to interconnect transistors on the IC 300. In some examples, the alternate gate 325 may be an additional gate 324 to control the current flow on each side of the drain metal line 304 and / or the source metal line 302. In such examples, the alternate gate 325 is coupled to the gate metal line 326 by an additional via 327 (not shown). Those skilled in the art should recognize that the source 314 and the drain 316 are portions of the diffusion region 308 that may function as a source 314 under a first voltage applied to one of the transistors 312 and as a drain 316 under a second voltage.

[0026] The source metal lines 302 extend in a first direction (e.g., a +Y-axis direction) and the gate metal lines 326 extend in a second (X-axis) direction, so that the source metal lines 302 are orthogonal to the gate metal lines 326 in this example. Thus, each of the source metal lines 302 includes a first end 328 that is proximal to (i.e., located near) the gate metal line 326 and a second end 330 that is distal to (i.e., located away from) the gate metal line 326. Similarly, each of the drain metal lines 304 includes a first end 332 that is proximal to (i.e., located away from) the gate metal line 326 and a second end 334 that is distal to (i.e., located away from) the gate metal line 326. In the example of FIG. 3A, the first end 328 of the source metal line 302 extends farther in the +Y-axis direction than the first end 332 of the drain metal line 304. In other words, the source metal to gate metal distance D between the first end 328 of the source metal line 302 and the gate metal line 326 is SGis the drain metal to gate metal distance D between the first end 332 of the drain metal line 304 and the gate metal line 326 DG is less than.

[0027] In the example of FIG. 3A, the source metal line 302 is closer to the gate metal line 326 than the drain metal line 304, but in alternative embodiments of the disclosed aspects, the first end 332 of the drain metal line 304 may be further in the +Y-axis direction than the first end 328 of the source metal line 302. Thus, in the IC 300, the first metal line is one of the source metal line 302 and the drain metal line 304, and extends further in the first direction than the second metal line, which is the other of the source metal line 302 and the drain metal line 304. In the example of FIG. 3A, the first metal line is the source metal line 302. The IC 300 also includes a signal metal line 336 (shown in each of FIGS. 3A-3C for reference) extending in a second direction (e.g., in the X-axis direction) that may be coupled to one of the source metal line 302 or the drain metal line 304 of the transistor 312. The signal metal line 336 is at least a minimum separation distance in the +Y direction from the second end 330 and the second end 334 .

[0028] In some examples of IC 300 of FIG. 3A, the drain metal to gate metal distance D DG may be the minimum separation distance allowed in the metallization pattern between the first end 332 of the drain metal line 304 and the side S 326 of the gate metal line 326. As previously mentioned, the source metal to gate metal distance D in FIG. SG is the distance D from the drain metal to the gate metal DG3. Thus, in such an example, the source metal line 302 may not be formed in the same metallization pattern as the drain metal line 304. In an example, the drain metal line 304 and the gate metal line 326 may be formed in a first metallization pattern for forming the metal layer 318, and the source metal line 302 is formed in a second metallization pattern for forming the metal layer 318 to avoid minimum dimension limitations of the metallization patterns, which allows the source metal line 302 to extend farther in the first direction. The extent to which the first end 328 of the source metal line 302 extends in the +Y-axis direction may be limited based on capacitance considerations between the source metal line 302 and the gate metal line 326.

[0029] 3B and 3C are provided to illustrate the changes that can be made to the vias above and below the source metal line 302 by extending the source metal line 302. FIG. 3B illustrates a top view of the source metal line 302 and drain metal line 304 of one of the transistors 312 in the IC 300 of FIG. 3A. FIG. 3B illustrates a via landing area 306 on the top surface 342 of the source metal line 302. The via landing area 306 is a cross-sectional area A of a via 344 located on the top surface 342. 344 3B, the length of the via 344 in the first direction can be increased to increase the resistance of the via 344. This reduces the resistance of the via 344. Additionally, in FIG. 3B, it can be seen that the via landing region 306 is shifted in the first direction so that it is not directly opposite the via 346 on the drain metal line 304. As a result of shifting the via landing region 306, the capacitance between the via 344 and the via 346 is reduced. Note again that while this example shows the source metal line 302 extending in the +Y direction to reduce the resistance in the connection to the source 314, in an alternative, the drain metal line 304, rather than the source metal line 302, can similarly extend in the +Y direction to reduce the resistance in the connection to the drain 316. In another alternative, the first of the source metal line 302 and the drain metal line 304 can extend in the -Y direction, as shown below.

[0030] 3C is a diagram illustrating a top view of the source metal line 302 and the drain metal line 304 of the transistor 312 of FIG. 3B. FIG. 3C shows a via landing area 348 for a via 350 on a bottom surface 352 of the extending source metal line 302. A via 354 couples the drain metal line 304 to the drain 316. In FIG. 3C, the via 350 coupled to the source 314 is shifted in the +Y direction away from the via 354 coupled to the drain 316 to reduce the via-to-via capacitance while still maintaining the minimum via-to-via spacing constraint. Here, the via 350 coupled to the source 314 is not resized in this example, although it could be increased in size to reduce resistance.

[0031] FIG. 4 is a top view of an example IC 400 in which source metal lines 402(1)-402(4) of a transistor 406 extend farther in a first direction (e.g., in the +Y-axis direction) than drain metal lines 404(1)-404(4) by different distances to increase the size of the via landing area (not shown) to reduce resistance and to shift the via landing area to reduce via-to-via capacitance. In another aspect, IC 400 corresponds to IC 300 of FIGS. 3A-3C. In FIG. 4, source metal line 402(1), source metal line 402(2), and source metal line 402(4) each have a separation distance D between gate metal line 410 and first ends 412 of corresponding drain metal lines 404(1), 404(2), and 404(4). 408 A separation distance D between the first end 408 of the source metal line 402 and the gate metal line 410 that is less than 412 (1), D 408 (2), D 408As shown, source metal line 402(2) extends farther in the +Y-axis direction than drain metal line 404(2), but does not extend all the way to source metal lines 402(1) and 402(4). Thus, the via coupled to source metal line 402(2) may be larger in area than the via coupled to source metal line 402(3), but not as large as the via coupled to source metal lines 402(1) and 402(4). In this regard, it may be determined that an intermediate reduction in resistance or capacitance in the metal interconnect coupled to source metal line 402(2) is sufficient to meet the requirements. In another example, any of source metal lines 402(1)-402(4) may extend any desired distance farther than drain metal lines 404(1)-404(4). In alternative examples, one or more of the drain metal lines 404(1)-404(4) may extend a different distance farther in the first direction than the source metal lines 402(1)-402(4) to reduce resistance or capacitance. In the example of FIG. 4, each of the source metal lines 402(1)-402(4) and the drain metal lines 404(1)-404(4) are the same distance D from the signal metal line 414. 414 It is.

[0032] FIG. 5A is a diagram of a top view of an exemplary IC 500, showing the length L of a via landing area 508. VIAIn one embodiment, a first one of the drain metal line 502 and the source metal line 504 of the transistor 506 extends farther in a first direction (e.g., in the -Y-axis (negative Y-axis) direction) to provide a greater distance for increasing the resistance of the via 510 (see FIGS. 5B and 5C) and shifting the via landing area 508 of at least one via 510 to reduce capacitance. The drain metal line 502 and the source metal line 504 extend in the first direction on either side of the gate 512. FIG. 5A is provided to illustrate that a first one of the drain metal line 502 and the source metal line 504 may extend away from the gate metal line 514 to achieve reduced resistance in the via 510 and shift the via landing area 508 away from the gate metal line 514 to reduce capacitance with the via 510 on the second metal line (i.e., the second one of the drain metal line 502 and the source metal line 504). In this example, the drain metal line 502 extends beyond the source metal line 504 to avoid increasing the capacitance between the source metal line 504 and the drain metal line 502. In FIG. 5A, the source metal line 504 is a distance D from the signal metal line 516 in a first direction. 504 In some cases, the distance D 504 is the minimum allowable separation distance. In some examples, the drain metal line 502 is spaced a smaller distance D from the signal metal line 516. 502 and may extend to have a distance D 502 may be less than the minimum allowable spacing distance. Thus, drain metal line 502 may be formed with a different metallization pattern than source metal line 504 and signal metal line 516. In other aspects, IC 500 may correspond to ICs 300 and 400 of Figures 3A-4.

[0033] 5B and 5C each show one of the transistors 506 of FIG. 5A including a drain metal line 502 and a source metal line 504 on either side of a gate 512 coupled to a gate metal line 514. One of the drain metal line 502 and the source metal line 504 may be coupled to a signal metal line 516. FIG. 5B shows a via 510 on a top surface 518 of the drain metal line 502 and the source metal line 504. The via 510 on the drain metal line 502 represents an increased via landing area A made possible by extending the drain metal line 502. 510 , and has an increased via landing area A 510 is the minimum via spacing D 510 5C shows a via 522 coupled to a bottom surface 524 of the drain metal line 502 and the source metal line 504. The via 522 coupled to the drain metal line 502 is also shifted in a first direction to reduce the via-to-via capacitance with the via 522 coupled to the source metal line 504. In addition, shifting both the via 522 and the via 510 in a first direction to align the via 522 between the via 510 and the drain 526 can provide a straight vertical path from the drain 526 through the via 522, the drain metal line 502, and the via 510 to a higher metal layer, which reduces the resistance of the metal interconnect to the drain 526.

[0034] 6 is a top view of an example IC 600 in which drain metal lines 602(1)-602(4) of a transistor 604 extend different distances farther in a first direction than source metal lines 606(1)-606(4) to increase the via landing area size and via cross-sectional area, where drain metal lines 602(1)-602(4) and source metal lines 606(1)-606(4) are the same distance D from gate metal line 608. 608 and various distances D 608 (1)~D 608(4). The amount that drain metal line 602 extends determines the amount that the vias can be shifted and the amount that the via landing area can be extended. Drain metal lines 602(1) and 602(4) extend further than drain metal line 602(2). Thus, the vias to drain metal lines 602(1) and 602(4) can have a lower resistance than the via to drain metal line 602(2), which has a lower resistance than the via to drain metal line 602(3). As discussed above, shifting the vias also provides a reduction in capacitance.

[0035] 7 is a top view of an exemplary IC 700 in which a drain metal line 702 of a transistor 704 extends further in a first direction than a source metal line 706 of the transistor 704, and the source metal line 706 extends further in a second direction than the drain metal line 702, in order to increase the size of the via landing area to reduce resistance without increasing capacitance, and to shift the via landing area in each direction to reduce via-to-via capacitance. In this example, metal interconnect resistance can be reduced for both the drain metal line 702 and the source metal line 706, and the source metal line 706 and drain metal line 702 can be extended in a tuned manner in each transistor to achieve different levels of reduction in resistance and capacitance. Although the transistors 704 of FIG. 7 are coupled in parallel to a gate metal line 710, the transistors 704 are not limited in this regard, and the gate metal line 710 shown in FIG. 7 may be coupled in parallel to a gate metal line 710 such that each of the transistors 704 is coupled to a respective gate voltage V GATE Either the source metal line 706 or the drain metal line 702 may be coupled to a signal metal line 712.

[0036] FIG. 8 illustrates an exemplary wireless communication device 800 that may include an exemplary IC, including RF components formed from one or more ICs 802, where at least one of the source and drain metal lines of a transistor extends farther in one direction than the other metal lines to increase via landing area for reduced interconnect resistance, including the ICs of FIGS. 3A-7, according to any of the aspects disclosed herein. The wireless communication device 800 may include or be provided within any of the devices mentioned above, as examples. As shown in FIG. 8, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include a memory that stores data and program codes. The transceiver 804 includes a transmitter 808 and a receiver 810 that support bidirectional communication. In general, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or a portion of the transceiver 804 may be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.

[0037] The transmitter 808 or receiver 810 may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, a signal is frequency converted between RF and baseband in multiple stages, e.g., from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne architecture and the direct-conversion architecture may use different circuit blocks and / or have different requirements. In the wireless communication device 800 of FIG. 8, the transmitter 808 and receiver 810 are implemented with a direct-conversion architecture.

[0038] On the transmit path, a data processor 806 processes data to be transmitted and provides I and Q analog output signals to a transmitter 808. In the example wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1), 812(2) to convert digital signals generated by the data processor 806 into I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0039] Within the transmitter 808, low pass filters 814(1), 814(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the previous digital-to-analog conversion. The low pass filters 814(1), 814(2) may be implemented as an AW filter package 803. Amplifiers (AMPs) 816(1), 816(2) amplify the signals from the low pass filters 814(1), 814(2), respectively, and provide I and Q baseband signals. An upconverter 818 upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator 822 through mixers 820(1), 820(2) to provide an upconverted signal 824. A filter 826 filters the upconverted signal 824 to remove undesired signals caused by frequency upconversion as well as noise in the receive frequency band. A power amplifier (PA) 828 amplifies the upconverted signal 824 from the filter 826 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 830 and transmitted via an antenna 832. Either the low pass filters 814(1) and 814(2) or the filter 826 can be an acoustic wave filter (AW filter) package 803.

[0040] In the receive path, an antenna 832 receives a signal transmitted by a base station and provides a receive RF signal, which is routed through a duplexer or switch 830 and provided to a low noise amplifier (LNA) 834. The duplexer or switch 830 is designed to operate with a specific receive (RX) to TX duplexer frequency separation such that the RX signal is isolated from the TX signal. The received RF signal is amplified by the LNA 834 and filtered by a filter 836 to obtain a desired RF input signal. Downconversion mixers 838(1), 838(2) mix the output of the filter 836 with the I RX LO signal and the Q RX LO signal (i.e., LO_I and LO_Q) from a RX LO signal generator 840 to generate an I baseband signal and a Q baseband signal. The I and Q baseband signals are amplified by AMPs 842(1), 842(2) and further filtered by low pass filters 844(1), 844(2) to obtain I and Q analog input signals, which are provided to data processor 806. Both filter 836 and low pass filters 844(1), 844(2) may be AW filter package 803. In this example, data processor 806 includes analog-to-digital converters (ADCs) 846(1), 846(2) for converting the analog input signals to digital signals for further processing by data processor 806.

[0041] In the wireless communication device 800 of FIG. 8, a TX LO signal generator 822 generates an I TX LO signal and a Q TX LO signal used for frequency up-conversion, while a RX LO signal generator 840 generates an I RX LO signal and a Q RX LO signal used for frequency down-conversion. Each LO signal is a periodic signal having a particular fundamental frequency. A TX phase-locked loop (PLL) circuit 848 receives timing information from the data processor 806 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 822. Similarly, a RX PLL circuit 850 receives timing information from the data processor 806 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 840.

[0042] Wireless communication device 800, which may include the ICs of FIGS. 3A-7 and each include an example IC according to any of the aspects disclosed herein in which at least one of the source and drain metal lines of a transistor extends farther in one direction than the other metal lines to increase via landing area for reduced interconnect resistance, may be provided within or incorporated into any processor-based device. Examples include, but are not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter.

[0043] FIG. 9 illustrates an example of a processor-based system 900 including the IC of FIGS. 3A-7 and including an exemplary IC in which at least one of the source and drain metal lines of a transistor extends farther in one direction than the other metal lines to increase via landing area for reduced interconnect resistance according to any aspect disclosed herein. In this example, the processor-based system 900 includes one or more central processor units (CPUs) 902, sometimes referred to as CPUs or processor cores, each including one or more processors 904. The CPUs 902 may have cache memory 906 coupled to the processors 904 for fast access to temporarily stored data. The CPUs 902 are coupled to a system bus 908, which may interconnect master and slave devices included within the processor-based system 900. As is well known, the CPUs 902 communicate with these other devices by exchanging address, control, and data information via the system bus 908. For example, the CPU 902 may communicate bus transaction requests to the memory controller 910 as an example of a slave device. Although not shown in Figure 9, multiple system buses 908 may be provided. Each system bus 908 constitutes a different fabric.

[0044] Other master and slave devices may be connected to the system bus 908. As shown in FIG. 9, these devices may include, by way of example, a memory system 912 including a memory controller 910 and one or more memory arrays 914, one or more input devices 916, one or more output devices 918, one or more network interface devices 920, and one or more display controllers 922. The input devices 916 may include any type of input device including, but not limited to, input keys, switches, voice processors, and the like. The output devices 918 may include any type of output device including, but not limited to, audio, video, other visual indicators, and the like. The network interface device(s) 920 may be any device configured to enable the exchange of data to and from a network 924. The network 924 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH network, and the Internet. The network interface device(s) 920 may be configured to support any type of communication protocol desired.

[0045] The CPU 902 may also be configured to access display controller(s) 922 via the system bus 908 to control information sent to one or more displays 926. The display controller(s) 922 send information to be displayed to the display(s) 926 via one or more video processors 928, which process the information to be displayed in a format suitable for the display(s) 926. The display(s) 926 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light-emitting diode (LED) display, etc.

[0046] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described with respect to the aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The master and slave devices described herein may be employed in any circuit, hardware component, IC, or IC chip, as examples. The memories disclosed herein may be of any type and size and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may realize the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0047] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0048] Aspects disclosed herein may be embodied in hardware and instructions stored in the hardware and may be embodied in, for example, a Random Access Memory (RAM), a flash memory, a Read-Only Memory (ROM), an Electrically Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0049] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that many different modifications may be made to the operational steps shown in the flow chart diagrams, as would be readily apparent to one of ordinary skill in the art. One of ordinary skill in the art will also understand that information and signals may be represented using a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0050] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0051] The following numbered clauses describe example implementations. 1. An integrated circuit comprising: a semiconductor including a diffusion region; a transistor including a source and a drain each disposed within the diffusion region; A metal layer, a source metal line coupled to the source and extending in a first direction; a metal layer comprising a drain metal line coupled to the drain and extending in a first direction; An integrated circuit, wherein a first one of the source and drain metal lines extends farther in a first direction than a second one of the source and drain metal lines. 2. The transistor further comprises a gate disposed on the diffusion region between the source metal line and the drain metal line, the gate extending in a first direction; The integrated circuit further comprises a gate metal line coupled to the gate, the gate metal line extending in a second direction; Each of the first metal line and the second metal line is a proximal first end of a gate metal line; and a distal second end of the gate metal line. 3. The integrated circuit of clause 2, wherein a first distance in a first direction between a first end of the first metal line and the gate metal line is less than a second distance in the first direction between the first end of the second metal line and the gate metal line. 4. 3. The integrated circuit of claim 2, wherein a first distance in a first direction between a first end of the first metal line and the gate metal line is the same as a second distance in the first direction between a first end of the second metal line and the gate metal line. 5. a first via disposed on a surface of the first metal line and adjacent a first end of the first metal line; a second via disposed on the surface of the second metal line and adjacent to the first end of the second metal line; 5. The integrated circuit of any of clauses 2 to 4, wherein a first via landing area of ​​a first via is longer in a first direction than a second via landing area of ​​a second via in the first direction. 6. The integrated circuit of clause 5, wherein the first via landing area is closer to the gate metal line in the first direction than the second via landing area. 7. The semiconductor device further includes a second source metal line and a second drain metal line disposed on either side of a second gate extending in a first direction, the second gate being coupled to the gate metal line; a first one of the second source metal line and the second drain metal line extends further in a first direction than a second one of the second source metal line and the second drain metal line; 7. The integrated circuit of any of clauses 3 to 6, wherein a third distance between a first one of the second source metal line and the second drain metal line and the gate metal line is less than the first distance. 8. a third via disposed on the surface of the first metal line and adjacent to the second end of the first metal line; a fourth via disposed on the surface of the second metal line and adjacent to the second end of the second metal line; 8. The integrated circuit of any of clauses 5 to 7, wherein the third via landing area is closer to the gate metal line in the first direction than the fourth via landing area. 9. The integrated circuit of any of clauses 1 to 10 integrated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a mobile phone, a smartphone, a Session Initiation Protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter. 10. A method of manufacturing an integrated circuit, comprising: forming a transistor including a source and a drain in a semiconductor diffusion region; forming a metal layer, forming a source metal line coupled to the source and extending in a first direction; forming a metal layer including forming a drain metal line coupled to the drain and extending in a first direction; A method, wherein a first one of the source and drain metal lines is formed to extend farther in a first direction than a second one of the source and drain metal lines. 11. forming a gate on the diffusion region between the source metal line and the drain metal line, the gate extending in a first direction; forming a gate metal line extending in a second direction; Each of the first metal line and the second metal line is a proximal first end of a gate metal line; and a distal second end of the gate metal line. 12. a first end of the first metal line is a first distance from the gate metal line; the first end of the second metal line is a second distance from the gate metal line; 12. The method of claim 11, wherein the first distance is less than the second distance. 13. a first end of the first metal line is a first distance from the gate metal line; the first end of the second metal line is a second distance from the gate metal line; 12. The method of claim 11, wherein the first distance is the same as the second distance. 14. forming a first via disposed on a surface of the first metal line and adjacent a first end of the first metal line; forming a second via disposed on a surface of the second metal line and adjacent to a first end of the second metal line; 14. The method of any of clauses 11-13, wherein a first via landing area of ​​a first via is longer in a first direction than a second via landing area of ​​a second via in the first direction. 15. The method of claim 14, further comprising forming the first via landing area closer to the gate metal line in the first direction than the second via landing area. 16. The method further includes forming a second source metal line and a second drain metal line disposed on either side of a second gate extending in the first direction, the second gate being coupled to the gate metal line; a first one of the second source metal line and the second drain metal line extends further in a first direction than a second one of the second source metal line and the second drain metal line; 16. The method of any of clauses 12-15, wherein a third distance between the gate metal line and a first one of the second source metal line and the second drain metal line is less than the first distance. 17. forming a third via disposed on a surface of the first metal line and adjacent a second end of the first metal line; forming a fourth via disposed on a surface of the second metal line and adjacent a second end of the second metal line; 17. The method of any of clauses 14-16, further comprising forming a third via landing area closer to the gate metal line than the fourth via landing area in the first direction. 18. Forming a metal layer forming a second metal line and a gate metal line in a first metallization pattern; 18. The method of any of clauses 11-17, further comprising forming the first metal lines in a second metallization pattern. 19. A transistor circuit comprising: A diffusion region; a source and a drain each disposed within the diffusion region; A metal layer, a source metal line coupled to the source and extending in a first direction; a metal layer comprising a drain metal line coupled to the drain and extending in a first direction; A transistor circuit, wherein a first one of the source and drain metal lines extends further in a first direction than a second one of the source and drain metal lines.

Claims

1. 1. An integrated circuit comprising: a semiconductor including a diffusion region; a transistor including a source and a drain, each of the source and the drain being disposed within the diffusion region; A metal layer, a source metal line coupled to the source and extending in a first direction; a metal layer comprising a drain metal line coupled to the drain and extending in the first direction; the transistor further comprises a gate disposed on the diffusion region between the source metal line and the drain metal line, the gate extending in the first direction; the integrated circuit further comprises a gate metal line coupled to the gate, the gate metal line extending along a second direction across a width of the source metal line and the drain metal line, the second direction being orthogonal to the first direction; a first one of the source metal line and the drain metal line extends farther in the first direction than a second one of the source metal line and the drain metal line, and each of the first metal line and the second metal line a proximal first end of the gate metal line; a distal second end of the gate metal line; and Equipped with Integrated circuit.

2. 2. The integrated circuit of claim 1, wherein a first distance in the first direction between the first end of the first metal line and the gate metal line is less than a second distance in the first direction between the first end of the second metal line and the gate metal line.

3. a first via disposed on a surface of the first metal line and adjacent to the first end of the first metal line; a second via disposed on a surface of the second metal line and adjacent to the first end of the second metal line; 2. The integrated circuit of claim 1, wherein a first via landing area of ​​the first via is longer in the first direction than a second via landing area of ​​the second via in the first direction.

4. 4. The integrated circuit of claim 3, wherein the first via landing area is closer to the gate metal line in the first direction than the second via landing area.

5. a third via disposed on the surface of the first metal line and adjacent the second end of the first metal line; a fourth via disposed on the surface of the second metal line and adjacent the second end of the second metal line; 4. The integrated circuit of claim 3, wherein a third via landing area is closer to the gate metal line in the first direction than a fourth via landing area.

6. 10. The integrated circuit of claim 1 integrated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cell phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter.

7. 1. A method of manufacturing an integrated circuit, comprising: forming a transistor including a source and a drain in a semiconductor diffusion region; forming a metal layer, forming a source metal line coupled to the source and extending in a first direction; forming a drain metal line coupled to the drain and extending in the first direction; forming a metal layer; forming a gate disposed on the diffusion region between the source metal line and the drain metal line, the gate extending in the first direction; forming a gate metal line coupled to the gate, the gate metal line extending along a second direction across a width of the source metal line and the drain metal line, the second direction being orthogonal to the first direction; Including, A first metal line of the source metal line and the drain metal line is formed to extend farther in the first direction than a second metal line of the source metal line and the drain metal line, and each of the first metal line and the second metal line is a proximal first end of the gate metal line; a distal second end of the gate metal line; and Equipped with method.

8. the first end of the first metal line is a first distance from the gate metal line; the first end of the second metal line is a second distance from the gate metal line; The method of claim 7 , wherein the first distance is less than the second distance.

9. forming a first via disposed on a surface of the first metal line and adjacent the first end of the first metal line; forming a second via disposed on a surface of the second metal line and adjacent to the first end of the second metal line; 8. The method of claim 7, wherein a first via landing area of ​​the first via is longer in the first direction than a second via landing area of ​​the second via in the first direction.

10. 10. The method of claim 9, further comprising forming the first via landing region closer to the gate metal line than the second via landing region in the first direction.

11. forming a second source metal line and a second drain metal line disposed on either side of a second gate extending in the first direction, the second gate being coupled to the gate metal line; a first one of the second source metal line and the second drain metal line extends further in the first direction than a second one of the second source metal line and the second drain metal line; 9. The method of claim 8, wherein a third distance between the gate metal line and the first one of the second source metal line and the second drain metal line is less than the first distance.

12. forming a third via disposed on the surface of the first metal line and adjacent the second end of the first metal line; forming a fourth via disposed on the surface of the second metal line and adjacent the second end of the second metal line; 10. The method of claim 9, further comprising: forming a third via landing region closer to the gate metal line in the first direction than a fourth via landing region.

13. forming the metal layer forming the second metal line and the gate metal line in a first metallization pattern; 8. The method of claim 7, further comprising: forming the first metal lines with a second metallization pattern.

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