Simulated low bitwidth quantization using bit-shifted neural network parameters

Abstract

The processor-implemented method includes bit-shifting a binary representation of a neural network parameter, the neural network parameter having bits b that are less than the number of hardware bits B supported by hardware that processes the neural network parameter. The bit-shifting adds 2 bits to the neural network parameter. B-b The method also multiplies the quantization scale by 2 to get the updated quantization scale. B-b The method further includes quantizing the bit-shifted binary representation with the updated quantization scale to obtain a value of the neural network parameter.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to U.S. provisional patent application No. 63 / 323,450, entitled "SIMULATED LOW BIT-WIDTH QUANTIZATION USING BIT SHIFTED NEURAL NETWORK PARAMETERS," filed on March 24, 2022, which claims the benefit of U.S. provisional patent application No. 18 / 103,428, entitled "SIMULATED LOW BIT-WIDTH QUANTIZATION USING BIT SHIFTED NEURAL NETWORK PARAMETERS," filed on January 30, 2023, the disclosures of which are expressly incorporated by reference in their entireties into this specification.

[0002] Aspects of the present disclosure relate generally to reducing power consumption by neural networks, and more specifically, to bit-shifting neural network parameters to simulate low bit-width quantization. [Background technology]

[0003]

[0003] An artificial neural network may comprise an interconnected group of artificial neurons (e.g., neuron models). An artificial neural network may be a computational device or may be represented as a method to be executed by a computational device. A convolutional neural network (CNN) is a type of feed-forward artificial neural network. A convolutional neural network may include a collection of neurons, each with a receptive field, that collectively tile the input space. Convolutional neural networks, such as deep convolutional neural networks (DCNs), have numerous applications. In particular, these neural network architectures are used in a variety of technologies, such as image recognition, speech recognition, acoustic scene classification, keyword spotting, autonomous driving, and other classification tasks.

[0004]

[0004] Although neural networks have achieved impressive breakthroughs in various fields, they consume a significant amount of power. Recently, neural network quantization (e.g., running neural networks on dedicated low-bit-width integer hardware) has been used to reduce neural network power consumption, since lower bit-width can result in proportionally reduced power consumption. However, designing and manufacturing dedicated low-bit-width hardware is difficult and expensive. Summary of the Invention

[0005]

[0005] The present disclosure is set out in the independent claims, some aspects of which are set out in the dependent claims.

[0006] In an aspect of the disclosure, a processor-implemented method includes bit-shifting, by the processor, a binary representation of a neural network parameter, the neural network parameter having bits b that are less than the number of hardware bits B supported by hardware that processes the neural network parameter. The bit-shifting adds 2 bits to the neural network parameter. B-b The method implemented by the processor also includes multiplying the quantization scale by 2 to obtain an updated quantization scale. B-b The processor-implemented method further includes quantizing, by the processor, the bit-shifted binary representation with the updated quantization scale to obtain a value of the neural network parameter.

[0007] Another aspect of the disclosure is directed to an apparatus. The apparatus includes a memory and one or more processors coupled to the memory. The processor(s) are configured to bit-shift a binary representation of a neural network parameter. The neural network parameter has bits b that are less than a number of hardware bits B supported by hardware that processes the neural network parameter. The bit-shifting adds two bits to the neural network parameter. B-b To obtain the updated quantization scale, the processor(s) also multiply the quantization scale by 2. B-b The processor(s) is further configured to quantize the bit-shifted binary representation with the updated quantization scale to obtain the value of the neural network parameter.

[0008] Another aspect of the present disclosure is directed to an apparatus. The apparatus includes means for bit-shifting a binary representation of a neural network parameter, the neural network parameter having bits b that are less than a number of hardware bits B supported by hardware that processes the neural network parameter. The bit-shifting adds 2 bits to the neural network parameter. B-b The device also multiplies the quantization scale by 2 to obtain the updated quantization scale. B-b The apparatus further includes means for quantizing the bit-shifted binary representation with the updated quantization scale to obtain a value of the neural network parameter.

[0009] In another aspect of the present disclosure, a non-transitory computer readable medium having recorded thereon program code is disclosed. The program code includes program code for, when executed by a processor, bit-shifting a binary representation of a neural network parameter. The neural network parameter had bits b that are less than the number of hardware bits B supported by hardware that processes the neural network parameter. The bit-shifting adds 2 bits to the neural network parameter. B-b The program code also multiplies the quantization scale by 2 to get the updated quantization scale. B-b The program code includes program code for dividing the bit-shifted binary representation by the updated quantization scale to obtain a value of the neural network parameter.

[0010]

[0010] Additional features and advantages of the present disclosure are described below. Those skilled in the art will appreciate that the present disclosure may be easily utilized as a basis for modifying or designing other structures for carrying out the same purpose of the present disclosure. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features believed to be characteristic of the present disclosure, both in terms of its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in conjunction with the accompanying figures. It should be expressly understood, however, that each of the figures is provided for illustration and description only, and is not intended to define the scope of the present disclosure. [Brief description of the drawings]

[0011]

[0011] The features, nature, and advantages of the present disclosure will become more apparent from the detailed description set forth below when read in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Figure 1]

[0012] 1 illustrates an example implementation of a neural network using a system-on-a-chip (SOC) that includes a general-purpose processor, in accordance with some aspects of the present disclosure. [Figure 2A]

[0013] FIG. 1 illustrates a neural network according to an aspect of the present disclosure. [Figure 2B] FIG. 1 illustrates a neural network according to an aspect of the present disclosure. [Figure 2C] FIG. 1 illustrates a neural network according to an aspect of the present disclosure. [Figure 2D]

[0014] FIG. 1 illustrates an exemplary deep convolutional network (DCN), in accordance with aspects of the present disclosure. [Diagram 3]

[0015] FIG. 1 is a block diagram illustrating an example deep convolutional network (DCN), in accordance with aspects of the present disclosure. [Figure 4]

[0016] FIG. 1 is a block diagram illustrating an example software architecture that may modularize artificial intelligence (AI) functionality, according to aspects of the present disclosure. [Diagram 5]

[0017] FIG. 1 is a process flow diagram illustrating a processor-implemented method for reducing power consumption in a neural network by bit shifting, according to an aspect of the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0018] The detailed description of the invention described below with reference to the accompanying drawings illustrates various configurations and does not represent the only configurations in which the described concepts may be practiced. The detailed description of the invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0013]

[0019] Based on the teachings, those skilled in the art should understand that the scope of the present disclosure is intended to encompass any aspect of the present disclosure, whether implemented independently of or in combination with any other aspect of the present disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects described. In addition, the scope of the present disclosure is intended to encompass such an apparatus or method that is practiced using other structures, functions, or structures and functions in addition to or other than the various aspects of the present disclosure described. It should be understood that any aspect of the present disclosure disclosed may be embodied by one or more elements of a claim.

[0014]

[0020] The word "exemplary" is used to mean "serving as an example, instance, or illustration." Any aspect described as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0015]

[0021] Although specific aspects are described, many variations and permutations of these aspects fall within the scope of the present disclosure. Although some benefits and advantages of the preferred aspects are described, the scope of the present disclosure is not limited to any particular benefit, application, or purpose. Rather, the aspects of the present disclosure are intended to be broadly applicable to different technologies, system configurations, networks, and protocols, some of which are illustrated by way of example in the figures and the following description of the preferred aspects. The detailed description and drawings are merely illustrative of the present disclosure, rather than limiting, the scope of the present disclosure being defined by the appended claims and their equivalents.

[0016]

[0022] Some conventional matrix multiplication hardware accelerators divide large matrix multiplications into chunks of weights and activations that can be computed in dedicated multiply-accumulate (MAC) arrays, which can reduce power consumption as a result of data transfers over increased locality. If a bit in an individual MAC array multiplier unit is 0 for two or more consecutive cycles (referred to as a "consecutive 0 bit"), the multiplier can consume less power.

[0017]

[0023] Aspects of the present disclosure introduce low bit-width quantization using the most significant bits (MSBs). In these aspects, the neural network parameter bits are shifted such that the least significant bits (LSBs) are always 0. These aspects can be applied to any type of neural network.

[0018]

[0024] According to an aspect of the present disclosure, in the case of b bits on B-bit hardware where b < B, all values are bit-shifted by only B - b bits. In other words, all values can be multiplied by 2 (B-b) . This multiplication can be canceled by dividing by the corresponding quantization scale by 2 (B-b) . This technique can ensure that the least significant bits of B - b are always 0 for both positive and negative values.

[0019]

[0025] Aspects of the present disclosure may be applicable to quantization for each channel or to any per-block quantization technique. Further, aspects of the present disclosure can enable different simulated bit widths in different channels / blocks. In this case, each block may be shifted by a different number of bits, and each corresponding quantization scale is divided by a different correction factor 2 (b’-B) , where b’ represents the bit width per channel / per block.

[0020]

[0026] Thus, aspects of the present disclosure can be advantageously employed on existing hardware without explicit support for (simulated) low-bitwidth quantization.

[0021]

[0027] 1 shows an example implementation of a system-on-chip (SOC) 100 that may include a central processing unit (CPU) 102 or a multi-core CPU with low-precision multipliers for evaluation of low-bitwidth quantized neural networks. Variables (e.g., neural signals and synaptic weights), system parameters associated with a computational device (e.g., a neural network with weights), delays, frequency bin information, and task information may be stored in a memory block associated with a neural processing unit (NPU) 108, in a memory block associated with the CPU 102, in a memory block associated with a graphics processing unit (GPU) 104, in a memory block associated with a digital signal processor (DSP) 106, in a memory block 118, or distributed across multiple blocks. Instructions executed in the CPU 102 may be loaded from a program memory associated with the CPU 102 or from the memory block 118.

[0022]

[0028] The SOC 100 may also include a GPU 104, a DSP 106, a connectivity block 110 that may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc., as well as additional processing blocks adapted to specific functions, such as a multimedia processor 112 that may detect and recognize gestures. In one implementation, the NPU 108 is implemented in the CPU 102, the DSP 106, and / or the GPU 104. The SOC 100 may also include a sensor processor 114, image signal processors (ISPs) 116, and / or a navigation module 120 that may include a global positioning system.

[0023]

[0029] The SOC 100 may be based on the ARM instruction set. In an embodiment of the present disclosure, the instructions loaded into the general purpose processor 102 may include code for bit-shifting the binary representation of the neural network parameters. The general purpose processor 102 may also shift the quantization scale by two to obtain an updated quantization scale. B-b The general purpose processor 102 may include code for dividing by the updated quantization scale. The general purpose processor 102 may also include code for quantizing the bit-shifted binary representation with the updated quantization scale to obtain the value of the neural network parameter.

[0024]

[0030] Deep learning architectures may perform object recognition tasks by learning to represent inputs at successively higher levels of abstraction within each layer, thereby building useful feature representations of the input data. In this way, deep learning addresses a major bottleneck of traditional machine learning. Prior to the advent of deep learning, machine learning approaches to object recognition problems may have relied heavily on human-designed features, possibly in combination with shallow classifiers. A shallow classifier may be, for example, a two-class linear classifier that can compare a weighted sum of feature vector components to a threshold to predict which class an input belongs to. Human-designed features may be templates or kernels that are adapted to a particular problem domain by an engineer with domain expertise. In contrast, deep learning architectures may learn, but through training, to represent features that are similar to those that a human engineer could design. Furthermore, deep networks may learn to represent and recognize new types of features that humans may not have thought of.

[0025]

[0031] Deep learning architectures may learn a hierarchy of features. When presented with visual data, for example, a first layer may learn to recognize relatively simple features such as edges in the input stream. In another example, when presented with auditory data, the first layer may learn to recognize spectral power at specific frequencies. A second layer, taking as input the output of the first layer, may learn to recognize combinations of features such as simple shapes in the case of visual data, or combinations of sounds in the case of auditory data. For example, higher layers may learn to represent complex shapes in visual data or words in auditory data. Even higher layers may learn to recognize common visual objects or spoken phrases.

[0026]

[0032] Deep learning architectures may work particularly well when applied to problems that have a natural hierarchical structure. For example, classification of electric vehicles may benefit from first learning to recognize wheels, windshields, and other features. These features may be combined in different ways at higher layers to recognize cars, trucks, and planes.

[0027]

[0033] Neural networks may be designed with various connectivity patterns. In feedforward networks, each neuron in a given layer communicates with neurons in a higher layer, so that information is passed from lower layers to higher layers. As described above, hierarchical representations may be constructed in successive layers of a feedforward network. Neural networks may also have recurrent or feedback (also called top-down) connections. In recurrent connections, the output from a neuron in a given layer may be transmitted to another neuron in the same layer. Recurrent architectures may be useful in recognizing patterns across two or more of the input data chunks delivered in sequence to the neural network. Connections from neurons in a given layer to neurons in a lower layer are called feedback (or top-down) connections. Networks with many feedback connections may be useful when recognition of high-level concepts can help discriminate certain low-level features of the input.

[0028]

[0034] The connections between layers of a neural network may be fully connected or locally connected. FIG. 2A shows an example of a fully connected neural network 202. In the fully connected neural network 202, a neuron in a first layer may transmit its output to every neuron in a second layer, so that each neuron in the second layer receives input from every neuron in the first layer. FIG. 2B shows an example of a locally connected neural network 204. In the locally connected neural network 204, a neuron in a first layer may be connected to a limited number of neurons in the second layer. More generally, the locally connected layers of the locally connected neural network 204 may be configured such that each neuron in a layer has the same or similar connectivity pattern, but with connection strengths that may have different values ​​(e.g., 210, 212, 214, and 216). Because higher layer neurons in a given region may receive inputs that are tuned through training to the properties of a limited subset of all inputs to the network, the connectivity patterns of local connections may give rise to spatially distinct receptive fields within the higher layers.

[0029]

[0035] An example of a locally connected neural network is a convolutional neural network. Figure 2C shows an example of a convolutional neural network 206. The convolutional neural network 206 may be configured such that the connection strengths associated with the inputs for each neuron in the second layer are shared (e.g., 208). Convolutional neural networks may be suitable for problems where the spatial location of the inputs is meaningful.

[0030]

[0036] One type of convolutional neural network is the deep convolutional network (DCN). Figure 2D shows a detailed example of a DCN 200 designed to recognize visual features from images 226 input from an image capture device 230, such as an on-board camera. The DCN 200 in this example may be trained to identify traffic signs and numbers on traffic signs. Of course, the DCN 200 may be trained for other tasks, such as identifying lane markings or identifying traffic signals.

[0031]

[0037] The DCN 200 may be trained using supervised learning. During training, the DCN 200 may be presented with an image, such as an image 226 of a speed limit sign, and then a forward pass may be computed to generate the output 222. The DCN 200 may include a feature extraction section and a classification section. Upon receiving the image 226, the convolution layer 232 may apply a convolution kernel (not shown) to the image 226 to generate the first set of feature maps 218. As an example, the convolution kernel for the convolution layer 232 may be a 5×5 kernel that generates a 28×28 feature map. In this example, four different convolution kernels were applied to the image 226 in the convolution layer 232 because four different feature maps are generated in the first set of feature maps 218. A convolution kernel may also be referred to as a filter or a convolution filter.

[0032]

[0038] The first set of feature maps 218 may be subsampled by a max pooling layer (not shown) to generate a second set of feature maps 220. The max pooling layer reduces the size of the first set of feature maps 218. That is, the size of the second set of feature maps 220, such as 14×14, is smaller than the size of the first set of feature maps 218, such as 28×28. The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 220 may be further convolved through one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

[0033]

[0039] In the example of Figure 2D, the second set of feature maps 220 are convolved to generate a first feature vector 224. Furthermore, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature in the second feature vector 228 may include a number corresponding to a possible feature of the image 226, such as "sign", "60", and "100". A softmax function (not shown) may convert the numbers in the second feature vector 228 into probabilities. Thus, the output 222 of the DCN 200 is the probability that the image 226 contains one or more features.

[0034]

[0040] In this example, the probability in output 222 for "sign" and "60" is higher than the probability for other of the outputs 222 such as "30", "40", "50", "70", "80", "90", and "100". Before training, the output 222 generated by DCN 200 may be inaccurate. Therefore, an error may be calculated between the output 222 and a target output. The target output is the ground truth of the image 226 (e.g., "sign" and "60"). The weights of DCN 200 may then be adjusted so that the output 222 of DCN 200 is more closely aligned with the target output.

[0035]

[0041] To adjust the weights, the learning algorithm may calculate a gradient vector for the weights. The gradient can indicate the amount by which the error would increase or decrease if the weights were adjusted. In the top layer, the gradient can correspond directly to the values ​​of the weights connecting the activated neurons in the penultimate layer to the neurons in the output layer. In lower layers, the gradient can depend on the values ​​of the weights and the calculated error gradients of the upper layers. The weights can then be adjusted to reduce the error. This method of adjusting weights is sometimes called "backpropagation" because it involves a "backward pass" through the neural network.

[0036]

[0042] In practice, the error gradient of the weights may be calculated over a small number of examples such that the calculated gradient approximates the true error gradient. This approximation may be referred to as stochastic gradient descent. Stochastic gradient descent may be repeated until the achievable error rate of the entire system stops decreasing or until the error rate reaches a target level. After training, the DCN 200 may be presented with new images and a forward pass through the network of the DCN 200 may result in an output 222, which may be considered the inference or prediction of the DCN 200.

[0037]

[0043] Deep belief networks (DBNs) are probabilistic models with multiple layers of hidden nodes. DBNs may be used to extract a hierarchical representation of a training dataset. DBNs may be obtained by stacking layers of Restricted Boltzmann Machines (RBMs). RBMs are a type of artificial neural network that can learn a probability distribution over a set of inputs. RBMs are frequently used in unsupervised learning because they can learn a probability distribution without information about the class into which each input should be categorized. Using a hybrid unsupervised-supervised paradigm, the lower RBM of the DBN can be trained in an unsupervised manner and can function as a feature extractor, and the upper RBM can be trained in a supervised manner (on the joint distribution of inputs from previous layers and the target class) and can function as a classifier.

[0038]

[0044] Deep convolutional networks (DCNs) are networks of convolutional networks constructed with additional pooling and normalization layers. DCNs have achieved state-of-the-art performance for many tasks. DCNs can be trained using supervised learning, where both the input and output targets are known for a large number of examples and are used to modify the network weights by using gradient descent.

[0039]

[0045] The DCN may be a feedforward network. In addition, as described above, connections from neurons in a first layer of the DCN to groups of neurons in the next higher layer are shared across neurons in the first layer. The feedforward and shared connections of the DCN can be exploited for high speed processing. The computational burden of the DCN may be much smaller than that of a similarly sized neural network that includes, for example, recurrent or feedback connections.

[0040]

[0046] The processing of each layer of the convolutional network may be considered as a spatially invariant template or basis projection. If the input is initially decomposed into multiple channels, such as the red, green, and blue channels of a color image, the convolutional network trained on that input may be considered as three-dimensional, with two spatial dimensions along the axes of the image and a third dimension capturing color information. The output of the convolutional connections may be considered to form a feature map in the subsequent layer, with each element of the feature map (e.g., 220) receiving input from a range of neurons in the previous layer (e.g., feature map 218) and from each of multiple channels. The values ​​in the feature map may be further processed using nonlinearities such as rectification, max(0,x), etc. Values ​​from neighboring neurons may be further pooled, corresponding to downsampling, to provide additional local invariance and dimensionality reduction. Normalization, corresponding to whitening, may also be applied through lateral inhibition between neurons in the feature map.

[0041]

[0047] The performance of deep learning architectures can improve as more labeled data points become available or as computational power increases. Modern deep neural networks are routinely trained with computational resources thousands of times greater than those available to a typical researcher only 15 years ago. New architectures and training paradigms can further improve deep learning performance. Rectified linear units may reduce the training problem known as vanishing gradients. New training techniques may reduce overfitting and therefore allow larger models to achieve better generalization. Encapsulation techniques extract data within a given receptive field and may further improve overall performance.

[0042]

[0048] FIG. 3 is a block diagram illustrating a deep convolutional network 350. The deep convolutional network 350 may include multiple different types of layers based on connectivity and weight sharing. As shown in FIG. 3, the deep convolutional network 350 includes convolutional blocks 354A, 354B. Each of the convolutional blocks 354A, 354B may be configured with a convolutional layer (CONV) 356, a normalization layer (LNorm) 358, and a max pooling layer (MAX POOL) 360. Although only two of the convolutional blocks 354A, 354B are shown, the present disclosure is not so limited and instead any number of convolutional blocks 354A, 354B may be included in the deep convolutional network 350 according to design preferences.

[0043]

[0049] The convolution layer 356 may include one or more convolution filters that may be applied to the input data to generate feature maps. The normalization layer 358 may normalize the output of the convolution filters. For example, the normalization layer 358 may provide whitening or lateral inhibition. The max pooling layer 360 may provide downsampling aggregation across the space for local invariance and dimensionality reduction.

[0044]

[0050] For example, a parallel filter bank of a deep convolutional network may be loaded onto the CPU 102 or GPU 104 of the SOC 100 (e.g., FIG. 1) to achieve high performance and low power consumption. In alternative embodiments, the parallel filter bank may be loaded onto the DSP 106 or ISP 116 of the SOC 100. In addition, the deep convolutional network 350 may access other processing blocks that may be present on the SOC 100, such as the sensor processor 114 and navigation module 120, which are dedicated to sensors and navigation, respectively.

[0045]

[0051] The deep convolutional network 350 may also include one or more fully connected layers 362 (FC1 and FC2). The deep convolutional network 350 may further include a logistic regression (LR) layer 364. Between each layer 356, 358, 360, 362, 364 of the deep convolutional network 350, there are weights (not shown) that are to be updated. The output of each of the layers (e.g., 356, 358, 360, 362, 364) may serve as an input of a subsequent one of the layers (e.g., 356, 358, 360, 362, 364) in the deep convolutional network 350 to learn a hierarchical feature representation from the input data 352 (e.g., image, audio, video, sensor data, and / or other input data) provided initially to the convolution block 354A. The output of the deep convolutional network 350 is a classification score 366 for the input data 352. The classification score 366 may be a set of probabilities, where each probability is the probability that the input data contains a feature from the set of features.

[0046]

[0052] 4 is a block diagram illustrating an example software architecture 400 that may modularize artificial intelligence (AI) functions. This architecture 400 may be used to design applications that may enable various processing blocks (e.g., CPU 422, DSP 424, GPU 426, and / or NPU 428) of a SOC 420 (which may be similar to SoC 100 of FIG. 1) to support simulation of low bitwidth quantization for an AI application 402, according to aspects of the present disclosure. Architecture 400 may be included in a computing device, such as, for example, a smartphone.

[0047]

[0053] The AI ​​application 402 can be configured to invoke functions defined in user space 404 that can provide, for example, scene detection and recognition indicative of the location in which a computing device including architecture 400 is currently operating. The AI ​​application 402 can configure microphones and cameras differently depending on, for example, whether the scene to be recognized is an office, an auditorium, a restaurant, or an outdoor setting such as a lake. The AI ​​application 402 can make requests to compiled program code associated with libraries defined in the AI ​​function application programming interface (API) 406. The requests can ultimately rely on the output of a deep neural network configured to provide an inference response based on, for example, the video and positioning data.

[0048]

[0054] A runtime engine 408, which may be compiled code of a runtime framework, may be further accessible to the AI ​​application 402. The AI ​​application 402 may cause the runtime engine 408 to request inference, for example, at a particular time interval or triggered by an event detected by the user interface of the AI ​​application 402. The runtime engine 408 may then signal an operating system in the operating system (OS) space 410, such as a kernel 412 running on the SOC 420, when it is required to provide an inference response. In some embodiments, the kernel 412 may be a Linux kernel. The operating system may then perform successive relaxations of quantization on the CPU 422, the DSP 424, the GPU 426, the NPU 428, or some combination thereof. The CPU 422 may be accessed directly by the operating system, and the other processing blocks may be accessed through drivers, such as drivers 414, 416, or 418 for the DSP 424, the GPU 426, or the NPU 428, respectively. In an illustrative example, the deep neural network may be configured to run on a combination of processing blocks such as CPU 422, DSP 424, and GPU 426, or may run on NPU 428.

[0049]

[0055] The AI ​​application 402 can be configured to invoke functions defined in user space 404 that can provide, for example, scene detection and recognition indicative of the location in which a computing device including architecture 400 is currently operating. The AI ​​application 402 can configure microphones and cameras differently depending on, for example, whether the scene to be recognized is an office, an auditorium, a restaurant, or an outdoor setting such as a lake. The AI ​​application 402 can make a request to compiled program code associated with a library defined in SceneDetect application programming interface (API) 406 to provide an estimate of the current scene. The request may ultimately rely on the output of, for example, a differential neural network configured to provide a scene estimate based on video and positioning data.

[0050]

[0056] A runtime engine 408, which may be compiled code of a runtime framework, may be further accessible to the AI ​​application 402. The AI ​​application 402 may have the runtime engine 408 request scene inference, for example, at a particular time interval or triggered by an event detected by the application's user interface. The runtime engine 408 may then signal an operating system 410, such as a Linux kernel 412 running on the SOC 420, when the scene has been inferred. The operating system 410 may then cause the calculations to be performed on the CPU 422, the DSP 424, the GPU 426, the NPU 428, or some combination thereof. The CPU 422 may be accessed directly by the operating system, and other processing blocks may be accessed through drivers, such as drivers 414-418 for the DSP 424, the GPU 426, or the NPU 428. In an exemplary embodiment, the differential neural network may be configured to run on a combination of processing blocks, such as the CPU 422 and the GPU 426, or may run on the NPU 428.

[0051]

[0057] Generally speaking, neural networks can consume a significant amount of power. High power consumption in the computational cores can result in poorer battery life. As a result, the computational cores may be power-throttled, in other words, the clock speed may be reduced to reduce power consumption.

[0052]

[0058] Neural signal processor (NSP) multipliers consume less power if the received input is 0 for two consecutive cycles. This effect works at the bit level; that is, if the same bit is 0 in the same multiplier for two consecutive cycles, power consumption is reduced. Using a lower bit width on a higher bit width hardware increases the number of bits that have 0 value. For example, when using a 4-bit value on 8-bit hardware, for positive values, the four most significant bits are always 0. A 4-bit integer (INT4) has an unsigned range: [0, 15] in decimal, which is [00000000, 00001111] in binary for an 8-bit integer (INT8).

[0053]

[0059] However, this solution does not work for signed negative values, since negative integers are encoded using two's complement encoding. Continuing with the example of a 4-bit value on 8-bit hardware in decimal, the signed INT4 range is [-8, 7], which in INT8 binary is [11111000, 00000111]. It is desirable for some bits to always be 0. However, this is not possible with existing solutions when the range of possible values ​​includes negative numbers.

[0054]

[0060] To use efficient low-bit integer hardware, the network can be quantized to an appropriate bit-width. As an example, an 8-bit quantization of a floating-point tensor X can be given by:

[0055]

number

[0056] where (int_min,int_max) is (0, 255) for unsigned tensors and (-128, 127) for signed tensors, and s xis the quantization scale for tensor X, set heuristically or by gradient descent for some target loss function. The matrix-matrix product WX can be approximated as follows:

[0057]

number

[0058] In the formula, W represents the weight, and s w is the quantization scale of the weight W. Only integer multiplication can be done with the product W int X int Since the computation is used to calculate x, y ...

[0059]

[0061] To improve quantized performance, quantization-aware training (QAT) can be employed. In some conventional approaches, (non-differentiable) quantization operations are used in the forward pass but ignored in the backward pass. However, these conventional quantization procedures introduce noise into the weights and activation tensors. Because some neural network layers are more sensitive to noise than others, some conventional approaches utilize mixed precision quantization (MPQ). Mixed precision quantization uses tensor-specific bit-widths instead of fixed bit-widths for each tensor in the network. However, the resulting space of MPQ constructions grows exponentially with the number of layers in the network, precluding exhaustive search.

[0060]

[0062] The computation of a neural network layer can be viewed as a matrix-matrix multiplication Y=WX between the input activations X and the weights W. The product WX involves multiplying each element in W with an element in X, and adding (accumulating) the resulting scalar products. A neural network accelerator can be implemented in hardware as a multiply-accumulate (MAC) array, where a subset of the weights are multiplied by a subset of the activations in parallel on each cycle, and then accumulated. For example, with 16 weights W as input, 1:4,1:4 and 4 Activation X 1:4,k A MAC array with nm X mk is the multiplier M nm It can be computed in parallel on (n,m∈[1,4]). 1:4,k The (partial) results for can be stored in an accumulator.

[0061]

[0063] Multiplier M mn If one of the inputs to the multiplier M is 0 for two or more consecutive cycles, mn may consume no power. This power savings occurs at the bit level. That is, if the same input bit in a multiplier is 0 for two consecutive cycles, the activity in the gates that toggle the bit between 0 or 1 may be reduced, and in some aspects avoided. Thus, the power consumption for each such input bit that remains 0 for consecutive cycles may be significantly reduced, and in some aspects avoided.

[0062]

[0064] Therefore, to reduce power consumption, aspects of the present disclosure aim to increase consecutive 0 bits. According to aspects of the present disclosure, low bit width (e.g., 4 bits) quantization can be simulated in higher bit width (e.g., 8 bits or 16 bits) hardware. Since activation tensors in a rectifier linear unit (ReLU) network can be sparser than the corresponding weights, significant gains can be achieved by increasing the number of consecutive 0 bits in the weights. However, this is by way of example only and is not limiting. Aspects of the present disclosure can be applied to other tensors and other types of neural networks.

[0063]

[0065] Low bit-width weights can be simulated on higher bit-width hardware by restricting the range of (integer) values ​​that the weights can take. For example, simulating 4-bit integer quantization on 8-bit hardware can be achieved by restricting the range of integer weight values ​​to [-8,7]. However, due to the sign extension that results from the two's complement encoding of negative numbers, negative values ​​can be represented with 1s in the most significant bits (MSBs). This property may be undesirable since one objective is to increase, and in some aspects maximize, the number of consecutive 0 bits.

[0064]

[0066] To avoid sign extension in two's complement encoding, we can instead bit-shift the low-bit integer weights by the appropriate amount. Bit-shifting an integer by b bits is equivalent to bit-shifting an integer by 2 b This can be thought of as equivalent to multiplying each value by 2. Therefore, when simulating signed b-bit quantization on B-bit hardware, we multiply each value by 2. B-b To offset the effect of the bit shift, the quantization scale s can be multiplied by

[0065]

number

[0066] can be adjusted according to

[0067] In one embodiment, signed 4-bit weights can be simulated on 8-bit hardware. A signed weight tensor W with values ​​in the range [−8, 7] is int and the associated scale s w The binary representation of the range [-8,7] may be given by [11111000,00000111]. In this example, consecutive 0 bits can occur only if the consecutive values ​​are either both positive or both negative. To avoid this scenario,

[0068]

number

[0069] This may be defined as W int Each value in may be effectively shifted by 4 bits. Doing so can result in a range from [-128, 112] in decimal representation, or [10000000, 01110000] in binary representation. Since the resulting values ​​are multiples of 16, the least significant 4 bits will now be 0, regardless of the represented value. In some aspects, the effect of multiplying by 16 is to reduce the quantization scale

[0070]

number

[0071] Therefore, the resulting integer matrix product remains mathematically equivalent as given by:

[0072]

number

[0073] FIG. 5 is a process flow diagram illustrating a processor-implemented method 500 for reducing power consumption of a neural network by bit shifting, according to aspects of the disclosure. In some aspects, the processor-implemented method 500 may be performed by a processor, such as, for example, CPU 102 or NPU 108. As shown in FIG. 5, at block 502, the processor may bit-shift a binary representation of the neural network parameters. The neural network parameters have bits b that are less than the number of hardware bits B supported by the hardware that processes the neural network parameters. The bit shifting adds two bits to the neural network parameters. B-b effectively multiplying

[0074]

[0069] In block 504, to obtain an updated quantization scale, the processor B-b As explained, to counteract the effect of bit shifting, the quantization scale s is

[0075]

number

[0076] can be adjusted according to

[0077]

[0070] At block 506, the processor quantizes the bit-shifted binary representation using the updated quantization scale to obtain values ​​of the neural network parameters.

[0078] Exemplary Aspects

[0071] Aspect 1: Bit-shifting, by a processor, a binary representation of a neural network parameter, the binary representation having bits b less than a number B of hardware bits supported by hardware that processes the neural network parameter, to add 2 bits to the neural network parameter. B-b This effectively multiplies the quantization scale by 2, which is then bit-shifted by the processor to get the updated quantization scale. B-b and quantizing, by the processor, the bit-shifted binary representation with the updated quantization scale to obtain values ​​of the neural network parameters.

[0079]

[0072] Aspect 2: A method implemented by the processor of aspect 1, wherein the neural network parameters have 7 bits or less and the hardware supports 8-bit values.

[0080]

[0073] Aspect 3: A method implemented by a processor according to aspect 1 or 2, wherein the neural network parameters have 4 bits and the hardware supports 8-bit values.

[0081]

[0074] Aspect 4: A method implemented by a processor described in any one of aspects 1 to 3, wherein the binary representation of the neural network parameters is bit-shifted such that the least significant bit difference Bb has a value of 0.

[0082]

[0075] Aspect 5: A method implemented by a processor described in any one of aspects 1 to 4, wherein the neural network parameters include neural network weight tensors or neural network activation tensors.

[0083]

[0076] Aspect 6: An apparatus comprising a memory and at least one processor coupled to the memory, the at least one processor performing bit shifting of a binary representation of a neural network parameter, the neural network parameter having bits b that are less than a number B of hardware bits supported by hardware processing the neural network parameter, to add 2 bits to the neural network parameter. B-b To effectively multiply, bit shift, and get the updated quantization scale, we multiply the quantization scale by 2. B-b and quantizing the bit-shifted binary representation with the updated quantization scale to obtain values ​​of the neural network parameters.

[0084]

[0077] Aspect 7: The apparatus of aspect 6, wherein the neural network parameters have 7 bits or less and the hardware supports 8-bit values.

[0085]

[0078] Aspect 8: The apparatus of aspect 6 or 7, wherein the neural network parameters have 4 bits and the hardware supports 8-bit values.

[0086]

[0079] Aspect 9: An apparatus described in any one of aspects 6 to 8, wherein at least one processor is further configured to bit-shift the binary representation of the neural network parameters so that the least significant bit difference Bb has a value of 0.

[0087]

[0080] Aspect 10: An apparatus described in any one of aspects 6 to 9, wherein the neural network parameters include a neural network weight tensor or a neural network activation tensor.

[0088]

[0081] Aspect 11: Means for bit-shifting a binary representation of a neural network parameter, the neural network parameter having bits b less than the number of hardware bits B supported by hardware processing the neural network parameter, comprising: B-b This effectively multiplies and bit-shifts the quantization scale by 2 to get the updated quantization scale. B-b and means for quantizing the bit-shifted binary representation with the updated quantization scale to obtain a value of a neural network parameter.

[0089]

[0082] Aspect 12: The apparatus of aspect 11, wherein the neural network parameters have 7 bits or less and the hardware supports 8-bit values.

[0090]

[0083] Aspect 13: The apparatus of aspect 11 or 12, wherein the neural network parameters have 4 bits and the hardware supports 8-bit values.

[0091]

[0084] Aspect 14: An apparatus described in any one of aspects 11 to 13, further comprising means for bit-shifting the binary representation of the neural network parameters so that the least significant bit difference Bb has a value of 0.

[0092]

[0085] Aspect 15: An apparatus described in any one of aspects 11 to 14, wherein the neural network parameters include a neural network weight tensor or a neural network activation tensor.

[0093] Aspect 16: A non-transitory computer readable medium having program code recorded thereon, the program code being executed by a processor to perform bit shifting of a binary representation of a neural network parameter, the binary representation having b bits less than a number B of hardware bits supported by hardware for processing the neural network parameter, the neural network parameter being shifted by 2 B-b The program code for bit shifting effectively multiplies the quantization scale by 2 to get the updated quantization scale. B-b and program code for quantizing the bit-shifted binary representation with an updated quantization scale to obtain a value of a neural network parameter.

[0094]

[0087] Aspect 17: The non-transitory computer-readable medium of aspect 16, wherein the neural network parameters have 7 bits or less and the hardware supports 8-bit values.

[0095]

[0088] Aspect 18: The non-transitory computer-readable medium of aspect 16 or 17, wherein the neural network parameters have 4 bits and the hardware supports 8-bit values.

[0096]

[0089] Aspect 19: A non-transitory computer-readable medium described in any one of aspects 16 to 18, further comprising program code for bit-shifting the binary representation of the neural network parameters so that the least significant bit difference Bb has a value of 0.

[0097]

[0090] Aspect 20: A non-transitory computer-readable medium described in any one of aspects 16 to 19, wherein the neural network parameters include a neural network weight tensor or a neural network activation tensor.

[0098] In one aspect, the bit-shifting means, the dividing means, and / or the quantizing means may be the CPU 102, the program memory associated with the CPU 102, the dedicated memory block 118, the fully connected layer 362, the NPU 428, and / or the routing connection processing unit 216 configured to perform the recited functions. In another configuration, the above-mentioned means may be any module or any device configured to perform the recited functions by the above-mentioned means.

[0099]

[0092] The various operations of the above-described methods may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software component(s) and / or module(s), including but not limited to circuits, application specific integrated circuits (ASICs), or processors. In general, where there are operations illustrated in a figure, those operations may have corresponding counterpart means-plus-function components similarly numbered.

[0100]

[0093] When used, the term "determining" encompasses a wide variety of actions. For example, "determining / determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, database, or another data structure), ascertaining, and the like. In addition, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Further, "determining" may include resolving, selecting, choosing, establishing, and the like.

[0101]

[0094] When used, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to include a, b, c, ab, ac, bc, and abc.

[0102]

[0095] The various example logic blocks, modules and circuits described in connection with this disclosure may be implemented or performed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the described functions. A general purpose processor may be a microprocessor, but alternatively, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0103]

[0096] The steps of a method or algorithm described in relation to the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in any form of storage medium known in the art. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, etc. A software module may comprise a single instruction or many instructions, and may be distributed across several different code segments, among different programs, across multiple storage media. The storage medium may be coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral to the processor.

[0104]

[0097] The disclosed methods include one or more steps or actions for achieving the described method. The steps and / or actions of those methods may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order of specific steps and / or actions and / or the use of those steps and / or actions may be modified without departing from the scope of the claims.

[0105]

[0098] The described functions may be implemented in hardware, software, firmware, or any combination thereof. When implemented in hardware, an exemplary hardware configuration may comprise a processing system in a device. The processing system may be implemented using a bus architecture. The bus may include any number of interconnected buses and bridges depending on the particular application of the processing system and the overall design constraints. The bus may link various circuits together, including the processor, the machine-readable medium, and the bus interface. The bus interface may be used to connect, among other things, a network adapter to the processing system via the bus. The network adapter may be used to implement signal processing functions. In some aspects, a user interface (e.g., a keypad, a display, a mouse, a joystick, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and therefore will not be described further.

[0106]

[0099] The processor may be responsible for managing the bus and general processing including executing software stored on the machine-readable medium. The processor may be implemented using one or more general-purpose processors and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry capable of executing software. Software shall be broadly construed to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The machine-readable medium may include, by way of example, a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a magnetic disk, an optical disk, a hard drive, or any other suitable storage medium, or any combination thereof. The machine-readable medium may be embodied in a computer program product. The computer program product may comprise packaging materials.

[0107]

[0100] In a hardware implementation, the machine-readable medium may be part of a processing system separate from the processor. However, as one skilled in the art will readily appreciate, the machine-readable medium or any part thereof may be external to the processing system. By way of example, the machine-readable medium may include a transmission line, a carrier wave modulated by data, and / or a computer product separate from the device, all of which may be accessed by the processor through a bus interface. Alternatively, or in addition, the machine-readable medium or any part thereof may be integrated into the processor, as may be a cache and / or a general-purpose register file. Although the various components discussed may be described as having a particular location, such as a local component, these components may also be configured in various ways, such as some components configured as part of a distributed computing system.

[0108]

[0101] The processing system may be configured as a general-purpose processing system having one or more microprocessors providing processor functions and an external memory providing at least a portion of the machine-readable medium, all linked together with other support circuits through an external bus architecture. Alternatively, the processing system may include one or more neuromorphic processors for implementing the described neuron model and model of the neural system. As another alternative, the processing system may be implemented using an application specific integrated circuit (ASIC) having a processor, bus interface, user interface, support circuits, and at least a portion of the machine-readable medium integrated into a single chip, or using one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gate logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits capable of performing the various functions described throughout this disclosure. Those skilled in the art will recognize how to best implement the described functions for the processing system depending on the particular application and the overall design constraints imposed on the entire system.

[0109]

[0102] The machine-readable medium may comprise several software modules. The software modules include instructions that, when executed by the processor, cause the processing system to perform various functions. The software modules may include a transmitting module and a receiving module. Each software module may reside in a single storage device or may be distributed across multiple storage devices. As an example, the software modules may be loaded into RAM from a hard drive when a triggering event occurs. During execution of the software modules, the processor may load some of the instructions into a cache to increase access speed. One or more cache lines may then be loaded into a general-purpose register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor upon executing instructions from that software module. Furthermore, it will be understood that aspects of the present disclosure provide for improved functionality of a processor, computer, machine, or other system implementing such aspects.

[0110]

[0103] If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically and discs reproduce data optically using lasers. Thus, in some aspects computer readable medium may comprise non-transitory computer readable medium (e.g., tangible media). Additionally, in other aspects computer readable medium may comprise transitory computer readable medium (e.g., signal). Combinations of the above should also be included within the scope of computer-readable media.

[0111]

[0104] Accordingly, some aspects may comprise a computer program product for performing the presented operations. For example, such a computer program product may comprise a computer-readable medium having stored thereon (and / or encoded thereon) instructions executable by one or more processors to perform the described operations. In some aspects, the computer program product may include packaging materials.

[0112]

[0105] Furthermore, it should be understood that modules and / or other suitable means for performing the described methods and techniques may be downloaded and / or otherwise obtained by a user terminal and / or base station, where applicable. For example, such devices may be coupled to a server to facilitate the transfer of means for performing the described methods. Alternatively, the various methods described may be provided via a storage means, such that the user terminal and / or base station may obtain the various methods upon coupling or providing the storage means (e.g., RAM, ROM, physical storage medium such as a compact disk (CD) or floppy disk, etc.) to the device. Furthermore, any other suitable technique for providing the described methods and techniques to the device may be utilized.

[0113]

[0106] It should be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations may be made in the configuration, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. The processor performs a bit shift on the binary representation of a neural network parameter, wherein the binary representation of the neural network parameter has fewer bits b than the number of hardware bits B supported by the hardware processing the neural network parameter, thereby 2 Ｂ－ｂ Effectively multiplying, bit shifting, To obtain an updated quantization scale, the processor modifies the quantization scale by 2 Ｂ－ｂ Dividing by and In order to obtain the values ​​of the neural network parameters, the processor quantizes the bit-shifted binary representation using the updated quantization scale, A method that includes implementing it on the processor.

2. The method of implementing the process using the processor according to claim 1, wherein the neural network parameters have 7 bits or less, and the hardware supports 8-bit values.

3. The method of implementing the process according to claim 1, wherein the neural network parameters have 4 bits and the hardware supports 8-bit values.

4. The method of implementing the process using the processor according to claim 1, wherein the binary representation of the neural network parameters is bit-shifted such that the difference B-b of the least significant bits is 0.

5. The method of implementation using the processor according to claim 1, wherein the neural network parameters include a neural network weight tensor or a neural network activation tensor.

6. It is a device, Memory and The system comprises at least one processor coupled to the memory, wherein the at least one processor A bit shift of the binary representation of a neural network parameter, wherein the neural network parameter has fewer bits b than the number of hardware bits B supported by the hardware processing the neural network parameter, and the neural network parameter has two bits b. Ｂ－ｂ Perform a bit shift to effectively multiply, To obtain the updated quantization scale, set the quantization scale to 2 Ｂ－ｂ Divide by, To obtain the values ​​of the neural network parameters, the bit-shifted binary representation is quantized using the updated quantization scale. It is structured in such a way. Device.

7. The apparatus according to claim 6, wherein the neural network parameters have 7 bits or less, and the hardware supports 8-bit values.

8. The apparatus according to claim 6, wherein the neural network parameters have 4 bits and the hardware supports 8-bit values.

9. The apparatus according to claim 6, wherein the at least one processor is further configured to bit-shift the binary representation of the neural network parameters such that the difference B-b of the least significant bits is zero.

10. The apparatus according to claim 6, wherein the neural network parameters include a neural network weight tensor or a neural network activation tensor.

11. A non-temporary computer-readable medium on which program code is recorded, wherein the program code is When executed by the processor, the processor provides a bit shift of the binary representation of a neural network parameter, wherein the neural network parameter has fewer bits b than the number of hardware bits B supported by the hardware processing the neural network parameter, and the neural network parameter has two bits Ｂ－ｂ Program code that performs bit shifts to effectively multiply, When executed by the processor, the processor is given two quantization scales in order to obtain the updated quantization scale. Ｂ－ｂ Program code that performs division by, When executed by the processor, the program code causes the processor to quantize the bit-shifted binary representation using the updated quantization scale in order to obtain the values ​​of the neural network parameters, including, Non-temporary computer-readable media.

12. The non-temporary computer-readable medium according to claim 11, wherein the neural network parameters have 7 bits or less, and the hardware supports 8-bit values.

13. The non-temporary computer-readable medium according to claim 11, wherein the neural network parameters have 4 bits and the hardware supports 8-bit values.

14. The non-temporary computer-readable medium according to claim 11, further comprising program code that, when executed by a processor, causes the processor to bit-shift the binary representation of the neural network parameters such that the difference B-b of the least significant bits has a value of 0.

15. The non-temporary computer-readable medium according to claim 11, wherein the neural network parameters include a neural network weight tensor or a neural network activation tensor.

Images