Optical neural network multi-architecture adaptive computing chip and computing method thereof

Abstract

The invention discloses an optical neural network multi-architecture adaptive computing chip and a computing method thereof. The chip comprises an optical signal input unit, an input data modulation unit, a weight and bias processing unit and a photoelectric detection unit. The optical signal input unit is used for generating and outputting an optical signal; the input data modulation unit is used for modulating and loading information carried by the source data and the bias data to an optical signal output by the optical signal input unit; the weight and bias processing unit comprises a photon weight module and a photon bias module, and the photon weight module is used for carrying out optical coding on weights and realizing optical multiplication and addition calculation of input data of optical signals and corresponding weight parameters; the photon bias module is used for bias coding, summing the bias coding and an optical multiplication and addition operation result, and outputting an operation result containing bias compensation; the photoelectric detection unit is used for converting operation results into electric signals to be output. The method has high universality, and the calculation accuracy of the optical neural network is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of optical neural network chip technology, and in particular to an optical neural network multi-architecture adaptation computing chip and its computing method. Background Technology

[0002] Optical neural networks, as the core carrier for the deep integration of optical computing technology and artificial intelligence, have become a key technology direction for breaking through the computing power bottleneck of traditional electronic neural networks in large-scale data processing, thanks to the parallel transmission characteristics of photons, high bandwidth, and low energy consumption. As AI technology evolves towards multimodal and large-parameter operations, higher demands are placed on the processing speed, dimensionality, and accuracy of computing systems. Electronic neural networks, limited by electron mobility and wiring delays, struggle to meet the demand for multiply-accumulate operations exceeding tens of billions per second. In contrast, optical neural networks achieve parallel computing through multidimensional modulation of the wavelength, phase, and intensity of optical signals, increasing computing speed to the nanosecond level while significantly reducing energy consumption per unit of computing power. Therefore, optical neural networks exhibit irreplaceable application potential.

[0003] Optical neural network chips enable neural network computation through photons, significantly improving computing performance. However, current technologies primarily focus on processing input data and weights, neglecting the introduction of bias terms. This lack of bias term introduction mechanisms directly leads to insufficient nonlinear fitting capabilities in optical neural networks, resulting in low accuracy in complex tasks and failing to meet the demands of high-reliability applications. Furthermore, existing optical neural network chip designs often employ a single-architecture-specific approach, designing a complete chip module for a particular optical architecture. This module is incompatible with other architectures, leading to extremely high architecture adaptation costs and hindering the formation of standardized optical computing platforms. This severely impedes the large-scale adoption of optical computing technology across various fields.

[0004] Therefore, developing a technical solution that can uniformly introduce bias mechanisms in multiple mainstream optical computing architectures without large-scale reconstruction of chip structures has become a key problem that urgently needs to be solved in the field of optical neural networks. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide an optical neural network multi-architecture adaptation computing chip and its computing method, so as to overcome the defects of existing optical neural network technology, such as low accuracy and poor multi-architecture adaptability due to the lack of bias terms.

[0006] The technical solution adopted by the present invention to solve its technical problem is: an optical neural network multi-architecture adaptation computing chip, comprising: an optical signal input unit, an input data modulation unit, a weight and bias processing unit and a photoelectric detection unit that are sequentially signal-coupled along the optical signal transmission path; The optical signal input unit is used to generate and output an optical signal that meets the optical computing bandwidth requirements. The input data modulation unit is configured as the input layer of an optical neural network, used to modulate and load the information carried by the source data and the preset bias data onto the optical signal output by the optical signal input unit, and obtain an optical signal loaded with mixed data. The weighting and biasing processing unit includes a photonic weighting module and a photonic biasing module. The photonic weighting module is used to optically encode multiple preset weighting parameters and adjust the amplitude of the optical signal loaded with mixed data based on the encoded weighting parameters, thereby realizing optical multiplication and addition calculation between the input data of the optical signal and the corresponding weighting parameters. The photonic biasing module is used to optically encode multiple preset biasing parameters and perform one-to-one summation processing on the encoded biasing parameters and the results of the optical multiplication and addition operation, outputting the calculation result including bias compensation. The photoelectric detection unit is used to receive the optical signal corresponding to the calculation result containing the bias, and convert it into an electrical signal for output; In the optical neural network multi-architecture adaptation computing chip, the weight and bias processing unit can be implemented based on any one of the following: micro-ring array structure, Mach-Zehnder interferometer array structure, on-chip diffraction unit structure, and cascaded time-domain modulator structure, in order to complete the optical multiplication and addition of input data and weight parameters and the bias summation.

[0007] As a further improvement of the present invention, the optical signal input unit includes a single laser or a laser array; wherein the single laser is used to output a continuous optical signal of a single wavelength, and the laser array is used to output multiple parallel optical signals of different wavelengths.

[0008] As a further improvement of the present invention, when the weight and bias processing unit is implemented based on a micro-ring array structure: The photonic weighting module includes multiple photonic weighting sub-units distributed along the intersection nodes of the transverse and longitudinal waveguides. Each photonic weighting sub-unit contains a column of first microring resonators. Each first microring resonator encodes its corresponding weights through thermal tuning or electro-optic response tuning. The photonic biasing module includes multiple photonic biasing sub-units. The photonic biasing sub-units correspond one-to-one with the vertical columns of the photonic weighting sub-units. Each photonic biasing sub-unit contains an independent second microring resonator. Each second microring resonator encodes a bias for the corresponding photonic biasing sub-unit using the same tuning method as the first microring resonator.

[0009] As a further improvement of the present invention, when the weight and bias processing unit is implemented based on a Mach-Zehnder interferometer array structure: The photonic weighting module includes multiple parallel photonic weighting sub-units. Each photonic weighting sub-unit is composed of an MZI interferometer array and is used to encode the corresponding weights by means of thermal tuning or electro-optic response tuning. The photon biasing module includes multiple photon biasing sub-units, which correspond one-to-one with the photon weighting sub-units. Each photon biasing sub-unit is encoded with a bias, and the bias encoding method is thermal tuning or electro-optic response tuning.

[0010] As a further improvement of the present invention, when the weighting and biasing processing unit is implemented based on an on-chip diffraction unit structure: The photon weighting module includes multiple photon weighting sub-units arranged in a two-dimensional array. Each photon weighting sub-unit includes a set of on-chip diffraction units, and each on-chip diffraction unit is used to encode the corresponding weights. The photon biasing module includes multiple photon biasing sub-units, and the column directions of the photon biasing sub-units correspond one-to-one with those of the photon weighting sub-units. Each photon biasing sub-unit includes a set of on-chip diffraction units with the same structure as the photon weighting sub-units, which are used to encode bias parameters through a fixed diffraction mode.

[0011] As a further improvement of the present invention, when the weighting and biasing processing unit is implemented based on a cascaded time-domain modulator structure: The photonic weighting module includes multiple photonic weighting sub-units allocated according to time sequence. Each photonic weighting sub-unit is configured with an independent modulation bit in the time-domain modulator. Each modulation bit is used to encode the corresponding weights respectively. The photonic bias module includes multiple photonic bias sub-units, and the photonic bias sub-units correspond one-to-one with the photonic weighting sub-units. Each photonic bias sub-unit encodes the bias parameters by adding a bias constant term with a fixed amplitude to the end of the temporal modulation sequence of the source data and loading it onto the input optical signal.

[0012] As a further improvement of the present invention, the weight and bias processing unit further includes a time-domain integration subunit, which is used to calculate the electrical signal output by the photoelectric detection unit to achieve multiplication, addition and bias summation.

[0013] As a further improvement of the present invention, the time-domain integrator is a time-domain integrator based on an analog amplifier. The integration circuit of the analog amplifier is used to sample the electrical signal output by the photoelectric detection unit. The capacitor of the analog amplifier is used to accumulate charge for charging. The process from the completion of charging to the completion of releasing the capacitor is one integration process.

[0014] As a further improvement of the present invention, the photodetector unit adopts a germanium-silicon photodetector with epitaxial germanium on silicon to realize the conversion of optical signals to electrical signals.

[0015] This invention also provides a computation method for an optical neural network multi-architecture adaptation computing chip, implemented based on the optical neural network multi-architecture adaptation computing chip described above, including the following steps: S1, according to the target architecture adopted by the weight and bias processing unit, control the optical signal input unit to generate and output an optical signal with an optical signal wavelength or optical field mode that matches the target architecture; wherein, the target architecture is any one of the following: micro-ring array structure, Mach-Zehnder interferometer array structure, on-chip diffraction unit structure, and cascaded time-domain modulator structure. S2, the information carried by the source data and the bias data is co-modulated and loaded onto the optical signal output in step S1 by the input data modulation unit to form an optical signal loaded with mixed data; S3, the preset weight parameters are optically encoded by the photonic weight module of the weight and bias processing unit, and the amplitude of the optical signal loading the mixed data is adjusted based on the encoded weight parameters to complete the optical multiplication and addition calculation of the input data and the corresponding weight; at the same time, the preset bias parameters are optically encoded by the photonic bias module, and the encoded bias parameters and the results of the optical multiplication and addition calculation are summed one-to-one to obtain the calculation result including bias compensation; S4: The photoelectric detection unit receives the optical signal corresponding to the calculation result including bias compensation output in step S3, converts it into an electrical signal and outputs it, thus completing a single optical neural network forward calculation.

[0016] The beneficial effects of this invention are as follows: This invention provides an optical neural network multi-architecture adaptable computing chip and its computing method, which has extremely strong adaptability and flexibility. It is not only applicable to micro-ring array structures, Mach-Zehnder interferometer array structures, and on-chip diffraction unit structures, but also covers a variety of mainstream optical computing platforms such as cascaded time-domain modulator structures. Through the bias introduction mechanism, the neural network can take into account more nonlinear factors during the calculation process. This enhancement of nonlinearity allows the neural network to better fit complex data patterns, significantly enhancing the integrity and performance of the neural network, thereby effectively improving the calculation accuracy of the optical neural network. At the same time, the introduction of bias also enhances the robustness of the neural network, enabling it to maintain good calculation performance and accuracy even when facing adverse conditions such as noise interference and missing data. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic block diagram of the optical neural network multi-architecture adaptation computing chip of the present invention; Figure 2 This is a flowchart illustrating the steps of the computation method for the optical neural network multi-architecture adaptation computing chip of the present invention. Figure 3 This is a schematic diagram illustrating the principle of the weight and bias processing unit based on a micro-ring array structure in this invention. Figure 4 This is a schematic diagram illustrating the principle of the weight and bias processing unit in this invention, which is based on a Mach-Zehnder interferometer array structure. Figure 5 This is a schematic diagram illustrating the principle of the weight and bias processing unit implemented based on the on-chip diffraction unit structure in this invention. Figure 6 This is a schematic diagram illustrating the principle of the weight and bias processing unit in this invention, which is based on a cascaded time-domain modulator structure.

[0019] Referring to the accompanying drawings, the following explanations are provided: 1. Optical signal input unit; 2. Input data modulation unit; 3. Weighting and bias processing unit; 301. Photon weighting module; 302. Photon biasing module; 4. Photoelectric detection unit. Detailed Implementation

[0020] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0022] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0023] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0024] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0025] Example 1

[0026] See Figure 1 The present invention provides an optical neural network multi-architecture adaptation computing chip, including an optical signal input unit 1, an input data modulation unit 2, a weight and bias processing unit 3 and a photoelectric detection unit 4, which are sequentially coupled along the optical signal transmission path.

[0027] It should be noted that the optical signal coupling connection mentioned in this embodiment can be achieved using silicon-based optical waveguide coupling. The tuning method and encoding accuracy are all based on existing mature optoelectronic processes. Those skilled in the art can adjust the specific parameters according to the actual application scenario without affecting the implementation of the core technical solution of this invention.

[0028] Among them, the optical signal input unit 1 is used to generate and output an optical signal that meets the optical computing bandwidth requirements.

[0029] Optionally, the optical signal input unit 1 includes a single laser or a laser array; wherein the single laser is used to output a continuous optical signal of a single wavelength, and the laser array is used to output multiple parallel optical signals of different wavelengths.

[0030] The input data modulation unit 2 is configured as the input layer of an optical neural network, used to modulate and load the information carried by the source data and the preset bias data onto the optical signal output by the optical signal input unit 1, and obtain an optical signal loaded with mixed data.

[0031] The weighting and biasing processing unit 3 includes a photonic weighting module 301 and a photonic biasing module 302. The photonic weighting module 301 is used to optically encode multiple preset weighting parameters and adjust the amplitude of the optical signal loaded with mixed data based on the encoded weighting parameters to realize optical multiplication and addition calculation between the input data of the optical signal and the corresponding weighting parameters. The photonic biasing module 302 is used to optically encode multiple preset biasing parameters and perform one-to-one summation processing between the encoded biasing parameters and the results of optical multiplication and addition operations to output the calculation result including bias compensation.

[0032] The photoelectric detection unit 4 is used to receive the optical signal corresponding to the calculation result containing the bias and convert it into an electrical signal for output.

[0033] Optionally, the photodetector unit 4 uses a germanium-silicon photodetector with epitaxial germanium on silicon to realize the conversion of optical signals to electrical signals.

[0034] In the optical neural network multi-architecture adaptation computing chip of the present invention, the weight and bias processing unit 3 can be implemented based on any one of the following: micro-ring array structure, Mach-Zehnder interferometer array structure, on-chip diffraction unit structure and cascaded time-domain modulator structure, so as to complete the optical multiplication and addition of input data and weight parameters and bias summation.

[0035] As can be seen, the optical neural network multi-architecture adaptable computing chip proposed in this invention has extremely strong adaptability and flexibility. It is not only applicable to micro-ring array structures, Mach-Zehnder interferometer array structures, and on-chip diffraction unit structures, but also covers a variety of mainstream optical computing platforms such as cascaded time-domain modulator structures. In the implementation process, there is no need to modify or redesign the existing optical computing structure. Only a specific bias introduction mechanism needs to be added to the input layer and the weight and bias processing unit 3. This highly universal design enables this invention to be easily integrated into various existing optical computing systems, greatly reducing the cost and risk of technology upgrades and modifications.

[0036] Furthermore, this invention significantly enhances the integrity and performance of neural networks by uniformly introducing a bias mechanism across different optical computing architectures, thereby effectively improving the computational accuracy of optical neural networks. This bias introduction enables the neural network to better fit complex data distributions and patterns, improving the model's performance in tasks such as image recognition and semantic segmentation. For example, in image recognition tasks, by introducing a bias, the neural network can more accurately identify target objects and features in images; in semantic segmentation tasks, it can more finely segment different semantic regions in images. The bias introduction mechanism of this invention adds a constant bias term to the data through optical or temporal methods, allowing the neural network to consider more nonlinear factors during computation. This enhanced nonlinearity enables the neural network to better fit complex data patterns, improving the model's expressive power and predictive ability for unknown data. Simultaneously, the introduction of the bias also enhances the robustness of the neural network, enabling it to maintain good computational performance and accuracy even in the face of adverse conditions such as noise interference and missing data.

[0037] See Figure 2 The present invention also provides a computation method for an optical neural network multi-architecture adaptation computing chip, which is implemented based on the optical neural network multi-architecture adaptation computing chip described above, and includes the following steps S1 to S4: S1, according to the target architecture adopted by the weight and bias processing unit 3, controls the optical signal input unit 1 to generate and output an optical signal with an optical signal wavelength or optical field mode that matches the target architecture; wherein, the target architecture is any one of the following: micro-ring array structure, Mach-Zehnder interferometer array structure, on-chip diffraction unit structure and cascaded time-domain modulator structure.

[0038] S2, the information carried by the source data and the bias data is co-modulated and loaded onto the optical signal output in step S1 by the input data modulation unit 2 to form an optical signal loaded with mixed data.

[0039] S3, the photonic weighting module 301 of the weighting and biasing processing unit 3 optically encodes the preset weighting parameters, and adjusts the amplitude of the optical signal loading the mixed data based on the encoded weighting parameters to complete the optical multiplication and addition calculation of the input data and the corresponding weights; at the same time, the photonic biasing module 302 optically encodes the preset biasing parameters, and performs a one-to-one summation process on the encoded biasing parameters and the results of the optical multiplication and addition calculation to obtain the calculation result including bias compensation.

[0040] S4: The photoelectric detection unit 4 receives the optical signal corresponding to the calculation result including bias compensation output in step S3, converts it into an electrical signal and outputs it to complete the single optical neural network forward calculation.

[0041] The computational method proposed in this invention, based on a multi-architecture adaptive computing chip for optical neural networks, also possesses strong adaptability and flexibility. It is applicable not only to micro-ring array structures, Mach-Zehnder interferometer array structures, and on-chip diffraction unit structures, but also to various mainstream optical computing platforms such as cascaded time-domain modulator structures. Through the bias introduction mechanism, the neural network can consider more nonlinear factors during the computation process. This enhancement of nonlinearity allows the neural network to better fit complex data patterns, significantly improving the integrity and performance of the neural network, thereby effectively improving the computational accuracy of the optical neural network. At the same time, the introduction of bias also enhances the robustness of the neural network, enabling it to maintain good computational performance and accuracy even when facing adverse conditions such as noise interference and missing data.

[0042] In one embodiment of the present invention, the weighting and biasing processing unit 3 is implemented based on a micro-ring array structure. The photonic weighting module 301 includes multiple photonic weighting sub-units distributed along the intersection nodes of the transverse and longitudinal waveguides. Each photonic weighting sub-unit includes a column of first micro-ring resonators. Each first micro-ring resonator encodes its corresponding weight using thermal tuning or electro-optic response tuning. The photonic biasing module 302 includes multiple photonic biasing sub-units. The vertical columns of the photonic biasing sub-units correspond one-to-one with the photonic weighting sub-units. Each photonic biasing sub-unit includes an independent second micro-ring resonator. Each second micro-ring resonator encodes a bias for its corresponding photonic biasing sub-unit using the same tuning method as the first micro-ring resonator.

[0043] Figure 3 The diagram shows a schematic of a multi-architecture adaptive computing chip for optical neural networks based on a micro-ring array structure. Three optical signals of different wavelengths, λ1, λ2, and λ3, are generated by the optical signal input unit 1. These three wavelengths are then modulated by the input data modulation unit 2, resulting in input data represented by x1, x2, and x3. Simultaneously, an additional bias optical signal λ4 with constant power is input, its power being constant and independent of the input data signal.

[0044] The photonic weighting module 301 employs a 3×3 microring resonator cross array structure (3 transverse waveguides and 3 longitudinal waveguides). A first microring resonator is positioned at each cross node, and weighting is implemented through a column of these first microring resonators. To introduce bias, a set of second microring resonators corresponding to the bias light is added for bias encoding. After the input optical signal passes through the photonic weighting module 301, optical multiplication and addition calculations are performed; for example, for a single output, y=w... 11 x1+w 12 x2+w 13 x3.

[0045] The photonic bias module 302 includes three photonic bias sub-units, which correspond one-to-one with the vertical columns of the photonic weighting sub-units. Each photonic bias sub-unit contains a second micro-ring resonator, which encodes the bias value through the same thermal tuning method, and superimposes the amplitude of the bias optical signal with the optical multiply-accumulate calculation result output by the photonic weighting module 301, resulting in the output result y1 = y + b1.

[0046] The advantage of this embodiment is its compact structure. The bias light is combined with the data signal through wavelength division multiplexing, which improves the parallelism.

[0047] Example 2

[0048] In another embodiment of the present invention, the weight and bias processing unit 3 is implemented based on a Mach-Zehnder interferometer array structure.

[0049] Figure 4 The diagram shown is a schematic of the principle of an optical neural network multi-architecture adaptation computing chip based on a Mach-Zehnder interferometer array structure. The difference between this embodiment and the first embodiment is that the modulation unit used in the weight and bias processing unit 3 in this embodiment is an MZI interferometer (Mach-Zehnder interferometer).

[0050] Specifically, in the input layer, both data optical signals and bias optical signals are input to the MZI interferometer array. The bias light has a constant power.

[0051] The photonic weighting module 301 includes multiple parallel photonic weighting sub-units, each composed of an MZI interferometer array, used to encode the corresponding weights through thermal tuning or electro-optic response tuning. The photonic biasing module 302 includes multiple photonic biasing sub-units, which correspond one-to-one with the photonic weighting sub-units. The bias value is encoded through electro-optic tuning, and the bias signal is summed with the optical multiply-add calculation result output by the photonic detection unit 4.

[0052] This embodiment utilizes the interference characteristics of the MZI interferometer to improve modulation accuracy.

[0053] Example 3

[0054] In another embodiment of the present invention, the weight and bias processing unit 3 is implemented based on an on-chip diffraction unit structure.

[0055] Figure 5The diagram illustrates the principle of a multi-architecture adaptation computing chip for optical neural networks based on an on-chip diffraction unit structure. In this embodiment, the photonic weighting module 301 includes multiple photonic weighting sub-units arranged in a two-dimensional array. Each photonic weighting sub-unit includes a set of on-chip diffraction units, which are used to encode the corresponding weights. The on-chip diffraction units can be metasurface diffraction structures or phase-modulated grating structures. By controlling the phase and intensity of the incident light through a preset diffraction phase distribution, the optical encoding of the weight parameters is achieved. The photonic biasing module 302 includes multiple photonic biasing sub-units, with a one-to-one correspondence between the column directions of the photonic biasing sub-units and the photonic weighting sub-units. Each photonic biasing sub-unit includes a set of on-chip diffraction units with the same structure as the photonic weighting sub-units, used to encode the bias parameters through a fixed diffraction mode.

[0056] In the input layer, data optical signals and bias optical signals are input through diffraction units. The optical signals are weighted and modulated by the on-chip diffraction units, while the bias light is encoded by a specific diffraction mode to achieve optical multiply-add calculation. The photodetector unit 4 directly detects the diffraction output, and the result includes bias summation.

[0057] This embodiment is suitable for large-scale parallel computing, and the on-chip diffraction unit is easy to integrate.

[0058] Example 4

[0059] In another embodiment of the present invention, the weight and bias processing unit 3 is implemented based on a cascaded time-domain modulator structure.

[0060] Figure 6 The diagram illustrates the principle of a multi-architecture adaptation computing chip for optical neural networks based on a cascaded time-domain modulator. In this embodiment, the photonic weighting module 301 includes multiple photonic weighting sub-units allocated according to a time sequence. Each photonic weighting sub-unit is configured with an independent modulation bit in the time-domain modulator, and each modulation bit is used to encode the corresponding weight. The photonic biasing module 302 includes multiple photonic biasing sub-units, which correspond one-to-one with the photonic weighting sub-units. Each photonic biasing sub-unit encodes the bias parameters by adding a bias constant term of fixed amplitude to the end of the time-domain modulation sequence of the source data and loading it onto the input optical signal.

[0061] The weight and bias processing unit 3 also includes a time-domain integration subunit, which is used to calculate the electrical signal output by the photoelectric detection unit 4 to achieve multiplication, addition and bias summation.

[0062] Among them, the time-domain integrator is a time-domain integrator based on an analog amplifier. The integration circuit of the analog amplifier is used to sample the electrical signal output by the photoelectric detection unit 4. The capacitor of the analog amplifier is used to accumulate charge for charging. The process from the completion of capacitor charging to the completion of capacitor release is one integration process.

[0063] Specifically, a constant term is added as a bias after the source data input to the input layer, such as x1, x2, x3, forming an extended data stream [x1, x2, x3, 1]; the optical signal input region modulates the extended data onto the optical carrier. The time-domain modulator carries the input data weights and bias weights, such as [w 11 ,w 12 ,w 13 [b1] Optical multiplication and addition calculations are achieved through intensity modulation. The optical signal varies with time, representing different data points. The photoelectric detection unit 4 converts the optical signal into an electrical signal, which is then accumulated by a capacitor charging process based on an analog amplifier using a time-domain integrator. The integration time can be adjusted by the RC parameter, and the output result is y1=w 11 x1+w 12 x2+w 13 x3+b1.

[0064] The advantage of this embodiment is that it can support ultra-large-scale data input and achieve efficient accumulation through the time domain dimension.

[0065] The same or similar parts between the various embodiments in this specification can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments.

[0066] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An optical neural network multi-architecture adaptation computing chip, characterized in that, It includes an optical signal input unit (1), an input data modulation unit (2), a weighting and biasing processing unit (3), and a photoelectric detection unit (4) that are sequentially coupled along the optical signal transmission path. The optical signal input unit (1) is used to generate and output an optical signal that meets the optical computing bandwidth requirements; The input data modulation unit (2) is configured as the input layer of an optical neural network, used to modulate and load the information carried by the source data and the preset bias data onto the optical signal output by the optical signal input unit (1), and obtain an optical signal loaded with mixed data. The weighting and biasing processing unit (3) includes a photonic weighting module (301) and a photonic biasing module (302). The photonic weighting module (301) is used to optically encode multiple preset weighting parameters and adjust the amplitude of the optical signal loaded with mixed data based on the encoded weighting parameters to realize the optical multiplication and addition calculation of the input data of the optical signal and the corresponding weighting parameters. The photonic biasing module (302) is used to optically encode multiple preset biasing parameters and perform one-to-one summation processing on the encoded biasing parameters and the results of the optical multiplication and addition operation to output the calculation result containing bias compensation. The photoelectric detection unit (4) is used to receive the optical signal corresponding to the calculation result containing the bias and convert it into an electrical signal for output; In the optical neural network multi-architecture adaptation computing chip, the weight and bias processing unit (3) can be implemented based on any one of the following: micro-ring array structure, Mach-Zehnder interferometer array structure, on-chip diffraction unit structure and cascaded time-domain modulator structure, in order to complete the optical multiplication and addition of input data and weight parameters and bias summation.

2. The optical neural network multi-architecture adaptive computing chip of claim 1, wherein, The optical signal input unit (1) includes a single laser or a laser array; wherein the single laser is used to output a continuous optical signal of a single wavelength, and the laser array is used to output multiple parallel optical signals of different wavelengths.

3. The optical neural network multi-architecture adaptive computing chip of claim 1, wherein, When the weight and bias processing unit (3) is implemented based on a micro-ring array structure: The photonic weighting module (301) includes multiple photonic weighting sub-units distributed along the intersection nodes of the transverse and longitudinal waveguides. Each photonic weighting sub-unit contains a column of first micro-ring resonators. Each first micro-ring resonator encodes its corresponding weights through thermal tuning or electro-optic response tuning. The photonic bias module (302) includes multiple photonic bias sub-units. The photonic bias sub-units correspond one-to-one with the vertical columns of the photonic weight sub-units. Each photonic bias sub-unit contains an independent second micro-ring resonator. Each second micro-ring resonator encodes a bias for the corresponding photonic bias sub-unit using the same tuning method as the first micro-ring resonator.

4. The optical neural network multi-architecture adaptive computing chip of claim 1, wherein, When the weight and bias processing unit (3) is implemented based on the Mach-Zehnder interferometer array structure: The photonic weighting module (301) includes multiple parallel photonic weighting sub-units. Each photonic weighting sub-unit is composed of an MZI interferometer array and is used to encode the corresponding weights by means of thermal tuning or electro-optic response tuning. The photon bias module (302) includes multiple photon bias sub-units, and the photon bias sub-units correspond one-to-one with the photon weight sub-units. Each photon bias sub-unit is encoded with a bias, and the bias encoding method is thermal tuning or electro-optic response tuning.

5. The optical neural network multi-architecture adaptation computing chip according to claim 1, characterized in that, When the weight and bias processing unit (3) is implemented based on an on-chip diffraction unit structure: The photon weighting module (301) includes multiple photon weighting sub-units arranged in a two-dimensional array. Each photon weighting sub-unit includes a set of on-chip diffraction units, and each on-chip diffraction unit is used to encode the corresponding weights. The photon biasing module (302) includes multiple photon biasing sub-units, and the column directions of the photon biasing sub-units correspond one-to-one with those of the photon weighting sub-units. Each photon biasing sub-unit includes a set of on-chip diffraction units with the same structure as the photon weighting sub-units, which are used to encode the bias parameters through a fixed diffraction mode.

6. The optical neural network multi-architecture adaptation computing chip according to claim 1, characterized in that, When the weight and bias processing unit (3) is implemented based on a cascaded time-domain modulator structure: The photonic weighting module (301) includes multiple photonic weighting sub-units allocated according to time sequence. Each photonic weighting sub-unit is configured with an independent modulation bit in the time-domain modulator. Each modulation bit is used to encode the corresponding weights respectively. The photonic bias module (302) includes multiple photonic bias sub-units, and the photonic bias sub-units correspond one-to-one with the photonic weighting sub-units. Each photonic bias sub-unit encodes the bias parameters by adding a bias constant term with a fixed amplitude to the end of the temporal modulation sequence of the source data and loading it onto the input optical signal.

7. The optical neural network multi-architecture adaptation computing chip according to claim 6, characterized in that, The weight and bias processing unit (3) further includes a time-domain integration subunit, which is used to calculate the electrical signal output by the photoelectric detection unit (4) to achieve multiplication, addition and bias summation.

8. The optical neural network multi-architecture adaptation computing chip according to claim 7, characterized in that, The time-domain integrator is a time-domain integrator based on an analog amplifier. The integration circuit of the analog amplifier is used to sample the electrical signal output by the photoelectric detection unit (4). The capacitor of the analog amplifier is used to accumulate charge for charging. The process from the completion of charging to the completion of releasing the capacitor is one integration process.

9. The optical neural network multi-architecture adaptation computing chip according to claim 1, characterized in that, The photoelectric detection unit (4) uses a germanium-silicon photodetector with germanium epitaxial growth on silicon to realize the conversion of optical signals to electrical signals.

10. A computational method for an optical neural network multi-architecture adaptive computing chip, characterized in that, The optical neural network multi-architecture adaptation computing chip based on any one of claims 1 to 9 includes the following steps: S1, according to the target architecture adopted by the weight and bias processing unit (3), control the optical signal input unit (1) to generate and output an optical signal with an optical signal wavelength or optical field mode that matches the target architecture; wherein, the target architecture is any one of the following: micro-ring array structure, Mach-Zehnder interferometer array structure, on-chip diffraction unit structure and cascaded time-domain modulator structure. S2, the information carried by the source data and the bias data is co-modulated and loaded onto the optical signal output in step S1 through the input data modulation unit (2) to form an optical signal loaded with mixed data; S3, the preset weight parameters are optically encoded by the photonic weight module (301) of the weight and bias processing unit (3), and the amplitude of the optical signal loading the mixed data is adjusted based on the encoded weight parameters to complete the optical multiplication and addition calculation of the input data and the corresponding weight; at the same time, the preset bias parameters are optically encoded by the photonic bias module (302), and the encoded bias parameters and the result of the optical multiplication and addition calculation are summed one by one to obtain the calculation result including bias compensation; S4, the photoelectric detection unit (4) receives the optical signal corresponding to the calculation result including bias compensation output in step S3, converts it into an electrical signal and outputs it to complete the single optical neural network forward calculation.

Images