Three-dimensional memory, method, and memory system

Abstract

The present disclosure provides a three-dimensional memory and a manufacturing method thereof, a memory system, and an electronic device. The three-dimensional memory includes a stacked structure, a plurality of first stops arranged in a first direction X, a protective layer, and a plurality of contact posts. The stacked structure includes a step structure including a plurality of stair structures arranged in the first direction and having different heights in a second direction. The plurality of first stops are arranged in a plurality of steps of at least one of the stair structures. The protective layer covers the step structure and the first stops, and at least a portion of the protective layer is arranged between the first stops and a step adjacent to the first stops. The contact posts extend through the protective layer and the first stops and are connected to the gate layer at the steps corresponding to the first stops.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This disclosure is based on Chinese Patent Application No. 202210273522.3 filed on March 18, 2022 and Chinese Patent Application No. 202210273515.3 filed on March 18, 2022, and claims priority to these two Chinese patent applications, which are incorporated by reference herein in their entireties.

[0002] The present disclosure relates to the field of semiconductor chip technology, and in particular to a three-dimensional memory and its manufacturing method, a memory system, and an electronic device. [Background technology]

[0003] As the feature size of memory cells approaches the lower process limits, planar processes and manufacturing techniques become difficult and expensive, resulting in the memory density of 2D or planar NAND flash approaching the upper limit. To overcome the limitations posed by 2D or planar NAND flash, memory with three-dimensional structures (3D NAND) has been developed in the industry, which improves memory density by arranging memory cells three-dimensionally on a substrate.

[0004] In the actual manufacturing process of a 3D memory, to implement electrical connections between the contacts and the gate layers in the stack structure, contact holes exposing the respective gate layers in the staircase region need to be formed in the dielectric layer covering the stack structure, and then a conductive material is filled into the contact holes to form the contacts.

[0005] However, the higher the integration density of 3D memory and the more layers there are, the deeper the contact holes become, and the upper gate layer is etched during the contact hole formation process. In this case, after filling the contact holes with a conductive material to form contacts, a short circuit between different gate layers (i.e., an electrical connection between word lines in different layers) may occur, which may lead to memory failure. Summary of the Invention

[0006] Examples of the present disclosure provide a three-dimensional memory and a method for manufacturing the same, a memory system, and an electronic device.

[0007] The examples of the present disclosure adopt the following technical solutions.

[0008] In one embodiment, a three-dimensional memory is provided. The three-dimensional memory includes a stack structure, a plurality of first stops arranged in a first direction, a protective layer, and a plurality of contact posts. The stack structure includes gate layers and dielectric layers arranged in an alternating manner. The stack structure includes a step structure including a plurality of stair structures arranged in the first direction and having different heights in a second direction. The stair structure includes a plurality of steps. The first direction and the second direction are perpendicular to each other. The plurality of first stops arranged in the first direction are arranged in a plurality of steps of at least one stair structure, and each of the first stops is arranged in one of the steps. A protective layer covers the step structure and the first stops, and at least a portion of the protective layer is arranged between the first stops and the steps adjacent to the first stops. The contact posts extend through the protective layer and the first stops and are connected to the gate layer at the steps corresponding to the first stops.

[0009] In some examples, the three dimensional memory further includes an isolation structure extending through the stack structure in the first direction, the isolation structure dividing the stack structure into a plurality of memory blocks, each memory block including a step structure, and a stair structure in which the first stop is disposed, the step structure being spaced apart from the isolation structure.

[0010] In some examples, in the second direction, the memory block comprises a first staircase structure, a second staircase structure, and a third staircase structure, and the first stops are disposed on multiple steps of the second staircase structure.

[0011] In some examples, in the second direction, the memory block comprises a first staircase structure and a second staircase structure, the first staircase structure being spaced apart from the isolation structure, and the first stop portions being disposed at multiple steps of the first staircase structure.

[0012] In some examples, each memory block further includes a sidewall 16. The isolation structure includes a first isolation structure and a second isolation structure, where in the second direction, the first isolation structure is disposed between two adjacent sidewalls and the second isolation structure is disposed between two adjacent step structures, and where in the second direction, the step structures in the two memory blocks adjacent to the second isolation structure are symmetrically disposed.

[0013] In some examples, in the second direction, along a direction from the first isolation structure to the second isolation structure, the plurality of staircase structures in the memory block gradually decrease in height.

[0014] In some cases, the two adjacent stair structures on either side of the second isolation structure in the second direction have the same height.

[0015] In some examples, the three-dimensional memory further includes a plurality of second stops arranged in the first direction. The plurality of second stops arranged in the first direction are arranged on a plurality of steps of other staircase structures among the plurality of staircase structures other than the staircase structure in which the first stops are arranged. The protective layer further covers the second stops, and at least a portion of the protective layer is arranged between the second stops and the steps adjacent to the second stops.

[0016] In some examples, the three-dimensional memory further includes a plurality of gate line isolation structures extending in the first direction. The plurality of gate line isolation structures extending in the first direction are disposed between two adjacent isolation structures, and the gate line isolation structures extend through the second stop and the stack structure. Each gate line isolation structure includes a plurality of sub-isolation structures separated from each other along the first direction. The material of the second stop is the same as the material of the gate layer.

[0017] In some cases, the material of the second stop is the same as the material of the first stop.

[0018] In some examples, the material of the first stop includes silicon nitride.

[0019] In some cases, in a third direction, the thickness of the first stop is the same as the thickness of the gate layer of a previous step, the previous step being adjacent to and higher than the step corresponding to the first stop, and the third direction is perpendicular to the stacked structure.

[0020] In another aspect, a method for manufacturing a three dimensional memory is provided, the method comprising: forming an initial laminate structure, the initial laminate structure including alternating sacrificial layers and dielectric layers, the initial laminate structure including a step structure including a plurality of step structures arranged in a first direction and having different heights in a second direction, the step structure including a plurality of steps, the first direction and the second direction being perpendicular to each other; forming a plurality of first stops on at least one of a plurality of steps of the staircase structure, the plurality of first stops being disposed in a first direction, each of the first stops being disposed on one of the steps; forming a protective layer, the protective layer covering the step structure and the first stop, at least a portion of the protective layer being disposed between the first stop and a step adjacent to the first stop; replacing the sacrificial layer with a gate layer to form a stack structure; forming a plurality of contact posts extending through the protective layer and the first stops and electrically connected to the gate layer at steps corresponding to the first stops.

[0021] In some examples, forming a plurality of first stops on a plurality of steps of the at least one stair structure includes etching a sacrificial layer and a dielectric layer on a top of each step to form a plurality of first stops.

[0022] In some examples, the method further includes forming a first slit extending through the initial stack structure in a first direction, the first slit dividing the initial stack structure into a plurality of initial memory blocks each including a staircase structure, and a separation structure formed in the first slit.

[0023] In some examples, the manufacturing method further includes forming a second isolated sub-portion extending through the initial laminate structure in a first direction, and forming a first sub-slit, a second sub-slit, and a second slit extending through the initial laminate structure in the first direction, the first sub-slit and the second sub-slit contacting opposite ends of the second isolated sub-portion in the first direction, respectively, and the second slit being disposed between two adjacent second isolated sub-portions in the second direction. The first isolated sub-portion is formed in the first sub-slit, the third isolated sub-portion is formed in the second sub-slit, and the second isolated structure is formed in the second slit. The first isolated sub-portion, the third isolated sub-portion, and the second isolated sub-portion constitute at least a portion of the first isolated structure.

[0024] In some examples, the manufacturing method further includes forming a plurality of second stops on a plurality of steps of other staircase structures among the plurality of staircase structures other than the staircase structure in which the first stop is disposed, each of the second stops being disposed on one step.

[0025] In some examples, the manufacturing method further includes forming a plurality of third slits extending in the first direction, the third slits extending through the second stop and the initial stack structure, each of the third slits including a plurality of third sub-slits spaced apart from one another in the first direction, and a gate line isolation structure formed in the third slits.

[0026] In some examples, forming the plurality of contact posts includes etching the protective layer to a first stop to form a plurality of contact holes, etching the first stop exposed by the contact holes, etching the dielectric layer below the first stop so that the contact holes expose the gate layer, and forming contact posts in the contact holes.

[0027] In yet another aspect, a memory system is provided, the memory system including the controller and the three-dimensional memory of any of the above examples, the controller coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data.

[0028] In yet another aspect, an electronic device is provided, the electronic device comprising a memory system according to any of the examples above. [Brief description of the drawings]

[0029] In order to more clearly describe the technical solutions in the present disclosure, the drawings required in some examples of the present disclosure are briefly introduced. Obviously, the drawings in the following description are only drawings for some examples of the present disclosure, and those skilled in the art can obtain other drawings from these drawings. Furthermore, the drawings described below can be regarded as illustrative diagrams, and do not limit the actual size of the products, the actual flow of the methods, and the actual timing of the signals included in the examples of the present disclosure. [Figure 1] FIG. 1 is a perspective structural diagram of a three-dimensional memory, according to some examples. [Diagram 2] FIG. 1 is a structural diagram of a contact post and step in the prior art. [Diagram 3] FIG. 2 is another structural view of a contact post and step in the prior art. [Figure 4] 1A-1C are structural diagrams of contact posts according to some examples. [Figure 5A] 1 illustrates a top view of a three-dimensional memory, according to some examples. [Figure 5B] 1 illustrates a top view of a three-dimensional memory, according to some examples. [Figure 6] FIG. 5B is an enlarged view of the CC region in FIG. 5A. [Figure 7A] FIG. 7 is a cross-sectional view taken along the line DD' in FIG. [Figure 7B] 7 is another cross-sectional view taken along the line DD' in FIG. 6. [Figure 8] FIG. 7 is a cross-sectional view taken along the line EE' in FIG. [Figure 9] 7 is another cross-sectional view taken along the line EE' in FIG. 6. [Figure 10] FIG. 5B is another enlarged view of the CC region in FIG. 5A. [Figure 11] 11 is a cross-sectional view taken along the line FF' in FIG. [Figure 12A] 1A-1C are structural diagrams of stage structures according to some examples. [Figure 12B] 11A-11C are structural diagrams of other stage structures, according to some examples. [Figure 13] FIG. 5B is yet another enlarged view of the CC region in FIG. 5A. [Figure 14] FIG. 5B is yet another enlarged view of the CC region in FIG. 5A. [Figure 15] 15 is a cross-sectional view taken along the line GG' in FIG. 14. [Figure 16] FIG. 2 is a structural diagram of a memory string, according to some examples. [Figure 17] FIG. 17 is an equivalent circuit diagram of the memory string in FIG. [Figure 18] FIG. 5B is yet another enlarged view of the CC region in FIG. 5A. [Figure 19A] 19 is a cross-sectional view taken along the line HH' in FIG. 18. [Figure 19B] 19 is another cross-sectional view taken along the line HH' in FIG. 18. [Figure 20] 19 is a cross-sectional view taken along line II' in FIG. 18. [Figure 21] 19 is another cross-sectional view taken along the line II in FIG. 18. [Figure 22] FIG. 5B is yet another enlarged view of the CC region in FIG. 5A. [Figure 23] 23 is a cross-sectional view taken along the line JJ' in FIG. 22. [Figure 24A] 11A and 11B are structural diagrams of yet other stage structures according to some examples. [Figure 24B] 11A and 11B are structural diagrams of yet other stage structures according to some examples. [Diagram 25] FIG. 5B is yet another enlarged view of the CC region in FIG. 5A. [Figure 26] FIG. 5B is yet another enlarged view of the CC region in FIG. 5A. [Figure 27] FIG. 27 is a cross-sectional view taken along the line K-K' in FIG. 26. [Figure 28] 1 is a flowchart of a method for manufacturing a three-dimensional memory according to some implementation examples. [Figure 29A]1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 29B] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Diagram 30] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Diagram 31] 1 is a flowchart of a method for manufacturing a three-dimensional memory according to some implementation examples. [Diagram 32] 1 is a flowchart of a method for manufacturing a three-dimensional memory according to some implementation examples. [Figure 33A] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 33B] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Diagram 34] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 35A] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 35B] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Diagram 36] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 37] 1 is a flowchart of a method for manufacturing a three-dimensional memory according to some implementation examples. [Figure 38] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 39] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Diagram 40] 1 is a flowchart of a method for manufacturing a three-dimensional memory according to some implementation examples. [Figure 41A] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 41B] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Diagram 42] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Diagram 43] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Diagram 44]1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Diagram 45] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Diagram 46] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 47] 1 is a flowchart of a method for manufacturing a three-dimensional memory according to some implementation examples. [Figure 48] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 49] 1 is a flowchart of a method for manufacturing a three-dimensional memory according to some implementation examples. [Figure 50] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 51] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 52] 1 is a flowchart of a method for manufacturing a three-dimensional memory according to some implementation examples. [Figure 53] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 54] 1 is a flowchart of a method for manufacturing a three-dimensional memory according to some implementation examples. [Figure 55] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 56] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 57] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 58] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, according to some examples. [Figure 59] 1 is a flowchart of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 60] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 61] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 62] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 63] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 64] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 65] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 66] 1 is a flowchart of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 67] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 68] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 69] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 70] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 71] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 72] 1 is a flowchart of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 73] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 74] 1 is a flowchart of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 75] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 76] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 77] 1 is a flowchart of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 78] 1 is a flowchart of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 79] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 80] 1 is a flowchart of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 81]1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 82] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 83] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 84] 1 is a flow diagram of another method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 85] FIG. 13 is a structural diagram of another three-dimensional memory according to some examples. [Figure 86] FIG. 13 is a diagram of yet another three-dimensional memory structure according to some examples. [Figure 87] FIG. 2 is a structural diagram of a memory system, according to some examples. [Figure 88] FIG. 2 is a structural diagram of another memory system, in accordance with some examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] The technical solutions in some examples of the present disclosure are described below clearly and completely with the accompanying drawings. However, it is clear that the described examples are only some of the examples of the present disclosure, not all of them. All other examples obtained by those skilled in the art based on the examples provided in the present disclosure are within the scope of the present disclosure.

[0031] In describing this disclosure, terms such as "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, are understood to refer to orientations or positional relationships based on those depicted in the figures, for purposes of facilitating and simplifying the description of the disclosure only, and do not indicate or imply that the referenced device or element must have a particular orientation, or be constructed and operated in a particular orientation, and thus these terms cannot be construed as limiting the disclosure.

[0032] Unless the context clearly indicates otherwise, the term "include" is to be construed in an open and inclusive sense throughout the specification and claims, i.e., "including, but not limited to." In the description herein, the terms "one example," "some examples," "exemplary implementations," "examples," or "some examples" are intended to mean that a particular feature, structure, material, or characteristic associated with an example or implementation is included in at least one example or implementation of the present disclosure. Exemplary renditions of the above terms do not necessarily refer to the same example or implementation. Moreover, a particular feature, structure, material, or characteristic may be included in any one or more examples or implementations in any suitable manner.

[0033] In the following, terms such as "first", "second", etc. are not to be construed as indicating or implying a relative importance or a number of technical features indicated, but are used for descriptive purposes only. Thus, a feature defined by "first" or "second" can explicitly or implicitly include one or more instances of the feature. In the description of examples of the present disclosure, "plurality" means two or more, unless otherwise specified.

[0034] In describing some examples, expressions such as "couple" and "connect" and their extensions may be used. For example, the term "connect" may be used in describing some examples to indicate that two or more components have direct physical or electrical contact. As another example, the term "couple" may be used while describing some examples to indicate that two or more components have direct physical or electrical contact. However, the term "couple" may also indicate that there is no direct contact between two or more components, but that they still cooperate or interact with each other. The examples disclosed herein are not necessarily limited to the contents provided herein.

[0035] "At least one of A, B, and C" and "at least one of A, B, or C" have the same meaning and both include the following combinations of A, B, and C: A only; B only; C only; a combination of A and B; a combination of A and C; a combination of B and C; and a combination of A, B, and C.

[0036] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0037] As used herein, "about," "generally," or "approximately" includes stated and average values ​​within an acceptable deviation range of the particular value, which is determined by one of ordinary skill in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity, i.e., the limitations of the measurement system.

[0038] In this disclosure, the meanings of "on," "over," and "above" are to be interpreted in the broadest possible manner, such that "on" not only means "directly on" something, but also includes the meaning "on" of something with an intermediate feature or layer between them, and "over" or "above" not only means "over" or "above" something, but also includes the meaning "over" or "above" something without an intermediate feature or layer between them (e.g., directly on top of something).

[0039] Exemplary implementations are described herein with reference to cross-sectional and / or plan views as idealized exemplary drawings. In the drawings, thicknesses of layers and regions are exaggerated for illustrative purposes. Thus, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be expected. Thus, the exemplary implementations should not be construed as being limited to the shapes of regions shown herein, including, for example, shape deviations caused by manufacturing. For example, an etched region shown as a rectangle can have curved features. Thus, the regions shown in the drawings are exemplary in nature, and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the exemplary implementations.

[0040] Referring to FIGS. 1-3, FIG. 1 is a perspective structural view of a three-dimensional memory 100, and FIGS. 2 and 3 are two structural views of a portion of a contact post and a step in the prior art.

[0041] In some examples, as shown in FIG. 1, the three-dimensional memory 100 has a stepped structure and includes a stacked structure including a plurality of alternating gate layers G and dielectric layers (not shown in FIG. 1). Both the gate layers G and the dielectric layers extend in a first direction X. In a third direction Z, at least one bottom gate layer G of the plurality of gate layers G is configured as a source end select gate SGS, at least one top gate layer G of the plurality of gate layers G is configured as a drain end select gate SGD, and the gate layers G between the source end select gate SGS and the drain end select gate SGD are configured as a plurality of word lines WL.

[0042] In order to supply electrical signals to the source end select gate SGS, the drain end select gate SGD, and the word line WL, the three-dimensional memory 100 further includes a plurality of contact posts CNT. Of the plurality of contact posts CNT, the contact post CNT electrically connected to the drain end select gate SGD is configured as a drain end select gate contact post SGDCNT, the contact post CNT electrically connected to the source end select gate SGS is configured as a source end select gate contact post SGSCNT, and the contact post CNT electrically connected to the word line WL is configured as a word line contact post WLCNT.

[0043] 2, as the integration degree increases, the number of stacked gate layers G and dielectric layers in the 3D memory gradually increases, and the difference in depth between different contact posts CNT in the third direction Z becomes larger and larger. Therefore, in the process of forming a plurality of contact posts CNT, the upper layer stage is easily penetrated by the contact hole in which the contact post CNT is arranged, so that a short circuit occurs between different gate layers G after the formation of the plurality of contact posts CNT, which causes a failure of the 3D memory.

[0044] In view of this problem, referring to Fig. 3, in the prior art, the problem that the gate layer G is easily penetrated during the manufacture of the contact post CNT is improved by increasing the thickness of the gate layer G in the step. However, in order to prevent the contact hole from penetrating the gate layer G in the step, it is necessary to increase the thickness of the gate layer G in the step, which is very difficult to form.

[0045] For this reason, while making the thickness of the gate layer G in the step as thick as possible, in the conventional technology, the etching rate is reduced so that the contact hole does not penetrate the gate layer G in the step. However, as shown in FIG. 4, the etching rate is slow and the etching directionality is poor, so that the linearity of the contact hole obtained by etching is poor, and the linearity of the contact post CNT is also poor. In particular, in the process of etching the contact hole, due to the poor etching directionality, it is highly likely that the dummy channel structure adjacent to the contact hole will be etched, and as a result, after the contact post is formed, the conductive material will also be filled into the dummy channel structure, which will cause a short circuit between multiple gate layers, resulting in a poor-performance three-dimensional memory.

[0046] Furthermore, if the thickness of the gate layer G in a stage is large, during the process of replacing the gate layer using a gate line slit, conductive material may remain in the gate line slit, which may cause multiple gate layers to short-circuit, resulting in a failure of the 3D memory after the gate layer replacement.

[0047] To address at least one of the problems discussed above, with reference to FIGS. 5A-8, some examples of the present disclosure provide a three-dimensional memory 200.

[0048] As shown in Figures 5A and 5B, the three-dimensional memory 200 includes a core array region AA and a step region SS in the first direction X. As shown in Figure 5A, the three-dimensional memory 200 may include two core array regions AA and one step region SS disposed between the two core array regions AA. Alternatively, as shown in Figure 5B, the three-dimensional memory 200 may include two step regions SS and one core array region AA disposed between the two step regions SS.

[0049] It is understood that the method of distribution of the core array regions AA and stage regions SS in the three-dimensional memory 200 provided in some examples of the present disclosure is not limited thereto.

[0050] Fig. 6 is an enlarged view of a region CC in Fig. 5A, Figs. 7A and 7B are cross-sectional views taken along line DD' in Fig. 6, and Fig. 8 is a cross-sectional view taken along line EE' in Fig. 6.

[0051] 6 to 8, the three-dimensional memory 200 includes a laminated structure 10, a plurality of first stop portions 20 arranged in a first direction X, a protective layer 30, and a plurality of contact posts 40.

[0052] The stacked structure 10 includes alternating gate layers 11 and dielectric layers 12 .

[0053] 7A, in some examples, the gate layer 11 may be a single-layer structure, and includes a conductive layer 111. The material of the conductive layer 111 includes, but is not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, doped silicon and / or silicide.

[0054] In some examples, referring to Fig. 7B, the gate layer 11 may be a multi-layer composite structure. In this case, the gate layer 11 may be formed by sequentially forming a high dielectric constant layer 112, a metal compound layer 113, and a conductive layer 111. The material of the high dielectric constant layer 112 may be, for example, aluminum oxide (Al2O3), and the material of the metal compound 113 may be, for example, tantalum nitride or titanium nitride.

[0055] Illustratively, the dielectric layer 12 may be made of an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0056] It should be noted that in the stacked structure 10, the thicknesses of the gate layers 11 may be approximately the same or different. The thicknesses of the dielectric layers 12 may be approximately the same or different. The thicknesses of the gate layers 11 and the dielectric layers 12 can be selected according to actual demand. Furthermore, the number of stacks in the stacked structure 10 determines the number of memory cells. The more stacks in the stacked structure 10, the higher the integration, i.e., the more memory cells there are. In one example, the number and height of the stacked structure 10 can be designed based on actual memory demand, which is not limited in the present disclosure.

[0057] The laminated structure 10 includes a step structure 13 arranged in a first direction X and including a plurality of step structures 14 having different heights in a second direction Y. The step structure 14 includes a plurality of steps 141. The first direction X is perpendicular to the second direction Y.

[0058] When the step structure 13 is arranged in a first direction X and includes stair structures 14 having different heights in a second direction Y, it is understood that two adjacent stair structures 14 among the multiple stair structures 14 included in the step structure 13 have different heights, but two spaced apart stair structures 14 may have the same height.

[0059] In some examples, referring to Figures 6 and 8, the step structure 13 may include three staircase structures 14 arranged in the second direction Y and having different heights from each other.

[0060] In some other examples, referring to Figures 6 and 9, the step structure 13 may include three stair structures 14 arranged in the second direction Y, where the two stair structures 14 on either side have a different height from the central stair structure 14 and have the same height as each other.

[0061] Further, in some examples, referring to FIGS. 10 and 11, the step structure 13 may include two staircase structures 14 arranged in the second direction Y and having different heights.

[0062] It should be noted that the number of staircase structures 14 in the present disclosure is not limited thereto.

[0063] A plurality of first stops 20 are arranged in a first direction X and are disposed on a plurality of steps 141 of at least one stair structure 14, with each first stop 20 being disposed on one step 141.

[0064] As shown in Figures 8, 9, and 11, the first stops may be disposed only on the steps 141 of one staircase structure 14. It is also possible that the first stops 20 are disposed on the steps 141 of the multiple staircase structures 14.

[0065] 8, the stage 141 may include one gate layer 11 and one dielectric layer 12. Alternatively, the stage 141 may include multiple gate layers 11 and multiple dielectric layers 12. This is not a limitation in the present disclosure.

[0066] As shown in FIG. 8 , the protective layer 30 covers the step structure 13 and the first stop portion 20, and at least a portion of the protective layer 30 is positioned between the first stop portion 20 and the step 141 adjacent to the first stop portion 20.

[0067] It will be understood that "the step 141 adjacent to the first stop portion 20" may include not only the step 141 adjacent to the first stop portion 20 in the first direction X as shown in FIG. 7A, but also the step 141 adjacent to the first stop portion 20 in the second direction Y as shown in FIG. 8.

[0068] Exemplarily, the protective layer 30 may be made of silicon oxide, including, but not limited to, tetraethoxysilane (TEOS), siloxane, silsesquioxane, etc. Exemplarily, the protective layer 30 may be formed by a chemical vapor deposition (CVD) process, a spin-coating process, etc.

[0069] At least a portion of the protective layer 30 is present between the first stop 20 and the step 141 adjacent to the first stop 20. Thus, in the process of forming the gate layer 11, the sacrificial layer and the first stop 20 can be separated by the protective layer 30, thus preventing the sacrificial layer from being replaced with a gate layer and the first stop being replaced at the same time, which would otherwise cause the contact post to be electrically connected to multiple gate layers through the replaced first stop, thereby causing failure of the three-dimensional memory.

[0070] A contact post of the plurality of contact posts 40 extends through the protective layer 30 and the first stop 20 and connects to the gate layer 11 at a step corresponding to the first stop 20 .

[0071] Illustratively, the contact posts 40 may be made of conductive materials including, but not limited to, metals such as tungsten, copper, aluminum, metal silicides, metal nitrides, and / or doped polysilicon.

[0072] It is understood that the above-mentioned step structure 13 is disposed within a step region SS. When the step region SS is disposed between two core array regions AA, the topography of the step structure 13 may be as shown in Figures 12A and 12B. That is, the step structure 13 may include at least one step group in which the height of a plurality of steps 141 gradually increases or decreases in the first direction X.

[0073] 12A and 12B, the step structure 13 may include eight step groups in the first direction X, including a first step group 131, a second step group 132, a third step group 133, a fourth step group 134, a fifth step group 135, a sixth step group 136, a seventh step group 137, and an eighth step group 138. In the first direction X, the heights of the steps 141 in the first step group 131, the third step group 133, the fifth step group 135, and the seventh step group 137 are gradually decreased. In the first direction X, the heights of the steps 141 in the second step group 132, the fourth step group 134, the sixth step group 136, and the eighth step group 138 are gradually increased. Of course, the form of the step structure 13 in the present disclosure is not limited to this.

[0074] In the three-dimensional memory 200 provided in some examples of the present disclosure, a plurality of first stop portions 20 are disposed on at least one staircase structure 14 in the step structure 13. Thus, when forming the contact hole 41 in which the contact post 40 is disposed, an etching process such as wet etching can be used to remove a portion of the protective layer on the first stop portion 20 to expose a portion of the first stop portion 20, and then an etching process can be used to remove the exposed portion of the first stop portion 20 and the dielectric layer 12 between the first stop portion 20 and the gate layer 11 therebelow to expose a portion of the gate layer 11.

[0075] In the first etching step, due to the presence of the first stop portions 20, the contact holes 41 having different depths corresponding to the steps 141 having different heights may stop at the respective first stop portions 20 on the step 141. In the second etching step, since the distance between each first stop portion 20 and the gate layer 11 of the step 141 on which the first stop portion 20 is disposed is approximately the same, in the second etching step, the contact holes 41 having different depths corresponding to the steps 141 having different heights may stop at the respective gate layer 11 on the step 141 while simultaneously etching.

[0076] Thus, while forming the contact post 40 in the contact hole 41, the contact post 40 can contact the gate layer 11 of the corresponding stage 141, facilitating the avoidance of short circuits between multiple gate layers due to the contact post extending through the gate layer resulting from an increased number of layers in the stacked structure, thereby improving the electrical performance and yield of the three-dimensional memory.

[0077] At the same time, because the first stop 20 is provided, the etching rate may be faster while forming the contact hole in which the contact post is to be disposed by the etching process, thereby improving the linearity of the contact hole 41 (or the contact post 40), and then the dielectric layer in the dummy channel structure adjacent to the contact post 40 is less likely to be etched, thereby improving the yield of the three-dimensional memory 200.

[0078] 6 to 12B, in some examples, the three-dimensional memory 200 further includes an isolation structure 50. The isolation structure 50 extends through the stacked structure 10 in a first direction X. The isolation structure 50 divides the stacked structure 10 into a plurality of memory blocks 15. Each memory block 15 includes a step structure 13. The staircase structure 14 on which the first stop portion 20 is disposed is spaced apart from the isolation structure 50.

[0079] "The stair structure 14 on which the first stop portions 20 are located is spaced apart from the separation structure 50" means that a plurality of first stop portions 20 are spaced apart from the separation structure 50.

[0080] In some examples of the present disclosure, the stacked structure 10 is divided into multiple memory blocks 15 having the isolation structures 50, which can further improve the memory density of the three-dimensional memory 200. Meanwhile, the staircase structure 14 on which the first stop 20 is disposed is spaced apart from the isolation structures 50, which can also avoid the case where the first stop 20 is replaced in a subsequent process of forming the gate layer 11 by performing gate replacement using the slits on which the isolation structures 50 are disposed, thereby allowing the contact posts to penetrate the replaced first stop and electrically connect with multiple gate layers, resulting in failure of the three-dimensional memory.

[0081] It should be noted that when the isolation structure 50 divides the stacked structure 10 into multiple memory blocks 15, the isolation structure 50 also divides the gate layer 11 into multiple gate lines, such as source-end select gates or drain-end select gates or word lines. Each memory block 15 includes multiple gate lines spaced apart in the third direction Z.

[0082] For example, the first direction X may be the extension direction of the gate lines, the second direction Y may be the extension direction of the bit lines, and the third direction Z may be the stacking direction of the stacked structure 10.

[0083] In some examples, referring to Figures 6, 8 and 9, in the second direction Y, the memory block 15 includes a first staircase structure 14A, a second staircase structure 14B and a third staircase structure 14C, and the first stop portion 20 is arranged on a plurality of steps 141 of the second staircase structure 14B.

[0084] Thus, the second staircase structure 14B has a height difference in the third direction Z with both the first staircase structure 14A and the third staircase structure 14C and is spaced apart from the separation structure 50 (i.e., the first staircase structure 14A and the third staircase structure 14C are between the second staircase structure 14B and the separation structure 50), which facilitates subsequent etching of the steps and formation of the first stop 20 so that there is a gap between the first stop 20 and the adjacent step 141, thereby preventing replacement of the first stop.

[0085] In some other examples, referring to FIG. 11, in the second direction Y, the memory block 15 includes a first staircase structure 14A and a second staircase structure 14B, the first staircase structure 14A is spaced apart from the separation structure 50, and the first stop portion 20 is positioned on a plurality of steps 141 of the first staircase structure 14A.

[0086] Therefore, the first staircase structure 14A has a height difference with the second staircase structure 14B in the third direction Z and is spaced apart from the separation structure 50, which facilitates subsequent etching of the steps and formation of the first stop portion 20, so that a gap exists between the first stop portion 20 and the side of the adjacent step 141, thereby preventing the first stop portion 20 from being replaced.

[0087] In some examples, referring to FIG. 6 to FIG. 11, each memory block 15 further includes a sidewall 16 that functions as a bridge structure for connecting two core array regions AA. In some examples, a gate layer included in the staircase structure is connected to at least one gate layer of the two core array regions AA by a bridge structure. The isolation structure 50 includes a first isolation structure 51 and a second isolation structure 52. In the second direction Y, the first isolation structure 51 is disposed between two adjacent sidewalls 16, and the second isolation structure 52 is disposed between two adjacent step structures 13. The sidewalls 16 are configured to enhance the structural stability of the three-dimensional memory 200.

[0088] In some examples, the first separating structure 51 may be a one-piece structure, as shown in Figures 6 and 10. That is, when manufacturing the first separating structure 51, a slit in which the first separating structure 51 is disposed can be obtained by etching in a single etching step, and the first separating structure 51 can be formed in the slit.

[0089] 13 , the first isolated structure 51 may include a first isolated sub-portion 511, a second isolated sub-portion 512, and a third isolated sub-portion 513 that are sequentially connected in the first direction X. The size of the second isolated sub-portion 512 in the second direction Y is larger than that of the first isolated sub-portion 511 and larger than that of the third isolated sub-portion 513.

[0090] Exemplarily, the first separated sub-portion 511 has substantially the same size in the second direction Y as the third separated sub-portion 513.

[0091] Illustratively, the first isolated subportion 511 and the third isolated subportion 513 are disposed in the core array region AA, and the second isolated subportion 512 is disposed in the step region SS and contacts the sidewall 16 .

[0092] Exemplarily, the second isolation subportion 512 may be manufactured simultaneously with the dummy channel structure and the channel structure. The first isolation subportion 511 and the third isolation subportion 513 may be manufactured after the manufacturing of the channel structure is completed. Based on this, the material of the second isolation subportion 512 may be the same as the material of the dummy channel structure or the channel structure.

[0093] In some examples of the present disclosure, by providing a second isolation sub-portion 512, it is possible, on the one hand, to isolate two adjacent memory blocks 15, and, on the other hand, to support the stacked structure 10 and prevent the stacked structure 10 from collapsing.

[0094] In some examples, referring to Figures 6, 10 and 13, in the second direction Y, the step structures 13 in the two memory blocks 15 adjacent to the second isolation structure 52 are arranged symmetrically.

[0095] It is understood that "the step structures 13 in the two memory blocks 15 are arranged symmetrically" means that the number of staircase structures 14 included in the step structures 13 of the two memory blocks 15 is the same, and the two staircase structures 14 in the two step structures 13 having equal distances from the second isolation structure 52 have the same height.

[0096] In some examples, referring to Figures 8 and 11, in the second direction Y, the height of the multiple staircase structures 14 in the memory block 15 gradually decreases along the direction from the first isolation structure 51 to the second isolation structure 52.

[0097] In some other examples, referring to FIG. 9, in the second direction Y, along the direction from the first isolation structure 51 to the second isolation structure 52, the height of the multiple stair structures 14 in the memory block 15 first decreases and then increases.

[0098] In some examples, referring to Figures 8 and 9, in the second direction Y, the two adjacent staircase structures 14 on either side of the second isolation structure 52 have the same height.

[0099] 11, in some examples, the three-dimensional memory 200 further includes a plurality of second stop portions 60 arranged in the first direction X. The plurality of second stop portions 60 are arranged on a plurality of steps 141 of other staircase structures 14 among the plurality of staircase structures 14 other than the staircase structure 14 in which the first stop portion 20 is arranged.

[0100] The protective layer 30 further covers the second stop 60 , with at least a portion of the protective layer 30 being disposed between the second stop 60 and the step 141 adjacent the second stop 60 .

[0101] By way of example, referring to Figures 8 and 9, when the first stop portion 20 is positioned on the multiple steps 141 of the second staircase structure 14B, the second stop portion 60 can be positioned on the multiple steps 141 of the first staircase structure 14A and the third staircase structure 14C.

[0102] Illustratively, referring to FIG. 11, when the first stop portion 20 is positioned on a plurality of steps 141 of the first stair structure 14A, the second stop portion 60 may be positioned on a plurality of steps 141 of the second stair structure 14B.

[0103] In some examples, the material of the first stop 20 and the second stop 60 is the same. Illustratively, if the material of the first stop 20 and the second stop 60 is the same, the material of the first stop 20 and the second stop 60 may include, for example, carbon doped silicon nitride. Alternatively, in one example, if the material of the first stop 20 and the second stop 60 is the same, the material of the first stop 20 and the second stop 60 may be, for example, silicon nitride.

[0104] Illustratively, the material of the first stop 20 may be silicon nitride.

[0105] Thus, the material of the first stop 20 is different from the material of the gate layer 11, and the etching selectivity of the first stop 20 is different from the etching selectivity of the gate layer 11. The first stop 20 tends to be etched when the contact hole is formed by the etching process. Therefore, when manufacturing the contact hole 411 in which the contact post is arranged, the heights of the plurality of contact holes 41 corresponding to the step 141 can be made different from each other, and the distance between the bottom of each contact hole 41 and the step 141 can be made substantially the same, and the contact holes 41 can be stopped at the first stop 20. Then, the first stop 20 exposed by the plurality of contact holes 41 is etched, and the dielectric layer 12 below the first stop 20 is etched by the etching process, so that the contact holes 41 expose the gate layer 11 at their corresponding steps 141. Therefore, the problem that the contact hole penetrates the step of the upper layer and a short circuit occurs between the gate layers of the adjacent steps of the upper layer after the contact hole is filled with a conductive material to form the contact post is avoided, and the electrical performance and yield of the three-dimensional memory are improved.

[0106] 14 and 15, the three-dimensional memory 200 further includes a plurality of gate line isolation structures 70 extending in the first direction X and disposed between two adjacent isolation structures 50. The gate line isolation structures 70 extend through the second stop 60 and the stacked structure 10 therebelow. In the first direction X, each gate line isolation structure 70 includes a plurality of sub-isolation structures 71 separated from each other. The material of the second stop 60 is the same as the material of the gate layer 11.

[0107] "The gate line isolation structure 70 extends through the second stop 60 and the stacked structure 10 therebelow" means that the slit in which the gate line isolation structure 70 is disposed extends through the second stop 60 and the stacked structure 10 therebelow. Thus, the slit in which the gate line isolation structure 70 is disposed can be used to perform gate replacement to replace the sacrificial layer in the initial stacked structure 101 with the gate layer 11. At the same time, the slit in which the gate line isolation structure 70 is disposed is used to replace the material of the second stop with the material of the gate layer.

[0108] Providing the gate line isolation structure 70 can also relieve stress on the 3D memory 200 .

[0109] In some examples, the second stop 60 may be the same single layer structure as the gate layer 11. In this case, the second stop 60 also includes a conductive layer 111. Materials for the conductive layer 111 include, but are not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, doped silicon and / or silicide.

[0110] In some examples, the second stop 60 may be the same composite multi-layer structure as the gate layer 11. In this case, the second stop 60 may include a high dielectric constant layer 112, a metal compound layer 113, and a conductive layer 111, with the high dielectric constant layer 112 encasing the conductive layer 111 and the metal compound layer 113 being between the high dielectric constant layer 112 and the conductive layer 111. The material of the high dielectric constant layer 112 may include, for example, aluminum oxide (Al2O3), and the material of the metal compound 113 may include, for example, tantalum nitride or titanium nitride.

[0111] 8, 9, 11 and 15, in the third direction Z, the thickness of the first stop 20 is the same as the thickness of the gate layer 11 of a previous step 141 that is adjacent to and higher than the step 141 that corresponds to the first stop 20.

[0112] Then, it is possible to manufacture the first stop portion 20 having a sacrificial layer for manufacturing the gate layer 11 of the previous stage 141, thus eliminating the need to deposit the first stop portion 20 separately, thereby simplifying the manufacturing process of the three-dimensional memory 200 and reducing the manufacturing cost of the three-dimensional memory 200.

[0113] In some examples, the three-dimensional memory 200 includes a plurality of memory cell strings 201 arranged in an array in the core array area AA. Referring to FIG. 16, exemplarily, in the third direction Z, the memory cell string 201 includes a ground selection line layer 202 (bottom selection gate), a word line layer 203, a string selection line layer 204 (top selection gate), and a bit line 205 arranged in order. The memory cell string 201 further includes an array of channel structures 206 extending through the string selection line layer 204, the word line layer 203, and the ground selection line layer 202 in the third direction Z. The channel structures 206 connect the string selection line layer 204, the word line layer 203, and the ground selection line layer 202 in series to form the memory cell string 201.

[0114] In some examples, referring to FIG. 16, the channel structure 206 can include a blocking layer 2061, a storage layer 2062, a tunnel layer 2063, a channel layer 2064, and a fill layer 2065 arranged in sequence.

[0115] Exemplarily, the blocking layer 2061 may include a single layer, for example, a silicon dioxide (SiO2) layer. The blocking layer 2061 may also include multiple layers, for example, a stack of silicon dioxide and aluminum oxide (Al2O3). The storage layer 2062 may include a single layer, such as a silicon nitride (SiN) layer. The storage layer 2062 may also include multiple layers, such as a stack of silicon nitride, silicon oxynitride (SiON), and silicon nitride. The tunnel layer 2063 may include multiple layers, such as a stack of silicon monoxide (SiO), silicon oxynitride, and silicon oxide. The material of the channel layer 2064 may include a semiconductor material, such as polysilicon and / or single crystal silicon. The material of the filling layer 2065 may include an insulating material, such as silicon dioxide.

[0116] Referring to Fig. 17, one end of the memory cell string 201 is connected to a bit line 205, and the other end is connected to a source line SL. The memory cell string 201 includes a plurality of transistors connected in series between a first end and a second end, including at least one top select transistor Q1, at least one storage transistor M, and at least one bottom select transistor Q2. Fig. 17 exemplarily shows one top select transistor Q1, four storage transistors M, and one bottom select transistor Q2. The four storage transistors M are M1, M2, M3, and M4, respectively.

[0117] 5A, 5B, 18-21, some other examples of the present disclosure provide another three-dimensional memory 300.

[0118] Similarly, as shown in Figures 5A and 5B, the three-dimensional memory 300 includes a core array region AA and a step region SS in the first direction X. As shown in Figure 5A, the three-dimensional memory 300 may include two core array regions AA and one step region SS disposed between the two core array regions AA. Alternatively, as shown in Figure 5B, the three-dimensional memory 300 may include two step regions SS and one core array region AA disposed between the two step regions SS.

[0119] It is understood that the method of distribution of the core array area AA and the stage area SS in the three-dimensional memory 300 provided in some examples of the present disclosure is not limited thereto.

[0120] Referring to FIG. 18, a three-dimensional memory 300 includes a laminated structure 10', a plurality of first stop portions 20' arranged in a first direction X, an isolation layer 30', a protective layer 40', and a plurality of contact posts 50'.

[0121] The stacked structure 10' includes alternating gate layers 11' and dielectric layers 12'.

[0122] In some examples, as shown in Figure 19A, the gate layer 11' may be a single-layer structure. In this case, the gate layer 11' includes a conductive layer 111'. The material of the conductive layer 111' includes, but is not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, doped silicon and / or silicide.

[0123] In some other examples, as shown in Figure 19B, the gate layer 11' may be a multi-layer composite structure. At this time, the gate layer 11' may include a high dielectric constant layer 112', a metal compound layer 113', and a conductive layer 111', which are formed in sequence. The material of the high dielectric constant layer 112' may include, for example, aluminum oxide (Al2O3), and the material of the metal compound 113' may include, for example, tantalum nitride or titanium nitride.

[0124] Illustratively, the dielectric layer 12' may be made of an insulating material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0125] It should be noted that in the stacked structure 10', the thicknesses of the gate layers 11' may be approximately the same or different. The thicknesses of the dielectric layers 12' may be approximately the same or different. The thicknesses of the gate layers 11' and the dielectric layers 12' can be selected according to actual demand. Furthermore, the number of stacks in the stacked structure 10' determines the number of memory cells. The more stacks in the stacked structure 10', the higher the integration, i.e., the more memory cells there are. In one example, the number and height of the stacked structure 10' can be designed based on actual memory demand, which is not limited in the present disclosure.

[0126] The laminated structure 10' includes a step structure 13' arranged in a first direction X and including a plurality of step structures 14' having different heights in a second direction Y. The step structure 14' includes a plurality of steps 141'. The first direction X is perpendicular to the second direction Y.

[0127] When the step structure 13' includes stair structures 14' arranged in a first direction X and having different heights in a second direction Y, it is understood that two spaced apart stair structures 14' can have the same height, as long as it is ensured that two adjacent stair structures 14' among the multiple stair structures 14' included in the step structure 13' have different heights.

[0128] Based on this, in some examples, referring to FIG. 20, the step structure 13' may include three staircase structures 14' arranged in the second direction Y and having different heights from each other.

[0129] In some other examples, referring to FIG. 21 , the step structure 13′ can include three stair structures 14′ arranged in the second direction Y, with the two stair structures 14′ on either side having a different height from the height of the central stair structure but the same height as each other.

[0130] Further, in some examples, with reference to Figures 22 and 23, the step structure 13' may include two staircase structures 14' arranged in the second direction Y and having different heights from each other.

[0131] It should be noted that the number of staircase structures 14' in some examples of the present disclosure is not limited thereto.

[0132] A plurality of first stops 20' arranged in a first direction X are arranged on a plurality of steps 141' of at least one stair structure 14', and each of the first stops 20' is on one of the steps 141'.

[0133] As shown in Figures 20, 21 and 23, the first stops 20' may be arranged only on the steps 141' of one staircase structure 14'. It is also possible that the first stops 20' are arranged on the steps 141' of multiple staircase structures 14'.

[0134] As shown in Figures 20, 21 and 23, the step 141' can include one gate layer 11' and one dielectric layer 12'. Alternatively, the step 141' can include multiple gate layers 11' and multiple dielectric layers 12'. This is not a limitation of the present disclosure.

[0135] A separation layer 30' covers the step structure 13' and is disposed between the step structure 13' and the first stop 20'.

[0136] Illustratively, the isolation layer 30' may be made of an insulating material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0137] As shown in Figures 20, 21 and 23, "the separation layer 30' is positioned between the step structure 13' and the multiple first stop portions 20'" means that in the third direction Z, the separation layer 30' is positioned between the first stop portion 20' and the step 141' of the step structure 13', and in the first direction Z and the second direction Y, the separation layer 30' is positioned between the first stop portion 20' and the step 141' adjacent to the first stop portion 20'.

[0138] In some examples of the present disclosure, by providing the separation layer 30', on the one hand, the step structure 13' can be protected by the separation layer 30' and the stacked structure 10' can be protected. On the other hand, when forming the gate layer 11' of the step structure 13', the gate layer 11' of the step structure 13' and the first stop portion 20' can be separated to avoid connecting the first stop portion 20' to the sacrificial layer and replacing the first stop portion 20' as well, and the gate layer 11' and the first stop portion 20' can be electrically connected to each other, thereby preventing the three-dimensional memory 300 from failing.

[0139] A protective layer 40' covers the separation layer 30' and the first stop 20'.

[0140] Exemplarily, the protective layer 40' may be made of silicon oxide, including, but not limited to, tetraethoxysilane (TEOS), siloxane, silsesquioxane, etc. Exemplarily, the protective layer 40' may be formed by a chemical vapor deposition (CVD) process, a spin-coating process, etc.

[0141] In some examples, referring to Figures 19A and 20, when the protective layer 40' covers the separation layer 30' and the first stop portion 20', in the first direction X, at least a portion of the protective layer 40' is disposed between the side of the first stop portion 20' and the separation layer 30', and in the second direction Y, at least a portion of the protective layer 40' is disposed between the side of the first stop portion 20' and the separation layer 30'.

[0142] Therefore, it facilitates isolating the plurality of first stops 20' from each other and avoiding electrical connections between the plurality of first stops 20'.

[0143] A contact post 50' of the plurality of contact posts 50' extends through the protective layer 40', the first stop 20' and the isolation layer 30' and connects to the gate layer 11' at a step 141' corresponding to the first stop 20'.

[0144] Illustratively, the contact posts 50' may be made of conductive materials including, but not limited to, metals such as tungsten, copper, aluminum, metal silicides, metal nitrides, and / or doped polysilicon.

[0145] It is understood that the above-mentioned step structure 13' is disposed within the step region SS. When the step region SS is disposed between two core array regions AA, the topography of the step structure 13' may be as shown in Figures 24A and 24B. That is, the step structure 13' may include at least one step group in which the height of the multiple steps 141' gradually increases or decreases in the first direction X.

[0146] Exemplarily, as shown in FIGS. 24A and 24B, the step structure 13' may include eight step groups in the first direction X, which are a first step group 131', a second step group 132', a third step group 133', a fourth step group 134', a fifth step group 135', a sixth step group 136', a seventh step group 137', and an eighth step group 138'. In the first direction X, the heights of the steps 141' in the first step group 131', the third step group 133', the fifth step group 135', and the seventh step group 137' are gradually decreased. In the first direction X, the heights of the steps 141' in the second step group 132', the fourth step group 134', the sixth step group 136', and the eighth step group 138' are gradually increased. Of course, the form of the step structure 13' in the present disclosure is not limited to this.

[0147] In the three-dimensional memory 300 provided in some examples of the present disclosure, a plurality of first stops 20' are disposed on at least one staircase structure 14' in the step structure 13'. Therefore, when forming the contact hole 51' in which the contact post 50' is disposed, an etching process such as wet etching can be used to remove a portion of the protective layer on the first stops 20' to expose a portion of the first stops 20', and then an etching process can be used to remove the exposed portion of the first stops 20' and the isolation layer 30' and the dielectric layer 12' between the first stops 20' and the gate layer 11' therebelow to expose a portion of the gate layer 11'.

[0148] In the first etching step, due to the presence of the first stop 20', the contact holes 51' having different depths corresponding to the steps 141' having different heights can stop at the respective first stop 20' on the step 141'. In the second etching step, since the distance between each first stop 20' and the gate layer 11' of the step 141' on which the first stop 20' is disposed is approximately the same, in the second etching step, the contact holes 51' having different depths corresponding to the steps 141' having different heights can stop at the respective gate layer 11' on the step 141' while simultaneously etching.

[0149] Thus, while forming the contact post 50' in the contact hole 51', the contact post 50' can contact the gate layer 11' of the corresponding stage 141', facilitating avoidance of short circuits between multiple gate layers due to the contact post extending through multiple gate layers due to an increased number of layers in the stacked structure, thereby improving the electrical performance and yield of the three-dimensional memory.

[0150] At the same time, the provision of the first stop 20' can also enable the contact hole 51' to have a faster etch rate and the contact hole 51' (or the contact post 50') to have better linearity, which makes the dielectric layer in the dummy channel structure adjacent to the contact post 50' less susceptible to etching, thereby improving the yield of the three-dimensional memory 300.

[0151] 18 to 23, in some examples, the three-dimensional memory 300 further includes an isolation structure 60'. The isolation structure 60' extends through the stacked structure 10' in a first direction X. The isolation structure 60' divides the stacked structure 10' into a plurality of memory blocks 15'. Each memory block 15' includes a step structure 13'. A staircase structure 14' on which the first stop portion 20' is disposed is spaced apart from the isolation structure 60'.

[0152] It is understood that the isolation structure 60' extends through the laminate structure 10' and may also extend through the isolation layer 30'.

[0153] "The staircase structure 14' on which the first stop portion 20' is disposed is spaced apart from the separation structure 60'" means that the first stop portion 20' is spaced apart from the separation structure 60'.

[0154] In some examples of the present disclosure, the stacked structure 10' is divided into multiple memory blocks 15' having the isolation structures 60', which can further improve the memory density of the three-dimensional memory 300. Meanwhile, the staircase structure 14' on which the first stop 20' is disposed is spaced apart from the isolation structures 60', which can also avoid the case where the first stop 20' is replaced in the subsequent process of forming the gate layer 11' by performing gate replacement using the slits on which the isolation structures are disposed, thereby causing the contact posts to penetrate the replaced first stop and electrically connect with multiple gate layers, thus resulting in failure of the three-dimensional memory.

[0155] In some examples, referring to Figures 20 and 21, in the second direction Y, the memory block 15' includes a first staircase structure 14A', a second staircase structure 14B' and a third staircase structure 14C', and the first stop portion 20' is positioned on a plurality of steps 141' of the second staircase structure 14B'.

[0156] Thus, the second staircase structure 14B' has a height difference in the third direction Z with both the first staircase structure 14A' and the third staircase structure 14C' and is spaced apart from the separation structure 60' (i.e., the first staircase structure 14A' and the third staircase structure 14C' are between the second staircase structure 14B' and the separation structure 60'), facilitating preventing the first stop portion 20' from being displaced.

[0157] In some other examples, referring to FIG. 23, in the second direction Y, the memory block 15' includes a first staircase structure 14A' and a second staircase structure 14B', the first staircase structure 14A' is spaced apart from the separation structure 60', and the first stop portion 20' is positioned on a plurality of steps 141' of the first staircase structure 14A'.

[0158] In this way, the first staircase structure 14A' has a height difference in the third direction Z from the second staircase structure 14B' and is spaced apart from the separation structure 60', making it easy to prevent displacement of the first stop portion 20'.

[0159] In some examples, referring to FIGS. 20 to 24B, each memory block 15' further includes a sidewall 16'. The isolation structure 60' includes a first isolation structure 61' and a second isolation structure 62'. In the second direction Y, the first isolation structure 61' is disposed between two adjacent sidewalls 16', and the second isolation structure 62' is disposed between two adjacent step structures 13'. The sidewalls 16' are configured to enhance the structural stability of the three-dimensional memory 300.

[0160] In some examples, the first separating structure 61' may be a one-piece structure, as shown in Figures 18 and 22. That is, when manufacturing the first separating structure 61', a slit in which the first separating structure 61' is disposed can be obtained by etching in a single etching step, and the first separating structure 61' can be formed in the slit.

[0161] 25, the first isolated structure 61′ may include a first isolated sub-portion 611′, a second isolated sub-portion 612′, and a third isolated sub-portion 613′ connected sequentially in the first direction X. The second isolated sub-portion 612′ has a size in the second direction Y larger than the first isolated sub-portion 611′ and larger than the third isolated sub-portion 613′.

[0162] Illustratively, the first isolated subportion 611' and the third isolated subportion 613' are disposed in the core array region AA, and the second isolated subportion 612' is disposed in the step region SS and contacts the sidewall 16'.

[0163] Exemplarily, the second isolation subportion 612' may be manufactured simultaneously with the dummy channel structure and the channel structure. The first isolation subportion 611' and the third isolation subportion 613' may be manufactured after the fabrication of the channel structure is completed. Based on this, the material of the second isolation subportion 612' may be the same as the material of the dummy channel structure or the channel structure.

[0164] In some examples of the present disclosure, by providing a second isolation sub-portion 612', it is possible to isolate two adjacent memory blocks 15' on the one hand, and to support the stacked structure 10' on the other hand, thereby preventing the stacked structure 10' from collapsing.

[0165] In some examples, referring to Figures 22, 25 and 26, in the second direction Y, the step structures 13' in the two memory blocks 15' adjacent to the second isolation structure 62' are arranged symmetrically.

[0166] It is understood that "the step structures 13' in the two memory blocks 15' are arranged symmetrically" may mean that the number of staircase structures 14' included in the step structures 13' of the two memory blocks 15' is the same, and the two staircase structures 14' in the two step structures 13' having equal distances from the second isolation structure 62' have the same height.

[0167] In some examples, referring to Figures 20 and 23, in the second direction Y, the height of the multiple staircase structures 14' in the memory block 15' gradually decreases along the direction from the first isolation structure 61' to the second isolation structure 62'.

[0168] In some other examples, referring to FIG. 21, in the second direction Y, along the direction from the first isolation structure 61' to the second isolation structure 62', the heights of the multiple staircase structures 14' in the memory block 15' first decrease and then increase.

[0169] In some examples, referring to Figures 20 and 21, in the second direction Y, the two adjacent staircase structures 14' on either side of the second isolation structure 62' have the same height.

[0170] 20, 21 and 23, the three-dimensional memory 300 further includes a plurality of second stop portions 70' arranged in the first direction X. The plurality of second stop portions 70' are arranged on a plurality of steps of other staircase structures 14' among the plurality of staircase structures 14' other than the staircase structure 14' in which the first stop portion 20' is arranged.

[0171] The separation layer 30' is similarly arranged between the step structure 13' and the second stop 70'. Similarly, as shown in Fig. 23, "the separation layer 30' is similarly arranged between the step structure 13' and the plurality of second stops 70'" is understood to mean that in the third direction Z, the separation layer 30' is arranged between the second stop 70' and the step 141' of the step structure 13', and in the first direction X and the second direction Y, the separation layer 30' is arranged between the second stop 70' and the step 141' adjacent to the second stop 70'. A protective layer 40' further covers the second stop 70'.

[0172] Illustratively, when the protective layer 40' further covers the second stop portion 70', in the first direction X, at least a portion of the protective layer 40' is disposed between the side of the second stop portion 70' and the separation layer 30', and in the second direction Y, at least a portion of the protective layer 40' is disposed between the side of the second stop portion 70' and the separation layer 30'.

[0173] By way of example, referring to Figures 20 and 21, when the first stop portion 20' is positioned on the multiple steps 141' of the second staircase structure 14B', the second stop portion 70' may be positioned on the multiple steps 141' of the first staircase structure 14A' and the third staircase structure 14C'.

[0174] For example, referring to FIG. 23, when the first stop portion 20' is positioned on a plurality of steps 141' of the first stair structure 14A', the second stop portion 70' may be positioned on a plurality of steps 141' of the second stair structure 14B'.

[0175] In some cases, the material of the first stop 20' and the second stop 70' may be the same.

[0176] Based on this, the material of the first stop 20' and the second stop 70' may include, for example, carbon doped silicon nitride or silicon nitride.

[0177] In some cases, the materials of the first stop 20' and the second stop 70' may be different.

[0178] Illustratively, the material of the first stop 20' may be, for example, silicon nitride.

[0179] When the material of the first stop 20' includes silicon nitride or carbon-doped silicon nitride, the material of the first stop 20' and the material of the gate layer 11' are different, and the etching selectivity of the first stop 20' and the gate layer 11' are different. The first stop 20' tends to be etched when forming the contact hole by the etching process. Therefore, when manufacturing the contact hole 51' in which the contact post 50' is disposed, the heights of the multiple contact holes 51' corresponding to the steps 141' can be made different from each other and stopped at the first stop 20', and the distance between the bottom of each contact hole 51' and the steps 141' is approximately the same. Then, the first stop 20' exposed by the multiple contact holes 51' is etched, and the isolation layer 30' and the dielectric layer 12' under the first stop 20' are etched using the etching process, so that the contact holes 51' expose the gate layer 11' at their corresponding steps 141'. This avoids the problem that, after filling the contact hole with a conductive material to form a contact post, the contact hole penetrates the upper stage and a short circuit occurs between the gate layers of adjacent stages in the upper stage, thereby improving the electrical performance and yield of the 3D memory.

[0180] 26 and 27, the three-dimensional memory 300 further includes a plurality of gate line isolation structures 80' extending in the first direction X and disposed between two adjacent isolation structures 60'. The gate line isolation structures 80' extend through the second stop 70' and the stacked structure 10'. In the first direction X, each gate line isolation structure 80' includes a plurality of sub-isolation structures 81' separated from each other.

[0181] "The gate line isolation structure 80' extends through the second stop 70' and the stack structure 10'" means that the slit in which the gate line isolation structure 80' is disposed extends through the second stop 70' and the stack structure 10'.

[0182] Providing the gate line isolation structures 80 ′ can also relieve stress on the three-dimensional memory 300 .

[0183] In some cases, the thickness of the second stop 70' is less than or equal to the thickness of the gate layer 11', and the material of the second stop 70' is the same as the material of the gate layer.

[0184] It will be understood that if the thickness of the second stop portion 70' is less than or equal to the thickness of the gate layer 11', it is possible to use the slit in which the gate line isolation structure 80' is located to replace the sacrificial layer in the initial stacked structure 101' with the gate layer 11' and at the same time replace the material of the second stop portion 70' with the material of the gate layer 11'.

[0185] Based on this, in some examples, the second stop 70' may be the same single layer structure as the gate layer 11'. In this case, the second stop 70' also includes the conductive layer 111'. Materials for the conductive layer 111' include, but are not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, doped silicon and / or silicide.

[0186] In some other examples, the second stop 70' may be the same composite multi-layer structure as the gate layer 11'. In this case, the second stop 70' may include a high-k layer 112', a metal compound layer 113', and a conductive layer 111', where the high-k layer 112' encases the conductive layer 111' and the metal compound layer 113' is between the high-k layer 112' and the conductive layer 111'. The material of the high-k layer 112' may include, for example, aluminum oxide (Al2O3), and the material of the metal compound 113' may include, for example, tantalum nitride or titanium nitride.

[0187] In some other examples, the thickness of the second stop 70' is greater than the thickness of the gate layer 11', and the material of the second stop 70' is the same as the material of the gate line isolation structure 80'.

[0188] Based on this, in some examples, the material of the second stop 70' and the material of the gate line isolation structure 80' can both include a dielectric material, such as silicon oxide and / or silicon nitride. In some other examples, the second stop 70' and the gate line isolation structure 80' can be a composite stack structure. For example, the second stop 70' (or the gate line isolation structure 80') can include a dielectric material layer and a conductive material layer, such as at least one of tungsten, cobalt, copper, aluminum, or polysilicon, arranged in sequence. In yet some other examples, the second stop 70' can include a dielectric material and a high-k layer encasing the dielectric material. In yet some other examples, the second stop 70' can further include a composite stack structure and a high-k layer encasing the composite stack structure.

[0189] To address the technical problem that higher gate layers tend to be penetrated by contact posts, two types of 3D memories are introduced above. In the following, the manufacturing methods of the two types of 3D memories are respectively described.

[0190] Referring to FIG. 28, some examples of the present disclosure provide a manufacturing method for a three-dimensional memory 200 including operations S1 to S5.

[0191] 29A, 29B and 30, an initial laminated structure 101 is formed. The initial laminated structure 101 includes a sacrificial layer 110 and a dielectric layer 12. The initial laminated structure 101 includes a step structure 13 arranged in a first direction X and including a plurality of step structures 14 having different heights in a second direction Y. Each step structure 14 includes a plurality of steps 141. The first direction X is perpendicular to the second direction Y.

[0192] It should be noted that the sacrificial layer 110 and the dielectric layer 12 can be formed, for example, by a chemical vapor deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, a high-density plasma chemical vapor deposition (HDP-CVD) process, and an atomic layer deposition (ALD) process or a sputtering process.

[0193] Illustratively, the sacrificial layer 110 and the dielectric layer 12 have different etch selectivities such that the sacrificial layer 110 can be removed in a subsequent step while the dielectric layer 12 remains, thereby forming a gate line gap for forming the gate layer 11. Illustratively, the material of the sacrificial layer 110 can be silicon nitride, and the material of the dielectric layer 12 can be silicon oxide.

[0194] The number of sacrificial layers 110 and dielectric layers 12 in the initial laminated structure 101 can be designed according to actual needs. Illustratively, the initial laminated structure 101 can have 16 sacrificial layers 110 and dielectric layers 12, or 32 sacrificial layers 110 and dielectric layers 12. This is not limited in the present disclosure. Please note that in the accompanying drawings provided in the present disclosure, the number of initial layer pairs is only an example and is not a limitation of the present disclosure.

[0195] It should be noted that in the initial laminated structure 101, the thicknesses of the sacrificial layers 110 may be approximately the same or different. The thicknesses of the dielectric layers 12 may be approximately the same or different. The thicknesses of the sacrificial layers 110 and the dielectric layers 12 can be selected according to actual needs.

[0196] In some examples, as shown in FIG. 31, operation S1 of forming the initial laminated structure 101 includes:

[0197] S11, a pre-defined stack structure 1011 is formed, which includes alternating sacrificial layers 110 and dielectric layers 12.

[0198] S12: Etching the preset laminated structure 1011 to form a plurality of reference steps 142 arranged in the second direction Y. Each reference step 142 corresponds to one staircase structure 14.

[0199] In step S13, a plurality of steps 141 arranged in the first direction X are formed based on the reference step 142 by a trimming etching process and a cutting process to form the staircase structure 14. The initial laminated structure 101 includes a plurality of staircase structures 14.

[0200] In some examples, as shown in FIG. 32, the operation S12 of etching the preset laminated structure 1011 to form a plurality of reference steps 142 arranged in the second direction Y includes:

[0201] 33A and 33B1, a first mask layer 21 is formed on a preset laminated structure 1011. The first mask layer 21 exposes a first region W1 of the preset laminated structure 1011.

[0202] In S122, as shown in FIG. 34, at least one sacrificial layer 110 and at least one dielectric layer 12 in the first region W1 of the preset laminated structure 1011 are etched.

[0203] As shown in S123, FIGS. 35A and 35B, the first mask layer 21 is trimmed to expose a second region W2 of the preset laminated structure 1011. The first region W1 is disposed inside the second region W2. There is a gap between the boundary of the first region W1 and the boundary of the second region W2 along the second direction Y.

[0204] S124, as shown in FIG. 36, at least one sacrificial layer 110 and at least one dielectric layer 12 in the second region W2 of the pre-set laminated structure 1011 are etched to form three reference steps 142 having different heights in the second direction Y.

[0205] Illustratively, in operation S122, one sacrificial layer 110 and one dielectric layer 12 in a first region W1 of the preset laminated structure 1011 can be etched, and in operation S124, one sacrificial layer 110 and one dielectric layer 12 in a second region W2 of the preset laminated structure 1011 can be etched to form three reference steps 142 having different heights in the second direction Y.

[0206] When one sacrificial layer 110 and one dielectric layer 12 in a first region W1 of the preset laminated structure 1011 are etched in operation S122, and one sacrificial layer 110 and one dielectric layer 12 in a second region W2 of the preset laminated structure 1011 are etched in operation S124, the height difference between two adjacent stair structures 14 in the third direction Z is a height corresponding to one sacrificial layer 110 and one dielectric layer 12.

[0207] In some other examples, as shown in FIG. 37, the operation S12 of etching the preset laminated structure 1011 to form a plurality of reference steps 142 arranged in the second direction Y includes:

[0208] 38, a second mask layer 22 is formed on the preset laminated structure 1011. The second mask layer 22 exposes at least ⅓ region W3 of the preset laminated structure 1011.

[0209] FIG. 38 illustrates an example in which the second mask layer 22 exposes two third regions W3, but the present disclosure is not limited to this.

[0210] S126, as shown in FIG. 39, etch at least one sacrificial layer 110 and at least one dielectric layer 12 in the third region W3 of the pre-defined laminated structure 1011 to form three reference steps 142 whose height first decreases and then increases in the second direction Y.

[0211] Exemplarily, the pre-defined laminate structure 1011 can be etched by a wet etching process or a dry etching process.

[0212] It should be noted that although the above operations have been described with respect to an example of forming three reference stages 142, in other examples, two or more reference stages 142 may be formed.

[0213] Illustratively, when the step structure 13 includes two staircase structures 14, the two staircase structures 14 can be obtained simply by operations S121, S122, and S13.

[0214] Exemplarily, when the step structure 13 includes more than three staircase structures 14, after operations S121-S124, it is also possible to trim the first mask layer 21 multiple times so that an area of ​​the initial stacked structure exposed by the first mask layer 21 becomes larger and larger. Each time the first mask layer 21 is trimmed, at least one initial layer pair 102 of the portion of the initial stacked structure 101 exposed by the first mask layer 21 is etched to form more than three reference steps 142, thereby forming more than three staircase structures 14.

[0215] It should be noted that after obtaining the multiple staircase structures 14, the trimmed first mask layer 21 or the second mask layer 22 needs to be removed.

[0216] For example, in operation S13, in order to form the staircase structure 14, it is also possible to form the sidewall 16 while forming a plurality of steps 141 arranged in the first direction X based on the reference step 142 by a trimming etching process and a cutting process.

[0217] S2, forming a plurality of first stops 20 on a plurality of steps 141 of at least one stair structure 14.

[0218] In some examples, as shown in FIG. 40, the operation S2 of forming a plurality of first stops 20 on a plurality of steps 141 of at least one stair structure 14 includes:

[0219] S21, etch the sacrificial layer 110 and the dielectric layer 12 on the top of each step 141 to form a plurality of first stops 20.

[0220] 29A, 41A, 29B and 41B, etching the sacrificial layer 110 and dielectric layer 12 at the top of each step 141 may, for example, be etching portions 143 of the sacrificial layer 110 and dielectric layer 12 at the junction with the step 141 in the second direction Y. With reference to Figures 30 and 42, etching the sacrificial layer 110 and dielectric layer 12 at the top of each step 141 may, for example, be etching portions 144 of the sacrificial layer 110 and dielectric layer 12 at the junction with the step 141 in the first direction X.

[0221] In this manner, by etching the top sacrificial layer 110 and dielectric layer 12 of each step 141 to remove a portion of the top sacrificial layer 110 and dielectric layer 12 at the junction with the step 141, the need to separately deposit additional films to form multiple first stops 20 is eliminated, thereby reducing the manufacturing process and costs of the three-dimensional memory 200.

[0222] At the same time, because there is a gap between the formed first stop 20 and the step, the first stop 20 will not tend to be replaced in the subsequent step of replacing the sacrificial layer 110 with the gate layer 11. Therefore, in the subsequent step of forming the contact holes 41, the contact holes 41 corresponding to different steps 141 can firstly stop at their corresponding first stop 20 after the first etching, and then stop at the gate layer 11 after the second etching, thereby avoiding the problem that the contact holes penetrate the steps of the upper layer and short-circuit occurs between the steps of the upper layer after forming the contact posts.

[0223] 43 and 44, a protective layer 30 is formed. The protective layer 30 covers the step structure 13 and the first stop 20, and at least a portion of the protective layer 30 is disposed between the first stop 20 and the step 141 adjacent to the first stop 20.

[0224] The protective layer 30 may be made of silicon oxides, including but not limited to tetraethoxysilane (TEOS), siloxanes, silsesquioxanes, and the like.

[0225] Exemplarily, the protective layer 30 may be formed by a chemical vapor deposition (CVD) process, a spin coating process, or the like.

[0226] For example, after the protective layer 30 is formed, it may be planarized by a chemical mechanical polishing (CMP) process.

[0227] S4, referring to FIGS. 45 and 46, the sacrificial layer 110 is replaced with the gate layer 11 to form the stacked structure 10.

[0228] In some examples, three dimensional memory 200 includes an isolation structure 50 that includes a first isolation structure 51 and a second isolation structure 52, both of which are a unitary structure.

[0229] Based on this, in some examples, as shown in FIG. 47, the manufacturing method further includes:

[0230] S41, referring to FIG. 48, a first slit 501 is formed extending in a first direction X and extending through an initial stacked structure 101, the first slit 501 dividing the initial stacked structure 101 into a plurality of initial memory blocks 150, each initial memory block 150 including a step structure 13.

[0231] Exemplarily, the first slits 501 may be formed by a dry etching process. The first slits 501 extend through the initial laminated structure 101 in the third direction Z.

[0232] Exemplarily, the sacrificial layer 110 can be replaced with the gate layer 11 using the first slit 501. Exemplarily, an etching solution can be introduced into the initial stacked structure 101 from the first slit 501 by a wet etching process. At this time, since the etching selectivity of the sacrificial layer 10 and the dielectric layer 12 is different, in the etching process, the sacrificial layer 110 can be etched and the dielectric layer 12 can be left, thereby forming a cavity in the corresponding formation portion.

[0233] Illustratively, the gate layer 11 may be formed in the cavity using one or more of the following processes: CVD, PVD, and ALD.

[0234] The gate layer 11 may be a single layer structure. For example, the gate layer 11 includes a conductive material, including but not limited to tungsten, cobalt, copper, aluminum, or doped crystalline silicon. Alternatively, the gate layer 11 may be a multi-layer composite structure. For example, the gate layer 11 may include a high dielectric constant layer (such as aluminum oxide Al2O3), a metal compound layer (such as tantalum nitride, titanium nitride, etc.), and a conductive layer (such as tungsten) formed in sequence.

[0235] In some examples, as shown in FIG. 47, the manufacturing method further includes:

[0236] In S42, the isolation structure 50 is formed in the first slit 501 as shown in FIG.

[0237] Illustratively, isolation structure 50 may be formed using one or more of the following processes: CVD, PVD, and ALD. Isolation structure 50 may include only one or more layers of dielectric material, or may include one or more layers of dielectric material and at least one layer of conductive material disposed in sequence.

[0238] The isolation structure 50 can divide the stacked structure 10 into a plurality of memory blocks 15, and the memory density of the three-dimensional memory 200 can be further improved.

[0239] 13, the three-dimensional memory 200 includes an isolation structure 50 including a first isolation structure 51 and a second isolation structure 52. The first isolation structure 51 may include a first isolation sub-portion 511, a second isolation sub-portion 512, and a third isolation sub-portion 513 connected sequentially in the first direction X.

[0240] In some examples, as shown in FIG. 49, the manufacturing method may further include:

[0241] S43, referring to FIG. 50, a second separated sub-portion 512 is formed extending through the initial laminated structure 101 in the first direction X.

[0242] Based on this, exemplarily, the second isolated sub-portion 512 may be manufactured simultaneously with the dummy channel structure and the channel structure. For example, after forming the initial stacked structure 101, the second isolated sub-portion 512 may be formed before forming the protective layer 30.

[0243] 51, a first sub-slit 502, a second sub-slit 503 and a second slit 504 are formed extending in a first direction X and through the initial laminated structure 101. In the first direction X, the first sub-slit 502 and the second sub-slit 503 are in contact with both ends of the second separated sub-portion 512, respectively. In the second direction Y, the second slit 504 is disposed between two adjacent second separated sub-portions 512.

[0244] In some examples, as shown in FIG. 49, the manufacturing method may further include:

[0245] In S45, referring to FIG. 13, a first isolated sub-portion 511 is formed in the first sub-slit 502, a third isolated sub-portion 513 is formed in the second sub-slit 503, and a second isolated structure 52 is formed in the second slit 504.

[0246] The first isolated sub-portion 511 , the third isolated sub-portion 513 and the second isolated sub-portion 512 constitute at least a part of the first isolated structure 51 .

[0247] In some examples, referring to Figures 41A, 41B, and 42, the manufacturing method may further include:

[0248] A plurality of second stop portions 60 are formed on a plurality of steps 141 of the other staircase structures 14 among the plurality of staircase structures 14 other than the staircase structure 14 in which the first stop portion 20 is arranged.

[0249] In some examples, referring to FIG. 52, the manufacturing method may further include:

[0250] 53, third slits 505 extending in the first direction X are formed. The third slits 505 extend through the second stop 60 and the initial laminated structure 101. Each third slit 505 includes a plurality of third sub-slits 506 spaced apart from one another along the first direction X.

[0251] In some examples, referring to FIG. 41, the manufacturing method may further include:

[0252] In S47, referring to FIG. 45, a gate line isolation structure 70 is formed in the third slit 505.

[0253] Exemplarily, in operation S4, after the sacrificial layer 120 is replaced with the gate layer 11 to form the stacked structure 10, a plurality of third slits 505 extending in the first direction X may be formed. After operation S4, the gate line isolation structures 70 may be formed in the third slits 505.

[0254] In some examples, the third slit 505 may be formed simultaneously with the first slit 501. In other examples, the third slit 505 may be formed simultaneously with the first sub-slit 502, the second sub-slit 503, and the second slit 504.

[0255] Thereby, in the step of replacing the sacrificial layer 110 with the gate layer 11, the material of the second stopper portion can be replaced with the same material as that of the gate layer 11 by using the plurality of third slits 505.

[0256] 6 to 11, a plurality of contact posts 40 are formed. The contact posts 40 extend through the protective layer 30 and the first stop portions 20 and are electrically connected to the gate layer 11 at steps 141 corresponding to the first stop portions 20.

[0257] Exemplarily, with reference to FIG. 54, S5 of forming the plurality of contact posts 40 includes operations S51-S53.

[0258] S51, referring to FIGS. 55 and 56, the protective layer 30 is etched down to the first stop 20 to form a plurality of contact holes 41.

[0259] For example, the contact hole 41 may be formed by a wet etching process.

[0260] Because the first stop 20 and the gate layer 11 have different materials and different etching selectivity, in the process of forming the contact holes 41, the first stop 20 does not tend to be etched like the gate layer 11, and all the contact holes 41 corresponding to the steps 141 having different heights will stop at the first stop 20 on the corresponding step, thereby exposing the first stop 20.

[0261] S52, referring to Figures 57 and 58, the first stop 20 exposed by the contact hole 41 can be etched and the dielectric layer 12 below the first stop 20 can be etched so that the contact hole 41 exposes the gate layer 11.

[0262] Illustratively, the first stop 20 exposed by the contact hole 41 can be etched, and the dielectric layer 12 below the first stop 20 can be etched using a dry etching process so that the contact hole 41 exposes the gate layer 11.

[0263] The first stops 20 on different steps 141 have approximately the same distance from the gate layer 11 in the step 141. Therefore, it is possible to etch layers of the same thickness in different steps 141 to expose the gate layer 11. Therefore, all the contact holes 41 formed in the three-dimensional memory can make good contact with the gate layer 11 in the corresponding steps 141 and do not penetrate the gate layer 11 in their corresponding steps, thereby effectively avoiding the case where the gate layer is penetrated and different gate layers are short-circuited after forming the contact posts 40, and thus improving the electrical performance and yield of the three-dimensional memory.

[0264] In step S53, referring to FIGS. 6 to 11, a contact post 40 is formed in a contact hole 41.

[0265] Illustratively, the contact posts 40 can be formed by any of CVD, PVD, and ALD. The material of the contact posts 40 is a conductive material such as at least one of tungsten, cobalt, copper, aluminum, doped crystalline silicon, or a silicide.

[0266] Some examples of the present disclosure further provide manufacturing methods for other three-dimensional memories 300, and the manufacturing methods for the three-dimensional memory 200 provided in the above examples can be referenced to implement operations similar to those in the above examples.

[0267] With reference to FIG. 59, the method for manufacturing three-dimensional memory 300 includes operations S1' to S6'.

[0268] Referring to S1', FIG. 60 and FIG. 61, an initial laminated structure 101' is formed. The initial laminated structure 101' includes sacrificial layers 110' and dielectric layers 12' arranged alternately. The initial laminated structure 101' includes an initial step structure 130' including a plurality of step structures 14' arranged in a first direction X and having different heights in a second direction Y. The step structure 14' includes a plurality of steps 141'. The first direction X is perpendicular to the second direction Y.

[0269] Similar to the manufacturing method of the three-dimensional memory 200 provided in the previous example, the sacrificial layer 110' and the dielectric layer 12' can be formed, for example, by a chemical vapor deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, a high-density plasma chemical vapor deposition (HDP-CVD) process, and an atomic layer deposition (ALD) process or a sputtering process.

[0270] The sacrificial layer 110' and the dielectric layer 12' have different etch selectivity, so that the sacrificial layer 110' can be removed in a subsequent step while the dielectric layer 12' remains, thereby forming a gate line gap for forming the gate layer 11'. Illustratively, the material of the sacrificial layer 110' can be silicon nitride, and the material of the dielectric layer 12' can be silicon oxide.

[0271] The number of sacrificial layers 110' and dielectric layers 12' in the initial laminated structure 101' can be designed according to actual needs. Illustratively, the initial laminated structure 101' can have 16 pairs of sacrificial layers 110' and dielectric layers 12', or 32 pairs of sacrificial layers 110' and dielectric layers 12', which is not limited in the present disclosure. Please note that in the accompanying drawings provided in the present disclosure, the number of initial layer pairs 102' is only illustrative and is not limited in the present disclosure.

[0272] It should be noted that in the initial laminated structure 101', the thicknesses of the sacrificial layers 110' may be approximately the same or different, and the thicknesses of the dielectric layers 12' may be approximately the same or different. The thicknesses of the sacrificial layers 110' and the dielectric layers 12' can be selected according to actual needs.

[0273] For the process of forming initial stacked structure 101', operations S11 to S13 in the method for manufacturing three-dimensional memory 200 described above can be referred to.

[0274] S2', forming a separation layer 30' covering the stage structure 13' as shown in Figs.

[0275] Illustratively, the isolation layer 30' may be made of an insulating material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0276] S3', referring to Figures 64 and 65, a plurality of first stops 20' are formed on a side of the separation layer 30' remote from the step structure 13'. The plurality of first stops 20' are arranged in a first direction X and are arranged on a plurality of steps 141' of the at least one stair structure 14', each first stop 20' being on one step 141'.

[0277] In some examples, referring to FIG. 66, the operation S3' of forming the plurality of first stop portions 20' on a side of the separation layer 30' away from the step structure 13' may include:

[0278] S31', referring to Figures 67 and 68, a preset stop layer 21' is formed on the side of the separation layer 30' remote from the step structure 13'.

[0279] S32', referring to Figures 64 and 65, portions 211' of the pre-defined stop layer 21' at the junctions with corresponding steps 141' are removed to form a plurality of first stop portions 20'.

[0280] In some cases, the material of the preset stopping layer 21' may be the same as the material of the sacrificial layer 120'.

[0281] In some cases, the material of the preset stop layer 21' may be different from the material of the sacrificial layer 120'. Here, by way of example, the material of the preset stop layer 21' may be carbon-doped silicon nitride.

[0282] S4', referring to Figures 69 and 70, a protective layer 40' is formed. The protective layer 40' covers the separation layer 30' and the first stop 20'.

[0283] 64 and 65, it can be seen that after forming the plurality of first stop portions 20', there are gaps between the sides of the first stop portions 20' and the separation layer 30' in the first direction X and the second direction Y. Thus, after subsequently forming the protective layer 40', at least a portion of the protective layer 40' falls into the gaps between the sides of the first stop portions 20' and the separation layer 30'.

[0284] S5', referring to FIG. 71, the sacrificial layer 110' is replaced with a gate layer 11' to form a stacked structure 10'.

[0285] In some examples, the three dimensional memory 300 further includes an isolation structure 60'. The isolation structure 60' includes a first isolation structure 61' and a second isolation structure 62', both of which are a unitary structure.

[0286] Based on this, in some examples, as shown in FIG. 72, the manufacturing method further includes:

[0287] 73, a first slit 601' is formed extending through the initial stacked structure 101' in a first direction X, and the first slit 601' divides the initial stacked structure 101' into a plurality of initial memory blocks 150'. Each initial memory block 150' includes a step structure 13'.

[0288] Exemplarily, the first slits 601' can be formed by a dry etching process. The first slits 601' extend through the initial laminated structure 101' in the third direction Z.

[0289] Exemplarily, the sacrificial layer 110' can be replaced with the gate layer 11' by using the first slit 601'. Exemplarily, an etching solution can be introduced into the initial stacked structure 101' from the first separation portion 601' by using a wet etching process. At this time, since the etching selectivity of the sacrificial layer 110' and the dielectric layer 12' is different, in the etching process, the sacrificial layer 110' can be etched and the dielectric layer 12' can be left, thereby forming a cavity in the corresponding formation portion.

[0290] By way of example, one or more of the following processes may be used to form the gate layer 11' within the cavity: CVD, PVD, and ALD.

[0291] In some examples, as shown in FIG. 72, the manufacturing method may further include:

[0292] S52', referring to FIG. 71, forming an isolation structure 60' in a first slit 601'.

[0293] Illustratively, one or more of the processes CVD, PVD, and ALD can be used to form the isolation structure 60'. The isolation structure 60' may include only one or more dielectric material layers, or may include one or more dielectric material layers and at least one conductive material layer disposed in sequence.

[0294] 25, the three-dimensional memory 300 includes an isolation structure 60' including a first isolation structure 61' and a second isolation structure 62'. The first isolation structure 61' may include a first isolation sub-portion 611', a second isolation sub-portion 612', and a third isolation sub-portion 613' sequentially connected in the first direction X.

[0295] Based on this, in some examples, as shown in FIG. 74, the manufacturing method may further include:

[0296] S53', referring to FIG. 75, forms a second separated sub-portion 612' extending in the first direction X through the initial laminated structure 101'.

[0297] Based on this, exemplarily, the second isolated sub-portion 612' may be fabricated simultaneously with the dummy channel structure and the channel structure. For example, it is possible to form the second isolated sub-portion 612' after forming the initial stacked structure 101' and before forming the protective layer 40'.

[0298] 76, a first sub-slit 602', a second sub-slit 603', and a second slit 604' are formed in the first direction X, which extend through the initial laminated structure 101'. In the first direction X, the first sub-slit 602' and the second sub-slit 603' are in contact with both ends of the second separated sub-portion 612', respectively. In the second direction Y, the second slit 604' is disposed between two adjacent second separated sub-portions 612'.

[0299] In some examples, as shown in FIG. 74, the manufacturing method may further include:

[0300] S55', referring to FIG. 71, a first isolated sub-portion 611' is formed in the first sub-slit 602', a third isolated sub-portion 613' is formed in the second sub-slit 603', and a second isolated structure 62' is formed in the second slit 604'.

[0301] The first isolated sub-portion 611', the third isolated sub-portion 613' and the second isolated sub-portion 612' constitute at least a part of a first isolated structure 61'.

[0302] In some examples, as shown in FIG. 77, the manufacturing method may further include:

[0303] S7', referring to Fig. 71, a plurality of second stop portions 70' are formed on a side of the separation layer 30' remote from the step structure 13'. The plurality of second stop portions 70 are arranged in the first direction X and are arranged on a plurality of steps 141' of other stair structures 14' among the plurality of stair structures 14' other than the stair structure 14' in which the first stop portion 20' is arranged. Each second stop portion 70' is arranged on one step 141'.

[0304] In some examples, as shown in FIG. 78, the manufacturing method may further include:

[0305] 79, third slits 605' are formed extending in the first direction X. The third slits 605' extend through the second stop 70' and the initial laminated structure 101'. Each third slit 605' includes a plurality of third sub-slits 606' spaced apart from one another in the first direction X.

[0306] Exemplarily, the third slit 605' may be formed simultaneously with the first slit 601', or the third slit 605' may be formed simultaneously with the first sub-slit 602', the second sub-slit 603' and the second slit 604'.

[0307] In some examples, as shown in FIG. 78, the manufacturing method may further include:

[0308] In S57', referring to FIG. 71, a gate line isolation structure 80' is formed in the third slit 605'.

[0309] Illustratively, before replacing the sacrificial layer 120' with the gate layer 11' to form the stacked structure 10' in operation S5', a plurality of third slits 605' extending in the first direction X may be formed. After operation S5', gate line isolation structures 80' may be formed in the third slits 605'.

[0310] Thereby, in the step of replacing the sacrificial layer 110' with the gate layer 11', the material of the second stopper portion 70' can be replaced with the same material as that of the gate layer 11' by using the plurality of third slits 505'.

[0311] S6' forms a plurality of contact posts 50'. The contact posts 50' extend through the protective layer 40', the first stops 20', and the isolation layer 30' and connect to the gate layer 11' at steps 141' corresponding to the first stops 20'.

[0312] Exemplarily, with reference to FIG. 80, S6' of forming a plurality of contact posts 50' includes operations S61'-S63'.

[0313] S61', referring to Figures 81 and 82, the protective layer 40' is etched down to the first stop 20', thereby forming a plurality of contact holes 51'.

[0314] S62', referring to Figures 83 and 84, the first stopping portion 20' exposed by the contact hole 51' can be etched, and the isolation layer 30' and the dielectric layer 12' under the first stopping portion 20' can be etched so that the contact hole 51' exposes the gate layer 11'.

[0315] S63', referring to FIG. 19A, a contact post 50' is formed in a contact hole 51'.

[0316] In some examples, referring to FIGS. 85 and 86, the three-dimensional memory 200 (or the three-dimensional memory 300) may further include a peripheral device 400.

[0317] Illustratively, and referring again to FIGS. 85 and 86, a peripheral device 400 includes a substrate 401 and a peripheral circuit layer 402 .

[0318] There are many types of the above-mentioned peripheral circuit layer 402, which can be selected according to actual needs. The above-mentioned peripheral circuit layer 402 can include, for example, a page buffer, a decoder (such as a row decoder and a column decoder), a sense amplifier, a driver (such as a word line driver), or any active or passive components of a circuit, such as a transistor, a diode, a resistor, and a capacitor.

[0319] The above-mentioned peripheral circuit layer 402 may include, for example, a plurality of transistors, at least a portion of which are formed in the substrate 401 (e.g., below the top surface of the substrate 401) and / or directly on the substrate 401.

[0320] Additionally, the peripheral circuit layer 402 may further include any other circuitry that supports high-level logic processing. Illustratively, the peripheral circuit layer 402 includes logic circuits, such as processors and programmable logic devices, and / or memory circuits, such as static random access memory.

[0321] As shown in FIG. 87, some examples of the present disclosure provide a memory system 1000 including a three-dimensional memory 200 (three-dimensional memory 300) and a controller 2000. The controller 2000 is coupled to the three-dimensional memory 200 (three-dimensional memory 300) and controls the three-dimensional memory 300 to store data.

[0322] The memory system 1000 may be integrated into various types of storage devices, such as in the same package (e.g., Universal Flash Storage Device (UFS)) or in an embedded multimedia card (eMMC) package, i.e., the memory system 1000 may be applied and packaged in different types of electronic products, such as mobile phones (e.g., handsets), desktop computers, tablets, notebook computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power sources, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having a storage device therein.

[0323] In some examples, referring to FIG. 87, memory system 1000 may include controller 2000 and three-dimensional memory 200 (or three-dimensional memory 300) and may be integrated into a memory card.

[0324] The memory card includes any one of a PC card (PCMCIA, International Association of Personal Computer Memory Cards), a CompactFlash (CF) card, a SmartMedia (SM) card, a memory stick, a MultiMedia Card (MMC), a Secure Digital Memory Card (SD), or a UFS.

[0325] In some other examples, referring to FIG. 88, a memory system 1000 includes a controller 2000 and a plurality of 3D memories 200 (or 3D memories 300) and is integrated into a solid-state drive (SSD).

[0326] In the memory system 1000, in some examples, the controller 2000 is configured to operate in low duty cycle environments, such as SD cards, CF cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0327] In some other examples, the controller 2000 is configured to operate in high duty cycle environments SSDs or eMMCs used as data stores in mobile devices such as smart phones, tablet and notebook computers, and enterprise memory arrays.

[0328] In some examples, the controller 2000 may be configured to manage data stored in the 3D memory 200 (or the 3D memory 300) and communicate with external devices (such as a host). In some examples, the controller 2000 may be configured to control operations of the 3D memory 200 (or the 3D memory 300), such as read, erase, and program operations. In some examples, the controller 2000 may also be configured to manage various functions related to data stored or to be stored in the memory 200 (or the 3D memory 300), including at least one of bad block management, garbage collection, logical-physical address translation, wear leveling, and the like. In some examples, the controller 2000 is further configured to process error correction codes with respect to data read from and written to the 3D memory 200 (or the 3D memory 300).

[0329] Of course, any other suitable functionality may also be performed by controller 2000, such as formatting three-dimensional memory 200 (or three-dimensional memory 300). For example, controller 2000 may communicate with an external device, such as a host, via at least one of a variety of interface protocols.

[0330] It should be noted that the interface protocols include at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Area Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

[0331] Some examples of the present disclosure provide an electronic device, which may be any one of a mobile phone, a desktop computer, a tablet, a notebook computer, a server, an in-vehicle device, a wearable device such as a smart watch, a smart bracelet and a smart glass, a mobile power source, a game console, a digital multimedia player, etc.

[0332] The electronic device may include the memory system 1000 as described above, and may further include at least one of a central processing unit and a cache.

[0333] The above is merely an implementation form of the present disclosure. However, the scope of the present disclosure is not limited thereto, and any modifications or replacements that a person skilled in the art can easily conceive within the scope disclosed in the present disclosure should be included in the scope of the present disclosure. Therefore, the scope of the present disclosure should be determined by the scope of the claims.

Claims

1. a stack structure including alternating gate layers and dielectric layers, the stack structure comprising a step structure arranged in a first direction and comprising a plurality of step structures having different heights in a second direction, the step structure comprising a plurality of steps, the first direction being perpendicular to the second direction; A plurality of first stops arranged in the first direction and arranged on at least one of the plurality of steps of the staircase structure, each of the plurality of first stops being arranged on a corresponding one of the plurality of steps; a protective layer covering the step structure and the first stop portion; a plurality of contact posts, each of which extends through the protection layer and the first stop and is connected to the gate layer at the step corresponding to the first stop.

2. an isolation structure extending through the stack structure in the first direction, the isolation structure dividing the stack structure into a plurality of memory blocks, each memory block including the step structure; The three-dimensional memory of claim 1 , wherein the stair structure on which the first stop is disposed is spaced apart from the isolation structure.

3. 3. The three dimensional memory of claim 2, wherein in the second direction, the memory blocks comprise a first staircase structure, a second staircase structure, and a third staircase structure, and the first stops are disposed at the steps of the second staircase structure.

4. 3. The three dimensional memory of claim 2, wherein in the second direction, the memory blocks comprise a first staircase structure and a second staircase structure, the first staircase structure being spaced apart from the isolation structure, and the first stops being located at the steps of the first staircase structure.

5. Each memory block further includes a sidewall. the isolation structure includes a first isolation structure and a second isolation structure; 3. The three dimensional memory of claim 2, wherein in the second direction, the first isolation structure is disposed between two adjacent sidewalls in different memory blocks and the second isolation structure is disposed between two adjacent step structures, and the step structures in two memory blocks adjacent to the second isolation structure are disposed symmetrically in the second direction.

6. The three-dimensional memory of claim 5 , wherein heights of the plurality of staircase structures in the memory block gradually decrease along a direction from the first isolation structure to the second isolation structure in the second direction.

7. The three-dimensional memory of claim 5 , wherein two staircase structures adjacent to either side of the second isolation structure in the second direction have the same height.

8. Further comprising a plurality of second stop portions arranged in the first direction and arranged on the plurality of steps of other staircase structures among the plurality of staircase structures other than the staircase structure in which the first stop portion is arranged; 3. The three dimensional memory of claim 2, wherein the protective layer further covers the second stop, at least a portion of the protective layer being disposed between the second stop and the step adjacent to the second stop.

9. the memory block includes a plurality of gate line isolation structures each extending through the second stop and the stack structure and extending in the first direction, each gate line isolation structure including a plurality of spaced apart sub-isolation structures; The three dimensional memory of claim 8 , wherein a material of the second stop is the same as a material of the gate layer.

10. The three-dimensional memory of any one of claims 1 to 9, wherein the material of the first stop comprises silicon nitride.

11. In a third direction, a thickness of the first stop is the same as a thickness of the gate layer of a previous step, the previous step being adjacent to and higher than the step corresponding to the first stop; The three-dimensional memory according to claim 1 , wherein the third direction is perpendicular to the first direction and the second direction.

12. The three dimensional memory of claim 8 , wherein the first stops comprise carbon doped silicon nitride.

13. The three dimensional memory of claim 12 , wherein the material of the second stop is the same as the material of the first stop.

14. 9. The three dimensional memory of claim 8, wherein the second stop has a thickness greater than a thickness of the gate layer, the second stop comprising an insulating material.

15. The three dimensional memory of claim 1 , wherein at least a portion of the protection layer is disposed between the first stop and the step adjacent to the first stop.

16. The three dimensional memory of claim 1 further comprising an isolation layer covering said step structure and disposed between said step structure and said first stop.

17. forming an initial stack structure including alternating sacrificial and dielectric layers, the initial stack structure comprising a step structure including a plurality of step structures arranged in a first direction and having different heights in a second direction, the step structure including a plurality of steps, the first direction being perpendicular to the second direction; forming a plurality of first stops on the plurality of steps of at least one of the staircase structures, the plurality of first stops being arranged in the first direction, and each of the plurality of first stops being arranged on one of the plurality of steps; forming a protective layer covering the step structure and the first stop, at least a portion of the protective layer being disposed between the first stop and the step adjacent to the first stop; replacing the sacrificial layer with a gate layer to form a stacked structure; forming a plurality of contact posts, each of which extends through the protection layer and the first stop and is electrically connected to the gate layer at the step corresponding to the first stop.

18. forming the first stops on at least one of the steps of the staircase structure, The method of claim 17 further comprising etching the sacrificial layer and the dielectric layer on top of each step to form the plurality of first stops.

19. forming a first slit extending through the initial stack structure in the first direction, the first slit dividing the initial stack structure into a plurality of initial memory blocks, each of the initial memory blocks including the step structure; The method of claim 17 further comprising forming an isolation structure in the first slit.

20. forming a second isolated subportion extending through the initial laminate structure in the first direction; forming a first sub-slit, a second sub-slit, and a second slit extending through the initial laminate structure in the first direction, the first sub-slit and the second sub-slit being in contact with each other at both ends of the second separated sub-portion in the first direction, and the second slit being disposed between two second separated sub-portions adjacent to each other in the second direction; forming the first isolated sub-portion in the first sub-slit, forming a third isolated sub-portion in the second sub-slit, and forming a second isolated structure in the second sub-slit; The method of claim 17 , wherein the first isolated sub-portion, the third isolated sub-portion, and the second isolated sub-portion form at least a portion of the first isolated structure.

21. Further comprising forming a plurality of second stop portions on the plurality of steps of other staircase structures among the plurality of staircase structures other than the staircase structure on which the first stop portion is disposed; The method of claim 17 , wherein each second stop is disposed on a step.

22. forming a plurality of third slits extending in the first direction, the third slits extending through the second stop and the initial laminate structure, each of the third slits including a plurality of third sub-slits spaced apart from one another in the first direction; The method of claim 21 , further comprising: forming a gate line isolation structure in the third slit.

23. forming the plurality of contact posts comprises: Etching the protective layer to the first stop to form a plurality of contact holes; etching the first stop exposed by the contact hole and etching the dielectric layer below the first stop so that the contact hole exposes the gate layer; The method of claim 17, further comprising forming the contact post in the contact hole.

24. A controller; A three-dimensional memory according to any one of claims 1 to 16, The controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data.

25. 25. An electronic device comprising the memory system of claim 24.

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