Generation of quantum random numbers from single-photon avalanche diodes

Abstract

A system and method for random number generation is provided that includes receiving a first series of photons at a first single photon avalanche diode (SPAD), converting the first series of photons into a first series of electrical pulses by the first SPAD, the first series of electrical pulses having a first random time interval between each pulse of the first series of electrical pulses, and outputting a random binary stream based at least in part on the first series of electrical pulses by an output circuit in communication with the first SPAD. To generate random numbers, a system is provided that includes one or more SPADs, associated one or more quenching circuits, and output electronics configured to adjust thresholds, combine signals generated by an array of SPADs, condition signals, and output a stream of generated random numbers.

Description

[Technical field]

[0001] The present invention relates to random number generation and associated encryption of communications, as well as the creation and use of unique keys based on generated random numbers. [Background technology]

[0002] Data stores and computing devices are becoming targets for hackers who find new ways to exploit security vulnerabilities. A basic defense tactic to prevent unauthorized access to data is to use encryption to make the data inaccessible if compromised or stolen. The basis of all encryption schemes relies on the ability to generate random encryption keys. In asymmetric encryption, also known as public key cryptography, a public key and a private key are used to encrypt and decrypt data. These keys are large numbers that are paired but not identical (asymmetric). Random numbers are sometimes used to generate session keys, and therefore randomness is important to ensure the security of the system. Unfortunately, many encryption algorithms are not based on true random numbers, but rather on predictable patterns. If a random number generator produces an output with a predictable pattern or variation, it can be reverse engineered.

[0003] The development of hardware random number generators that use natural entropy sources as random seed numbers has led scientists to question the "randomness" and "quantum" nature of some of the technical claims associated with such devices. Although all modern electronic devices are quantum at some level, the randomness they generate could be considered classical noise.

[0004] The source of quantum randomness must be a quantitative and measurable source of entropy. Quantum measurements are inherently unknown, as explained in the famous Heisenberg uncertainty principle, which shows that quantum systems are probabilistic at a fundamental level. Further literature, explained in Bell's theorem, proves that quantum randomness is inherent in quantum measurements, and that the outcome of hidden or unknown variables does not determine the conclusion.

[0005] Building quantum electronic systems that separate quantum signals from classical noise is difficult. This difficulty is exacerbated by the variability found in modern manufacturing techniques, especially at the microchip level. Controlling, calculating, and measuring these signals is the critical difference between the illusion of randomness and actual quantum randomness. Improved quantum random number generators remain needed. Summary of the Invention

[0006] The disclosed technology provides a system and method for generating random numbers that can be used for encryption keys.

[0007] In accordance with certain exemplary implementations of the disclosed technology, a method for generating random numbers is provided that includes receiving a first series of photons at a first single-photon avalanche diode (SPAD), converting the first series of photons into a first series of electrical pulses by the first SPAD, the first series of electrical pulses having a first random time interval between each pulse in the first series of electrical pulses, and outputting, by an output circuit in communication with the first SPAD, a random binary stream based at least in part on the first series of electrical pulses.

[0008] Certain exemplary implementations of the disclosed technology include a quantum random number generator comprising one or more single photon avalanche diodes (SPADs), each configured to receive a corresponding sequence of photons, one or more quenching circuits in communication with each of the one or more corresponding SPADs, the one or more quenching circuits configured to convert the corresponding sequence of photons into a corresponding sequence of electrical pulses, each of the corresponding sequence of electrical pulses having a corresponding random time interval between each pulse of the corresponding sequence of electrical pulses, and an output circuit in communication with the one or more quenching circuits, the output circuit configured to output a random binary stream based at least in part on the corresponding sequence of electrical pulses.

[0009] Other features of the disclosed design and advantages offered thereby are described in more detail below with respect to specific embodiments illustrated in the accompanying drawings, in which like elements designate like references. [Brief description of the drawings]

[0010] The above and other aspects of the present invention are further explained in the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like structural elements and features in the various views. The drawings are not necessarily to scale, with emphasis instead being placed on illustrating the principles of the invention. The drawings depict one or more implementations of an apparatus according to the present invention by way of example only and not by way of limitation.

[0011] [Figure 1A] FIG. 1A illustrates an example of a SPAD-based system for random number generation in accordance with one embodiment of the present disclosure.

[0012] [Figure 1B] FIG. 1B illustrates another example of a SPAD-based random number generation system with a quenching circuit in accordance with an embodiment of the present disclosure.

[0013] [Figure 1C] FIG. 1C illustrates various input pulses for generating an output signal of the example device of FIG. 1A or FIG. 1B based on a sequence of photons received at a SPAD, according to one embodiment of the present disclosure.

[0014] [Figure 2A] FIG. 2A illustrates an example of a device including an array of SPADs, according to one embodiment of the present disclosure.

[0015] [Figure 2B] FIG. 2B is a diagram illustrating various input pulses for generating an input signal for the exemplary array of SPADs of FIG. 2A based on a sequence of photons received at the array of SPADs, according to one embodiment of the present disclosure.

[0016] [Figure 3A] FIG. 3A is a diagram illustrating a voltage threshold control of an output circuit according to one embodiment of the present disclosure.

[0017] [Figure 3B] FIG. 3B illustrates another voltage threshold control of an output circuit according to one embodiment of the present disclosure.

[0018] [Figure 3C] FIG. 3C illustrates yet another voltage threshold control of an output circuit according to an embodiment of the present disclosure.

[0019] [Figure 4A] FIG. 4A illustrates an example of a random binary stream output based on input voltage threshold control of an output circuit in accordance with one embodiment of the present disclosure.

[0020] [Figure 4B] FIG. 4B illustrates an example of a random binary stream output based on input voltage threshold control of an output circuit in accordance with one embodiment of the present disclosure.

[0021] [Diagram 5] FIG. 5 is a diagram illustrating an example of a random flip-flop (RFF) circuit with a voltage threshold control input in accordance with one embodiment of the present disclosure.

[0022] [Figure 6] FIG. 6 is a diagram illustrating another example of a random binary stream output according to an embodiment of the present disclosure.

[0023] [Figure 7] FIG. 7 is a flow diagram of a method according to a particular exemplary implementation of the disclosed technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The disclosed technology includes methods and systems for random number generation by controlling quantum microelectronics to generate truly random numbers. The systems and methods described herein may rely on the randomness of photons, low detector efficiency of diodes, and threshold voltage adjustment of output circuits to generate random binary streams. Certain exemplary devices, systems, and methods presented herein may enable entropy harvesting and random number generation.

[0025] FIG. 1A illustrates an exemplary system 100A for random number generation according to an embodiment of the present disclosure. The system 100A can detect incident photons 102 using a single-photon avalanche diode ("SPAD") 110. The term "SPAD" defines a class of photodetectors capable of detecting low-intensity photon radiation (down to a single photon) and signaling the arrival time of the photon with high time resolution (tens of picoseconds). A SPAD is a semiconductor device based on a reverse-biased pn junction at a voltage higher than its breakdown voltage. A SPAD operates like an avalanche photodiode (APD) by detecting incident radiation using a photon-triggered avalanche current.

[0026] The fundamental difference between SPADs and APDs is that SPADs are specifically designed to operate at reverse bias voltages well above the breakdown voltage, whereas APDs are typically operated at biases lower than the breakdown voltage. Under high reverse bias, the electric field at the p-n junction of a SPAD is high enough that a single charge carrier injected into the depletion layer (as a result of an incident photon) can induce a self-sustaining avalanche. Once a self-sustaining avalanche occurs, the resulting "avalanche" current rises rapidly to a steady-state level.

[0027] According to certain exemplary implementations of the disclosed technology, the output of SPAD 110 may be further conditioned / controlled by output circuit 120 in communication with SPAD 110. Output circuit 120 may output a random binary stream 130 that may be used as a random number seed (or sequence) for encryption. Random binary stream 130 may then be used, for example, in communication techniques, encryption software, hardware, or any combination thereof. In certain exemplary implementations, output circuit 120 may include an adjustable voltage threshold control input (as further described below with reference to FIG. 5).

[0028] FIG. 1B illustrates another exemplary SPAD-based random number generation system 100B with a quenching circuit 140 according to an embodiment of the present disclosure. However, in certain implementations, the quenching circuit may be packaged with the SPAD 110 or the output circuit 120. As described above, once an incident photon 102 induces a self-sustaining avalanche in the SPAD 110, the current continues to flow until the avalanche current ceases by lowering the bias voltage to the breakdown voltage (or below). To allow another photon to be detected, the bias voltage is again raised above the breakdown voltage. The quenching circuit 140 can be utilized to perform such trigger detection and bias control.

[0029] In certain exemplary implementations, the quenching circuit 140 may detect the rising edge of the avalanche current output from the SPAD 110. In certain exemplary implementations, the quenching circuit 140 may generate a standard output pulse synchronous to the avalanche build-up. In certain implementations, the quenching circuit 140 may quench the avalanche by lowering the bias voltage of the SPAD 110 to the breakdown voltage (or below), which may "reset" the SPAD 110 to allow detection of a subsequently arriving photon 102. According to certain exemplary implementations of the disclosed technology, it is possible to selectively reset the SPAD 110 after a photon has (or has not) triggered an avalanche in order to synchronize (or not) photon detection with a clock base and / or an adjustable decision threshold.

[0030] The disclosed technology can take advantage of the random nature of each photon received by the SPAD 110, which is received at a random time interval. The impact of the first series of photons 102 on the SPAD 110 causes a current avalanche, which can be, for example, in the form of an exponential growth of charge carriers. The first series of photons 102 incident on the SPAD 110 can then be converted into a first series of electrical pulses. The first series of electrical pulses can have a first random time interval between each pulse of the first series of pulses. The output circuit 120 can receive the first series of electrical pulses and generate a random binary stream 130 based at least in part on the first series of electrical pulses.

[0031] According to certain exemplary implementations of the disclosed technology, the SPADs 110 can be combined in any number of geometries, including 2D and 3D arrays (as described with reference to FIG. 2A below). The output circuit 120 can include a number of other inputs and / or outputs. For example, the random binary stream 130 generated by the output circuit 120 can be controlled or manipulated by an input threshold control voltage.

[0032] As described below with reference to FIG. 5, the output circuit 120 may include AND gates, OR gates, XOR gates, NOT gates, inverters, Schmitt triggers, NAND gates, NOR gates, XNOR gates, EXOR gates, EXNOR gates, multiplexers, flip-flops, and other logic gates, or combinations thereof.

[0033] As mentioned above, FIG. 1B further illustrates device 100B comprising SPAD 110, output circuit 120, and quenching circuit 140 in electrical communication with SPAD 110 and output circuit 120. In certain exemplary implementations, SPAD 110 may include a pn junction that operates at a bias voltage above the pn junction breakdown voltage when actively detecting a photon. At such a bias voltage, the electric field may be high enough that a single charge carrier injected into the depletion layer (e.g., via receipt of a photon) may trigger a self-sustaining avalanche. The resulting current may rapidly rise to a steady level and continue to flow until the avalanche is allowed to cease by quenching circuit 140 by lowering the bias voltage below the breakdown voltage. The bias voltage is then restored by quenching circuit 140, and SPAD 110 and associated circuitry may be used to detect another photon. This process may be repeated.

[0034] In certain exemplary implementations, the quenching operation can employ a suitable quenching circuit 140 capable of one or more of the following: (a) sensing the rising edge of the avalanche current, (b) generating a standard output pulse well synchronized with the rising edge of the avalanche, (c) quenching the avalanche by reducing the bias to the breakdown voltage (or below), and / or (d) restoring the SPAD bias voltage to an operating level.

[0035] According to certain exemplary implementations of the disclosed technology, the SPAD 110 can detect the first series of photons 102 impinging on the SPAD 110. The quenching circuit 140 then converts the first series of photons 102 into a first series of electrical pulses. The latency between the rising edges of the electrical pulses can be random according to an exponential probability distribution function. In certain exemplary implementations, the quenching circuit 140 can generate a randomized clock pulse input based at least in part on the first series of electrical pulses. In certain exemplary implementations, the quenching circuit 140 can include other inputs, outputs, AND gates, OR gates, XOR gates, NOT gates, NAND gates, NOR gates, XNOR gates, EXOR gates, EXNOR gates, multiplexers, and other logic gates, or combinations thereof. The output circuit 120 can receive the randomized clock pulse input and generate a random binary stream 130 based at least in part on the first series of electrical pulses.

[0036] In some embodiments, the dead time between quenching of the SPAD 110 or the quenching circuit 140 can be varied to ensure unbiased operation. In other embodiments, another control point to ensure unbiased operation may include asynchronously operating the SPAD 110, the quenching circuit 140, the output circuit 120, the state meter, flip-flops, and logic gates of the quenching circuit 140 and the output circuit 120 by using different clocks and clock combinations.

[0037] FIG. 1C shows a timing diagram 100C of various pulses relative to an input pulse for generating an output signal of the exemplary device of FIG. 1A or FIG. 1B based on a series of photons 102 received at the SPAD 110. This exemplary timing diagram 100C is based on a SPAD, a quenching circuit, and an output circuit (e.g., an output circuit 120 as described above with reference to FIG. 1A or FIG. 1B or described below with reference to FIG. 5). For example, the output circuit can include a toggle flip-flop and a data flip-flop. A flip-flop is a basic circuit element that can store two states controlled by an input signal. A random flip-flop is a circuit that performs an operation when the state of a clock pulse input changes from low to high. The output of the random flip-flop can be clocked separately to sample the bits to generate a random binary stream of ones and zeros 130. In some embodiments, output circuit 120 may include flip-flops, inputs, outputs, AND gates, OR gates, XOR gates, NOT gates, NAND gates, NOR gates, XNOR gates, EXOR gates, EXNOR gates, multiplexers, and other logic gates, flip-flops, or circuits, or combinations thereof.

[0038] As shown in FIG. 1C, each SPAD pulse 112 (toggle flip-flop clock input) is characterized by a rising edge and a falling edge. The toggle flip-flop generates an output Q signal 114 in response to the SPAD pulse 112. The Q signal 114 may be provided as an input to a data flip-flop. As shown in FIG. 1C, the output Q signal 114 of the toggle flip-flop is toggled high and low by the rising edge of the SPAD pulse 112. A circuit clock signal 116 may be provided to a clock input of the data flip-flop, which may generate a DATA_OUT signal 118. According to certain exemplary implementations of the disclosed technology, the DATA_OUT signal 118 output from the data flip-flop may be used to generate a random binary stream output 130. In certain exemplary implementations, the DATA_OUT signal 118 of the data flip-flop may be clocked separately. In some implementations, for example, on every rising edge of the DATA_OUT signal 118, a "1" may be output at the random binary stream output 130. Conversely, on every falling edge of the DATA_OUT signal 118, a "0" may be output at the random binary stream output 130. If the state of the DATA_OUT signal 118 does not change, the previous state may be output at the random binary stream output 130. In other words, the DATA_OUT signal 118 may be sampled to generate a random binary stream of 1's and 0's 130 as shown in FIG. 1C.

[0039] 2A shows a system 200A that includes an array of SPADs (110A, 110B, ..., 110n) with corresponding quenching circuits (140A, 140B, ..., 140n). The quenching circuits (140A, 140B, ..., 140n) provide n corresponding SPAD signals (SPAD1, SPAD2, ..., SPADn) that are input to an OR gate 150 to generate a randomized clock pulse input (SPADout) for the output circuit 120. Here, each SPAD (110A, 110B, ..., 110n) of the array detects its own respective sequence of photons 102 from the multiple sets of sequences of photons 102-102' (as described above with reference to FIGS. 1A and 2A). A corresponding series of quenching circuits (140A, 140B, ..., 140n) may be used in conjunction with a corresponding SPAD (110A, 110B, ..., 110n) to detect each series of photons 102, 102' and convert them into a series of electrical pulses.

[0040] According to certain exemplary implementations of the disclosed technology, various circuits and / or gates can be used to combine the signals from the array of SPADs (110A, 110B, ..., 110n) to output a single randomized clock pulse input (SPADout) to the output circuit 120' as described above. Other logic gates (including, but not limited to, AND gates, OR gates, XOR gates, NOT gates, NAND gates, NOR gates, XNOR gates, EXOR gates, EXNOR gates, multiplexers, and other logic gates or combinations thereof) may be used to combine the signals from each quenching circuit (140A, 140B, ..., 140n). The single randomized clock pulse input can be provided to an output circuit 120', which may include one or more flip-flops and / or other logic circuit equivalents, to generate a random binary stream 130 based at least in part on the randomized clock pulse input (SPADout). In some examples, a single randomized clock pulse input (SPADout) may be fed into a series of flip-flops to generate the random binary stream 130.

[0041] 2A, the output circuit 120' may include random flip-flops, which may include one or more toggle flip-flops and one or more data flip-flops. The output circuit 120' may further include an analog-to-digital converter.

[0042] In some embodiments, the systems 100A, 100B, and / or 200A may be provided with control points to ensure unbiased operation, for example by varying or switching on and off the light intensity on the SPAD 110 or the array of SPADs (110A, 110B, ..., 110n). In certain exemplary implementations, blocks of SPAD subarrays may be utilized to provide differential distribution of illumination on these arrays from multiple light sources. In certain embodiments, continuous health checks may be performed on the SPAD 110 or the array of SPADs (110A, 110B, ..., 110n) to measure response variations, dark counts, jitter, correlation, defects, and toggling on / off. Dark counts are the average rate of counts registered without any incident light on the SPAD 110. Health checks on jitter timing of the SPAD 110 help determine the fast time response operation of the SPAD 110. By ensuring the overall health of the SPAD array (110A, 110B, ..., 110n), the unbiased operation of the random number generator can be verified. In another example, to ensure unbiased operation of the random number generator, the SPAD array (110A, 110B, ..., 110n) can be arranged in a grid and continuously monitored for bias using columns, rows, or any combination to identify non-random behavior. If an individual SPAD 110 in the SPAD array (110A, 110B, ..., 110n) is malfunctioning, the non-random behavior of the individual SPAD 110 can be identified by comparing the output of the individual SPAD 110 with its neighboring SPADs (110A, 110B, ..., 110n), which can be another control point to ensure unbiased operation.

[0043] 2B shows a timing diagram 200B of various pulses associated with generating an output signal of the OR gate 150 based on a series of photons 102, 102' received at the SPADs (110A, 110B, ..., 110n). In this diagram, each SPAD in the array of SPADs (110A, 110B, ..., 110n) has a corresponding pulse train (112A, 112B, ..., 112n) having rising and falling edges. As shown in FIG. 2A, the series of electrical pulses from each corresponding quenching circuit (140A, 140B, ..., 140n) can be input to the OR gate 150 and result in a combined output 112' that can be used as a single randomized clock pulse input to the output circuit 120'. Other logic gates (including but not limited to AND gates, OR gates, XOR gates, NOT gates, NAND gates, NOR gates, XNOR gates, EXOR gates, EXNOR gates, multiplexers, and other logic gates or combinations thereof) can be used to combine the multiple input pulse trains (112A, 112B, ..., 112n) into the combined output 112'. In this example, the rising and falling edges of each SPAD in the array of SPADs (110A, 110B, ..., 110n) are included as rising and falling edges, respectively, in the combined output 112'.

[0044] 3A-3C show threshold voltages V 122, 122A, 122B for controlling the threshold voltage levels (122, 122A, 122B) at which an output circuit (e.g., output circuit 120 shown in FIGS. 1A and / or 1B and / or output circuit 120′ shown in FIG. 2A) interprets corresponding input signals received from a SPAD and / or other combinational logic (e.g., OR gate 150 shown in FIG. 2A) as binary 0s or 1s for output. THR 3 shows various implementations of setting 302.

[0045] FIG. 3A illustrates, for example, a voltage threshold V set at approximately 50% of the full range of the normalized input voltage V(norm) such that input voltages below the set threshold voltage level 122 are interpreted as 0 and input voltages above the set threshold voltage level 122 are interpreted as 1. THR It shows 302.

[0046] FIG. 3B illustrates a voltage threshold V(norm) set to about 25% of the full range of the normalized input voltage V(norm), such that input voltages below the set threshold voltage level 122A are interpreted as 0 and input voltages above the set threshold voltage level 122A are interpreted as 1. THR It shows 302.

[0047] FIG. 3C illustrates a voltage threshold V(norm) set to about 75% of the full range of the normalized input voltage V(norm), such that input voltages below the set threshold voltage level 122B are interpreted as 0 and input voltages above the set threshold voltage level 122B are interpreted as 1. THR It shows 302.

[0048] According to certain exemplary implementations of the disclosed technology, as shown in FIGS. 3A-3C, an input signal (such as from a SPAD) may have an associated slew rate (i.e., a rise or fall level that is not instantaneous), so that the voltage threshold V THR By adjusting 302, the durations associated with output 1's and 0's can be altered. This can provide a controllable way to further randomize the decision points when interpreting inputs from one or more SPADs as 0's or 1's for output. In certain exemplary implementations, V THR 302 can be controlled based on randomized inputs (including but not limited to the output of one or more SPADs).

[0049] 4A and 4B show how the voltage threshold V THR302 can affect the random binary stream outputs 402A, 402B based on a toggled voltage threshold control input. THR A voltage threshold V 122 is set at approximately 50% of the full range of normalized input voltages such that an input voltage 404 below 302 is interpreted as a 0 (at each rising edge of the clock signal 406) and an input voltage above the set threshold voltage level 122 is interpreted as a 1 (at each rising edge of the circuit clock signal 406). THR 302. FIG. 4B shows, for example, a set voltage threshold V THR A voltage threshold V is set at approximately 75% of the full range of normalized input voltages such that an input voltage 404 below 302 is interpreted as a 0 (at each rising edge of the clock signal 406) and an input voltage 404 above the set threshold voltage level 122 is interpreted as a 1 (at each rising edge of the clock signal 406). THR 302. The comparison of the random binary stream outputs 402A, 402B is performed based on a voltage threshold V THR 302. In a particular exemplary implementation, the voltage threshold V THR 302 may be controlled based on a randomized input (including, but not limited to, the output of one or more SPADs) to further randomize the (already randomized) binary stream output. In this regard, the voltage threshold V THR 302 may provide a desired additional level of randomization in the random number generator. In a particular exemplary implementation, the voltage threshold V THR 302 may be configured to control the ratio of 0's and 1's in the randomized binary stream output 402A, 402B over a period of time.

[0050] FIG. 5 illustrates an exemplary circuit 500 (including a SPAD 110) with various circuit components that may be utilized to provide a DATA_OUT output 550 (i.e., a randomized binary stream output) based on the receipt (and detection) of photons 102 by the SPAD 110. While other circuit components, arrangements, and / or control inputs may be utilized, the circuit 500 illustrates an exemplary embodiment that may be utilized in practical applications. The exemplary circuit 500 may include one or more field effect transistors 502, 504, 506, and 510, one or more inverters 512 and 514, one or more Schmitt triggers 516, one or more NOR gates 518, one or more toggle flip-flops 520, and / or one or more data flip-flops 530. In accordance with certain exemplary implementations of the disclosed technology, the circuit 500 illustrated in FIG. 5 may include a voltage threshold control input V_THRESH 504 (e.g., the voltage threshold control input may be the voltage threshold V THR 302). The RFF circuit may also include various quenching control inputs V_CAS, V_Q, V_RECHARGE, and V_HOLD, which may be used to control the biasing and quenching of the SPAD 110, as described above. The RFF circuit may also include other controls, such as a BIT GEN CLK (which may be similar or equivalent to the circuit clock 406 described with reference to FIGS. 4A and 4B). Certain exemplary implementations may include a TOGGLE input as an input to a toggle flip-flop 520. In certain implementations, the Q output of the toggle flip-flop 520 may be used as a data input for the data flip-flop 530. The arrangement and interaction between the various components of the circuit 500 will be understood by one of ordinary skill in the art of electronic circuit and logic design.

[0051] According to a particular exemplary implementation of the disclosed technology, a photon 102 can be detected by a SPAD 110, which can generate a signal that passes through a series of circuits and gates (which may form a quenching circuit) to generate a randomized clock pulse input 522 to a toggle flip-flop 520. The toggle flip-flop 520 is a sequential logic circuit that toggles an output depending on an input state. In this example, the output state of the toggle flip-flop 520 can be toggled high or low by a rising edge of the randomized clock pulse 522 from the SPAD 110 and / or associated quenching circuitry. The toggle flip-flop 520 can provide its output (Q) to a data input (D) of a data flip-flop 530. The data flip-flop 530 can then capture the input value at a designated edge of a clock signal CLK provided to the data flip-flop 520. A threshold voltage control input V_THRESH 540 can adjust the data flip-flop 530 to correspond to the rise and fall times of the output from the toggle flip-flop 520. A regular oscillating clock signal can be used as the clock input CLK of the data flip-flop 530. The data flip-flop 530 allows the output of the toggle flip-flop 520 to be synchronized to the clock. The data outputs 550 of the data flip-flop 530 can be individually clocked and the corresponding output bits sampled to generate a random binary stream of ones and zeros (as described above with reference to the random binary stream 130 of FIGS. 1A, 1B, 1C, 2, and / or the random binary streams 402A and 402B of FIGS. 4A and 4B).

[0052] In some embodiments, the reverse bias breakdown voltage of the SPAD 110 can be varied to modify and adjust the randomized clock pulse input 522 to the toggle flip-flop 520.

[0053] In some embodiments, as described above, the threshold voltage V_THRESH (VTHR 302) may be provided to control the random binary stream output 550 such that the ratio of ones and zeros output in the random binary stream output 550 may be adjusted. For example, the ratio of ones and zeros output in the random binary stream output 550 may be adjusted in a range of 0.01 to 100. In certain exemplary implementations, it may be desirable to set the ratio of ones and zeros output in the random binary stream output 550 to be approximately one (i.e., 1:1) over a predetermined period of time. In certain exemplary implementations, an averaging circuit may additionally be utilized to provide feedback to control the threshold voltage.

[0054] In certain exemplary implementations, instead of feeding the output 523 from the toggle flip-flop 520 to the data flip-flop 530, the voltage of the output 523 of the toggle flip-flop 530 can be measured directly to generate the random binary stream 130. In other embodiments, the toggle flip-flop 530 can be combined with an analog-to-digital converter to generate the random binary stream 130. FIG. 6 is a timing diagram 600 illustrating the generation of a random binary stream output 602. The diagram 600 shows a SPAD pulse 604 (which may correspond to the input 522 of the toggle flip-flop 520 as described in FIG. 5), a Q output 606 (which may correspond to the D input 523 of the data flip-flop 530 as described in FIG. 5), a clock signal 608 (which may correspond to the clock signal 535 as described in FIG. 5), and a DATA_OUT signal 610 (which may correspond to the DATA_OUT 550 as described in FIG. 5). Diagram 600 further illustrates a delay t 612 that can be provided (or set), for example, such that the timing of the evaluation of SPAD pulse 604 occurs a predetermined time after the rising edge of clock 608 .

[0055]

[0056] 6, the Q output 606 may toggle on with each rising edge of the SPAD pulse 604. In certain example implementations, the DATA_OUT signal 610 may be generated based on a combination of the Q output 606 logic level, the clock 608 logic level, and the delay t 612. Thus, according to certain example implementations of the disclosed technology, the delay t 612 may be utilized to further vary or randomize the DATA_OUT 610 compared to the Q output 606.

[0057] 7 is a flow diagram of a method 700 according to a particular example implementation of the disclosed technology. At block 702, the method 700 includes receiving a first series of photons at a first single-photon avalanche diode (SPAD). At block 704, the method 700 includes converting the first series of photons into a first series of electrical pulses by the first SPAD, the first series of electrical pulses having a first random time interval between each pulse of the first series of electrical pulses. At block 706, the method 700 includes outputting, by an output circuit in communication with the first SPAD, a random binary stream based at least in part on the first series of electrical pulses.

[0058] Certain exemplary implementations of the disclosed technology can include receiving a second series of photons at a second single-photon avalanche diode (SPAD). Some implementations include converting the second series of photons into a second series of electrical pulses by the second SPAD, where the second series of electrical pulses has a second random time interval between each pulse of the second series of electrical pulses. Further, outputting, by an output circuit, a random binary stream based at least in part on the first series of electrical pulses and the second series of electrical pulses.

[0059] Certain example implementations of the disclosed technology can include adjusting a bias voltage of the SPAD with a quenching circuit in response to photon detection by the SPAD. In some implementations, the quenching circuit can be configured to convert the first series of photons into a first series of electrical pulses.

[0060] Certain example implementations of the disclosed techniques can include generating, by a quenching circuit, randomized clock pulses that are based at least in part on the first series of electrical pulses.

[0061] In certain example implementations, the output circuit may include one or more of a toggle flip-flop (TFF), a data flip-flop (DFF), a random flip-flop (RFF), an analog-to-digital converter (ADC), or a combination thereof. In certain example implementations, the RFF may include a TFF and / or a DFF. In some implementations, the input to the TFF may be a randomized clock pulse input generated based at least in part on the first series of electrical pulses.

[0062] Certain exemplary implementations of the disclosed technology may include toggling the output of the TFF based on a rising edge of a randomized clock pulse input. Certain exemplary implementations of the disclosed technology may include toggling the output of the TFF based on a delay after the rising edge of the randomized clock pulse input. In some implementations, the output of the TFF may be provided as a data input to the DFF.

[0063] According to one exemplary implementation of the disclosed technology, a regularly oscillating clock signal can be provided to the clock input of a DFF.

[0064] In some implementations, the DFF may further include a voltage threshold control input.

[0065] A particular exemplary implementation of the disclosed technology is a voltage threshold V THR to control the input of the output circuit and cause the output circuit to output a random binary stream such that the random binary stream outputs a controllable ratio of ones and zeros. THR can be controlled so that the average number of zeros output in the random binary stream is approximately equal to the average number of ones.

[0066] A particular exemplary implementation of the disclosed technology is a voltage threshold V THR to control an input of the output circuit to cause the output circuit to output a random binary stream such that the random binary stream outputs an average number of zeros that is not equal to the average number of ones.

[0067] Certain exemplary implementations of the disclosed technology can include emitting a first series of photons from a light source in thermal equilibrium for detection by one or more SPADs. In certain exemplary implementations of the disclosed technology, the light source can include one or more of a light emitting diode (LED), a pulsed laser, and combinations thereof. In certain exemplary implementations, the light source can include ambient light.

[0068] Certain example implementations of the disclosed technology can include digitizing one or more of the first series of electrical pulses and the random binary stream with an analog-to-digital converter (ADC). Some implementations can include varying a dead time for receiving the first series of photons at the SPAD, where the first series of photons includes a first random time interval between the arrival of each photon in the first series of photons.

[0069] Certain exemplary implementations of the disclosed technology may include receiving the second series of photons at a second single photon avalanche diode (SPAD). Certain exemplary implementations of the disclosed technology may include converting the second series of photons into a second series of electrical pulses by the second SPAD, where the second series of electrical pulses has a second random time interval between each pulse of the second series of electrical pulses. Certain exemplary implementations of the disclosed technology may include outputting, by an output circuit, a random binary stream based at least in part on the first series of electrical pulses and the second series of electrical pulses. According to one exemplary implementation of the disclosed technology, the output circuit may include one or more of a NOT gate, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, an XNOR gate, and combinations thereof.

[0070] The disclosed technology includes a quantum random number generator that can include one or more single photon avalanche diodes (SPADs) configured to receive a respective corresponding sequence of photons, and one or more quenching circuits in communication with the respective one or more SPADs. The one or more quenching circuits can be configured to convert the corresponding sequence of photons into a corresponding sequence of electrical pulses, each corresponding sequence of electrical pulses can have a corresponding random time interval between each pulse of the corresponding sequence of electrical pulses. The system can include an output circuit in communication with the one or more quenching circuits. The output circuit can be configured to output a random binary stream based at least in part on the corresponding sequence of electrical pulses.

[0071] The description contained herein is an example of an embodiment of the disclosed technology and is not intended to limit the scope of the invention in any way. As described herein, many variations and modifications of the random number generation system are contemplated herein, including additional communication functions, additional functions to meet end-user needs not specifically described herein, additional and / or alternative random number sources, additional and / or alternative schemes and means for generating random bit streams, additional and / or alternative schemes for encrypting and / or encapsulating random numbers for secure transfer over insecure networks, additional and / or alternative schemes for creating virtual entropy sources, etc. These modifications would be apparent to one skilled in the art to which the invention pertains and are intended to be included within the scope of the claims set forth below.

Claims

1. 1. A method for generating random numbers, comprising: receiving a first series of photons at a first single-photon avalanche diode (SPAD); converting, by the first SPAD, the first series of photons into a first series of electrical pulses, the first series of electrical pulses having a first random time interval between each pulse of the first series of electrical pulses; generating a pulse waveform having the first series of electrical pulses; generating, by an output circuit in communication with the first SPAD, an output Q signal that toggles state in response to each electrical pulse in the pulse waveform; and outputting, by the output circuitry, a random binary stream based at least in part on the output Q signal.

2. receiving a second series of photons at a second single-photon avalanche diode (SPAD); converting the second series of photons into a second series of electrical pulses by the second SPAD, the second series of electrical pulses having a second random time interval between each pulse in the second series of electrical pulses; The method of claim 1 , wherein the pulse waveform comprises the first series of electrical pulses and the second series of electrical pulses.

3. The method of claim 1 , further comprising adjusting a bias voltage of the SPAD with a quenching circuit in response to photon detection by the SPAD.

4. The method of claim 3 , wherein the quenching circuit is configured to convert the first series of photons into the first series of electrical pulses.

5. the output circuit includes a toggle flip-flop (TFF) having a first clock input and a first state output; 2. The method of claim 1, wherein the TFF is configured to receive the pulse waveform at the first clock input and to provide the output Q signal at the first state output.

6. the output circuit includes a data flip-flop (DFF) having a second clock input, a state input, and a second state output; the DFF is configured to receive the output Q signal at the state input, to receive a clock signal at the second clock input, and to provide an output data signal at the second state output; The method of claim 5 , wherein the random binary stream is based at least in part on the output Q signal by virtue of the random binary stream being based at least in part on the output data signal.

7. The method of claim 6, wherein the clock signal comprises a regularly oscillating clock signal to the second clock input of the DFF.

8. The method of claim 6, further comprising generating the random binary stream such that the 1s and 0s of the random binary stream correspond to each state of the output data signal.

9. The method of claim 6, wherein the output data signal is based at least in part on the output Q signal, the clock signal, and a time delay from the clock signal.

10. The method of claim 9, comprising utilizing the time delay to further randomize the output data signal.

11. The TFF further comprises a voltage threshold control input; A voltage threshold V ＴＨＲ 6. The method of claim 5, further comprising the step of adjusting the n-th order so that the random binary stream outputs an average number of zeros approximately equal to an average number of ones.

12. The method of claim 11, wherein the voltage threshold V THR is set to a percentage of a full range of normalized voltages of the pulse waveform.

13. The TFF further comprises a voltage threshold control input; A voltage threshold V ＴＨＲ 6. The method of claim 5, further comprising the step of adjusting the n-th order so that the random binary stream outputs an average number of zeros that is not equal to the average number of ones.

14. The TFF further comprises a voltage threshold control input; The method of claim 5 further comprising adjusting a voltage threshold V THR at the voltage threshold control input based on a randomized input.

15. The method of claim 14, wherein the randomized input is based at least in part on an output from a second SPAD.

16. The TFF further includes a voltage threshold control input, and the output circuit includes an averaging circuit; averaging the output data signal with the averaging circuit; 7. The method of claim 6, further comprising: adjusting a voltage threshold V THR based at least in part on feedback from the averaging circuit.

17. The method of claim 1 , further comprising emitting the first series of photons from a light source in thermal equilibrium.

18. 20. The method of claim 17, wherein the light source comprises one or more of a light emitting diode (LED), a pulsed laser, and combinations thereof.

19. 2. The method of claim 1, further comprising varying a dead time at the first SPAD for receiving a first series of photons, the first series of photons having the first random time interval between arrival of each photon in the first series of photons.

20. receiving a second series of photons at a second single-photon avalanche diode (SPAD); converting the second series of photons into a second series of electrical pulses by the second SPAD, the second series of electrical pulses having a second random time interval between each pulse of the second series of electrical pulses; 2. The method of claim 1, further comprising: outputting, by the output circuitry, the random binary stream based at least in part on the first series of electrical pulses and the second series of electrical pulses, the output circuitry comprising one or more of a NOT gate, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, an XNOR gate, and combinations thereof.

21. one or more single photon avalanche diodes (SPADs), each configured to receive a corresponding stream of photons; one or more quenching circuits, each in communication with a corresponding one or more SPADs, configured to convert the corresponding series of photons into a corresponding series of electrical pulses, each of the corresponding series of electrical pulses having a corresponding random time interval between each pulse of the corresponding series of electrical pulses; an output circuit in communication with the one or more quenching circuits, generating a pulse waveform based at least in part on the corresponding series of electrical pulses for each of the one or more SPADs; generating an output Q signal that toggles state in response to each electrical pulse in the pulse waveform; and an output circuit configured to output a random binary stream based at least in part on the output Q signal.

22. The output circuit comprises: generating a data output signal by sampling the output Q signal based on a clock input; 22. The quantum random number generator of claim 21 configured to generate the random binary stream based at least in part on the data output signal, such that the random binary stream is based at least in part on the data output signal, such that the random binary stream is based at least in part on the output Q signal.

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