Method for forming a semiconductor package using dielectric alignment marks and a laser lift-off process - Patents.com

Abstract

A method of forming a semiconductor package includes forming a plurality of alignment marks in or on a carrier substrate, positioning and bonding a plurality of semiconductor dies to the carrier substrate based on the plurality of alignment marks, further processing the plurality of semiconductor dies into a reconstituted wafer, and separating the reconstituted wafer from the carrier substrate at an interface using a laser source, the alignment marks being interposed between the interface and the laser source.

Description

[Technical field]

[0001] Cross-references to related patents and applications This application claims priority to and the benefit of the filing date of U.S. Non-provisional Patent Application No. 17 / 727,495, filed April 22, 2022, the entirety of which is incorporated herein by reference.

[0002] The present disclosure relates generally to the field of packaging for semiconductor devices. [Background technology]

[0003] The semiconductor industry has grown rapidly due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density has been achieved by iteratively reducing the size of the minimum feature, allowing more components to be integrated into a given area. As the demand for smaller size, higher speed and bandwidth, as well as reduced power consumption and latency, has increased in recent years, there has been an increasing need for smaller and more ingenious packaging techniques for semiconductor dies. Summary of the Invention [Problem to be solved by the invention]

[0004] In die-to-wafer (D2W) bonding, a known good die (KGD) is bonded to supporting wafer with patterned alignment marks. After laser lift-off (LLO) process, remaining films need to be chemical-mechanical polished (CMP) to expose the bonding layer of KGD. The copper alignment mark pattern is bonded directly to the SiO2 die, which can cause uniformity issues and blockage of the LLO process if placed under the lift-off layer (LOL). [Means for solving the problem]

[0005] To eliminate CMP uniformity issues and LLO process concerns, it may be desirable to create SiO2 alignment marks embedded in the silicon substrate and place them under the LOL. The embodiments herein enable the use of SiO2 mark patterns and LLO processes in silicon substrates for alignment of D2W junctions. This approach can preserve the alignment mark process and its compatibility with the LLO process along with the integration scheme. In one configuration, the SiO2 alignment marks in the silicon substrate are under the SiN lift-off layer so that the alignment marks do not interfere with the laser and are more easily removed.

[0006] In one embodiment, a method may include forming a plurality of alignment marks in or on a carrier substrate, positioning and bonding a plurality of semiconductor dies to the carrier substrate based on the plurality of alignment marks, further processing the plurality of semiconductor dies into a reconstituted wafer, and separating the reconstituted wafer from the carrier substrate at an interface using a laser source, wherein the alignment marks are between the interface and the laser source.

[0007] Each of the plurality of alignment marks may include a material that is optically transparent to a wavelength of the optical energy of the laser source. Each of the plurality of alignment marks may include silicon dioxide. Each of the plurality of alignment marks may be formed as a shallow trench isolation extending into the carrier substrate.

[0008] Prior to the step of positioning the plurality of semiconductor dies on the carrier substrate, the method may further include forming a first dielectric layer to provide alignment marks, forming a second dielectric layer over the plurality of alignment marks, and forming a third dielectric layer over the second dielectric layer, the second and third dielectric layers being interposed between the plurality of semiconductor dies and the plurality of alignment marks after bonding. The third dielectric layer may be configured to prevent heat induced by the laser source from propagating to the plurality of semiconductor dies.

[0009] The laser source can deliver energy through the second surface of the carrier substrate to an interface between the carrier substrate and the second dielectric layer.

[0010] The method may further include separating the second dielectric layer from the carrier substrate without separating the plurality of alignment marks from the second dielectric layer.The method may further include separating the second dielectric layer from the carrier substrate and the plurality of alignment marks.

[0011] Following the step of separating the plurality of first semiconductor dies from the carrier substrate, the method may further include exposing the respective plurality of connectors of each of the plurality of positioned semiconductor dies, and bonding a second reconstructed wafer including the plurality of positioned second semiconductor dies to the reconstructed wafer.

[0012] In another embodiment, a method may include forming a first dielectric layer in the plurality of alignment marks along a surface of a carrier substrate, forming a second dielectric layer over the plurality of alignment marks, forming a third dielectric layer over the second dielectric layer, positioning and bonding a plurality of semiconductor dies on the carrier substrate based on the plurality of alignment marks, further processing the plurality of semiconductor dies into a reconstituted wafer, separating the reconstituted wafer and the third dielectric layer from the carrier substrate using a laser lift-off (LLO) process, and removing the third dielectric layer to expose the plurality of semiconductor dies.

[0013] Separating the plurality of semiconductor dies from the carrier substrate may further include separating the second dielectric layer from the carrier substrate with the plurality of alignment marks attached to the second dielectric layer. Separating the plurality of semiconductor dies from the carrier substrate may further include separating the second dielectric layer from the carrier substrate with the plurality of alignment marks not attached to the second dielectric layer.

[0014] The step of removing the first dielectric layer and the second dielectric layer may further include polishing at least the second dielectric layer and then the third dielectric layer to expose the respective plurality of connectors of each of the plurality of semiconductor dies.

[0015] Further processing the plurality of semiconductor dies into a reconstituted wafer may further include forming a layer of material between the dies.

[0016] Each of the plurality of alignment marks may include a material that is optically transparent to a wavelength of optical energy of the LLO process. Each of the plurality of alignment marks may include silicon dioxide.

[0017] The LLO process can include transferring energy through the second surface of the carrier substrate to an interface between the carrier substrate and the second dielectric layer.

[0018] In yet another embodiment, the method may include forming a plurality of alignment marks along a surface of a carrier substrate, positioning a plurality of semiconductor dies on the carrier substrate based on the plurality of first alignment marks such that a exfoliation layer is positioned between the alignment marks and the plurality of semiconductor dies, further processing the plurality of semiconductor dies into a reconstituted wafer, separating the reconstituted wafer from the carrier substrate at the exfoliation layer using a laser directed at the exfoliation layer, and exposing a bonding surface of the reconstituted wafer.

[0019] A laser can pass through the alignment mark to separate the release layer from the carrier substrate.

[0020] These and other aspects and implementations are described in detail below. The above information and the following detailed description, including illustrative examples of the various aspects and implementations, provide an overview or framework for understanding the nature and characteristics of the claimed aspects and implementations. The drawings illustrate the various aspects and implementations to provide a further understanding, and are incorporated in and constitute a part of this specification. It will be readily understood that aspects can be combined and that features described in connection with one aspect can be combined with other aspects. The aspects can be implemented in any convenient form. As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

[0021] Non-limiting embodiments of the present disclosure will now be described by way of example with reference to the accompanying drawings, which are schematic and are not intended to be drawn to scale. Unless otherwise indicated as representing background art, the drawings represent aspects of the present disclosure. For simplicity, not every element is necessarily labeled in every drawing. [Brief description of the drawings]

[0022] [Figure 1] 1 is a flowchart of an exemplary method of making a semiconductor package, according to some embodiments. [Figure 2A] 2A-2D are cross-sectional views of respective semiconductor packages produced by the method of FIG. 1 during various stages of manufacture, according to some embodiments. [Figure 2B] 2A-2D are cross-sectional views of respective semiconductor packages produced by the method of FIG. 1 during various stages of manufacture, according to some embodiments. [Figure 2C] 2A-2D are cross-sectional views of respective semiconductor packages produced by the method of FIG. 1 during various stages of manufacture, according to some embodiments. [Figure 2D] 2A-2D are cross-sectional views of respective semiconductor packages produced by the method of FIG. 1 during various stages of manufacture, according to some embodiments. [Figure 2E]2A-2D are cross-sectional views of respective semiconductor packages produced by the method of FIG. 1 during various stages of manufacture, according to some embodiments. [Figure 2F] 2A-2D are cross-sectional views of respective semiconductor packages produced by the method of FIG. 1 during various stages of manufacture, according to some embodiments. [Figure 2G] 2A-2D are cross-sectional views of respective semiconductor packages produced by the method of FIG. 1 during various stages of manufacture, according to some embodiments. [Figure 2H] 2A-2D are cross-sectional views of respective semiconductor packages produced by the method of FIG. 1 during various stages of manufacture, according to some embodiments. [Figure 2I] 2A-2D are cross-sectional views of respective semiconductor packages produced by the method of FIG. 1 during various stages of manufacture, according to some embodiments. [Figure 2J] 2A-2D are cross-sectional views of respective semiconductor packages produced by the method of FIG. 1 during various stages of manufacture, according to some embodiments. [Figure 2K] 2A-2D are cross-sectional views of respective semiconductor packages produced by the method of FIG. 1 during various stages of manufacture, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Reference will now be made to exemplary embodiments illustrated in the drawings, and specific terms will be used to describe the embodiments herein. However, it will be understood that no limitation of the scope of the claims or the present disclosure is intended in any way. Alterations and further modifications to the features of the invention illustrated herein, and further applications of the principles of the subject matter illustrated herein that may occur to those skilled in the art in possession of this disclosure, are intended to be within the scope of the subject matter disclosed herein. Other embodiments may be used and / or other changes may be made without departing from the spirit or scope of the present disclosure. The exemplary embodiments described in the detailed description do not limit the subject matter presented.

[0024] As semiconductor technology continues to advance, stacked semiconductor devices, such as 3D stacked semiconductor devices (3DIC), have emerged as an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, and processor circuits are fabricated on different semiconductor wafers. To further reduce the form factor of a semiconductor device, two or more semiconductor wafers may be placed on top of each other.

[0025] The two semiconductor wafers or dies may be bonded by a suitable bonding technique. Commonly used bonding techniques include direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermocompression bonding, reactive bonding, etc. Electrical connections may be provided between stacked semiconductor wafers (or stacked semiconductor devices). Stacked semiconductor devices may provide increased density in a smaller form factor, allowing for increased performance and reduced power consumption.

[0026] Laser lift-off (LLO) processes have been proposed to remove a carrier (or sacrificial) substrate from one or more positioned (or aligned) semiconductor dies during various manufacturing stages of the bonding process. In general, LLO processes may utilize optical energy at wavelengths that are optically transparent to the carrier substrate. In this manner, once the optical energy is applied to the carrier substrate, the semiconductor die may be separated from the carrier substrate for further manufacturing. However, in existing technologies, alignment marks, typically made from metal materials, are used to align the semiconductor die on the carrier substrate. These metal alignment marks, located between the carrier substrate and the semiconductor die, may interfere with manufacturing. For example, the metal alignment marks may interfere with the optical energy used during the LLO process, causing the LLO process to fail. In another example, the presence of metal alignment marks may cause problems with the polishing process (e.g., used to remove the metal alignment marks) even if the carrier substrate is successfully lifted off. Thus, existing packaging technologies based on laser lift-off processes are not entirely satisfactory in many aspects.

[0027] The present disclosure provides various embodiments for forming a semiconductor package based on a laser lift-off process. In some embodiments, a plurality of alignment marks made from a dielectric material are formed along a major surface of a carrier substrate. The alignment marks may be utilized to position a plurality of semiconductor dies on the carrier substrate. An intermediate reconstructed wafer may be formed with the semiconductor dies positioned on the carrier substrate. By interposing one or more sacrificial dielectric layers between the semiconductor dies and the carrier substrate, the LLO process may transfer its full optical energy across the carrier substrate without being interfered with by the dielectric alignment marks. In this manner, the semiconductor die (with the sacrificial dielectric layers attached) may be removed from the carrier substrate. Such sacrificial dielectric layers may be easily removed by a polishing process (e.g., a CMP process) while holding the semiconductor die in place, thereby forming a reconstructed wafer. The reconstructed wafer may be bonded to another similarly formed reconstructed wafer.

[0028] For a better visual understanding of the packaging techniques described herein, reference is now made to figures showing a substrate undergoing a process flow in cross-section. Unless otherwise noted, each figure represents one (or a set) of manufacturing steps / operations in the process flow for manufacturing a semiconductor package (device) described herein. In the cross-sections of the figures, connections between conductive layers or materials may be shown. However, it should be understood that these connections between various layers and masks are merely exemplary and are intended to illustrate the ability to provide such connections, and should not be considered as limiting the scope of the claims.

[0029] Similarly, while figures and aspects of the present disclosure may depict or describe the devices described herein as having particular shapes, it should be understood that such shapes are merely exemplary and should not be considered as limiting the scope of the technology described herein. For example, while certain figures depict various layers that define transistor structures or other electrical structures in a circular configuration, other shapes are contemplated, and indeed the technology described herein may be implemented in any shape or geometric configuration.

[0030] 1 shows a flow chart of an exemplary method 100 for forming a semiconductor package with at least one reconstituted wafer having a plurality of semiconductor dies aligned based on a plurality of dielectric alignment marks. It should be noted that the method 100 is merely an example and is not intended to be limiting of the present disclosure. Thus, it should be understood that additional steps may occur before, during, and after the method 100 of FIG. 1, and some other steps may only be briefly described herein.

[0031] In various embodiments, the steps of method 100 may be associated with cross-sectional views of an example semiconductor package 200 at various stages of manufacture, as shown in Figures 2A-2K, which are described in further detail below. It should be understood that the semiconductor device 200 shown in Figures 2A-2K may include a number of other devices, such as inductors, fuses, capacitors, coils, etc., without departing from the scope of the present disclosure.

[0032] Briefly, the method 100 begins at step 102 with forming a plurality of recesses along a first surface of a carrier substrate. The method 100 proceeds to step 104 with depositing a first dielectric material to fill the recesses. The method 100 proceeds to step 106 with forming a plurality of alignment marks in the carrier substrate. The method 100 proceeds to step 108 with depositing a second dielectric material. The method 100 proceeds to step 110 with depositing a third dielectric material. The method 100 proceeds to step 112 with bonding a plurality of semiconductor dies to the carrier substrate with second and third dielectric materials interposed therebetween. The method 100 proceeds to step 114 with performing a laser lift-off process through a second surface of the carrier substrate. The method 100 proceeds to step 116 with removing the alignment marks (if present), the second dielectric material, and the third dielectric material. The method 100 proceeds to step 118 with bonding the reconstituted wafer including the aligned semiconductor dies to another reconstituted wafer.

[0033] Corresponding to step 102 of FIG. 1, FIG. 2A is a cross-sectional view of a semiconductor package 200 having multiple recesses 204 formed along a first surface 203 of a substrate 202 at one of various stages of manufacture according to various embodiments.

[0034] The substrate 202 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, which may or may not be doped (e.g., with p-type or n-type dopants). The substrate 202 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 202 may include compound semiconductors including silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof.

[0035] As shown in FIG. 2A, recesses 204 are formed along the surface 203 of the substrate 202. Each of the recesses 204 can extend away from the surface 203 at a particular depth. In the illustrated example of FIG. 2A (and some of the following figures), three recesses 204 are shown, but it should be understood that any number of recesses can be formed along the surface 203 without departing from the scope of the present disclosure. In various embodiments, the recesses 204 that will be filled with a dielectric material to form a plurality of alignment marks can be formed with any of a variety of profiles or arrangements. For example, some of the recesses 204 can be formed with a cross-shaped profile. In another example, some of the recesses 204 can be formed with an L-shaped profile.

[0036] The recesses 204 may be formed by etching the substrate 202 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. Furthermore, the recesses 204 may be patterned in any suitable manner. For example, the recesses 204 may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. In general, a double patterning process or a multi-patterning process combines photolithography and a self-aligned process to allow for creating patterns having smaller pitches than can be obtained using, for example, a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on top of the substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers or mandrels may then be used to pattern the substrate 202.

[0037] Corresponding to step 104 of FIG. 1, FIG. 2B is a cross-sectional view of a semiconductor package 200 with a first dielectric material 206 deposited on a substrate 202 at various stages of manufacture, according to various embodiments.

[0038] As shown, the first dielectric material 206 is formed on the surface 203 with a particular thickness to fill each of the recesses 204. In some embodiments, the first dielectric material 206 may include an oxide, such as silicon oxide, a nitride, or the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and a post cure to convert it to another material, such as an oxide), or the like, or a combination thereof. Other insulating materials and / or other formation processes may be used. Once the insulating material is formed, an annealing process may be performed.

[0039] Corresponding to step 106 of FIG. 1, FIG. 2C is a cross-sectional view of a semiconductor package 200 having multiple alignment marks 208 formed along a first surface 203 of a substrate 202 at one of various stages of manufacturing according to various embodiments.

[0040] The alignment mark 208 is formed by performing a planarization process, such as chemical mechanical polishing (CMP), on the first dielectric material 206. The planarization process can remove excess first dielectric material 206 until the surface 203 is exposed again, thereby making the top surface of the alignment mark 208 coplanar with the surface 203.

[0041] 2D is a cross-sectional view of a semiconductor package 200 with a second dielectric material 210 formed on a surface 203 of a substrate 202 at various stages of manufacture, according to various embodiments. As shown, the second dielectric material 210 is formed on a coplanar surface shared by the alignment mark 208 and the surface 203. In some embodiments, the second dielectric material 210 may have etch selectivity with respect to the material of the alignment mark 208. For example, the second dielectric material 210 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, multilayers thereof, and the like, and may be deposited or thermally grown.

[0042] 1, FIG. 2E is a cross-sectional view of a semiconductor package 200 with a third dielectric material 212 formed on a second dielectric material 210, according to various embodiments. In some embodiments, the third dielectric material 212 can act as a buffer layer to protect one or more semiconductor dies from damage caused by the energy of the laser lift-off process. For example, the third dielectric material 212 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, multilayers thereof, and the like, and can be deposited or thermally grown.

[0043] Corresponding to step 112 of FIG. 1, FIG. 2F is a cross-sectional view of semiconductor package 200 with semiconductor die 220 bonded to substrate 202 at various stages of manufacture according to various embodiments.

[0044] As shown, the semiconductor die 220 has a number of device features (e.g., transistors, not shown for clarity) formed along a surface of the substrate 222 and a number of interconnect structures 224 (e.g., metal lines, metal vias, metal pads, etc.) formed on the device features. The interconnect structures 224 are configured to electrically connect the device features to one another to form an integrated circuit that may function as a logic device, a memory device, an input / output device, etc. These interconnect structures 224 may be embedded in one or more dielectric layers (e.g., low-k dielectric materials). It should be understood that the semiconductor die 220 in FIG. 2F is shown upside down. Thus, a top one of the dielectric layers contacts the third dielectric material 212. The semiconductor die 220 and the third dielectric material 212 are bonded using a direct surface bond, such as, for example, an oxide-oxide bond, a hybrid bond, etc.

[0045] Although one semiconductor die 220 is shown bonded to the third dielectric material 212, it should be understood that any number of semiconductor dies may be bonded to the third dielectric material 212. Moreover, such semiconductor dies are bonded to the third dielectric material 212 based on the alignment marks 208 according to various embodiments. For example, the alignment marks 208 may each function as an anchor or define a footprint for one or more corresponding ones of the semiconductor dies. In this manner, the semiconductor dies may be laterally positioned relative to one another at corresponding positions. To position the semiconductor dies, the alignment marks 208 may be recognized using an optical microscope or a scanning electron microscope.

[0046] 1, Figure 2G is a cross-sectional view of semiconductor package 200 during various stages of manufacturing in which optical energy 230 of an LLO process is applied through second surface 205 of substrate 202, according to various embodiments. Figures 2H and 2I each show alternative cross-sectional views of semiconductor package 200 during an LLO process.

[0047] After semiconductor die 220 is bonded and positioned to third dielectric material 212 (step 112 in FIG. 1 ), a molding compound 226 is formed around semiconductor die 220 and over third dielectric material 212. In some embodiments, molding compound 226 can hold semiconductor die 220 (and other dies, not shown, that are bonded to third dielectric material 212) in place during various later manufacturing stages. Such a substrate (e.g., substrate 202) having multiple semiconductor dies positioned (based on alignment marks 208) and secured (by molding compound 226) may sometimes be referred to as a reconstituted wafer.

[0048] The molding compound 226 is shaped or molded using, for example, a mold (not shown) that may have boundaries or other features to retain the molding compound 226 once applied. Such a mold may be used to pressure mold the molding compound 226 around the semiconductor die 220 to force the molding compound 226 into the openings and recesses while eliminating air pockets and the like within the molding compound 226. In one embodiment, the molding compound 226 is a non-conductive or dielectric material such as an epoxy, resin, moldable polymer such as PBO or another moldable material. For example, the molding compound 226 is an epoxy or resin that is cured via a chemical reaction or by drying. In another embodiment, the molding compound 226 is an ultraviolet (UV) cured polymer. Following the formation of the molding compound 226, a grinding or polishing process may be performed to remove excess molding compound until the backside of the substrate 222 is exposed and optionally thinned. The reconstituted wafer may utilize one or more inorganic layers to reduce the mismatch in coefficient of thermal expansion (CTE) between the die and the material between the die. Such inorganic layers (eg, silicon oxide, silicon nitride, etc.) can augment or completely replace molding compound 226.

[0049] In the LLO process, optical energy (e.g., a laser beam) 230 is irradiated onto the composite structure through the surface 205 of the substrate 202, and the irradiation passes through the carrier substrate 202 and reaches the interface between the surface 203 and the second dielectric material 210. In various embodiments, the respective materials of the carrier substrate 202 and the alignment marks 208 may be optically transparent to the wavelength of the optical energy 230. As a non-limiting example, the laser irradiation incident on the carrier substrate 202 may be 248 nm irradiation from a KrF pulsed excimer laser having a pulse width of 38 ns. This irradiation passes easily through the carrier substrate 202 without the alignment marks 208 significantly blocking the energy. The energy is then absorbed by the second dielectric material 210, which acts as a release layer. The LLO process may be performed in either vacuum, air, or other ambient environments. After performing the LLO process, the second dielectric material 210 (along with the third dielectric material 212 and the positioned and secured semiconductor die 220 disposed thereon) may be separated from the carrier substrate 202 with and without the alignment marks 208 attached, as shown in Figures 2H and 2I, respectively. Additionally or alternatively, some or all of the second dielectric material 210 may be ablated, sublimated, or otherwise removed from both the first and third dielectric layers by the energy of a laser.

[0050] Corresponding to step 116 of FIG. 1, FIG. 2J is a cross-sectional view of semiconductor package 200 with alignment mark 208 (if present), second dielectric material 210, and third dielectric material 212 removed at one of various stages of manufacturing according to various embodiments.

[0051] If any remaining alignment marks 208 (e.g., formed of silicon oxide) are present, such alignment marks 208 may be removed by applying dilute hydrofluoric acid (DHF) across the workpiece. A polishing process may then be performed to remove the second dielectric material 210, followed by the third dielectric material 212. In some embodiments, the polishing process may be terminated until a bonding surface of the semiconductor die 220 is exposed. Such bonding surface may include (or may expose) multiple bonding pads of the semiconductor die 220. In various embodiments, removing the second and third dielectric materials (i.e., exposing one or more aligned and secured bonding surfaces of the semiconductor die) results in a reconstituted wafer in preparation for further bonding with another wafer, reconstituted wafer, or panel.

[0052] Corresponding to step 118 of FIG. 1, FIG. 2K is a cross-sectional view of a semiconductor package 200 having a first reconstituted wafer 270 and a second reconstituted wafer 280 bonded together at one of various stages of manufacture, according to various embodiments. Each of the first reconstituted wafer 270 and the second reconstituted wafer 280 may be formed via steps 102-116 of FIG. 1. For example, each of the first reconstituted wafer 270 and the second reconstituted wafer 280 may include a plurality of semiconductor dies (e.g., 220) positioned by a plurality of dielectric alignment marks (e.g., 208) and secured by a molding compound (e.g., 226). Additionally, the first reconstituted wafer 270 and the second reconstituted wafer 280 may have their respective bond pads aligned with one another. However, it should be understood that the reconstituted wafers formed by the disclosed steps may be bonded to any of a variety of other wafers without departing from the scope of the present disclosure. For example, the disclosed reconstituted wafers may be bonded to a standard wafer.

[0053] Having now described several exemplary implementations, it should be apparent that the foregoing is presented by way of example and not limitation. In particular, while many of the examples presented herein involve particular combinations of method acts or system elements, those acts and those elements may be combined in other ways to achieve the same purpose. Acts, elements, and features described only in the context of one implementation are not intended to be excluded from a similar role in other implementations.

[0054] The phrases and terms used herein are for descriptive purposes and should not be considered limiting. The use of "comprising," "including," "having," "containing," "including," "characterized by," "characterized by," and variations thereof herein are meant to cover the items listed thereafter, equivalents thereof, and additional items, as well as alternative implementations consisting only of the items listed thereafter. In one implementation, the systems and methods described herein consist of one, any combination of two or more of, or all of the described elements, acts, or components.

[0055] A "substrate" or "target substrate" may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, lower or upper layer, whether patterned or not, but is intended to include any such layer or base structure, as well as any combination of layers and / or base structures. While the description may refer to a particular type of substrate, this is for illustrative purposes only.

[0056] Any reference herein to system and method implementations, elements, or acts in the singular may also include implementations that include a plurality of those elements, and any reference herein to implementations, elements, or acts in the plural may also include implementations that include only a single element. References in the singular or plural are not intended to limit the presently disclosed systems or methods, their components, acts, or elements to a single or multiple configuration. References to any act or element being based on any information, act, or element may include implementations in which the act or element is based at least in part on any information, act, or element.

[0057] The implementations disclosed herein may be combined with other implementations, and references to "implementations," "several implementations," "alternative implementations," "various implementations," "an implementation," etc. are not necessarily mutually exclusive, and are intended to indicate that a particular feature, structure, or characteristic described in connection with that implementation may be included in at least one implementation. Such terms as used herein do not necessarily all refer to the same implementation. Any implementation may be combined with any other implementation, inclusively or exclusively, in any manner not inconsistent with the aspects and implementations disclosed herein.

[0058] References to "or" may be construed as inclusive, such that any term described using "or" may refer to either a single one, more than one, or all of the described term.

[0059] When a reference sign follows a technical feature in a drawing, the detailed description, or any claim, the reference sign is included solely for the purpose of enhancing the comprehension of the drawing, the detailed description, and the claims, and thus the presence or absence of the reference sign does not have any limiting effect on the scope of any claim element.

[0060] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the embodiments described herein and variations thereof. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the spirit or scope of the subject matter disclosed herein. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but is intended to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.

[0061] While various aspects and embodiments have been disclosed, other aspects and embodiments are contemplated. The various aspects and embodiments disclosed are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

Claims

1. forming a plurality of alignment marks in or on a carrier substrate; positioning and bonding a plurality of semiconductor dies to the carrier substrate based on the plurality of alignment marks; further processing the plurality of semiconductor dies into a reconstituted wafer; separating the reconstituted wafer from the carrier substrate at an interface using a laser source, the alignment mark being between the interface and the laser source; A method comprising:

2. The method of claim 1 , wherein each of the plurality of alignment marks comprises a material that is optically transparent to a wavelength of optical energy of the laser source.

3. The method of claim 1 , wherein each of the plurality of alignment marks comprises silicon dioxide.

4. Prior to the step of positioning a plurality of semiconductor dies on the carrier substrate, forming a first dielectric layer to provide said alignment marks; forming a second dielectric layer over the plurality of alignment marks; forming a third dielectric layer over the second dielectric layer; 2. The method of claim 1, further comprising: wherein the second and third dielectric layers are interposed between the plurality of semiconductor dies and the plurality of alignment marks after bonding.

5. 5. The method of claim 4, wherein the third dielectric layer is configured to prevent or reduce heat induced by the laser source from propagating to the plurality of semiconductor dies.

6. The method of claim 4 , wherein the laser source delivers energy through a second surface of the carrier substrate to an interface between the carrier substrate and the second dielectric layer.

7. The method of claim 6 , further comprising: separating the second dielectric layer from the carrier substrate without separating the plurality of alignment marks from the second dielectric layer.

8. The method of claim 6 , further comprising: separating the second dielectric layer from the carrier substrate and the plurality of alignment marks.

9. Following the step of separating the reconstituted wafer from the carrier substrate, exposing a respective plurality of connectors on each of the plurality of positioned semiconductor dies; bonding a second reconstructed wafer including a plurality of positioned second semiconductor dies to the reconstructed wafer; The method of claim 1 further comprising:

10. The method of claim 1 , wherein each of the plurality of alignment marks is formed as a shallow trench isolation extending into the carrier substrate.

11. forming a first dielectric layer along a surface of a carrier substrate and within the plurality of alignment marks; forming a second dielectric layer over the plurality of alignment marks; forming a third dielectric layer over the second dielectric layer; positioning and bonding a plurality of semiconductor dies onto the carrier substrate based on the plurality of alignment marks; further processing the plurality of semiconductor dies into a reconstituted wafer; separating the reconstituted wafer and the third dielectric layer from the carrier substrate using a laser lift-off (LLO) process; removing the third dielectric layer to expose the plurality of semiconductor dies; A method comprising:

12. 12. The method of claim 11 , wherein the step of separating the reconstituted wafer from the carrier substrate further comprises: separating the second dielectric layer from the carrier substrate with the plurality of alignment marks attached to the second dielectric layer.

13. 12. The method of claim 11 , wherein the step of separating the reconstituted wafer from the carrier substrate further comprises: separating the second dielectric layer from the carrier substrate while the plurality of alignment marks are not attached to the second dielectric layer.

14. 12. The method of claim 11 , wherein the step of removing the second and third dielectric layers further comprises polishing at least the second and then the third dielectric layer to expose a respective plurality of connectors on each of the plurality of semiconductor dies.

15. The method of claim 11 , wherein further processing the plurality of semiconductor dies into a reconstituted wafer comprises forming a layer of material between the semiconductor dies.

16. The method of claim 11 , wherein each of the plurality of alignment marks comprises a material that is optically transparent to a wavelength of optical energy of the LLO process.

17. The method of claim 11 , wherein each of the plurality of alignment marks comprises silicon dioxide.

18. The method of claim 11 , wherein the LLO process comprises transferring energy through a second surface of the carrier substrate to an interface between the carrier substrate and the second dielectric layer.

19. forming a plurality of alignment marks along a surface of a carrier substrate; positioning the semiconductor dies on the carrier substrate based on the alignment marks such that a release layer is positioned between the alignment marks and the semiconductor dies; further processing the plurality of semiconductor dies into a reconstituted wafer; separating the reconstituted wafer from the carrier substrate at the exfoliation layer using a laser directed at the exfoliation layer; exposing a bonding surface of the reconstituted wafer; A method comprising:

20. 20. The method of claim 19, wherein the laser passes through the alignment mark to separate the release layer from the carrier substrate.

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