Inverted current amplification and related touch systems - Patents.com

Abstract

One or more embodiments relate to inverted current amplification and related touch systems. The apparatus includes a first transistor, a second transistor, and a feedback loop. The first transistor and the second transistor provide a controlled current in the second transistor that is a copy of the current in the first transistor when the respective drain-source voltages of the first transistor and the second transistor are substantially equal. The feedback loop sets the respective drain-source voltages of the first transistor and the second transistor to be substantially equal, and the responsiveness of the feedback loop is proportional to the set transconductance of the feedback loop.

Description

[Technical field]

[0001] (Priority Claim) This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 63 / 363,695, entitled “CURRENT AMPLIFICATION AND TOUCH CONTROLLER INCLUDING THE SAME,” filed April 27, 2022, the disclosure of which is incorporated herein by reference in its entirety.

[0002] (Technical field) One or more embodiments relate to inverting current amplification. One or more embodiments relate to differential current amplification using inverting current amplification. One or more embodiments relate to measuring electrode capacitance using differential and inverting current amplification. One or more embodiments relate to touch sensing. [Background technology]

[0003] Inverting and differential current amplifiers are utilized in a variety of operating situations, including, but not limited to, capacitance measurements and touch sensing. [Brief description of the drawings]

[0004] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which that element is first introduced. [Figure 1] 1 is a schematic diagram of an inverting current amplifier in accordance with one or more embodiments. [Diagram 2] 2 is a schematic diagram illustrating an inverting current amplifier portion corresponding to the upper stage of the inverting current amplifier of FIG. 1. [Diagram 3] FIG. 11 is a flow diagram illustrating a process for inverting a current signal in accordance with one or more embodiments. [Figure 4] 1 is a block diagram illustrating an apparatus for canceling a baseline charge signal received from a measured charge signal received from a touch electrode in accordance with one or more embodiments. [Diagram 5]1 is a block diagram illustrating an apparatus for canceling a baseline charge signal received from a measured charge signal received from a touch electrode in accordance with one or more embodiments. [Figure 6] 2 is a flow diagram illustrating a process for setting the bandwidth of an OTA in a feedback loop utilized in the inverting current amplifier of FIG. 1 in accordance with one or more embodiments. [Figure 7] 2 is a flow diagram illustrating a process for setting the bandwidth of an OTA in a feedback loop utilized in the inverting current amplifier of FIG. 1 in accordance with one or more embodiments. [Figure 8] FIG. 11 is a flow diagram illustrating a process for determining a state of an electrode of a capacitive sensor including canceling a baseline charge signal from a measured charge signal in accordance with one or more embodiments. [Figure 9] FIG. 1 is a block diagram illustrating a system for sensing touch via capacitance in accordance with one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] The illustrative diagrams presented herein are not meant to be actual diagrams of any particular method, system, device, or structure, but are merely idealized representations used to explain embodiments of the present disclosure. The drawings presented herein are not necessarily drawn to scale. Similar structures or components in various drawings may retain the same or similar numbering for the convenience of the reader. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0006] The following description may include examples to aid in enabling those skilled in the art to practice the disclosed embodiments. The use of the terms "exemplary," "example," and "for example" means that the associated description is illustrative, and the scope of the disclosure is intended to encompass examples and legal equivalents, and the use of such terms is not intended to limit the examples or the scope of the disclosure to the specified components, steps, features, functions, etc.

[0007] It will be readily understood that the components of the examples as generally described herein and illustrated in the Figures could be arranged and designed in a wide variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the disclosure, but is merely representative of various embodiments. Although various aspects of the examples may be presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0008] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Furthermore, the block definitions and partitioning of logic between various blocks are illustrative of specific implementations. It will be readily apparent to one skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like are omitted, and such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of one skilled in the art.

[0009] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. Some figures may illustrate a signal as a single signal for clarity of display and explanation. Those skilled in the art will understand that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal.

[0010] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer, and a general purpose computer is configured to execute computing instructions (e.g., software code) related to the embodiments of the present disclosure.

[0011] The embodiments may be described in terms of a process depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different order, in parallel, or substantially simultaneously. Additionally, the order of the acts may be rearranged. A process may correspond to, but is not limited to, a method, a thread, a function, a procedure, a subroutine, a subprogram. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.

[0012] Any reference to an element herein using a designation such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitation is expressly stated. Rather, these designations may be used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to a first element and a second element does not imply that only two elements may be used or that the first element must precede the second element in any manner. In addition, unless otherwise specified, a set of elements may include one or more elements.

[0013] As used herein, any relative terms, such as "over," "under," "on," "underlying," "upper," "lower," and the like, are used for clarity and convenience in understanding the disclosure and the accompanying drawings, and are not intended to imply or depend on any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0014] As used herein, the term "substantially" when referring to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with small variations, such as, for example, within acceptable manufacturing tolerances. As an example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

[0015] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with one another. When an element is described as "coupled" to another element, the elements may be in direct physical or electrical contact, or there may be intervening elements or layers present. In contrast, when an element is described as "directly coupled" to another element, there are no intervening elements or layers present. The terms "on" and "connected" may be used interchangeably with the term "coupled" herein and have the same meaning unless expressly stated otherwise or the context otherwise indicates otherwise to one of ordinary skill in the art.

[0016] The capacitance of the electrodes of a touch sensor may be utilized by a touch controller to detect changes in the state of the electrodes or the touch sensor more generally. Non-limiting examples of detectable states include the presence of an object spaced from the electrode but not in physical contact with the electrode or an implement in contact with the electrode (also called "hover"), the presence of an object in physical contact with the electrode or an implement in capacitive contact with the electrode (also called "touch"), or the absence of an object (also called "no touch"). Some touch controllers do not distinguish between hover and touch, or between hover and no touch.

[0017] Some touch sensing systems use the amount of charge transferred between an electrode and a measurement circuit to determine the capacitance of the electrode. The rate at which charge is transferred between the electrode and the measurement circuit changes in response to changes in the capacitance of the electrode, which changes in response to the presence of an object, and thus the rate of charge transfer, or the amount of charge transferred during a given duration, indicates the presence of an object, e.g., "touch" or "no touch."

[0018] The portion of the determined capacitance of an electrode (e.g., via, but not limited to, self-capacitance measurements) attributable to the electrode and coupling circuitry of a touch sensor (or touch sensor and a host device including the touch sensor) is referred to as the "baseline capacitance" or "baseline cap," and the amount of charge transferred attributable to the electrode and coupling circuitry of a touch sensor is referred to as the "baseline capacitance charge" or "baseline cap Q." Generally speaking, the baseline cap is the determined capacitance of the electrode when no object is present, and the baseline cap Q is the determined amount of charge transferred when no object is present.

[0019] The portion of the determined capacitance of an electrode (e.g., via, but not limited to, self-capacitance measurements) that is due to the presence of an object other than the touch sensor (or the touch sensor and a host device that includes the touch sensor) is referred to as the "projected capacitance" or "projected cap," and the amount of transferred charge that is due to the presence of an object other than the touch sensor (or the touch sensor and a host device that includes the touch sensor) is referred to as the "projected capacitance charge" or "projected cap Q." Generally speaking, the projected cap is the determined capacitance of the electrode when an object is present minus the baseline capacitance, and the projected cap Q is the determined amount of charge transferred when an object is present minus the baseline cap Q.

[0020] Generally speaking, the determined total capacitance of an electrode is equal to the baseline capacitance plus the projected capacitance, and the determined total charge transferred is equal to the baseline cap Q plus the projected cap Q. The determined total capacitance of an electrode is referred to as the "measured capacitance" of the electrode, and the total charge transferred (e.g., input current) is referred to as the "measured capacitance charge" or "measured cap Q." Information regarding the measured capacitance of the electrode is referred to as the "measured signal," and information regarding the charge on the measured capacitance is referred to as the "measured charge signal." The measured charge signal may be utilized to represent or determine the measured signal.

[0021] The information in the measurement signal related to the baseline cap is referred to herein as the "baseline signal," and the information in the measurement charge signal related to the baseline capacitance charge (baseline cap Q) is referred to herein as the "baseline charge signal" or "baseline Q signal." The information in the measurement signal related to the projection cap is referred to herein as the "touch signal," and the information in the measurement charge signal related to the projected capacitance charge (projection cap Q) is referred to herein as the "touch charge signal" or "touch Q signal." The baseline charge signal may represent or be utilized to determine the baseline signal. The touch charge signal may represent or be utilized to determine the touch signal.

[0022] The "sensitivity" of a touch controller refers to the magnitude of the change in the touch signal, and therefore the magnitude of the change in the touch charge signal that can be detected by the touch controller. Increasing the sensitivity of a touch controller means that the touch controller can detect changes in the touch signal that are smaller than before the sensitivity was increased. Decreasing the sensitivity of a touch controller means that the touch controller can only detect changes in the touch signal that are larger than before the sensitivity was decreased.

[0023] When an object (e.g., but not limited to, a finger, hand, or stylus) hovers above the touch screen (i.e., at least momentarily separated from the touch electrodes of the touch screen by some distance (e.g., but not limited to, by an air gap)), the touch signal is smaller (e.g., but not limited to, by several orders of magnitude smaller) than the baseline signal.

[0024] One approach is to reduce or cancel the baseline signal from the measurement signal to reduce or eliminate the effect of the baseline capacitance on the measurement signal. The baseline signal is inverted (i.e., a gain of -1) and the inverted baseline signal is combined with the measurement signal to cancel the baseline signal from the measurement signal.

[0025] An inverting current amplifier may be used to invert the baseline signal, but as discussed below, some inverting current amplifiers using cascode current mirrors exhibit imperfect inverse gain (i.e., achieve an inverse gain different from -1), at least when used for touch sensing. Thus, the baseline signal may not be reliably completely cancelled (or reduced to a negligible magnitude) based solely on the output of such an inverting current amplifier. Such uncanceled portion of the baseline cap signal is referred to herein as the "offset signal," and the charge of the offset signal is referred to herein as the "offset Q." The offset signal, if included with a touch signal, may be large enough to destroy touch detection, i.e., inadvertent detection of a "touch" condition, such inadvertent detection will result in a touch error.

[0026] If the input signal received at the measurement circuit includes a touch signal and an offset signal, the measurement circuit may experience touch errors. Touch sensing systems known to the inventors of the present disclosure that reduce or cancel the baseline signal from the measurement signal apply some additional gain to the touch signal to account for the offset signal so that the touch signal can be measured.

[0027] If the baseline signal is canceled so that the touch signal can be used directly by the touch measurement circuit or is the only signal that must be amplified, the operating range (e.g., but not limited to, the input range) of the touch measurement circuit may accommodate touch signals that are typically smaller signals than the baseline signal.

[0028] Some inverting current amplifiers utilize cascode current mirrors. Cascode current mirrors are sensitive to voltage spikes caused by transient currents injected at the input of the inverting current amplifier, which causes inaccurate current gain (i.e., the gain of the inverting current amplifier is not -1). Although the cascode current mirror requires sufficient voltage headroom to exhibit accurate current gain, voltage spikes reduce the voltage headroom of the cascode current mirror, so that the voltage headroom is insufficient for the cascode current mirror and thus the inverting current amplifier including it may operate in an unpredictable manner. The inventors of the present disclosure understand that such voltage spikes can cause the drain-source voltages (Vds) of the primary and secondary transistors in the cascode current mirror to diverge, at least momentarily, and the sufficiently divergent drain-source voltages cause inaccurate current mirroring. The inventors of the present disclosure understand that increasing the responsivity of the current mirror of the inverting current amplifier to reduce or eliminate the divergent drain-source voltages will increase the accuracy of the current mirroring and the gain of the inverting current amplifier.

[0029] The inventors of the present disclosure realize that an inverting current amplifier exhibiting a precise current gain of substantially -1 (i.e., with an accuracy of 99% or better) can be used to completely cancel (i.e., cancel by 99% or better) the baseline cap Q in the input current.

[0030] One or more embodiments generally relate to an inverting current amplifier structure that is less sensitive to voltage spikes caused by transient currents injected into the input of the inverting current amplifier (i.e., than those using a typical cascaded current mirror) and therefore less susceptible to providing inaccurate current gains due to such transient currents. The exemplary inverting current amplifiers discussed herein may achieve an inverting gain of substantially -1 (i.e., with an accuracy of 99% or better).

[0031] One or more embodiments generally relate to a set of differential current amplifiers each including an exemplary inverting current amplifier as discussed herein. The differential current amplifiers amplify their respective input currents, combine the amplified input currents, utilize respective exemplary inverting current amplifiers as discussed herein to invert their respective amplified input currents, and combine their respective amplified input currents with respective inverted amplified input currents generated by other differential current amplifiers of the set. In one or more embodiments, the differential current amplifiers of the set are adjacent differential amplifiers (i.e., process input currents from sensor lines that are physically located immediately adjacent to each other). In one or more embodiments, adjacent differential current amplifiers may, but need not, be physically located immediately adjacent to each other.

[0032] One or more embodiments generally relate to a touch controller or touch sensing system including at least one exemplary set of differential current amplifiers discussed herein for respectively receiving input signals generated in response to a touch measurement process from touch electrodes (i.e., two different touch electrodes). Each exemplary inverting current amplifier discussed herein of the set of differential current amplifiers is utilized to generate a baseline cap Q (i.e., an inverted baseline cap Q), or more generally, a baseline signal (i.e., an inverted baseline signal). The baseline signal is utilized to cancel (e.g., but not limited to, cancel completely or cancel such that only a negligible amount that can be ignored remains) a baseline signal present in at least one of the input signals. Thus, in one or more embodiments, an offset signal is not present (e.g., but not limited to, not present completely or present to a negligible extent that can be ignored) in the signal provided to the measurement circuitry of the touch controller. In the case of a differential current amplifier canceling the baseline Q signal, only the touch Q signal or a multiple thereof that was present in the input current received from the electrode, or more generally from the touch sensor, is present in the output current of the differential current amplifier.

[0033] In one or more embodiments, the amount of touch Q signal in an output current provided by an example differential amplifier discussed herein may have a predetermined relationship (e.g., but not limited to, a ratio or multiple) to the amount of touch Q signal present in an input current received by the differential amplifier. For purposes of distinction herein, the amount of touch Q signal present in the input current may be referred to herein as the "input touch Q signal," and the amount of touch Q signal in the output current may be referred to herein as the "output touch Q signal."

[0034] Because the output current of the differential amplifier includes only the touch Q signal, it may be processed (e.g., but not limited to, by a touch measurement circuit) without gain or without high gain. The touch controller may exhibit high sensitivity to modifications of the touch Q signal (in the case of both the input and output touch Q signals). The exemplary inverting current amplifier and the differential amplifier that includes it may increase the sensitivity of the touch measurement circuit or touch controller that includes it, as compared to known current amplifiers that implement similar gain.

[0035] One or more embodiments of the differential structures discussed herein may find application in touch sensing systems where, by way of non-limiting example, hover detection is desired.

[0036] 1 is a schematic diagram of an inverting current amplifier 100 in accordance with one or more embodiments. The inverting current amplifier 100 exhibits no or negligible error in the output touch Q signal.

[0037] The inverting current amplifier 100 includes an input terminal 112, an output terminal 114, an upper stage 102, a lower stage 104, and a translinear loop 106.

[0038] The translinear loop 106 (i.e., the arrangement of transistors M1, M2, M3, and M4 depicted in FIG. 1) supplies a DC bias current (I DCBIAS ) is provided.

[0039] NMOS transistors M1 and M2 are the same size, and PMOS transistors M3 and M4 are the same size. Their gates are coupled to the drains of NMOS transistor M1 and PMOS transistor M2, respectively. The gate of NMOS transistor M2 is coupled to the gate of NMOS transistor M1 and therefore to the drain of NMOS transistor M1. The gate of PMOS transistor M4 is coupled to the gate of PMOS transistor M3 and therefore to the drain of PMOS transistor M3.

[0040] DC bias current (I DCBIAS ) is represented in FIG. 1 by two DC current sources, a first DC current source coupled to the drain of NMOS transistor M1 and pointing from VDD to 0.5VDD through NMOS transistor M1, and a second DC current source coupled to the drain of PMOS transistor M3 and pointing from 0.5VDD to ground through PMOS transistor M3.

[0041] The respective DC bias currents provided by the first and second DC current sources are equal. The DC current mirrored in transistor M2 is the bias current of primary transistor 116, and the DC current mirrored in transistor M4 is the bias current of primary transistor 120.

[0042] The drain-source current of NMOS transistor M1 is set to the DC bias current provided by the first DC current source, and therefore the drain-source current in NMOS transistor M2, which is a copy of the drain-source current in NMOS transistor M1, is set equal to the DC bias current. Additionally, the drain-source current in primary transistor 116, which is in series with NMOS transistor M2, is set equal to the DC bias current.

[0043] The drain-source current of PMOS transistor M3 is set to the DC bias current provided by the second DC current source, and therefore the drain-source current in PMOS transistor M4, which is a copy of the drain-source current in PMOS transistor M3, is set equal to the DC bias current. Additionally, the drain-source current in primary transistor 120, which is in series with PMOS transistor M4, is set equal to the DC bias current.

[0044] In the bidirectional inverting current amplifier depicted by FIG. 1, a DC bias current enables both the upper current mirror 102 and the lower current mirror 104 to operate. The contemplated transient current is bidirectional. In the case of injection of a transient current into the input terminal 112, it can be mirrored by either the upper current mirror 102 or the lower current mirror 104 and then provided to the output terminal 114 as an output current that is an inverted version of the input transient current.

[0045] The node between NMOS transistor M1 and PMOS transistor M3 is set by an external voltage source (voltage source not shown) to a voltage that is half (1 / 2) the second supply voltage 138 (0.5VDD). The gate and drain of NMOS transistor M1 are set to 0.5VDD plus the gate-source voltage Vgs of NMOS transistor M1. The gate and drain of PMOS transistor M3 are set to 0.5VDD minus the gate-source voltage Vgs of PMOS transistor M3.

[0046] When NMOS transistor M2 is the same as NMOS transistor M1, PMOS transistor M4 is the same as PMOS transistor M3, the drain-source current of NMOS transistor M2 is equal to the drain-source current of NMOS transistor M1, and the drain-source current of PMOS transistor M4 is equal to the drain-source current of PMOS transistor M3, the gate-source voltage Vgs of NMOS transistor M1 is equal to the gate-source voltage Vgs of NMOS transistor M2, and the gate-source voltage Vgs of PMOS transistor M3 is equal to the gate-source voltage Vgs of PMOS transistor M4. Therefore, the source voltage of NMOS transistor M2 and the source voltage of PMOS transistor M4 are both set equal to 0.5VDD.

[0047] The upper stage 102 and the lower stage 104 are current mirrors that support unidirectional current output, albeit in opposite directions. The inverting current amplifier 100 includes both the upper stage 102 and the lower stage 104 to support bidirectional transient current input and output.

[0048] The upper stage 102 may also be referred to herein as the “upper current mirror 102,” and the lower stage 104 may also be referred to herein as the “lower current mirror 104.” As the transient input current to the inverting current amplifier 100 increases, the current drawn from the output terminal 114 increases, so that the upper stage 102 provides a gain of substantially −1 during current output in a first direction, and the lower stage 104 provides a gain of substantially −1 during current output in a second direction different from the first direction.

[0049] The top stage 102 includes a primary transistor 116 (also referred to as "first transistor 116"), a secondary transistor 118 (also referred to as "second transistor 118"), and a feedback loop 108 (also referred to as "upper feedback loop 108"). The primary transistor 116, the secondary transistor 118, and the feedback loop 108 of the top stage 102 provide a controlled current in the secondary transistor 118 that is an inverted copy of the current in the primary transistor 116, as discussed below. The primary transistor 116 and the secondary transistor 118 are p-type metal-oxide-semiconductor field effect transistors (PMOS).

[0050] The lower stage 104 includes a primary transistor 120 (also referred to as a "further first transistor 120"), a secondary transistor 122 (also referred to as a "further second transistor 122"), and a feedback loop 110 (also referred to as a "lower feedback loop 110"). The primary transistor 120, the secondary transistor 122, and the feedback loop 110 of the lower stage 104 provide a controlled current in the secondary transistor 122 that is an inverted copy of the current in the primary transistor 120, as discussed below. The primary transistor 120 and the secondary transistor 122 are n-type metal-oxide-semiconductor field effect transistors (NMOS).

[0051] Generally speaking, when the drain-source voltages Vds of the primary transistors 116, 120 and the secondary transistors 118, 122 are equal, the controlled current in the secondary transistors 118, 122 is a copy of the current in the primary transistors 116, 120 (the controlled current generated in the secondary transistor 118 may also be referred to as the “copy current”).

[0052] When the respective drain-source voltages Vds of the primary transistors 116, 120 and secondary transistors 118, 122 are not equal, the current in the secondary transistor 118 is not a copy of the current in the primary transistor 116.

[0053] In one or more embodiments, the ability of the inverting current amplifier 100 to accurately mirror sharp transient currents from the input terminal 112 to the output terminal 114 with a substantially (99% or greater) accurate gain of -1 is based at least in part on how quickly the respective drain-source voltages Vds of the primary transistors 116, 120 and associated secondary transistors 118, 122 are set equal by the feedback loops 108, 110, as discussed below.

[0054] The respective sources of the primary transistor 116 and the secondary transistor 118 are coupled to a first supply voltage, and the respective sources of the primary transistor 120 and the secondary transistor 122 are coupled to a second supply voltage. The first supply voltage 136 and the second supply voltage 138 are different. In one embodiment, the first supply voltage is Vdd and the second supply voltage is a common return, such as, but not limited to, ground. When the feedback loop 108 sets the voltage level at the drain of the secondary transistor 118 to be equal to the voltage level at the drain of the primary transistor 116, the respective drain-source voltages Vds of the primary transistor 116 and the secondary transistor 118 are equal. Similarly, when the feedback loop 108 sets the voltage level at the drain of the secondary transistor 122 to be equal to the voltage level at the drain of the primary transistor 120, the respective drain-source voltages Vds of the primary transistor 120 and the secondary transistor 122 are equal. Primary transistors 116, 120 remain in saturation due to their gates being tied to their drains, and since the Vgs of 116 is equal to the Vds of 116, 116 is in the same saturation state as 120.

[0055] When the respective drain-source voltages Vds of the primary transistors 116, 120 and the associated secondary transistors 118, 122 are equal, the primary transistors 116, 120 remain in saturation, and therefore the associated secondary transistors 118, 122 also remain in saturation due to obtaining the same drain-source voltage Vds.

[0056] As mentioned above, the ability of the inverting current amplifier 100 to accurately mirror a sharp transient current from the input terminal 112 to the output terminal 114 with a substantially (99% or better) accurate gain of -1 is based at least in part on how quickly the respective drain-source voltages Vds of the primary transistors 116, 120 and associated secondary transistors 118, 122 are set equal by the feedback loops 108, 110. When the feedback loops 108, 110 set the drain-source voltages Vds of the secondary transistors 118, 122 equal to the drain-source voltages Vds of the primary transistors 116, 120 for a short duration, the upper current mirror 102 and the lower current mirror 104 mirror the sharp transient current from the input terminal 112 to the output terminal 114 with a substantially (99% or better) accurate gain of -1.

[0057] The feedback loops 108, 110 include pass transistors 128, 130, operational transconductance amplifiers (OTAs) 124, 126, and controlled current sources 132, 134.

[0058] The feedback loops 108, 110 set the drain-source voltage Vds of the secondary transistors 118, 122 at least in part in response to a relationship between the voltages at the drains of the primary transistors 116, 120 and the secondary transistors 118, 122, respectively. In one or more embodiments, the relationship is the difference between the voltages at the drains of the primary transistors 116, 120 and the secondary transistors 118, 122, respectively.

[0059] The duration for setting the drain-source voltage Vds of the secondary transistors 118, 122 equal to the drain-source voltage Vds of the primary transistors 116, 120 is determined by the feedback loops 108, 110, as discussed below. The particular duration implemented is a matter of design choice and may be set based on particular operating conditions, as a non-limiting example.

[0060] Turning to the feedback loop 108 of the top stage 102, the inverting input of the OTA 124 is coupled to the drain of the secondary transistor 118. The non-inverting input of the OTA 124 is coupled to the drain of the primary transistor 116. Alternatively, the non-inverting input of the OTA 124 may be coupled to the drain of the primary transistor 116 and the inverting input of the OTA 124 may be coupled to the drain of the secondary transistor 118.

[0061] The bias input of the OTA 124 is coupled to a second supply voltage 138 via a controlled current source 132. The output of the OTA 124 is coupled to a gate of a pass transistor 128. The pass transistor 128 is coupled between the secondary transistor 118 and the output terminal 114 of the inverting current amplifier 100. The source of the pass transistor 128 is coupled to the drain of the secondary transistor 118, and the drain of the pass transistor 128 is coupled to the output terminal 114. In one or more embodiments, the controlled current source 132 may be set to provide a current with a magnitude proportional to a set value (this set value may also be referred to as a “control signal”). As discussed below, the magnitude of the current at the bias input of the OTA 124 may be utilized to set a transconductance of the OTA 124 (the “set transconductance”), which sets the bandwidth of the OTA 124.

[0062] Turning to the feedback loop 110 of the lower stage 104, the inverting input of the OTA 126 is coupled to the drain of the secondary transistor 122. The non-inverting input of the OTA 126 is coupled to the drain of the primary transistor 120. Alternatively, the non-inverting input of the OTA 126 may be coupled to the drain of the primary transistor 120 and the inverting input of the OTA 126 may be coupled to the drain of the secondary transistor 122.

[0063] A bias input of OTA 126 is coupled to a first supply voltage 136 via a controlled current source 134. An output of OTA 126 is coupled to a gate of pass transistor 130. Pass transistor 130 is coupled between secondary transistor 122 and an output terminal 114 of inverting current amplifier 100. A source of pass transistor 130 is coupled to a drain of secondary transistor 122 and a drain of pass transistor 130 is coupled to output terminal 114.

[0064] In one or more embodiments, the controlled current source 134 may be set to provide a current with a magnitude proportional to a set value (which may also be referred to as a “control signal”). As discussed below, the magnitude of the current at the bias input of the OTA 126 may be used to set the transconductance of the OTA 126 (the “set transconductance”), which sets the bandwidth of the OTA 126.

[0065] Generally speaking, a smaller magnitude of current at the bias inputs of the OTAs 124, 126 results in smaller transconductance and smaller bandwidth, as well as current savings. A larger magnitude of current at the bias inputs of the OTAs 124, 126 results in larger transconductance and larger bandwidth, but at a higher current cost.

[0066] In one or more embodiments, the voltage sources providing the first supply voltage 136 and the second supply voltage 138 are different. The first supply voltage 136 sets the voltage at the source of each of the primary transistor 116 and the secondary transistor 118 to the same voltage level and sets the direction of the current generated by the controlled current source 134. The second supply voltage 138 sets the voltage at the source of each of the primary transistor 120 and the secondary transistor 122 to the same voltage level and sets the direction of the current generated by the controlled current source 132. In the specific non-limiting embodiment illustrated by FIG. 1, the voltage source providing the second supply voltage 138 is a zero or ground voltage source and the voltage source providing the first supply voltage 136 is a non-zero voltage source.

[0067] Generally speaking, the OTAs 124, 126 are voltage controlled current sources that generate output currents at least in part in response to a differential input voltage received at their inverting and non-inverting inputs. The outputs of the OTAs 124, 126 provide currents to the gates of the pass transistors 128, 130, providing currents that charge or discharge the gate caps of the pass transistors, converting them into gate voltages.

[0068] The magnitude of the gate voltage at the pass transistors 128, 130 affects the conduction of the pass transistors 128, 130, which means that the voltage level at the source of the pass transistors 128, 130 can be changed via the magnitude of the gate voltage. For a PMOS pass transistor 128, increasing the gate voltage decreases the conductance and decreasing the gate voltage increases the conductance. For a PMOS pass transistor 128, a higher gate voltage sets a lower conductance than a lower gate voltage. For an NMOS pass transistor 130, increasing the gate voltage increases the conductance and decreasing the gate voltage decreases the conductance. For an NMOS pass transistor 130, a lower gate voltage sets a lower conductance than a higher gate voltage. Turning to the control of the drain-source voltages of the primary transistors 116, 120 and secondary transistors 118, 122, if the respective voltages at the inverting and non-inverting inputs of the OTAs 124, 126 are different (this is an abrupt voltage generation as opposed to a fast transient or voltage spike at 112), the OTAs 124, 126 will increase or decrease their output current, which will change the gate voltage of the pass transistors 128, 130, which will change the voltage level at the source of the pass transistors 128, 130, which will change the drain voltage of the secondary transistors 118, 122. The OTAs 124, 126 will accept the changed drain voltage of the secondary transistors 118, 122 and will continue to increase or decrease their output current until the drain voltage of the primary transistors 116, 120 is equal to the drain voltage of the secondary transistors 118, 122. The OTAs 124 , 126 stop modifying their output current when the drain voltages of the primary transistors 116 , 120 equal the drain voltages of the secondary transistors 118 , 122 .

[0069] As discussed below, the non-inverting input of OTA 124 monitors the drain voltage of primary transistor 116, the inverting input of OTA 124 monitors the drain voltage of secondary transistor 118, the non-inverting input of OTA 126 monitors the source voltage of primary transistor 120, and the inverting input of OTA 126 monitors the source voltage of secondary transistor 122.

[0070] Generally speaking, the duration over which the feedback loops 108, 110 set the drain voltages of the secondary transistors 118, 122 via the OTAs 124, 126 in response to the voltage difference between the inverting / non-inverting inputs of the OTAs 124, 126 is referred to herein as the “responsiveness” of the feedback loops 108, 110.

[0071] The "unity gain bandwidth" (or simply "bandwidth") of the OTA 124, 126 is the range of frequencies at which the OTA 124, 126 can accurately amplify signals, which may also be characterized as the frequency at which the gain falls below a threshold. The unity gain bandwidth may be expressed as a range of frequencies, also referred to as "width." In the case of abrupt changes in the voltage difference at the input of the OTA 124, 126, if the frequency of the input voltage signal is not within the unity gain bandwidth of the OTA 124, 126, the OTA 124, 126 may produce an inaccurate or unpredictable output current for the input voltage signal.

[0072] The "transconductance" of the OTAs 124, 126 is a characteristic of their ability to convert an input voltage signal into an output current signal. The transconductance of the OTAs 124, 126 is based at least in part on the transconductance of the input transistors of the OTAs 124, 126 (input transistors not shown), which is set by the magnitude of the current at the bias input of the OTAs 124, 126. The unity gain bandwidth of the OTAs 124, 126 can be expressed as the transconductance of the input transistors of the OTAs 124, 126 divided by the gate capacitance of the pass transistors 128, 130, i.e., unity gain bandwidth = Gm / Cload, where Gm is the input transistor transconductance and Cload is the load of the OTA, which in FIG. 1 is the gate capacitor of the pass transistor. Generally speaking, the higher the transconductance of the OTAs 124, 126, the wider the unity gain bandwidth of the OTAs 124, 126.

[0073] The transconductance of the OTAs 124, 126 is based at least in part on the magnitude of a current received at the bias input of the OTAs 124, 126. The current received at the bias input of the OTAs 124, 126 is utilized to bias an input stage (e.g., but not limited to, an input differential pair of transistors (e.g., but not limited to, bipolar junction transistors (BJTs)) or metal-oxide-semiconductor-field-effect transistors (MOSFETs)) of the OTAs 124, 126. Generally speaking, the higher the bias current, the higher the transconductance, the higher the unity gain bandwidth, and the wider the bandwidth.

[0074] The transconductance of the OTAs 124, 126 changes in response to changing the magnitude of the current received at the bias input of the OTAs 124, 126. Thus, the transconductance of the OTAs 124, 126 may be set via the current at the bias input of the OTAs 124, 126, and thus the bandwidth of the OTAs 124, 126 may be set via the current at the bias input of the OTAs 124, 126. As discussed below, the current at the bias input of the OTAs 124, 126 of the inverting current amplifier 100 may be set by the controlled current sources 132, 134, and thus may be changed by setting the magnitude (i.e., amplitude) of the current generated by the controlled current sources 132, 134.

[0075] The controlled current sources 132, 134 may be utilized to tune or set the bandwidth of the OTAs 124, 126. The controlled current sources 132, 134 may also be referred to herein as "tuning current sources 132, 134" when tuning the bandwidth of the OTAs 124, 126, or as "controlled current sources 132, 134" when setting the bandwidth of the OTAs 124, 126 (e.g., but not limited to, setting the transconductance to a predetermined value corresponding to a desired transconductance / bandwidth). Increasing the magnitude of the current generated by the controlled current sources 132, 134 increases the bandwidth of the OTAs 124, 126 to be higher, and decreasing the current amplitude of the current generated by the controlled current sources 132, 134 decreases the bandwidth of the OTAs 124, 126 to be lower.

[0076] The controlled current sources 132, 134 support a wide tuning bandwidth of the input transient current amplitude at the OTAs 124, 126 versus the input terminal 112, with larger input transient current amplitudes requiring larger bandwidths and smaller input transient current amplitudes requiring smaller bandwidths.

[0077] The voltage at the non-inverting input of the OTAs 124, 126 is forced to be equal to the voltage at the inverting input of the OTAs 124, 126 by a feedback loop that includes the gates of the pass transistors 128, 130. The faster the voltages at the inverting and non-inverting inputs of the OTAs 124, 126 are set equal (in time), the faster the drain-source voltages Vds of the primary transistors 116, 120 and secondary transistors 118, 122 are set equal (in time), and the more accurately the upper stage 102, lower stage 104, or, more generally, the inverting current amplifier 100, provides an output current with a gain of -1.

[0078] Thus, the accuracy of the inverting current amplifier 100 is proportional to the responsiveness of the feedback loop that includes the OTAs 124, 126 (or more generally, the responsiveness of the feedback loops 108, 110 that include the OTAs 124, 126). Transient signals exhibit abrupt changes in amplitude with short durations that can be tracked by an appropriately responsive feedback loop. The responsiveness of the feedback loop is set by the unity gain bandwidth of the OTAs 124, 126, and thus, as discussed above, the controlled current sources 132, 134 control the transconductance of the OTAs 124, 126, which controls the bandwidth of the OTAs 124, 126, which controls the responsiveness of the feedback loop that includes the OTAs 124, 126, and thus the responsiveness of the feedback loops 108, 110.

[0079] The relationship between the drain-source current Ids and the gate-source voltage Vgs is Ids=k * (Vgs-Vth)^2(1+λ *Vds), where k is a transconductance parameter, λ is a channel modulation parameter, Vds is the drain-source voltage, Vgs is the gate-source voltage, and Vth is the threshold voltage for turning the transistor on or off. An equation for the drain-source current Ids is included here to mathematically illustrate that if Vds is not equal in the primary transistors 116, 120 and the secondary transistors 118, 122, the respective drain-source currents Ids will be different and therefore will not be mirrored properly.

[0080] Once the bandwidth of the OTA 124, 126 is set, it can be adapted to a transient current at the input terminal 112 that corresponds to the set bandwidth. The duration of the transient current is proportional to the baseline capacitance of the touchscreen. A large touchscreen with a large baseline capacitance can experience a fast transient current and cause a fast transient current at the input terminal 112. A small touchscreen with a small baseline capacitance can experience a slower transient current and cause a slower transient current at the input terminal 112. In one or more embodiments, the bandwidth of the OTA 124, 126 can be set based at least in part on the size (dimension) of the touchscreen with which it is used or the capacitance of the touchscreen. For example, the bandwidth of the OTA 124 can be set in proportion to the touchscreen size, i.e., as the touchscreen size increases, the set bandwidth of the OTA 124 can increase. In addition to or instead of the dimension, in one or more embodiments, the bandwidth of the OTA 124, 126 can be tuned for a specific touchscreen or class of touchscreens.

[0081] In one or more embodiments, the bandwidth of the OTAs 124, 126 may be set according to a coarse and fine setup process, as a non-limiting example, according to the touchscreen or class of touchscreen to be utilized. In one or more embodiments, the fine selection of the bandwidth of the OTAs 124, 126 may be set according to a real-time testing procedure, such as, but not limited to, by sweeping the tuning controlled current sources 132, 134 in one or more small steps in current amplitude until an acceptable bandwidth is obtained.

[0082] In one or more embodiments, the bandwidth of OTA124, OTA126 may be tuned or pre-set to a bandwidth less than the maximum available bandwidth of OTA124, OTA126, in some cases, to conserve power or current, by way of non-limiting example.

[0083] Notably, inverting current amplifier 100 is not limited to applications where neither fast transient currents injected at the input nor voltage spikes caused thereby are expected or possible. Inverting current amplifier 100 may be utilized in applications where fast transient currents or voltage spikes are not expected, which is specifically contemplated. Broad applicability is a non-limiting example of an advantage of an inverting current amplifier according to one or more embodiments discussed herein.

[0084] 2 is a schematic diagram illustrating an inverting current amplifier portion 200 corresponding to the first upper stage 102 of the inverting current amplifier 100. FIG 2 illustrates some of the voltages and currents discussed above. The inverting current amplifier portion 200 includes a first transistor 202, a second transistor 204, and a feedback loop 214. The feedback loop 214 includes an OTA 220 having a set transconductance ("set gm").

[0085] The respective source voltages of the source 208 of the first transistor 202 and the source 210 of the second transistor 204 are set to a voltage Vs, and a feedback loop 214 sets the respective drain voltages of the drain 206 of the first transistor 202 and the drain 212 of the second transistor 204 to the same voltage level Vd. When the respective drain-source voltages of the first transistor 202 and the second transistor 204 are equal (both Vds), a controlled current 218 in the second transistor 204 is generated, which is a copy of the current 216 in the first transistor 202.

[0086] 3 is a flow diagram illustrating a process 300 for inverting a current signal according to one or more embodiments. One or more operations of the process 300 may be performed by the inverting current amplifier 100, as a non-limiting example.

[0087] Although the exemplary process 300 depicts a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order without substantially affecting the functionality of the process 300. In other examples, different components of an exemplary device or system implementing the process 300 may perform functions substantially simultaneously or in a particular order.

[0088] According to one or more embodiments, the process 300 includes, in operation 302, setting the drain voltages of the first transistor and the second transistor to be substantially equal using an operational transconductance amplifier having a set bandwidth.

[0089] According to one or more embodiments, the process 300 includes, at operation 304, providing a controlled current in the second transistor that is an inverted copy of the current in the first transistor when the respective drain-source voltages of the first transistor and the second transistor are substantially equal.

[0090] 4 and 5 are block diagrams illustrating an apparatus 400 for canceling a baseline cap Q received from a touch electrode, in accordance with one or more embodiments. When the apparatus 400 is included with a touch sensor, the apparatus 400 may be referred to as a "touch sensor unit 400."

[0091] The apparatus 400 includes a first amplifier circuit 434 and a second amplifier circuit 436. The first amplifier circuit 434 includes an electrode 402, a current amplifier 404, an inverting current amplifier 406, and a summer 408. The second amplifier circuit 436 includes an electrode 410, a current amplifier 412, an inverting current amplifier 414, and a summer 416. The electrode 402 and the electrode 410 are depicted within the first amplifier circuit 434 and the second amplifier circuit 436, respectively, for ease of illustration and should be considered optional elements of the first amplifier circuit 434 and the second amplifier circuit 436, as they are coupled to provide an input current 418 and an input current 426 to the first amplifier circuit 434 and the second amplifier circuit 436, respectively.

[0092] When generated in response to a touch measurement process, input current 418 and input current 426 are current signals, and the currents may include a component charge representing a baseline signal (a “first component charge”) and a component charge representing a touch signal (a “second component charge”).

[0093] The first amplifier circuit 434 and the second amplifier circuit 436 are current amplifier circuits, and more specifically, current differential amplifier circuits. The first amplifier circuit 434 and the second amplifier circuit 436 amplify the input current 418 and the input current 426, respectively, to generate the output current 422 and the output current 432, respectively, as discussed below. The gain of each of the first amplifier circuit 434 and the second amplifier circuit 436 may be programmable and may be set, as a non-limiting example, to generate the output current 422 and the output current 432 within the operating range of a touch measurement circuit (touch measurement circuit not shown).

[0094] Electrode 402 and electrode 410 exhibit substantially the same baseline cap in response to the capacitance measurement process. When unaffected by an object, electrode 402 and electrode 410 exhibit a capacitance equal to the baseline cap. When affected by an object, such as, but not limited to, a hovering finger depicted in FIG. 4, electrode 402 and electrode 410 exhibit a capacitance equal to the sum of the baseline cap and the projected cap. In the specific embodiment depicted by FIG. 4, electrode 402 exhibits a capacitance equal to the sum of the baseline cap and the projected cap (due to the hovering finger) and electrode 410 exhibits a capacitance equal to the baseline cap (no hovering finger or other object present).

[0095] Turning to the second amplifier circuit 436, when generated in response to a touch measurement process, the input current 426 includes only a baseline Q. Thus, when generated in response to a touch measurement process, the input current 426 is a current signal and includes a component charge representing the baseline signal. The component charge representing the touch signal is equal to zero or is absent (nonexistent or negligible) in the input current 426.

[0096] Current amplifier 412 amplifies the current signal received at its input (by adding or subtracting charge to increase the amplitude of the current signal in a predictable manner, or (in the case of a partial gain amplifier) ​​to decrease the amplitude of the current signal in a predictable manner) and provides an amplified current signal at its output, where current amplifier 412 accepts input current 426 and provides amplified input current 428. The baseline Q signal is present in amplified input current 428 in the same proportion as it was present in input current 426.

[0097] The output of the current amplifier 412 is coupled to an input of an inverting current amplifier 414 and to an input of a summer 416. A further input of the summer 416 is coupled to the output of an inverting current amplifier 406 of a first amplifier circuit 434, discussed below.

[0098] Inverting current amplifier 414 inverts the current signal received at its input and provides an inverted (i.e., reversed in polarity) current signal at its output. In one or more embodiments, inverting current amplifier 414 is or includes inverting current amplifier 100 of FIG. 1. Inverting current amplifier 414 is controlled by a control signal 440, which may represent a current generated by a current source (e.g., but not limited to, controlled current sources 132, 134) or a gain setting that controls the magnitude of the current generated by the current source. In either case, the gain of inverting current amplifier 414 is set by control signal 440.

[0099] Here, inverting current amplifier 414 accepts an amplified input current 428 and provides an inverted current 430. Inverting the amplified input current 428 also inverts (reverses polarity) the baseline Q signal present in the amplified input current 428 such that the baseline Q signal is present in the inverted current 430.

[0100] An output of the inverting current amplifier 414 is coupled to an input of a summer 408. A further input of the summer 408 is coupled to an output of the current amplifier 404 of the first amplifier circuit 434.

[0101] Turning to the first amplifier circuit 434, when generated in response to a touch measurement process, the input current 418 includes a baseline Q and a touch Q. Thus, when generated in response to a touch measurement process, the input current 418 is a current signal and includes a component charge representative of the touch signal and an additional component charge representative of the baseline signal.

[0102] Current amplifier 404 amplifies the current signal received at its input (by adding or subtracting charge to increase the amplitude of the current signal in a predictable manner, or (in the case of a partial gain amplifier) ​​decrease the amplitude of the current signal in a predictable manner) and provides an amplified current signal at its output, where current amplifier 404 accepts input current 418 and provides amplified input current 420. The baseline Q signal and touch Q signal are present in amplified input current 420 in the same proportions that they were present in input current 418.

[0103] The output of the current amplifier 404 is coupled to an input of an inverting current amplifier 406 and to an input of a summer 408. As discussed above, a further input of the summer 408 is coupled to the output of an inverting current amplifier 414 of the second amplifier circuit 436.

[0104] The inverting current amplifier 406 inverts the current signal received at its input and provides an inverted (i.e., reversed in polarity) current signal at its output. In one or more embodiments, the inverting current amplifier 406 is or includes the inverting current amplifier 100 of FIG. 1. The inverting current amplifier 406 is controlled by a control signal 438, which may represent a current generated by a current source (e.g., but not limited to, controlled current sources 132, 134) or a gain setting that controls the magnitude of the current generated by the current source. In either case, the gain of the inverting current amplifier 406 is set by a control signal 440.

[0105] A summer 408 sums the current signal received at its input and the sum of the input signals at its output, where the summer 408 receives an inverted current 430 including the baseline Q signal provided by an inverting current amplifier 414, and an amplified input current 420 including the baseline Q signal and the touch Q signal provided by a current amplifier 420. The summer 408 combines (sums) the amplified input current 420 and the inverted current 430, and because the inverted current 430 is of opposite polarity to the amplified input current 420, the summer 408 effectively subtracts the amplified input current 428 from the amplified input current 420. The baseline Q signal present in the inverted current 430 cancels the baseline Q signal present in the amplified input current 420. Thus, the output current 422 includes the touch Q signal but not the baseline Q signal.

[0106] Similarly, summer 416 combines (adds) inverting current 424 and amplified input current 428, where inverting current 424 comprises the baseline Q signal provided by inverting current amplifier 406 and amplified input current 428 provided by current amplifier 428 comprises the baseline Q signal, which cancel each other. Thus, output current 432 includes the touch Q signal but not the baseline Q signal, which is now the negative touch Q signal, which is taken as a null signal in the measurement system.

[0107] Because the inverting current amplifier 406 of the first amplifier circuit 434 and the inverting current amplifier 414 of the second amplifier circuit 436 each exhibit a gain of substantially -1 (with an accuracy of 99% or better), the first amplifier circuit 434 can cancel the baseline Q signal and provide an output current 422 that does not include the baseline Q signal and includes substantially only the touch Q signal.

[0108] FIG. 5 illustrates the apparatus 400, but with a baseline Q and a projection Q instead of the current signals illustrated in FIG.

[0109] FIG. 6 is a flow diagram illustrating a process 600 for setting the bandwidth of an OTA in a feedback loop utilized in an inverting current amplifier 100, in accordance with one or more embodiments.

[0110] Although the exemplary process 600 depicts a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order without substantially affecting the functionality of the process 600. In other examples, different components of an exemplary device or system implementing the process 600 may perform functions substantially simultaneously or in a particular order.

[0111] According to one or more embodiments, the process 600 includes, at operation 602, sweeping a current generated by a tuning current source coupled to a bias input of the OTA in a stepwise increase or decrease. In one or more embodiments, the amplitude of the current generated by the current source is swept in a stepwise increase or decrease. In one or more embodiments, the OTA is in a feedback loop to control the drain-source voltage of the secondary transistor to generate a copy of the current in the primary transistor in the secondary transistor.

[0112] According to one or more embodiments, the process 600 includes, in operation 604, observing one or more of a bandwidth or a transconductance of the OTA while sweeping the current generated by the current source.

[0113] According to one or more embodiments, process 600 includes setting a current source to a current corresponding to one or more of an observed predetermined bandwidth or an observed predetermined transconductance in operation 606. The observed predetermined bandwidth is the bandwidth observed in operation 604 that is greater than or equal to a predetermined value for the bandwidth. The observed predetermined transconductance is the transconductance observed in operation 604 that is greater than or equal to a predetermined value for the transconductance.

[0114] FIG. 7 is a flow diagram illustrating a process 700 for setting the bandwidth of an OTA in a feedback loop utilized in an inverting current amplifier 100, in accordance with one or more embodiments.

[0115] Although the exemplary process 700 depicts a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order without substantially affecting the functionality of the process 700. In other examples, different components of an exemplary device or system implementing the process 700 may perform functions substantially simultaneously or in a particular order.

[0116] According to one or more embodiments, the process 700 includes, at operation 702, sweeping a current generated by a current source coupled to a bias input of the OTA in a stepped up or down manner. In one or more embodiments, the amplitude of the current generated by the current source is swept up or down in a stepped manner. In one or more embodiments, the OTA is in a feedback loop to control the drain-source voltage of the secondary transistor to generate a copy of the current in the primary transistor in the secondary transistor.

[0117] According to one or more embodiments, the process 700 includes, in operation 704, observing an output signal of an inverting current amplifier while sweeping the current generated by the current source.

[0118] According to one or more embodiments, the process 700 includes setting the current source to a current that corresponds to the minimum observed output signal.

[0119] FIG. 8 is a flow diagram illustrating a process 800 for determining the state of electrodes of a capacitive sensor including canceling a baseline charge signal from a measured charge signal, in accordance with one or more embodiments.

[0120] Although the exemplary process 800 depicts a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order without substantially affecting the functionality of the process 800. In other examples, different components of an exemplary device or system implementing the process 800 may perform functions substantially simultaneously or in a particular order.

[0121] According to one or more embodiments, process 800 includes receiving a measured charge signal from a first electrode and a measured charge signal from a second electrode in response to a capacitance measurement process, at operation 802. The first electrode and the second electrode are adjacent electrodes.

[0122] According to one or more embodiments, the process 800 includes, at operation 804, generating inverted versions of the measured charge signal from the first electrode and the measured charge signal from the second electrode.

[0123] According to one or more embodiments, process 800 includes, at operation 806, obtaining a touch charge signal for the second electrode by combining an inverted version of the measured charge signal from the first electrode with the measured charge signal from the second electrode.

[0124] According to one or more embodiments, process 800 includes, at operation 808, obtaining a touch charge signal for the first electrode by combining an inverted version of the measured charge signal from the second electrode with the measured charge signal from the first electrode.

[0125] According to one or more embodiments, process 800 includes, at operation 810, detecting a state of the first electrode at least in part in response to the touch charge signal for the first electrode, and optionally detecting a state of the second electrode at least in part in response to the touch charge signal for the second electrode. In one or more embodiments, the detected state of the first electrode or the second electrode may include contact (i.e., a touch event) or non-contact (i.e., a no-touch event).

[0126] 9 is a block diagram illustrating a system 900 for sensing touch via capacitance in accordance with one or more embodiments. System 900 may be referred to herein as a “capacitive touch sensing system 900.”

[0127] The system 900 includes a capacitance sensor 902 , a differential amplifier circuit 904 , and a capacitance measurement circuit 906 .

[0128] The capacitance sensor 902 is or includes rows and columns of touch electrodes. Each electrode of the capacitance sensor 902 generates a measured charge signal at least in part in response to a capacitance measurement process. When operations of such a capacitance measurement process are performed, a measured charge signal is generated by the capacitance sensor 902 that has a known or predetermined relationship to the capacitance of the electrodes of the capacitance sensor 902. The measured charge signal can be read or processed to determine the capacitance of the electrodes of the capacitance sensor 902 and to determine the state of the capacitance sensor 902, as discussed above.

[0129] 4 or 5 (e.g., but not limited to, the first amplifier circuit 434 or the second amplifier circuit 436). The differential amplifier circuit 904 receives the measured charge signal from the capacitive sensor 902 and generates a modified measured charge signal that is provided to the capacitance measurement circuit 906. More specifically, the differential amplifier circuit 904 receives the first measured charge signal 908 and the second measured charge signal 910 and combines them as discussed above to cancel baseline signals present in the first measured charge signal 908 and the second measured charge signal 910 and obtain a modified first measured charge signal 912 and a modified second measured charge signal 914. Thus, the modified first measured charge signal 912 and the modified second measured charge signal 914 include only the touch signal present in the first measured charge signal 908 and the second measured charge signal 910.

[0130] The capacitance measurement circuit 906 is a logic circuit that controls the capacitance measurement process via a capacitance measurement process control signal 916 to cause the capacitance sensor 902 to generate measured charge signals, such as first measured charge signal 908 and second measured charge signal 910, and modified measured charge signals, such as modified first measured charge signal 912 and modified second measured charge signal 914. The capacitance measurement circuit 906 processes the modified first measured charge signal 912 and the modified second measured charge signal 914 in order to measure the capacitance experienced by the capacitance sensor 902, at least in part in response to one or more of the modified first measured charge signal 912 and the modified second measured charge signal 914.

[0131] The terms used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to", the term "having" should be interpreted as "having at least", the term "includes" should be interpreted as "includes, but is not limited to", etc.).

[0132] Additionally, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, such intent does not exist. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce the recitation of claims. However, the use of such phrases should not be construed as limiting any particular claim that includes such introduced claim recitation to embodiments that include only one such recitation, even if the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "one(a)" or "one(an)" (e.g., "one(a)" and / or "one(an)" should be construed to mean "at least one" or "one or more"). The same applies to the use of express articles used to introduce claim recitations.

[0133] In addition, even if a specific number of an introduced claim recitation is explicitly recited, one of ordinary skill in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the explicit recitation of "two recitations" without other modifiers means at least two recitations or more than two recitations). Furthermore, when a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, it is generally intended that such a structure include A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together.

[0134] Additionally, any disjunction or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B." As used herein, "each" means a part or a whole. As used herein, "each and all" means the whole.

[0135] In this description, characterizations such as "typical," "conventional," or "known" do not necessarily mean that the discussed aspects are disclosed in the prior art or that they are understood in the prior art. Nor do they necessarily mean that they are widely known, well understood, or routinely used in the relevant field. Such characterizations should be understood to mean "known to the inventors of the present disclosure."

[0136] Further non-limiting examples of the present disclosure are as follows. Example 1: An apparatus comprising: a first transistor and a second transistor for providing a controlled current in the second transistor that is a copy of the current in the first transistor when the respective drain-source voltages of the first transistor and the second transistor are substantially equal; and a feedback loop for setting the respective drain-source voltages of the first transistor and the second transistor to be substantially equal, the responsiveness of the feedback loop being proportional to a set transconductance of an operational transconductance amplifier (OTA) in the feedback loop.

[0137] Example 2: The apparatus of example 1, wherein the feedback loop comprises a pass transistor and an OTA, the OTA utilizing an output voltage generated by the OTA to set the drain-source voltage of the pass transistor.

[0138] Example 3: The apparatus of examples 1 and 2, wherein the OTA sets the drain-source voltage of the pass transistor at least in part in response to a relationship between the voltages at the drains of the first transistor and the second transistor.

[0139] Example 4: An apparatus as described in Examples 1 to 3, wherein one of the inverting input or the non-inverting input of the OTA receives the drain voltage of the first transistor, and the other of the inverting input or the non-inverting input of the OTA receives the drain voltage of the second transistor.

[0140] Example 5: The apparatus of examples 1-4, wherein the feedback loop comprises a controlled current source coupled to a bias input of the OTA.

[0141] Example 6: The apparatus of any one of examples 1 to 5, wherein the controlled current source is a variable current source that produces a current proportional to a control signal.

[0142] Example 7: The apparatus of any one of Examples 1 to 6, further comprising a further first transistor and a further second transistor for providing a controlled current in the further second transistor that is a copy of the current in the further first transistor when the respective drain-source voltages of the further first transistor and the further second transistor are substantially equal; a further feedback loop for setting the respective source voltages of the further first transistor and the further second transistor to be substantially equal; and a translinear loop for providing a DC bias current to the first transistor and the further first transistor.

[0143] Example 8: A device as described in examples 1 to 7, wherein the further first transistor and the further second transistor provide a controlled current in the further second transistor at least partially in response to an input current received at an input terminal of the device exhibiting a first current direction, and the first transistor and the second transistor provide a controlled current in the second transistor at least partially in response to an input current received at an input terminal of the device exhibiting a second current direction, the second current direction being different from the first current direction.

[0144] Example 9: A device according to any one of examples 1 to 8, wherein the first transistor and the second transistor are PMOS transistors and the further first transistor and the further second transistor are NMOS transistors.

[0145] Example 10: A device as described in examples 1 to 9, wherein a source of each of the first transistor and the second transistor receives a first supply voltage and a source of each of the further first transistor and the further second transistor receives a second supply voltage, the first supply voltage and the second supply voltage being different.

[0146] Example 11: An apparatus comprising: a first current amplification circuit for receiving an input current from a first touch electrode; and a second current amplification circuit for receiving an input current from a second touch electrode, wherein the first current amplification circuit comprises a current amplifier for amplifying the input current received from the first touch electrode, an inverting current amplifier for inverting the amplified input current with a gain ≧(−0.99), and an adder for combining the amplified input current generated in the second current amplification circuit and the inverted amplified input current.

[0147] Example 12: The device described in Example 11, wherein the second current amplifier circuit includes a corresponding current amplifier for amplifying an input current received from the second touch electrode, a corresponding inverting current amplifier for inverting the amplified input current, and a corresponding summer for combining the amplified input current generated in the first current amplifier circuit and the inverted amplified input current.

[0148] Example 13: The apparatus described in Examples 11 and 12, wherein the inverting current amplifier of the first current amplification circuit comprises a first transistor and a second transistor for providing a controlled current in the second transistor that is a copy of the current in the first transistor when the respective drain-source voltages of the first transistor and the second transistor are substantially equal, and a feedback loop for setting the respective drain-source voltages of the first transistor and the second transistor to be substantially equal.

[0149] Example 14: The apparatus of examples 11-13, wherein the transconductance feedback loop comprises an operational amplifier (OTA) having a controlled bandwidth.

[0150] Example 15: The device according to Examples 11 to 14, wherein the responsiveness of the feedback loop is proportional to the set bandwidth of the OTA.

[0151] Example 16: The apparatus of any one of examples 11 to 15, wherein the bandwidth of the inverting current amplifier of the first current amplification circuit is set by a control signal.

[0152] Example 17: A device as described in Examples 11 to 16, wherein a first component charge of the current from the first touch electrode is proportional to the self-capacitance of the first touch electrode, and a second component charge of the current from the first touch electrode is proportional to the projected capacitance of the first touch electrode.

[0153] Example 18: A device as described in Examples 11 to 17, wherein a first component charge of the current from the second touch electrode is proportional to the self-capacitance of the second touch electrode, and a second component charge of the current from the second touch electrode is proportional to the projected capacitance of the second touch electrode.

[0154] Example 19: An apparatus as described in Examples 11 to 18, comprising a first transistor and a second transistor for providing a controlled current in the second transistor that is a copy of the current in the first transistor when the respective drain-source voltages of the first transistor and the second transistor are substantially equal, and a feedback loop for setting the respective drain-source voltages of the first transistor and the second transistor to be substantially equal, the responsiveness of the feedback loop being proportional to the setting bandwidth of an OTA of the feedback loop.

[0155] Example 20: The apparatus of Examples 11-19, wherein the first touch electrode and the second touch electrode each generate a current indicative of their respective capacitance at least partially in response to a capacitance measurement process.

[0156] Example 21: A method comprising: receiving a measured charge signal from a first electrode and a measured charge signal from a second electrode in response to a capacitance measurement process; generating inverted versions of the measured charge signal received from the first electrode and the measured charge signal from the second electrode; obtaining a touch charge signal for the second electrode by combining the inverted version of the measured charge signal from the first electrode with the measured charge signal from the second electrode; and detecting a state of the first electrode at least in part in response to the touch charge signal for the first electrode.

[0157] Example 22: The method of Example 21, comprising: obtaining a touch charge signal for the first electrode by combining an inverted version of the measured charge signal from the second electrode with the measured charge signal from the first electrode; and detecting a state of the second electrode at least in part in response to the touch charge signal for the second electrode.

[0158] Example 23: The method described in Examples 21 and 22, wherein the step of generating an inverted version of the measured charge signal received from the first electrode and the measured charge signal from the second electrode includes a step of generating an inverted version of the measured charge signal received from the first electrode and the measured charge signal from the second electrode via an inverting current amplifier.

[0159] Example 24: The method described in Examples 21 to 23, wherein the inverting current amplifier comprises a first transistor and a second transistor for providing a controlled current in the second transistor that is a copy of the current in the first transistor when the respective drain-source voltages of the first transistor and the second transistor are substantially equal, and a feedback loop for setting the respective drain-source voltages of the first transistor and the second transistor to be substantially equal.

[0160] Example 25: The method of any one of examples 21 to 24, wherein the feedback loop comprises an operational transconductance amplifier (OTA), the OTA having a transconductance that is configurable via a bias input of the OTA.

[0161] Example 26: A method comprising: utilizing an operational transconductance amplifier (OTA) having a setting bandwidth to set respective drain voltages of a first transistor and a second transistor to be substantially equal; and providing a controlled current in the second transistor that is a copy of the current in the first transistor when the respective drain-source voltages of the first transistor and the second transistor are substantially equal.

[0162] Example 27: A method as described in Example 26, comprising the steps of: sweeping a current generated by a tuning current source coupled to a bias input of the OTA to increase or decrease in steps; observing one or more of the bandwidth or transconductance of the OTA while sweeping the current generated by the current source; and setting the current source to a current corresponding to one or more of the observed predetermined bandwidth or observed predetermined transconductance.

[0163] Example 28: A method as described in Examples 26 and 27, comprising: sweeping a current generated by a current source coupled to a bias input of the OTA to increase or decrease in steps; observing an output signal based at least in part on the controlled current in the second transistor while sweeping the current generated by the current source; and setting the current source to a current corresponding to the minimum observed output signal.

[0164] While this disclosure includes certain illustrated embodiments, those skilled in the art will recognize and understand that the invention is not so limited. Rather, numerous additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the invention as claimed below along with their legal equivalents. In addition, features of one embodiment can be combined, as contemplated by the inventor, with features of other disclosed embodiments and still fall within the scope of the present disclosure.

Claims

1. An apparatus comprising: a first transistor and a second transistor for providing a controlled current in the second transistor that is a copy of a current in the first transistor when respective drain-source voltages of the first transistor and the second transistor are substantially equal; a feedback loop for setting the respective drain-source voltages of the first transistor and the second transistor to be substantially equal, the responsiveness of the feedback loop being proportional to a set transconductance of an operational transconductance amplifier (OTA) of the feedback loop.

2. The feedback loop comprises: A pass transistor; 2. The apparatus of claim 1, further comprising: an OTA configured to utilize an output voltage generated by the OTA to set a drain-source voltage of the pass transistor.

3. 3. The apparatus of claim 2, wherein the OTA sets the drain-source voltage of the pass transistor at least in part in response to a relationship between voltages at the drains of the first and second transistors.

4. 3. The apparatus of claim 2, wherein one of the inverting or non-inverting input of the OTA receives a drain voltage of the first transistor, and the other of the inverting or non-inverting input of the OTA receives a drain voltage of the second transistor.

5. The feedback loop comprises: The apparatus of claim 2 comprising a controlled current source coupled to a bias input of the OTA.

6. 6. The apparatus of claim 5, wherein the controlled current source is a variable current source that produces a current proportional to a control signal.

7. a further first transistor and a further second transistor for providing the controlled current in the further second transistor which is a copy of the current in the further first transistor when the respective drain-source voltages of the further first transistor and the further second transistor are substantially equal; a further feedback loop for setting the respective source voltages of the further first transistor and the further second transistor to be substantially equal; 2. The apparatus of claim 1, further comprising: a translinear loop for providing a DC bias current to the first transistor and the further first transistor.

8. 8. The device of claim 7, wherein the further first transistor and the further second transistor provide the controlled current in the further second transistor at least in part in response to an input current received at an input terminal of the device exhibiting a first current direction, and the first transistor and the second transistor provide the controlled current in the second transistor at least in part in response to an input current received at the input terminal of the device exhibiting a second current direction, the second current direction being different from the first current direction.

9. the first transistor and the second transistor are PMOS transistors; 9. The apparatus of claim 8, wherein the further first transistor and the further second transistor are NMOS transistors.

10. 10. The apparatus of claim 9, wherein a respective source of the first transistor and the second transistor receives a first supply voltage and the respective sources of the further first transistor and the further second transistor receive a second supply voltage, the first supply voltage and the second supply voltage being different.

11. An apparatus comprising: a first current amplifier circuit for receiving an input current from the first touch electrode; a second current amplifier circuit for receiving an input current from the second touch electrode; The first current amplifier circuit includes: a current amplifier for amplifying the input current received from the first touch electrode; an inverting current amplifier for inverting the amplified input current with a gain ≧(−0.99); a summer for combining the amplified input current produced in the second current amplifier circuit and an inverted amplified input current.

12. The second current amplifier circuit includes: a corresponding current amplifier for amplifying the input current received from the second touch electrode; a corresponding inverting current amplifier for inverting the amplified input current; 12. The apparatus of claim 11, further comprising: a corresponding summer for combining the amplified input current produced in the first current amplifier circuit and the inverted amplified input current.

13. The inverting current amplifier of the first current amplifier circuit comprises: a first transistor and a second transistor for providing a controlled current in the second transistor that is a copy of a current in the first transistor when respective drain-source voltages of the first transistor and the second transistor are substantially equal; a feedback loop for setting the respective drain-source voltages of the first and second transistors to be substantially equal.

14. The feedback loop comprises:

14. The apparatus of claim 13, comprising an operational transconductance amplifier (OTA) having a controlled bandwidth.

15. The apparatus of claim 14 , wherein the responsiveness of the feedback loop is proportional to a set bandwidth of the OTA.

16. The apparatus of claim 11 , wherein a bandwidth of the inverting current amplifier of the first current amplifier circuit is set by a control signal.

17. a first component charge of a current from the first touch electrode is proportional to a self-capacitance of the first touch electrode; 12. The apparatus of claim 11, wherein a second component charge of a current from the first touch electrode is proportional to a projected capacitance of the first touch electrode.

18. a first component charge of a current from the second touch electrode is proportional to a self-capacitance of the second touch electrode; 12. The apparatus of claim 11, wherein a second component charge of a current from the second touch electrode is proportional to a projected capacitance of the second touch electrode.

19. The inverting current amplifier of the first current amplifier circuit comprises: a first transistor and a second transistor for providing a controlled current in the second transistor that is a copy of a current in the first transistor when respective drain-source voltages of the first transistor and the second transistor are substantially equal; 12. The apparatus of claim 11 , comprising: a feedback loop for setting the respective drain-source voltages of the first transistor and the second transistor to be substantially equal, the responsiveness of the feedback loop being proportional to a setting bandwidth of an OTA of the feedback loop.

20. 12. The apparatus of claim 11, wherein the first touch electrode and the second touch electrode each generate a current indicative of a respective capacitance at least partially in response to a capacitance measurement process.

21. 1. A method comprising: receiving a measured charge signal from the first electrode and a measured charge signal from the second electrode in response to a capacitance measurement process; generating an inverted version of the measurement charge signal received from the first electrode and the measurement charge signal from the second electrode; obtaining a touch charge signal for the second electrode by combining the inverted version of the measured charge signal from the first electrode with the measured charge signal from the second electrode; detecting a state of the first electrode at least in part in response to a touch charge signal for the first electrode.

22. obtaining a touch charge signal for the first electrode by combining the inverted version of the measured charge signal from the second electrode with the measured charge signal from the first electrode; and detecting a state of the second electrode at least partially in response to the touch charge signal for the second electrode.

23. The step of generating an inverted version of the measurement charge signal received from the first electrode and the measurement charge signal from the second electrode comprises:

22. The method of claim 21, comprising generating the inverted versions of the measured charge signal received from the first electrode and the measured charge signal from the second electrode via an inverting current amplifier.

24. The inverting current amplifier comprises: a first transistor and a second transistor for providing a controlled current in the second transistor that is a copy of a current in the first transistor when respective drain-source voltages of the first transistor and the second transistor are substantially equal; a feedback loop for setting the respective drain-source voltages of the first transistor and the second transistor to be substantially equal.

25. The feedback loop comprises:

25. The method of claim 24, comprising an operational transconductance amplifier (OTA) having a transconductance that is configurable via a bias input of the OTA.

26. 1. A method comprising: setting the drain voltages of the first and second transistors to be substantially equal using an operational transconductance amplifier (OTA) having a set bandwidth; providing a controlled current in the second transistor that is a copy of the current in the first transistor when the respective drain-source voltages of the first and second transistors are substantially equal.

27. sweeping the current generated by a tuning current source coupled to a bias input of the OTA up or down in steps; Observing one or more of a bandwidth or a transconductance of the OTA while sweeping the current generated by the current source; and setting the current source to a current corresponding to one or more of an observed predetermined bandwidth or an observed predetermined transconductance.

28. sweeping the current generated by a current source coupled to a bias input of the OTA in a stepwise increase or decrease; observing an output signal based at least in part on the controlled current in the second transistor while sweeping the current generated by the current source; and setting the current source to the current corresponding to a minimum observed output signal.

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