Electronic structures and methods for forming same

Abstract

The electronic structure includes a first substrate having a first under bump metallization (UBM) region and a second UBM region formed thereon. One or more solder bumps are deposited on the first UBM region. A downstop formed on the second UBM region is wider, shallower and more rigid than any one of the solder bumps formed on the first UBM region. The second substrate is bonded to the first substrate by the one or more solder bumps disposed on the first UBM region, and a height of the downstop limits a distance between at least one of the first substrate and the second substrate, or between an object and at least one of the first substrate and the second substrate.

Description

[Technical field]

[0001] The present disclosure relates generally to flip chip bonding, and more specifically, to bonding capable of supporting qubit devices. [Background technology]

[0002] Flip chip bonding is commonly used in the assembly of electronic devices. Bump bonds are placed on one of the two chips according to various methods, and then the chips are bonded by cold compression or by reflow bonding. The gap between the chips is determined either by the force of the bonding, the shape of the bumps and the underlying metallurgy, or by the use of rigid downstops. Rigid downstops are generally manufactured in one step, for example by depositing other materials or by etching the substrate to form a step with a precise height. When two chips are bonded by the rigid downstops, the chips are held apart from each other by the downstops. However, the manufacture of downstops may not be compatible with other manipulation processes employed in the chip manufacturing process, especially for qubit-structured devices. It is also desirable to reduce the complexity of downstop manufacturing. Summary of the Invention

[0003] According to one embodiment, an electronic structure includes a first substrate having a first under bump metallization (UBM) region and a second UBM region formed thereon. One or more solder bumps are present on the first UBM region. A downstop formed on the second UBM region is wider, shallower and more rigid than any one of the solder bumps formed on the first UBM region. The second substrate is bonded to the first substrate by the one or more solder bumps disposed on the first UBM region, and a height of the downstop limits a distance between at least one of the first substrate and the second substrate, or between an object and at least one of the first substrate and the second substrate. The electronic structure is less complex to assemble due to the presence of the downstop providing a predetermined distance between the first substrate and the second substrate to enhance reliability of operation.

[0004] In one embodiment, the object may be an interposer disposed at a predetermined distance from at least one of a first substrate and a second substrate. The first UBM region is a contact region and the second UBM region is a downstop region, the area of ​​the second UBM region being larger than the area of ​​the first UBM region. The larger area of ​​the second UBM provides improved reflow of the solder to form the downstop. The first UBM region is smaller to enhance the formation of the chamfered sphere that is the bump bond.

[0005] In one embodiment, the second substrate includes a third UBM region disposed in contact with one or more solder bumps, the third UBM region enhancing bonding of the second substrate to a top surface of the bump bonds deposited on the first substrate.

[0006] In one embodiment, the solder on the first and second UBM regions is formed by one of evaporation or electroplating, with each type of deposition having advantages when used to form the solder on the first and second UBM regions.

[0007] In one embodiment, the first UBM region and the second UBM region include pads that provide an enhanced connection to the substrate.

[0008] In one embodiment, the first UBM region and the second UBM region include pads etched from metal. The use of etching may enhance the formation and patterning of the UBM metallurgy on the substrate.

[0009] In one embodiment, the height of the downstop and the one or more solder bumps are determined by the volume of solder deposited on the first and second UBM regions and by the area of ​​the under-bump metallurgy for each of the first and second UBM regions. A precisely defined space may be formed to control the separation of a third semiconductor chip (which may or may not be part of another pair of bonded chips) without extensive calibration performed without the use of a downstop.

[0010] According to one embodiment, a method of forming an electronic structure includes providing a first under bump metallization (UBM) region and a second UBM region on a first substrate. Solder is deposited on the first UBM region and the second UBM region and reflowed to form one or more solder bumps on the first UBM region and a downstop on the second UBM region. The second substrate is bonded to the first substrate by the one or more solder bumps disposed on the first UBM region. The height of the downstop limits the distance between at least one of the first substrate and the second substrate, or between an object and at least one of the first substrate and the second substrate, and a less complicated configuration having a more precisely defined distance between the first substrate and the second substrate is achieved. The simultaneous formation of the downstop and the bump bond provides a less complicated configuration than previously known.

[0011] In one embodiment, the one or more solder bumps in the first UBM region and the downstops in the second UBM region are formed substantially simultaneously, resulting in a more efficient configuration with reduced manufacturing time.

[0012] In one embodiment, the area of ​​the second UBM region is larger than the area of ​​the first UBM region. The second area of ​​the UBM is larger to facilitate the formation of a downstop, while the first UBM region has a smaller area to facilitate the formation of a chamfered sphere that is the bump bond. The downstop is wider, shallower, and more rigid than the bump. The downstop functions as a mechanical downstop due to its relative incompressibility compared to the solder bump.

[0013] In one embodiment, prior to bonding the second substrate to the first substrate, a third UBM region is formed on the second substrate, the third UBM region being positioned to contact one or more solder bumps on the first substrate, the addition of the third UBM region facilitating bonding of the second substrate to an upper portion of the solder bumps disposed on the first substrate.

[0014] In one embodiment, the solder is deposited on the first UBM region and the second UBM region by one or more of evaporation, electroplating, or injection molding techniques, or a combination thereof, each technique offering advantages in the configuration.

[0015] In one embodiment, the height of the downstop and the height of the one or more solder bumps are determined according to the volume of solder deposited on the first UBM region and the second UBM region and by the area of ​​the under-bump metallurgy for each of the first UBM region and the second UBM region. The use of the downstop provides a precise distance between the first and second substrates. The use of the downstop can avoid precise calibrations associated with bonding the second substrate to the solder bumps of the first substrate. If a third substrate (e.g., third substrate, chip, interposer) is included in the structure, the downstop also provides precise separation of the third substrate of the device from the first and second substrates without precise calibrations.

[0016] In one embodiment, the solder bump or bumps are the same size. Electrical connection may be enhanced with this configuration.

[0017] In one embodiment, some of the solder bumps are different sizes. Bonding of the substrates may be enhanced.

[0018] In one embodiment, the volume of the solder bumps in the first UBM region and the second UBM region includes forming a solder structure on a surface of a substrate by deposition with a removable mold to control the solder volume. The removable mold can facilitate configuration.

[0019] In one embodiment, the removable mold is a photoresist. The photoresist may enhance the construction process.

[0020] In one embodiment, the solder bumps are restricted to a limited area. This configuration may enhance the operation of the electronic structure by allowing more qubits to be placed on the electronic structure.

[0021] In one embodiment, the solder bumps are the same size and the bump pattern is customized to increase reliable contact area. This embodiment results in improved reliability.

[0022] In one embodiment, some of the solder bumps are different sizes and the pattern of the bumps is customized to increase the reliable contact area, which results in improved reliability.

[0023] According to one embodiment, an electronic structure includes a first substrate having a first under bump metallization (UBM) region with one or more solder bumps thereon and a second UBM region. A downstop is formed in the second UBM region, the downstop having a surface area greater than a surface area of ​​the one or more solder bumps. The second substrate is bonded to the first substrate by the one or more solder bumps disposed on the first UBM region. The downstop has a height configured to limit a distance between at least one of the first substrate and the second substrate, or between an object and at least one of the first substrate and the second substrate. The electronic structure is less complex to assemble due to the presence of the downstop providing a predetermined distance between the first substrate and the second substrate to enhance reliability of operation.

[0024] The drawings are of exemplary embodiments. They do not represent all embodiments. Other embodiments may be used in addition or alternatively. Details that may be obvious or unnecessary may be omitted to save space or for a more effective explanation. Some embodiments may be practiced with additional components or steps, or without all the components or steps shown, or both. When the same number appears in different drawings, it refers to the same or similar components or steps. [Brief description of the drawings]

[0025] [Figure 1A]1 illustrates substrate fabrication including post solder patterning, consistent with an illustrative embodiment. [Figure 1B] 1 illustrates a substrate fabrication including post-solder reflow, consistent with an exemplary embodiment. [Diagram 2] FIG. 1 illustrates an example application of using standoffs to control chip gap and form bump bonds consistent with an example embodiment. [Diagram 3] 1 is a flowchart illustrating a method for manufacturing a substrate with a UBM by forming and patterning a UBM mask and substantially simultaneously depositing both solder bumps and solder standoffs, consistent with an example embodiment. [Figure 4] 1 is a flowchart illustrating a method for manufacturing a substrate comprising a UBM by depositing UBM metallurgy on the substrate using a patterning and etching process, consistent with an example embodiment. [Diagram 5] FIG. 1 illustrates a specifically configured computing device operable to perform one or more of the functions described herein, consistent with an exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] overview In the following detailed description, numerous specific details are set forth as examples to provide a thorough understanding of the relevant teachings. However, it should be understood that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components or circuits, or combinations thereof, have been described at a relatively high level, without detail, to avoid unnecessarily obscuring aspects of the present teachings. It should be understood that the present disclosure is not limited to the depictions in the drawings, and that there may be fewer or more elements than those shown and described.

[0027] In discussing the current technology, it may be helpful to explain various salient terms. In one aspect, spatially relative terms such as "front", "back", "top", "bottom", "lower", "lower", "upper", "upper", "side", "left", "right" and the like are used with respect to the orientation of the figures being described. Because components of the embodiments of the present disclosure can be positioned in many different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, elements described as "below" or "below" other elements or features will now be oriented "above" the other elements or features. Thus, for example, the term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced in other directions) and the spatially relative descriptors used herein should be interpreted accordingly.

[0028] As used herein, the terms "coupled" and / or "electrically coupled" are not intended to imply that elements must be directly coupled, and intervening elements may be provided between the "coupled" or "electrically coupled" elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. The term "electrically connected" refers to a low resistance electrical connection between elements that are electrically connected to one another. As used herein, the term "mechanically resistant" refers to electrical properties that are not significantly affected by mechanical alignment between the subject components.

[0029] Certain terms are used herein to indicate what might be considered idealized operation, such as "lossless," "superconductor," "superconducting," and "absolute zero," which are intended to cover functionality that may not be exactly ideal, but is within an acceptable margin for a given application. For example, certain levels of loss or tolerances may be acceptable, such that the resulting materials and structures may still be referred to by these "idealized" terms.

[0030] Terms such as first, second, third, etc. may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the exemplary embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] Exemplary embodiments are described herein with reference to schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations may be expected as a result, for example, of manufacturing techniques and / or tolerances. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not necessarily indicative of the actual shapes of regions of a device and are not limiting in scope.

[0032] It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the spirit and scope as defined by the claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0033] The present disclosure generally relates to flip chip bonding that can support and connect qubit devices, for example. Superconducting quantum computing is the implementation of quantum computers in superconducting electronic circuits. Quantum computing studies the application of quantum phenomena for information processing and communication. Various models of quantum computing exist, the most common model includes the concepts of qubits and quantum gates. A qubit is a generalization of a bit that has two possible states, but can be in a quantum superposition of both states. A quantum gate is a generalization of a logic gate, but a quantum gate describes the transformation that one or more qubits undergo after a gate is applied to them, given their initial state.

[0034] The ability to include many more superconducting qubits is remarkable for enabling the potential of quantum computers to be realized. However, it is difficult to produce a quantum processor on a monolithic qubit chip with the desired qubit characteristics, such as frequency and fidelity. Modular architectures including smaller modular units of interconnected devices can make it feasible to realize large-scale quantum processors. However, such modular architectures may require supporting connections between qubits or circuitry for the qubit chip on separate physical chips, or both. Various quantum phenomena, such as superposition and entanglement, have no analogue in the classical computing world, and therefore may require special structures, techniques, and materials to assemble electronic devices that can operate in cryogenic environments.

[0035] In one aspect, the teachings herein are based on the inventors' insight that directly applying conventional integrated circuit techniques for interacting with computing elements to superconducting quantum circuits may not be effective due to unique challenges presented by quantum circuits that were not present in classical computing architectures. Indeed, many of the systems and architectures discussed herein operate in cryogenic environments and may involve superconductivity. Thus, embodiments of the present disclosure are further based on the recognition that challenges unique to quantum circuits have been considered when evaluating the applicability of conventional integrated circuit techniques to building superconducting quantum circuits, and in particular, to selecting the methods and architectures used to connect the components of a quantum computer. The techniques described herein may be implemented in many ways. Exemplary implementations are provided below with reference to the following drawings:

[0036] Exemplary Architecture 1A and 1B respectively show substrate fabrication including after solder patterning 100a and after solder reflow 100B, consistent with an exemplary embodiment. Substrate 105 is prepared with under bump metallization (UBM) 120. The UBM provides electrical connection from the substrate to the solder bump (or bumps). For example, UBM 120 may provide a wettable surface for solder. Two regions are defined: an area for electrical contact 125 and a second area for standoff region 130. Solder 115 is deposited on the wafer and defined by lithography. Solder 115 is reflowed above the melting temperature of the solder, and the reflowed solder wets UBM surface 120. The UBM pattern in standoff region 130 is larger than in contact region 125.

[0037] Upon reflow, the solder forms a chamfered sphere at the contact area 130, as shown in FIG. 1B. The size of the standoff area 130 causes the solder to form a substantially flat area after reflow. The difference between a "solder bump" and a "downstop" discussed herein is the amount of solder deposited on each and the physical size (e.g., area) of the downstop UBM versus the bump UBM. Comparatively, a standoff is wider and shallower than a bump. On the other hand, a bump has height compared to its width, allowing room for the solder material to ooze out sideways. Due to the configuration of the standoff being wider and shallower than the bump, the standoff does not move (or moves very little) when pressed, thereby maintaining a relatively constant height. This allows the standoff height to be controllable (by the dimensions used as discussed in this paragraph). Because the standoff is relatively stiffer than the bump, the standoff can act as a height controller. It should be appreciated that the standoffs can be used as height controllers for the first and second substrates, as well as provide a precise separation distance for a third object from the first and second substrates. One such example of a third object can be an interposer that can provide connection to other chips.

[0038] After reflow, the solder in the reflowed portion of the standoff region 130 will be lower in height than in the contact region. Note that the amount of solder in both the contact region and the standoff region can vary by design, and the UBM dimensions can also have different sizes (e.g., area). The relationship between the solder volume and surface area of ​​the UBM can lead to a defined profile and therefore a predefined height of the reflowed solder. When the second chip is placed in place on the bump, a gap defined by the downstop is formed. Thus, the height of the solder bump for bonding is controllable and can be significantly different from the height of the downstop. In one embodiment, a fully reflowed standoff can be substantially incompressible due to its high aspect ratio. By not cleaning the downstop after fabrication, the downstop may not bond well to anything. For example, if the second chip surface is chosen to be terminated by bare silicon, or a non-bondable material such as silicon oxide, the second chip surface may be retained without bonding. More solder and less area of ​​the UBM results in a higher, more spherical bump than the downstop. Less solder and / or a larger UBM results in a lower, flatter downstop.

[0039] Additional features of the disclosed methods and apparatus are disclosed herein.

[0040] Exemplary embodiments 2 illustrates an example application 200 of using standoff regions to control chip clearance and form bump bonds consistent with an example embodiment. The post-solder patterning on a first substrate 205 with solder 215 on a UBM 220 and the post-reflow formation of chamfered spheres that form bump bonds 227 are the same as shown in FIGS. 1A and 1B.

[0041] A second substrate 255 having a UBM 260 connected to the bump bond 227 is pressed against the bump bond 227. The bump bond 227 is compressed by the second substrate 255, while a downstop 217 deposited on the substrate 205 serves to separate the second substrate 255 a predetermined distance from the first substrate 205. This configuration can prevent the bump bond 227 from being compressed to the point where it is damaged or where it creates a short on the substrate 205.

[0042] The UBM pattern in the standoff area is larger than in the contact area, and after reflow, the solder in the reflowed portion is lower in height than in the contact area. In other words, the area for solder is wider and shallower in the standoff area than in the contact area. Both the amount of solder on the contact area and the standoff area can vary by design, and the UBM dimensions can also be of different sizes (areas). The relationship between the solder volume and the surface area of ​​the UBM leads to a predetermined profile and therefore the height of the solder. When the second chip is placed in contact with the downstop, the downstop can form a predetermined gap. Thus, the height of the solder bump for bonding is controllable and can be significantly different from the height of the standoff. A fully reflowed standoff is substantially incompressible because it has such a high aspect ratio. If the downstop is not cleaned after fabrication, good bonding of the downstop to anything does not occur. If the second chip surface is selected to be terminated by a non-bondable material including bare silicon or silicon oxide, the chip surface may be retained without bonding.

[0043] Another advantage of the downstop positioned at a predetermined distance between the first substrate 205 and the second substrate is that it keeps the distance between the substrates substantially uniform. Variations in the distance between the first and second substrates 205, 255 may adversely affect the performance of the operating parameters of the first substrate 205.

[0044] In addition, the downstop may also control the separation of a third substrate (eg, chip) that may or may not be part of another pair of bonded chips.

[0045] The configuration of FIG. 2 provides advantages over previous configurations in which the second substrate 255 is pressed toward the first substrate 205 with a predetermined amount of force without the use of a downstop. For example, the configuration shown in FIG. 2 provides a more precise spacing between the first and second substrates 205, 255 without requiring complex calibrations to be performed when bonding the substrates. Also, the configuration shown in FIG. 2 prevents possible damage from additional downward pressure that may be placed on the second substrate 255 due to additional mechanical handling. For example, if a cap or thermal sink is deposited on the top surface of the second substrate 255, the downstop prevents gap variations that may occur based on additional mechanical handling to attach the cap or thermal sink. Additionally, although the downstop 217 shown in FIG. 2 appears to be located at one corner or one side of the space between the first and second substrates 205, 255, it should be understood that multiple downstops (e.g., at all four corners or other areas) may be present between the first and second substrates 205, 255. The downstop may function to accommodate flatness variations between the first and second substrates 205,255.

[0046] Example Process With the above overview of the exemplary architecture in mind, it may be helpful to now consider a high-level discussion of the exemplary process. To that end, Figures 3 and 4 are flowcharts 300, 400 illustrating a method of manufacturing a substrate, consistent with respective exemplary embodiments.

[0047] 3 and 4 are illustrated as a collection of blocks in a logical order, which represents a sequence of operations that may be implemented in hardware, software, or a combination thereof. The order in which the operations are described in each process is not intended to be construed as a limitation, and any number of the described blocks may be combined in any order and / or performed in parallel to implement a process.

[0048] FIG. 3 is a flow chart illustrating a method for manufacturing a substrate with a UBM by forming and patterning a UBM mask and substantially simultaneously depositing both solder bumps and solder standoffs, consistent with an example embodiment.

[0049] In operation 302, a UBM mask is formed and patterned on a first substrate. The UBM mask may have contact regions 130 and standoff regions 125 as shown in Figure 1. There may also be multiple standoff regions to form multiple downstops on the first substrate.

[0050] In operation 304, a UBM is deposited on the substrate. The UBM provides the metallurgy for connecting the substrate to the bump bonds. The UBM also provides a base for one or more downstops.

[0051] In operation 306, the UBM mask is removed, leaving the UBM pattern on the first substrate. Standoff regions 125 are located on the first substrate where the downstops will be formed. Contact regions 130 are areas where the bump bonds will be formed.

[0052] A patterned solder mask is deposited on the UBM in operation 308. Both the standoff and contact areas may have solder deposited and reflowed to simultaneously form the downstop and bump bonds.

[0053] In operation 310, solder is deposited on both the standoff and bump (e.g., contact) areas as shown in FIG. 1A. The solder mask is removed (operation 312) and the solder is reflowed (operation 314). The larger area of ​​the standoff area helps the reflowed solder form a downstop, while the contact area results in the solder forming a chamfered solder ball 127 (see FIG. 1B). The solder is reflowed above the melting temperature of the solder, and the reflowed solder wets the UBM surface. The process of UBM and solder patterning followed by solder reflow ends in operation 314. A second substrate (see, e.g., FIG. 2) may then be placed on top of the bump bond, with the downstop creating a gap between the first and second substrates. The second substrate may also have a UBM surface patterned to match the location of the bump bond.

[0054] FIG. 4 is a flow chart illustrating a method for fabricating a substrate comprising a UBM by depositing UBM metallurgy on a substrate using a patterning and etching process, consistent with an example embodiment.

[0055] In operation 402, UBM metallurgy is deposited on a substrate, and a UBM mask is formed and patterned on the substrate in operation 404. The UBM mask is used to form standoff and contact areas for bump bonding.

[0056] In operation 406, the UBM metal is etched into formed pads. The pads may provide electrical connections from the substrate to the bump bonds.

[0057] The UBM mask is removed in operation 408. A solder mask is pattern deposited over the UBM in operation 410. The solder provides the material for both the downstop and bump bonds, which may be formed simultaneously.

[0058] Solder is deposited on both the standoffs and the contact areas in operation 412. The area of ​​the standoff areas may have a larger area than the area of ​​the contact areas.

[0059] In operation 414, the solder mask is removed and then the solder is reflowed to form one or more downstops in the standoff regions and bump bonds in the contact regions in operation 416. A second substrate having a UBM region may then be attached to the portion opposite the bump bonds, with the downstops acting as spacers at a predetermined distance between the two substrates.

[0060] With respect to the methods described above in the flow charts of FIG. 3 and FIG. 4, these embodiments are not exhaustive of the scope of the disclosure. For example, the method may include one or more operations in addition to or in place of other operations. For example, one or more solder bumps may have the same size, or some of the solder bumps may have different sizes. In addition, the volume of the solder bumps in the first UBM region and the second UBM region may include forming a solder structure on the surface of the substrate by deposition using a removable mold to control the solder volume. The removable mold may be a photoresist. The solder bumps may be confined to a limited area of ​​the substrate. The pattern of the bumps may be customized to increase the reliable contact area. The operations described above are not exhaustive of the method operations that may be performed to fabricate the electronic structures shown and described herein.

[0061] Exemplary Computer Platform As discussed above, the functions associated with the control operations, including forming a substrate including both solder bumps and solder downstops, may be performed through the use of one or more computing devices. Figure 5 provides a functional block diagram of a computer hardware platform 500 that may be used to implement a specifically configured computing device capable of hosting a solder engine 540. In particular, Figure 5 illustrates a network or host computer platform 500 such as may be used to implement a suitably configured server.

[0062] The computer platform 500 may include a central processing unit (CPU) 504, a hard disk drive (HDD) 506, a random access memory (RAM) and / or read only memory (ROM) 508, a keyboard 510, a mouse 512, a display 514, and a communication interface 516, which are connected to a system bus 502.

[0063] In one embodiment, HDD 506 has capabilities including storing programs capable of executing various processes, such as solder engine 540, in the manner described herein. Solder engine 540 may have various modules configured to perform different functions, such as those discussed in connection with the figures discussed herein. For example, solder engine 540 may include modules such as electroplating control module 572, deposition control module 574, pattern control module 576, some or all of which may be used to control the application of the UBM regions to the substrate and solder disposed thereon. Compression control module 578 may be configured to control the bonding of the second substrate to the first substrate. The modules shown in FIG. 5 may be combined into several modules, which are not inclusive or required to perform any particular operation.

[0064] Although modules 572-578 are shown in FIG. 5 as being part of HDD 506, in some embodiments, one or more of these modules may be implemented in the hardware of computing device 500. For example, the modules discussed herein may be implemented in the form of part hardware and part software. That is, one or more of the components of solder engine 540 shown in FIG. 5 may be implemented in the form of electronic circuits comprising transistors, diodes, capacitors, resistors, inductors, varactors or memristors or combinations thereof. In other words, solder engine 540 may be implemented by one or more specially designed electronic circuits that perform the specific tasks and functions described herein. Artificial intelligence modules for process training and operation may also be included and may be involved in the preparation and operation of the manufacturing process.

[0065] conclusion The description of various embodiments of the present teachings is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to enable other skilled in the art to understand the embodiments disclosed herein.

[0066] While the foregoing describes what is believed to be the best mode and / or alternative embodiments, it is understood that various modifications may be made thereto, that the subject matter disclosed herein may be embodied in a variety of forms and embodiments, and that the present teachings may be applied to numerous applications, only a few of which are described herein. It is intended by the following claims to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0067] The components, operations, steps, features, objects, benefits, and advantages discussed herein are merely exemplary. None of them, nor any discussion related thereto, are intended to limit the scope of protection. Although various advantages have been described herein, it should be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, dimensions, sizes, and other specifications set forth herein, which are included in the following claims, are approximate and not precise. They are intended to have a reasonable range consistent with the functions to which they relate and the customary practices in the art to which they relate.

[0068] Numerous other embodiments are contemplated, including embodiments having fewer, additional, or different or combinations of components, steps, features, objects, benefits, and advantages, as well as embodiments in which the components or steps or combinations thereof are in different arrangements or orders or combinations thereof.

[0069] The flowcharts and diagrams in the Figures herein illustrate the architecture, functionality, and operation of possible implementations according to various embodiments of the present disclosure.

[0070] Although the foregoing has been described in connection with exemplary embodiments, the term "exemplary" means merely an example, not the best or optimal. Except as stated immediately above, nothing described or illustrated is intended or should be construed to result in the provision to the public of any element, step, feature, object, benefit, advantage, or equivalent, whether or not recited in the claims.

[0071] The terms and expressions used herein shall be understood to have ordinary meanings consistent with such terms and expressions with respect to the respective corresponding fields of investigation and study, unless a specific meaning is otherwise indicated herein. Relative terms such as first, second, etc. may be used only to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between such entities or operations. The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements may include other elements not expressly listed or inherent to such process, method, article, or apparatus, rather than including only those elements. An element preceded by "a" or "an" does not, without further constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0072] The Abstract of the Disclosure is provided to enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, it will be appreciated that in the foregoing Detailed Description, various features have been grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. An electronic structure comprising: a first substrate having a first under bump metallization (UBM) region and a second UBM region formed thereon; one or more solder bumps on the first UBM region; a downstop formed on the second UBM region that is wider, shallower and more rigid than any one of the solder bumps formed on the first UBM region; a second substrate joined to the first substrate by the one or more solder bumps disposed on the first UBM region, wherein a height of the downstop limits a distance between at least one of the first substrate and the second substrate, or between an object and at least one of the first substrate and the second substrate.

2. the object includes an interposer disposed a predetermined distance from at least one of the first substrate and the second substrate; the first UBM region includes a contact region; the second UBM region includes a downstop region; The electronic structure of claim 1 , wherein an area of ​​the second UBM region is greater than an area of ​​the first UBM region.

3. a distance between the first substrate and the second substrate, or between the object and at least one of the first substrate and the second substrate, is limited by a height of the downstop based on a height of the second UBM region; The electronic structure of claim 1 or 2, wherein the second substrate includes a third UBM region positioned in contact with the one or more solder bumps.

4. The electronic structure of claim 2 , wherein the solder on the first UBM region and the second UBM region is formed by at least one of evaporation or electroplating.

5. The electronic structure of claim 2 , wherein the first UBM region and the second UBM region on the first substrate comprise pads.

6. The electronic structure of claim 2 , wherein the first UBM region and the second UBM region comprise pads etched from metal.

7. 7. The electronic structure of claim 1, wherein a height of the downstop and a height of the one or more solder bumps are based on a volume of solder deposited on the first UBM region and the second UBM region and by an area of ​​under-bump metallurgy for each of the first UBM region and the second UBM region.

8. The electronic structure of claim 1 , wherein the one or more solder bumps have the same size.

9. The electronic structure of claim 1 , wherein at least some of the solder bumps include different sizes.

10. Providing a first under bump metallization (UBM) region and a second UBM region on a first substrate; depositing solder on the first UBM region and the second UBM region; reflowing the deposited solder to form one or more solder bumps on the first UBM area and downstops on the second UBM area; and bonding a second substrate to the first substrate by the one or more solder bumps disposed on the first UBM region, wherein a distance between at least one of the first substrate and the second substrate, or between an object and at least one of the first substrate and the second substrate, is limited by a height of the downstop based on a height of the second UBM region.

11. The method of claim 10 , wherein the one or more solder bumps in the first UBM region and the downstops in the second UBM region are formed substantially simultaneously.

12. The method of claim 10 or 11, wherein an area of ​​the second UBM region is greater than an area of ​​the first UBM region.

13. forming a third UBM region on the second substrate prior to bonding the second substrate to the first substrate; 13. The method of claim 10, further comprising: placing the third UBM region in contact with the one or more solder bumps on the first substrate.

14. 14. The method of claim 10, wherein the solder of the solder bumps of the first and second UBM regions is deposited on the first and second UBM regions by one or more of evaporation, electroplating, or injection molding techniques, or a combination thereof.

15. 15. The method of claim 10, wherein the first UBM region and the second UBM region deposited on the first substrate each include a pad.

16. 16. The method of claim 10, wherein providing the first and second UBM regions on the first substrate comprises etching pads from metal.

17. 17. The method of claim 10, further comprising determining a height of the downstop and a height of the one or more solder bumps by an area of ​​under bump metallurgy for each of the first UBM region and the second UBM region according to a volume of solder deposited on the first UBM region and the second UBM region.

18. 18. The method of claim 10, wherein the one or more solder bumps disposed on the first UBM region have the same size.

19. 19. The method of claim 10, wherein some of the solder bumps in the first UBM region have different sizes.

20. 20. The method of claim 10, wherein depositing solder bumps at the first UBM region and the second UBM region comprises forming a solder structure on a surface of the first substrate by deposition using a removable mold to control solder volume.

21. The method of claim 20 , wherein the removable mold comprises a photoresist.

22. 22. The method of claim 10, wherein the solder bumps of the first UBM region are confined to a limited area.

23. the solder bumps have the same size; 23. The method of any of claims 10 to 22, wherein the pattern of the solder bumps is customized to increase reliable contact area.

24. 24. The method of any of claims 10 to 23, wherein some of the solder bumps are different sizes and the pattern of the bumps is customized to increase reliable contact area.

25. An electronic structure comprising: a first substrate having a first under bump metallization (UBM) region with one or more solder bumps thereon and a second UBM region; a second substrate joined to the first substrate by the one or more solder bumps disposed on the first UBM region; an electronic structure comprising: a downstop formed in the second UBM region, the downstop having a surface area greater than a surface area of ​​the one or more solder bumps and a height configured to limit a distance between at least one of the first substrate and the second substrate, or between an object and at least one of the first substrate and the second substrate.

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