Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes a first insulating layer, a first circuit layer disposed on the first insulating layer, a first buffer layer disposed on the first circuit layer, and a second insulating layer disposed on the first insulating layer and the first buffer layer, the first circuit layer including a surface layer including nitrogen (N), and the first buffer including a first functional group that bonds with the surface layer and a second functional group that bonds with the second insulating layer.

Description

[Technical field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] Components mounted on a circuit board transmit and receive signals via a circuit pattern arranged on the circuit board. Recently, as portable electronic devices and the like have become more sophisticated, signals are becoming increasingly high-frequency in order to process large amounts of information at high speed. This has led to a demand for circuit boards suitable for high-frequency applications. Here, a circuit board suitable for high-frequency applications should include a low-roughness circuit pattern capable of transmitting high-frequency signals without signal transmission loss. That is, the circuit pattern should enable signal transmission while minimizing signal transmission loss and maintaining the quality of the high-frequency signal.

[0003] In this case, the transmission loss of the circuit pattern of the circuit board is mainly composed of conductor loss caused by a thin metal film such as copper, and dielectric loss caused by an insulator such as an insulating layer.

[0004] Conductor loss caused by a metal thin film is related to the surface roughness of a circuit pattern. That is, as the surface roughness of a circuit pattern increases, transmission loss can increase due to the skin effect.

[0005] In this case, reducing the surface roughness of the circuit pattern has the effect of minimizing transmission loss, but it has the problem of reducing the bonding strength or adhesion strength between the circuit pattern and the insulating layer.

[0006] Meanwhile, in order to achieve high data transmission rates, the frequency bands used by 5G and higher communication systems are gradually increasing. For example, 5G and higher communication systems use ultra-high frequency (mmWave) bands (sub-6 GHz, 28 GHz, 38 GHz, or higher frequencies).

[0007] Therefore, low roughness of the circuit pattern included in the circuit board is required.

[0008] However, as described above, when the roughness of the circuit pattern is reduced, a problem occurs in the adhesive strength with the insulating layer, and when the roughness of the circuit pattern is increased, a problem occurs in that signal transmission loss increases.

[0009] This has created a demand for a new circuit pattern surface treatment technique that can improve the bonding strength between the circuit pattern and the insulating layer while reducing the surface roughness of the circuit pattern. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Korean Patent Publication No. 10-2010-0005881 Summary of the Invention [Problem to be solved by the invention]

[0011] The embodiments provide a circuit board capable of minimizing signal transmission loss and a semiconductor package including the same.

[0012] Furthermore, the embodiments provide a circuit board having improved adhesion between an insulating layer and a circuit layer, and a semiconductor package including the same.

[0013] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0014] A circuit board according to an embodiment includes a first insulating layer, a first circuit layer disposed on the first insulating layer, a first buffer layer disposed on the first circuit layer, and a second insulating layer disposed on the first insulating layer and the first buffer layer, the first circuit layer including a surface layer including nitrogen (N), and the first buffer including a first functional group that bonds with the surface layer and a second functional group that bonds with the second insulating layer.

[0015] In addition, the surface layer of the first circuit layer is a nitride layer formed on the surface of the first circuit layer.

[0016] The first circuit layer also includes a third functional group including the nitrogen (N) that forms a coordinate bond with the first functional group of the first buffer layer, which is the nitride layer of the first circuit layer.

[0017] The first functional group includes at least one azole group selected from the group consisting of diazole, triazole, tetraazole, benzotriazole, benzothiazole, and nitrotriazole.

[0018] Additionally, the second functional group includes a siloxane group that is covalently bonded to the second insulating layer.

[0019] The first buffer layer is formed of an organosilane agent that includes an azole group that corresponds to the first functional group.

[0020] The first insulating layer includes a first region overlapping the first circuit layer in a thickness direction and a second region excluding the first region, and a fourth functional group including nitrogen (N) is formed on an upper surface of the second region of the first insulating layer.

[0021] The first circuit layer includes a first surface in contact with the first buffer layer, and the first surface of the first circuit layer has a roughness Ra in the range of 0.1 μm to 0.9 μm.

[0022] The first circuit layer also includes a second surface in contact with the first insulating layer, the second surface of the first circuit layer having a roughness Ra different from the roughness Ra of the first surface.

[0023] Furthermore, the roughness Ra of the first buffer layer corresponds to the roughness Ra of the first surface of the first circuit layer.

[0024] The circuit board further includes a through electrode that penetrates at least one of the first insulating layer and the second insulating layer, and the roughness Ra of the side surface of the through electrode is different from the roughness Ra of the first surface of the first circuit layer.

[0025] The adhesion strength (90° Peel Strength) between the first circuit layer and the second insulating layer is in the range of 0.55 to 1.5 kgf / cm.

[0026] The circuit board also includes a second circuit layer disposed on an upper surface of the second insulating layer, a second buffer layer disposed on the second circuit layer, and a first protective layer disposed on the second insulating layer and the second buffer layer, the second buffer layer having functional groups corresponding to the first and second functional groups of the first buffer layer.

[0027] The first buffer layer further includes a metal ion that forms a coordinate bond with one of the first functional group and the third functional group.

[0028] On the other hand, a semiconductor package according to an embodiment includes a first insulating layer, a first circuit layer disposed on the first insulating layer, a first buffer layer disposed on the first circuit layer, a second insulating layer disposed on the first insulating layer and the first buffer layer, a second circuit layer disposed on the second insulating layer, a second buffer layer disposed on the second circuit layer, a first protective layer disposed on the second insulating layer and the second buffer layer and including an opening, a first connection portion disposed on the second circuit layer overlapping the opening of the first protective layer in a thickness direction, and a chip mounted on the first connection portion, each of the first and second circuit layers including a surface layer including nitrogen (N), each of the first and second buffer layers including a first functional group that bonds with a surface layer of any one of the first and second circuit layers and a second functional group that bonds with the second insulating layer, and each of the first and second buffer layers including a metal ion that coordinately bonds with the first functional group and the surface layer. Effect of the Invention

[0029] The embodiment can improve the reliability of the circuit board.

[0030] Advantageously, the embodiments may improve the electrical and physical reliability of the circuit board.

[0031] To this end, the embodiment forms a nitrogen-containing functional group on a surface of a circuit layer disposed on a first insulating layer. For example, the embodiment forms a nitride layer by plasma-treating the surface of the circuit layer. Then, the embodiment forms a buffer layer on the nitride layer of the circuit layer.

[0032] The buffer layer includes a first functional group that bonds with the circuit layer and a second functional group that bonds with a second insulating layer disposed on the circuit layer. The first functional group may be an azole group. The first functional group may be coordinately bonded with a functional group containing nitrogen (N) formed on the surface of the circuit layer. Also, the second functional group may be covalently bonded with a functional group included in the second insulating layer. To this end, the buffer layer may be formed of an organosilane agent containing an azole group.

[0033] Thus, the embodiment can improve adhesion between the circuit layer and the second insulating layer by using the buffer layer, thereby resolving a physical reliability problem that the second insulating layer peels off from the circuit layer.

[0034] In this embodiment, the upper surface of the first insulating layer is also plasma-treated when the circuit layer is plasma-treated. As a result, a functional group containing nitrogen (N) may be formed on the upper surface of the first insulating layer. The functional group formed on the upper surface of the first insulating layer may be shared with the functional group of the second insulating layer. As a result, the embodiment can improve not only the adhesion between the circuit layer and the second insulating layer, but also the adhesion between the first insulating layer and the second insulating layer.

[0035] In addition, the buffer layer of the embodiment includes metal ions. Preferably, the buffer layer includes copper ions. In this case, the copper ions can be coordinated with a nitrogen (N)-containing functional group of the circuit layer. Through this, the embodiment can further improve the adhesion between the buffer layer and the circuit layer.

[0036] Furthermore, the copper ions contained in the buffer layer may form a coordinate bond with the first functional group of the buffer layer. Thus, the embodiment may strengthen the internal cohesion of the buffer layer through the coordinate bond between the first functional group and the copper ions. Thus, the embodiment may further improve the adhesion between the circuit layer and the second insulating layer.

[0037] On the other hand, in the embodiment, the functional group of the circuit layer and the first and second functional groups of the buffer layer are used to ensure adhesion between the circuit layer and the second insulating layer. As a result, the embodiment does not require an additional roughening step to ensure the adhesion to the circuit layer. As a result, the embodiment can prevent deformation of the circuit layer and further improve the electrical properties of the circuit layer.

[0038] In addition, the embodiment can provide a circuit layer having a surface with fine roughness. This can be achieved by using the buffer layer to ensure the adhesion and thereby reducing the surface roughness of the circuit layer. As a result, the circuit layer of the embodiment can satisfy the surface roughness Ra range of 0.1 μm to 0.9 μm. Therefore, the embodiment can minimize the transmission loss of signals transmitted through the circuit layer. Furthermore, the embodiment can provide a circuit board applicable to products using high frequency bands. [Brief description of the drawings]

[0039] [Figure 1] FIG. 11 is a cross-sectional view showing a circuit board according to a comparative example. [Diagram 2] FIG. 11 is a diagram for explaining a signal transmission flow according to frequency. [Diagram 3] FIG. 1 is a cross-sectional view showing a circuit board according to a first embodiment. [Figure 4] FIG. 2 is a diagram for explaining the bonding relationship between a circuit layer, a buffer layer, and a second insulating layer in an embodiment. [Diagram 5] FIG. 2 is a diagram for explaining a method for measuring the adhesion (90° Peel Strength) of a circuit board according to an embodiment. [Figure 6] FIG. 2 is a diagram for explaining a method for measuring the adhesion (90° Peel Strength) of a circuit board according to an embodiment. [Figure 7] FIG. 11 is a cross-sectional view showing a circuit board according to a second embodiment. [Figure 8] FIG. 11 is a cross-sectional view showing a circuit board according to a third embodiment. [Figure 9] 2 is a cross-sectional view showing a layer structure of a circuit layer and a through electrode according to the first embodiment. FIG. [Figure 10] FIG. 11 is a cross-sectional view showing the layer structure of a circuit layer and electrodes according to a second embodiment. [Figure 11] 1A and 1B are diagrams illustrating a semiconductor package according to an embodiment. [Figure 12] 10A to 10C are diagrams showing a process sequence of a method for manufacturing another circuit board according to an embodiment of the present invention. [Figure 13]10A to 10C are diagrams showing a process sequence of a method for manufacturing another circuit board according to an embodiment of the present invention. [Figure 14] 10A to 10C are diagrams showing a process sequence of a method for manufacturing another circuit board according to an embodiment of the present invention. [Figure 15] 10A to 10C are diagrams showing a process sequence of a method for manufacturing another circuit board according to an embodiment of the present invention. [Figure 16] 10A to 10C are diagrams showing a process sequence of a method for manufacturing another circuit board according to an embodiment of the present invention. [Figure 17] 10A to 10C are diagrams showing a process sequence of a method for manufacturing another circuit board according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0040] Hereinafter, preferred embodiments of the present specification will be described in detail with reference to the accompanying drawings. However, the technical concept of the present invention is not limited to some of the embodiments described, and may be realized in various different forms, and one or more of the components may be selectively combined or substituted between the embodiments within the scope of the technical concept of the present invention.

[0041] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the embodiments of the present invention are to be interpreted as meanings that may be commonly understood by a person having ordinary knowledge in the technical field to which the present invention belongs, and commonly used terms, such as terms defined in a dictionary, may be interpreted in light of the contextual meaning of the relevant art.

[0042] In addition, the terms used in the embodiments of the present invention are intended to describe the embodiments and are not intended to limit the present invention. In the present specification, the singular form can include the plural form unless otherwise specified in the phrase, and when it is described as "A and (and) at least one (or more) of B and C", it can include one or more of all combinations that can be combined with A, B, and C.

[0043] In addition, in describing components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. are used. Such terms are merely used to distinguish the components from other components, and do not define the essence, order, or procedure of the components.

[0044] Furthermore, when a component is described as being "coupled," "coupled," or "connected" to another component, it includes not only cases where the component is directly coupled, coupled, or connected to the other component, but also cases where the component is "coupled," "coupled," or "connected" by another component between the component and the other component.

[0045] In addition, when described as being formed or disposed "above or below" each component, above or below includes not only the case where the two components are in direct contact with each other, but also the case where one or more other components are formed or disposed between the two components.

[0046] In addition, when it is expressed as "above" or "below," it can include the meaning of not only the upward direction but also the downward direction based on one component.

[0047] Prior to describing this embodiment, a circuit board according to a comparative example will be described first.

[0048] (Comparative Example)

[0049] FIG. 1 is a cross-sectional view showing a circuit board according to a comparative example, and FIG. 2 is a diagram for explaining a signal transfer flow according to frequency.

[0050] Referring to FIG. 1( a ), the circuit board of the comparative example includes a first insulating layer 10 and a first circuit layer 20 disposed on the first insulating layer 10 .

[0051] And, referring to FIG. 1(b), the comparative circuit board includes a second insulating layer 30 disposed on the first circuit layer 20 for multi-layer application.

[0052] At this time, in order to increase the bonding strength between the first circuit layer 20 and the second insulating layer 30, a certain level of roughness is imparted to the surface of the first circuit layer 20. For example, the surface of the first circuit layer 20 is imparted with a roughness Ra of about 1.0 μm. Through this, the comparative example improves the bonding strength between the first circuit layer 20 and the second insulating layer 30. However, if the surface roughness Ra of the first circuit layer 20 is 1.0 μm or more, signal transmission loss increases toward higher frequency bands.

[0053] Specifically, as the frequency of an application to which a circuit board is applied increases, the flow of signals moves to the surface of the conductor (circuit layer) due to the skin effect.

[0054] That is, in a first frequency range (e.g., 0 to 3 GHz), the signal flows in an area away from the surface of the conductor as shown in (a) of FIG. 2. Then, in a second frequency range (e.g., 3 to 7 GHz), the signal flows in an area adjacent to the surface of the conductor as shown in (b) of FIG. 2. Furthermore, in a third frequency range (e.g., 10 GHz or higher), the signal flows on the surface of the conductor as shown in (c) of FIG. 2.

[0055] Therefore, if the surface roughness Ra of the first circuit layer 20 exceeds 1.0 μm, the signal transmission loss increases in the high frequency band, making it difficult to apply the material to applications that use high frequencies.

[0056] Therefore, in the comparative example, the surface of the first circuit layer 20 is given a roughness Ra of 0.9 μm or less to minimize signal transmission loss in the high frequency band. However, when the surface roughness Ra of the first circuit layer 20 is reduced to 0.9 μm or less, the bonding strength between the first circuit layer 20 and the second insulating layer 30 decreases. This causes a problem that the second insulating layer 30 peels off from the first circuit layer 20.

[0057] Meanwhile, recently, a surface treatment technology has been provided that can reduce the surface roughness of the first circuit layer 20 to minimize signal transmission loss while improving the adhesive strength with the second insulating layer 30.

[0058] For example, in the comparative example, a copper oxide layer is formed by oxidizing the surface of the first circuit layer 20. As a result, roughness corresponding to the copper oxide layer is imparted to the surface of the first circuit layer 20. Then, in the comparative example, the copper oxide layer is reduced back to the original copper in a state in which the roughness corresponding to the copper oxide layer is imparted.

[0059] At this time, the adhesion between the copper constituting the first circuit layer 20 and the copper oxide layer is low. This causes a problem that the copper oxide layer separates from a part of the surface of the first circuit layer 20. Therefore, there is a problem that a certain level of roughness is not imparted to a part of the surface of the first circuit layer 20.

[0060] In addition, in the comparative example, a problem occurs in that a part of the copper oxide layer is not reduced to copper during the process of reducing the copper oxide layer back to copper, which causes a problem of degrading the electrical properties of the first circuit layer 20. In addition, in the case of the first circuit layer 20 of the comparative example, the content of hydroxide (OH) on the surface is low, which limits the improvement of the bonding strength with the second insulating layer 30.

[0061] Therefore, the embodiments provide a new surface treatment technology that can reduce the surface roughness of a circuit layer to minimize signal transmission loss while maintaining the electrical properties of the circuit layer, and further improve the bonding or adhesion to an insulating layer.

[0062] -Electronic Devices-

[0063] Prior to describing the embodiments, an electronic device including a semiconductor package according to the embodiments will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be electrically connected to the semiconductor package according to the embodiments. Various elements may be mounted on the semiconductor package.

[0064] For example, the semiconductor package may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory, as well as application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), antenna chips, digital signal processors, encryption processors, microprocessors, and microcontrollers, and logic chips such as analog-to-digital converters and ASICs (application-specific ICs).

[0065] For example, the semiconductor package may include at least one of various types of passive and active elements.

[0066] In this case, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, it is not limited thereto, and in addition to these, it may be any other electronic device that processes data.

[0067] Hereinafter, a circuit board and a semiconductor package according to the embodiment will be described in detail. Hereinafter, the circuit board may refer to a board before electronic elements are mounted thereon, and the semiconductor package may refer to a package in which electronic elements are mounted on the circuit board.

[0068] FIG. 3 is a cross-sectional view showing the circuit board according to the first embodiment, and FIG. 4 is a diagram for explaining the bonding relationship between the circuit layer, the buffer layer, and the second insulating layer of the embodiment.

[0069] 3 and 4, a circuit board can include an insulating layer and a circuit layer.

[0070] The insulating layer can include a first insulating layer 110 and a second insulating layer 140 .

[0071] The first insulating layer 110 and the second insulating layer 140 may include a prepreg PPG. The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass fiber yarn, with an epoxy resin or the like, and then performing thermocompression bonding. However, the embodiment is not limited thereto, and the prepreg constituting at least one of the first insulating layer 110 and the second insulating layer 140 may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

[0072] Additionally, at least one of the first insulating layer 110 and the second insulating layer 140 may be rigid or flexible.

[0073] At least one of the first insulating layer 110 and the second insulating layer 140 can have a thickness in the range of 10 μm to 60 μm. Preferably, at least one of the first insulating layer 110 and the second insulating layer 140 can have a thickness in the range of 12 μm to 50 μm. More preferably, at least one of the first insulating layer 110 and the second insulating layer 140 can have a thickness in the range of 15 μm to 40 μm.

[0074] If the thickness of at least one of the first insulating layer 110 and the second insulating layer 140 is less than 10 μm, the circuit layer 120 included in the circuit board may not be stably protected. If the thickness of at least one of the first insulating layer 110 and the second insulating layer 140 exceeds 60 μm, the thickness of the circuit board, the semiconductor package, and the electronic device including the same can increase. Also, if the thickness of at least one of the first insulating layer 110 and the second insulating layer 140 exceeds 60 μm, the thickness of the circuit layer 120 and the thickness of the vias (not shown) can increase correspondingly. And when the thickness of the circuit layer 120 and the thickness of the vias increase, the signal transmission loss can increase.

[0075] The circuit layer 120 can be disposed on the surface of the insulating layer.

[0076] The circuit layer 120 can be disposed on the surface of the first insulating layer 110 for signal transmission in the circuit board. For example, the circuit layer 120 can be disposed on the upper surface of the first insulating layer 110.

[0077] That is, FIG. 3 can show an area in the multilayer structure of the circuit board of the embodiment. For example, FIG. 3 can show the insulating layer regions disposed above and below the circuit layer 120 centered thereon.

[0078] For example, the circuit layer 120 can have a thickness in the range of 10 μm to 30 μm. Preferably, the circuit layer 120 can have a thickness in the range of 12 μm to 28 μm. More preferably, the circuit layer 120 can have a thickness in the range of 15 μm to 27 μm.

[0079] The circuit layer 120 may include a conductive material. For example, the circuit layer 120 may include at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the circuit layer 120 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0080] The circuit layer 120 can be formed by a typical circuit board manufacturing process such as an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP), and a detailed description thereof will be omitted here.

[0081] Although not shown in the drawings, the circuit layer 120 may include a nitride layer. For example, a nitride layer may be formed on a surface of the circuit layer 120 that is not in contact with the first insulating layer 110. Preferably, the circuit layer 120 is made of copper, and the nitride layer may be a copper nitride layer.

[0082] The circuit layer 120 includes multiple surfaces.

[0083] The circuit layer 120 may include a top surface 120T, a bottom surface 120B, a first side surface 120S1, and a second side surface 120S2.

[0084] Among the surfaces of the circuit layer 120, the lower surface 120B is the surface that comes into contact with the first insulating layer 110.

[0085] In this case, the nitride layer may be formed after the circuit layer 120 is formed on the first insulating layer 110. For example, the nitride layer may be formed on the surface of the circuit layer 120 before the second insulating layer 140 is laminated.

[0086] Therefore, the nitride layer may be formed on a surface of the circuit layer 120 that is not in contact with the first insulating layer 110. Preferably, the nitride layer may be formed on the top surface 120T, the first side surface 120S1, and / or the second side surface 120S2 of the surface of the circuit layer 120. The nitride layer may also be referred to as a surface layer of the top surface 120T, the first side surface 120S1, and / or the second side surface 120S2 of the circuit layer 120.

[0087] Thus, nitrogen (N) may be included in the top surface 120T, the first side surface 120S1, and / or the second side surface 120S2 of the circuit layer 120. The nitrogen (N) may be a functional group that bonds with the buffer layer 130 in the surface layer of the circuit layer 120.

[0088] The nitride layer may be formed by plasma treating the top surface 120T, the first side surface 120S1, and / or the second side surface 120S2 of the circuit layer 120.

[0089] For example, the nitride layer may include a nitride layer on the top surface 120T, the first side surface 120S1, and / or the second side surface 120S2 of the circuit layer 120. 2 or NH 3 The insulating layer can be formed by plasma treatment using

[0090] At this time, the N 2 When the circuit layer 120 is plasma treated using 2 The N 2 and H 2 When the circuit layer 120 is plasma-treated using these, the ratio thereof may be in the range of 1:3 to 3:1.

[0091] In the embodiment, in the manufacturing process of the circuit board, the surface of the circuit layer 120 is plasma treated before the second insulating layer 140 is laminated, so that a nitride layer having an atomic thickness may be formed on the surface of the circuit layer 120.

[0092] At this time, the reaction formula for forming the nitride layer is as follows:

[0093] (Reaction scheme)

[0094] N 2 +e - -> 2N+e -

[0095] 3Cu + +N 3- +e - -> C 3 N

[0096] 4Cu + +N 3- +e - -> C 3 N+Cu

[0097] As a result, the nitride layer formed on the surface of the circuit layer 120 is 3 N or C 3 N 2 or Cu 4 It may have the form N.

[0098] In this comparative example, before the second insulating layer is laminated, the surface of the circuit layer is roughened by chemical etching. However, when the circuit layer is roughened by chemical etching, the roughness Ra of the circuit layer exceeds 1.0 μm. If the roughness Ra of the circuit layer exceeds 1.0 μm, signal transmission loss may increase when transmitting high frequency band signals. If a certain level of roughness Ra is not imparted to the circuit layer, it is difficult to ensure the bonding strength or adhesion between the circuit layer and the second insulating layer.

[0099] In this embodiment, an additional process is performed on the circuit layer 120, and a process of providing roughness is not performed. As a result, in the embodiment, the surface of the circuit layer 120 may have fine roughness. For example, the surface of the circuit layer 120 in the embodiment has a roughness Ra corresponding to the nitride layer formed through the plasma treatment.

[0100] As described above, the nitride layer formed by the plasma treatment is selectively formed on the surface of the circuit layer 120. For example, the nitride layer is formed on the upper surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120 except for the lower surface 120B. As a result, the surface of the circuit layer 120 of the embodiment can have different roughnesses Ra in different regions.

[0101] The top surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120 may have corresponding roughnesses Ra. Here, having corresponding roughnesses may mean that the roughness deviation on the top surface 120S2, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120 is 50% or less, 40% or less, 30% or less, 15% or less, 10% or less, or 5% or less.

[0102] The roughness Ra of the upper surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120 may be in the range of 0.1 μm to 0.9 μm. Preferably, the roughness Ra of the upper surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120 may be in the range of 0.1 μm to 0.7 μm. More preferably, the roughness Ra of the upper surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120 may be in the range of 0.1 μm to 0.5 μm. This can be achieved by not performing a process of providing roughness by etching the upper surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120.

[0103] If the roughness Ra of the top surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120 is less than 0.1 μm, it may affect the bonding strength or adhesion to the second insulating layer 140. If the roughness Ra of the top surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120 is less than 0.1 μm, it may affect the bonding strength or adhesion to the buffer layer 130 disposed on the surface of the circuit layer 120.

[0104] Furthermore, if the roughness Ra of the top surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120 exceeds 0.9 μm, the transmission loss of a signal transmitted through the circuit layer 120 may increase. For example, if the roughness Ra of the top surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120 exceeds 0.9 μm, it may be difficult to use the circuit layer 120 in a product that transmits a high-frequency band signal.

[0105] Meanwhile, the roughness Ra of the lower surface 120B of the circuit layer 120 may be different from the roughness Ra of the upper surface 120T, the first side 120S1, and / or the second side 120S2 of the circuit layer 120. Preferably, the roughness Ra of the lower surface 120B of the circuit layer 120 may be greater than the roughness Ra of the upper surface 120T, the first side 120S1, and / or the second side 120S2 of the circuit layer 120.

[0106] The roughness Ra of the lower surface 120B of the circuit layer 120 may be in the range of 0.6 μm to 0.9 μm. Preferably, the roughness Ra of the lower surface 120B of the circuit layer 120 may be in the range of 0.65 μm to 0.9 μm. More preferably, the roughness Ra of the lower surface 120B of the circuit layer 120 may be in the range of 0.7 μm to 0.9 μm.

[0107] If the roughness Ra of the lower surface 120B of the circuit layer 120 is less than 0.6 μm, the adhesion or bonding strength between the circuit layer 120 and the first insulating layer 110 may be reduced. This may cause a problem that the circuit layer 120 peels off from the first insulating layer 110.

[0108] Furthermore, if the roughness Ra of the lower surface 120B of the circuit layer 120 exceeds 0.9 μm, the transmission loss of the signal transmitted through the circuit layer 120 increases, which may make it difficult to apply the circuit layer 120 to products using high frequency bands.

[0109] Meanwhile, the plasma treatment is performed on the entire exposed surface of the first insulating layer 110 with the circuit layer 120 disposed thereon.

[0110] Thus, the plasma treatment may be performed on the upper surface of the first insulating layer 110 on which the circuit layer 120 is not disposed. For example, the upper surface of the first insulating layer 110 may contain nitrogen (N).

[0111] In conclusion, in the embodiment, the surface of the circuit layer 120 and the surface of the first insulating layer 110 are plasma-treated using nitrogen (N) to form first functional groups (e.g., nitride groups) containing nitrogen (N) on the surfaces of the circuit layer 120 and the first insulating layer 110.

[0112] In an embodiment, a nitride layer containing nitrogen (N) is formed on the surface of the circuit layer 120. As a result, in an embodiment, the adhesion or bonding strength between the circuit layer 120 and the second insulating layer 140 can be improved without imparting a certain level of roughness to the surface of the circuit layer 120. This can be achieved by a buffer layer 130 disposed on the circuit layer 120.

[0113] The buffer layer 130 may be selectively formed on a surface of the circuit layer 120. Preferably, the buffer layer 130 may be formed on a surface of the circuit layer 120 that is not in contact with the first insulating layer 110. Specifically, the buffer layer 130 may be formed on a top surface 120T, a first side surface 120S1, and / or a second side surface 120S2 of the circuit layer 120.

[0114] The buffer layer 130 may have a certain level of roughness. In this case, the buffer layer 130 is formed in a thin film shape on the surface of the circuit layer 120. Thus, the roughness Ra of the buffer layer 130 may correspond to the roughness Ra of the circuit layer 120. Specifically, the roughness Ra of the buffer layer 130 may correspond to the roughness Ra of any one of the surface roughness Ra of the upper surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120.

[0115] The buffer layer 130 may have a thickness in the range of 10 nm to 50 nm. Preferably, the buffer layer 130 may have a thickness in the range of 12 nm to 48 nm. More preferably, the buffer layer 130 may have a thickness in the range of 15 nm to 45 nm.

[0116] If the thickness of the buffer layer 130 is less than 10 nm, the thickness of the buffer layer 130 is too thin, and the effect achieved by the buffer layer 130 may be insufficient. For example, if the thickness of the buffer layer 130 is less than 10 nm, the adhesion or bonding strength between the circuit layer 120 and the second insulating layer 140 may not be ensured.

[0117] In addition, if the thickness of the buffer layer 130 exceeds 50 nm, the process time for forming the buffer layer 130 may increase, and the process cost may increase. In addition, if the thickness of the buffer layer 130 exceeds 50 nm, the adhesion strength may not increase as the thickness of the buffer layer 130 increases. For example, the adhesion strength between the circuit layer 120 and the second insulating layer 140 when the thickness of the buffer layer 130 exceeds 50 nm may be similar to the adhesion strength between the circuit layer 120 and the second insulating layer 140 when the thickness of the buffer layer 130 is less than 50 nm. In addition, if the thickness of the buffer layer 130 exceeds 50 nm, the dielectric constant of the first insulating layer 110 or the second insulating layer 140 may be affected, which may make it difficult to apply the buffer layer 130 to products using high frequency bands.

[0118] The buffer layer 130 may include a number of elements.

[0119] The elements contained in the buffer layer 130 may be bonded to each other in the buffer layer 130 in a molecular form or in an ionic form, and the molecules, the molecules, and the molecules and the ions may be chemically bonded to each other to form the buffer layer 130.

[0120] The buffer layer 130 may include a plurality of functional groups. For example, the buffer layer 130 may include a first functional group and a second functional group. The first functional group may function to increase the adhesion between the buffer layer 130 and the circuit layer 120. The second functional group may function to increase the adhesion between the buffer layer 130 and the second insulating layer 140. In conclusion, the first functional group and the second functional group of the buffer layer 130 may function to increase the adhesion between the circuit layer 120 and the second insulating layer 140.

[0121] The buffer layer 130 may include at least one of copper, silicon, oxygen, hydrogen, carbon, sulfur, and nitrogen. In the buffer layer 130, the copper, oxygen, hydrogen, carbon, silicon, sulfur, and nitrogen elements may be bonded to each other in a molecular form or may be present in a single ionic form.

[0122] Some of the elements included in the buffer layer 130 may correspond to a first functional group of the buffer layer 130 that is bonded to the circuit layer 120. For example, a copper element and a nitrogen element included in the buffer layer 130 may correspond to a first functional group of the buffer layer 130 that is bonded to the circuit layer 120. For example, the first functional group of the buffer layer 130 may chemically bond to the circuit layer 120.

[0123] In addition, a remaining portion of the plurality of elements included in the buffer layer 130 may correspond to a second functional group of the buffer layer 130 that is bonded to the second insulating layer 140. The second functional group included in the buffer layer 130 may chemically bond to the second insulating layer 140.

[0124] Meanwhile, the molecules included in the buffer layer 130 may include at least two kinds of molecules depending on the size of the molecule or the size of the molecular weight. For example, the molecules may include a macromolecule and a unimolecular. For example, the macromolecule, the unimolecular, and the metal ion in the buffer layer 130 may have a structure in which they are chemically bonded and connected to each other by covalent bonds and coordinate bonds in the buffer layer 130.

[0125] The buffer layer 130 will now be described in detail.

[0126] The buffer layer 130 includes a first functional group and a second functional group. The first functional group and the second functional group may be defined as an end group of the buffer layer 130 that is connected to any one of a macromolecule, a monomolecule, or a metal ion that constitutes the buffer layer 130.

[0127] The buffer layer 130 may be formed of an organosilane agent containing an azole group. Preferably, the buffer layer 130 may be formed of a solution in which copper ions are added to an organosilane agent containing an azole group. The copper ions are Cu 2 + or Cu+, but is not limited to this.

[0128] Accordingly, the buffer layer 130 may have a structure as shown in Formula 1 below.

[0129] [ka]

[0130] The number 1 in Formula 1 may correspond to a first functional group of the buffer layer 130. That is, the buffer layer 130 may include a first functional group containing nitrogen. For example, the first functional group may include at least one azole group selected from the group consisting of diazole, triazole, tetraazole, benzotriazole, benzothiazole, and nitrotriazole.

[0131] The first functional group may act to improve the adhesion between the buffer layer 130 and the circuit layer 120 and to improve the cohesiveness of the buffer layer 130 .

[0132] For example, the first functional group of the buffer layer 130 can chemically bond with the circuit layer 120. Preferably, the first functional group of the buffer layer 130 can coordinately bond with nitrogen (N) of a nitride layer of the circuit layer 120.

[0133] In addition, the first functional group may form a coordinate bond with a metal ion contained in the buffer layer 130. For example, the buffer layer 130 may include copper ions. The first functional group may form a coordinate bond with the copper ions.

[0134] In this case, when the first functional group is used to form a coordinate bond with nitrogen (N) of the circuit layer 120, the adhesion between the circuit layer 120 and the buffer layer 130 can be ensured, but the internal cohesiveness of the buffer layer 130 itself may be reduced. If the internal cohesiveness of the buffer layer 130 is reduced, a peeling problem may occur in the buffer layer 130. Therefore, in an embodiment, the buffer layer 130 contains copper ions, which are metal ions, and the copper ions form a coordinate bond with the first functional group, thereby improving the adhesion between the buffer layer 130 and the circuit layer 120 and also improving the internal cohesiveness of the buffer layer 130.

[0135] At this time, the copper ions of the buffer layer 130 may be bonded to the first functional group to form a polymer network, which may be expressed by the following Equation 2:

[0136] [ka]

[0137] Furthermore, the copper ions contained in the buffer layer 130 may be bonded to the circuit layer 120. Preferably, the copper ions contained in the buffer layer 130 may be bonded to a nitride layer of the circuit layer 120. More preferably, the copper ions contained in the buffer layer 130 may be coordinately bonded to a nitride group including nitrogen (N) corresponding to the nitride layer of the circuit layer 120.

[0138] That is, in the embodiment, the first functional group of the buffer layer 130 and the nitride layer of the circuit layer 120 are coordinately bonded, and further, the copper ion of the buffer layer 130 and the nitride layer of the circuit layer 120 are coordinately bonded. As a result, in the embodiment, the internal cohesive force of the buffer layer 130 can be improved, and the adhesion between the buffer layer 130 and the circuit layer 120 can be further improved.

[0139] The number 3 in Formula 1 may correspond to a second functional group of the buffer layer 130. Preferably, the buffer layer 130 may include a second functional group that chemically bonds with the second insulating layer 140. The second functional group may include a siloxane group.

[0140] In this case, the silonic acid group in the first embodiment can contain methyl as shown in formula 1. For example, the second functional group in the first embodiment can be Si(OMe) 3 For example, the second functional group in the first embodiment may be a trimethylsiloxane group or a triethylsiloxane group.

[0141] However, the second functional group in the embodiment is not limited thereto. For example, the second functional group of the buffer layer 130 may be a siloxane group containing OH-, as shown in FIG.

[0142] Furthermore, the number 2 in the formula 1 may correspond to the alkyl group (R) contained in the buffer layer 130. The n of the alkyl group (R) in the formula 1 may be 3 to 5. The alkyl group (R) may have an alkyl chain or an aromatic ring shape. For example, the alkyl group (R) may have an alkyl chain shape containing sulfur or nitrogen.

[0143] Referring to FIG. 4, the bonding relationship between the circuit layer 120, the buffer layer 130 and the second insulating layer 140 of the embodiment will be described.

[0144] A nitride layer is formed on the surface of the circuit layer 120. For example, functional groups 121 containing nitrogen (N) are formed on the surface of the circuit layer 120.

[0145] At this time, as described above, the plasma treatment may be performed not only on the surface of the circuit layer 120 but also on the upper surface of the first insulating layer 110. Then, functional groups 111 containing nitrogen (N) may be formed on the upper surface of the first insulating layer 110. Then, the functional groups 111 of the first insulating layer 110 may be bonded to functional groups contained in the second insulating layer 140. For example, the functional groups 111 of the first insulating layer 110 may be covalently bonded to functional groups such as -NH or -OH of the second insulating layer 140. Thus, the embodiment may ensure not only the adhesion between the circuit layer 120 and the second insulating layer 140 but also the adhesion between the first insulating layer 110 and the second insulating layer 140. That is, the functional groups 111 of the first insulating layer 110 may be covalently bonded to functional groups such as -NH or -OH of the second insulating layer 140. 2 , NH, ≡NO 2 The functional group may be a nitrogen-containing chemical functional group such as

[0146] The buffer layer 130 may include a first functional group 130a. The first functional group 130a may be an azole group containing nitrogen (N). The first functional group 130a may form a coordinate bond with the functional group 121 of the circuit layer 120. This may improve the adhesion between the buffer layer 130 and the circuit layer 120.

[0147] The buffer layer 130 also includes an alkyl group 130b. The alkyl group 130b may be bonded between the first functional group 130a and the second functional group 130c.

[0148] The buffer layer 130 may include the second functional group 130c. The second functional group 130c may be a siloxane group. In one example, the second functional group 130c may include an —OH group.

[0149] The second functional group 130c can be covalently bonded to a functional group such as an -NH group or an -OH group of the second insulating layer 140. This can improve the adhesion between the buffer layer 130 and the second insulating layer 140, and further between the circuit layer 120 and the second insulating layer 140.

[0150] The buffer layer 130 includes copper ions 130d. The copper ions 130d include a first ion group 130d1 that exists alone in the buffer layer 130. The copper ions 130d may also include a second ion group 130d2 that is coordinate-bonded to any one of the first functional group 130a of the buffer layer 130 and the functional group 121 of the circuit layer 120.

[0151] The embodiment can improve the reliability of the circuit board.

[0152] Advantageously, the embodiments may improve the electrical and physical reliability of the circuit board.

[0153] To this end, in the embodiment, a nitrogen-containing functional group is formed on a surface of a circuit layer disposed on a first insulating layer. For example, in the embodiment, the surface of the circuit layer is plasma-treated to form a nitride layer. Then, in the embodiment, a buffer layer is formed on the nitride layer of the circuit layer.

[0154] The buffer layer includes a first functional group that bonds with the circuit layer and a second functional group that bonds with a second insulating layer disposed on the circuit layer. The first functional group may be an azole group. The first functional group may be coordinately bonded with a functional group containing nitrogen (N) formed on the surface of the circuit layer. Also, the second functional group may be covalently bonded with a functional group included in the second insulating layer. To this end, the buffer layer may be formed of an organosilane agent containing an azole group.

[0155] As a result, the embodiment can improve adhesion between the circuit layer and the second insulating layer by using the buffer layer, thereby resolving a physical reliability problem that the second insulating layer peels off from the circuit layer.

[0156] In this embodiment, the upper surface of the first insulating layer is also plasma-treated when the circuit layer is plasma-treated. As a result, a functional group containing nitrogen (N) may be formed on the upper surface of the first insulating layer. The functional group formed on the upper surface of the first insulating layer may be shared with the functional group of the second insulating layer. As a result, the embodiment can improve not only the adhesion between the circuit layer and the second insulating layer, but also the adhesion between the first insulating layer and the second insulating layer.

[0157] In addition, the buffer layer of the embodiment includes metal ions. Preferably, the buffer layer includes copper ions. In this case, the copper ions can be coordinated with a nitrogen (N)-containing functional group of the circuit layer. Through this, the embodiment can further improve the adhesion between the buffer layer and the circuit layer.

[0158] Furthermore, the copper ions contained in the buffer layer may form a coordinate bond with the first functional group of the buffer layer. Thus, the embodiment may strengthen the internal cohesion of the buffer layer through the coordinate bond between the first functional group and the copper ions. Thus, the embodiment may further improve the adhesion between the circuit layer and the second insulating layer.

[0159] On the other hand, in the embodiment, the adhesion between the circuit layer and the second insulating layer is ensured by using the functional group of the circuit layer and the first and second functional groups of the buffer layer. As a result, in the embodiment, an additional roughening step for ensuring the adhesion to the circuit layer is not required. As a result, in the embodiment, deformation of the circuit layer can be prevented, and the electrical properties of the circuit layer can be improved.

[0160] In addition, the embodiment can provide a circuit layer having a surface with fine roughness. This can be achieved by using the buffer layer to ensure the adhesion and thereby reducing the surface roughness of the circuit layer. As a result, the circuit layer of the embodiment can satisfy the surface roughness Ra range of 0.1 μm to 0.9 μm. Therefore, the embodiment can minimize the transmission loss of signals transmitted through the circuit layer. Furthermore, the embodiment can provide a circuit board applicable to products using high frequency bands.

[0161] Meanwhile, in the embodiment, the surface roughness Ra of the circuit layer 120 has fine roughness, and the adhesion between the circuit layer 120 and the second insulating layer 140 can be improved.

[0162] Preferably, the adhesion strength (90° Peel Strength) between the circuit layer 120 and the second insulating layer 140 in the embodiment may be in the range of 0.55 to 1.5 kgf / cm.

[0163] The adhesion strength (90° Peel Strength) can be measured by the following method: Figures 5 and 6 are diagrams for explaining a method for measuring the adhesion strength (90° Peel Strength) of a circuit board according to an embodiment.

[0164] Referring to FIG. 5, an embodiment prepares a base material for testing adhesion (90° Peel Strength). For example, an embodiment prepares a carrier board CB. The carrier board CB may be a CCL. For example, the carrier board CB may include a carrier insulating layer CB1 and a carrier copper foil layer CB2 disposed on both sides of the carrier insulating layer CB1.

[0165] Then, in the embodiment, a second insulating layer 140 is disposed on the carrier substrate CB, and a circuit layer 120 having a buffer layer 130 formed thereon according to the embodiment is attached on the second insulating layer 140.

[0166] Next, referring to FIG. 6, in the embodiment, an adhesion strength (90° Peel Strength) test is performed on a region A of the circuit layer 120 including the buffer layer 130.

[0167] The 90° Peel Strength test may be carried out in the following order:

[0168] (1) In the adhesion (90° Peel Strength) test, the circuit layer 120 on which the buffer layer 130 is formed is bonded together with the second insulating layer 140 onto the carrier substrate CB.

[0169] (2) Forming a sheath on one area of ​​the circuit layer 120 (e.g., a 1 cm wide area)

[0170] (3) Resistance-peel strength measurement when applying force at 90° to separate the area where the sheath is formed

[0171] The adhesion (90° Peel Strength) test can be performed according to an international standard for evaluation, such as ASTM-D6862.

[0172] In the embodiment thus tested, the adhesion strength (90° Peel Strength) between the circuit layer 120 and the second insulating layer 140 may be in the range of 0.55 to 1.5 kgf / cm.

[0173] Furthermore, the embodiment may also improve the adhesion between the first insulating layer 110 and the second insulating layer 140. At this time, the adhesion between the first insulating layer 110 and the second insulating layer 140 may be tested through a thermal reliability test such as IR reflow or solder dup.

[0174] FIG. 7 is a cross-sectional view showing a circuit board according to the second embodiment.

[0175] Referring to FIG. 7, the circuit board includes a first insulating layer 110 .

[0176] Furthermore, a circuit layer 120 is disposed on the first insulating layer 110 .

[0177] A buffer layer 130 is disposed on the upper surface of the first insulating layer 110 and on the circuit layer 120 .

[0178] A second insulating layer 140 is disposed on the buffer layer 130 .

[0179] According to the second embodiment, the buffer layer 130 is divided into a plurality of portions.

[0180] That is, the buffer layer 130 of the first embodiment is formed only on the top surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120.

[0181] Alternatively, the buffer layer 130 of the second embodiment may include a first portion 131 formed on the circuit layer 120 and a second portion 132 disposed on the upper surface of the first insulating layer 110 .

[0182] The first portion 131 of the buffer layer 130 may be disposed on the top surface 120T, the first side surface 120S1, and the second side surface 120S2 of the circuit layer 120. The first portion 131 of the buffer layer 130 may improve the adhesion between the circuit layer 120 and the second insulating layer 140.

[0183] The second portion 132 of the buffer layer 130 may be disposed in an area of ​​the upper surface of the first insulating layer 110 where the circuit layer 120 is not disposed. The second portion 132 of the buffer layer 130 may improve the adhesion between the first insulating layer 110 and the second insulating layer 140. However, the organic silane agent used to form the buffer layer 130 has a higher reactivity with the circuit layer 120 than with the first insulating layer 110. As a result, the buffer layer 130 may be formed in a concentrated manner on the circuit layer 120. However, in the second embodiment, the second portion 132 of the buffer layer 130 may be formed on at least a portion of the upper surface of the first insulating layer 110.

[0184] 7, the second portion 132 of the buffer layer 130 is illustrated as being entirely formed on the upper surface of the insulating layer 110, but is not limited thereto. Preferably, the second portion 132 of the buffer layer 130 may be partially formed on an upper surface region of the first insulating layer 110 where the circuit layer 120 is not disposed.

[0185] FIG. 8 is a cross-sectional view showing a circuit board according to the third embodiment.

[0186] Referring to FIG. 8, the circuit board of the third embodiment can have a multi-layer structure.

[0187] For example, a circuit board includes an insulating layer.

[0188] The insulating layers include a first insulating layer 211, a second insulating layer 212, and a third insulating layer 213. In this case, the circuit board is shown in the drawings as having a three-layer structure based on the number of insulating layers, but is not limited thereto. For example, the circuit board may have four or more layers based on the number of insulating layers.

[0189] The first insulating layer 211 may be an inner insulating layer located on the inner layer of the circuit board.

[0190] In addition, the second insulating layer 212 and the third insulating layer 213 may be outer insulating layers located on the outer layers of the circuit board. In addition, when the circuit board has four or more insulating layers, the inner insulating layer may include a plurality of first insulating layers.

[0191] The circuit board includes a circuit layer.

[0192] Specifically, the circuit layer includes a first circuit layer 221 disposed on an upper surface of the first insulating layer 211. The circuit layer also includes a second circuit layer 222 disposed on an upper surface of the second insulating layer 212. The circuit layer also includes a third circuit layer 223 disposed on a lower surface of the first insulating layer 211. The circuit layer also includes a fourth circuit layer 224 disposed on a lower surface of the third insulating layer 213.

[0193] The first circuit layer 221 and the third circuit layer 223 may be inner circuit layers located on the inner layer of a circuit board, and the second circuit layer 222 and the fourth circuit layer 224 may be outer circuit layers located on the outer layer of a circuit board.

[0194] The circuit board includes a buffer layer. Preferably, the circuit board of the embodiment includes a buffer layer disposed on each circuit layer.

[0195] A first buffer layer 231 is formed on the first circuit layer 221. The first buffer layer 231 may be formed to surround an upper surface and a side surface of the first circuit layer 221. The first buffer layer 231 may improve adhesion between the first circuit layer 221 and the second insulating layer 212.

[0196] The second buffer layer 232 is formed on the second circuit layer 222. The second buffer layer 232 may be formed to surround the upper surface and side surfaces of the second circuit layer 222. The second buffer layer 232 can improve the adhesion between the second circuit layer 222 and the first protective layer 251. That is, in the embodiment, a buffer layer is formed not only on the inner circuit layer but also on the outer circuit layer. As a result, in the embodiment, the adhesion between the outer circuit layer and the protective layer can be improved.

[0197] A third buffer layer 233 is formed on the third circuit layer 223. The third buffer layer 233 may be formed to surround a lower surface and a side surface of the third circuit layer 223. The third buffer layer 233 may improve adhesion between the third circuit layer 223 and the third insulating layer 213.

[0198] A fourth buffer layer 234 is formed on the fourth circuit layer 224. The fourth buffer layer 234 may be formed to surround a lower surface and a side surface of the fourth circuit layer 224. The fourth buffer layer 234 may improve adhesion between the fourth circuit layer 224 and the second protective layer 252.

[0199] The circuit board includes a through electrode, which can penetrate at least one of the insulating layers.

[0200] The circuit board includes a first through-hole electrode 241. The first through-hole electrode 241 penetrates the first insulating layer 211. The first through-hole electrode 241 electrically connects the first circuit layer 221 and the third circuit layer 223. At this time, the side of the first through-hole electrode 241 may have a roughness Ra different from the roughness Ra of the upper surface or the side of the first circuit layer 221. That is, the upper surface or the side of the first circuit layer 221 may have a fine roughness by securing adhesion through the plasma treatment as described above. In contrast, the side of the first through-hole electrode 241 may have a roughness Ra larger than the roughness Ra of the upper surface or the side of the first circuit layer 221.

[0201] The circuit board includes a second through electrode 242. The second through electrode 242 penetrates the second insulating layer 212. The second through electrode 242 electrically connects the first circuit layer 221 and the second circuit layer 222. The side of the second through electrode 242 may have a roughness Ra greater than the roughness Ra of the top surface or side surface of the second circuit layer 222. Meanwhile, in the drawings, the second through electrode 242 is illustrated as being disposed on the first buffer layer 231, but the first buffer layer 231 is not disposed on the first circuit layer 221 that overlaps vertically with the second through electrode 242. As a result, the second through electrode 242 directly contacts the top surface of the first circuit layer 221.

[0202] The circuit board includes a third through electrode 243. The third through electrode 243 penetrates the third insulating layer 213. The third through electrode 243 electrically connects the third circuit layer 223 and the fourth circuit layer 224. The side of the fourth through electrode 234 may have a roughness Ra greater than the roughness Ra of the side or lower surface of the third circuit layer 223 and the roughness Ra of the side or lower surface of the fourth circuit layer 224. Meanwhile, in the drawings, the third through electrode 243 is illustrated as being disposed on the third buffer layer 233, but the third buffer layer 233 is not disposed on the third circuit layer 223 that overlaps the third through electrode 243 vertically. Thus, the third through electrode 243 is in direct contact with the upper surface of the third circuit layer 223.

[0203] The circuit board includes a protective layer that protects the surfaces of the insulating layer and the circuit layer of the outer layer of the circuit board.

[0204] The protective layer includes a first protective layer 251 disposed on the second insulating layer 212. The first protective layer 251 can protect an upper surface of the second insulating layer 212 and an upper surface of the second circuit layer 222. The first protective layer 251 can include an opening (not shown) overlapping at least a portion of the upper surface of the second circuit layer 222 in a thickness direction.

[0205] The protective layer includes a second protective layer 252 disposed on the third insulating layer 213. The second protective layer 252 may protect a lower surface of the third insulating layer 213 and a lower surface of the fourth circuit layer 224. The second protective layer 252 may include an opening (not shown) overlapping at least a portion of the lower surface of the fourth circuit layer 224 in a thickness direction.

[0206] As described above, the circuit board of the third embodiment has a multi-layer structure. A buffer layer is formed on each circuit layer included in the multi-layer circuit board. Furthermore, in the embodiment, a buffer layer is also formed on the outermost circuit layer. Through this, the embodiment can improve the adhesion between the circuit layer and the protective layer.

[0207] Meanwhile, in the drawings, the buffer layer is also formed in the regions of the surfaces of the second circuit layer 222 and the fourth circuit layer 224 that overlap with the openings of the first protective layer 251 and the second protective layer 252 in the thickness direction, but this is not limited to this. For example, in the drawings, the buffer layer is not formed in the regions of the surfaces of the second circuit layer 222 and the fourth circuit layer 224 that overlap with the openings of the first protective layer 251 and the second protective layer 252 in the thickness direction, so that a connection portion for mounting a chip can be disposed.

[0208] The layer structure of the circuit layers and through electrodes included in the circuit board of the embodiment will be described below.

[0209] FIG. 9 is a cross-sectional view showing the layer structure of the circuit layer and the through electrode according to the first embodiment, and FIG. 10 is a cross-sectional view showing the layer structure of the circuit layer and the through electrode according to the second embodiment.

[0210] The following mainly describes one of the first circuit layer 221 to the fourth circuit layer 224. For example, the layer structure of the first circuit layer 221 will be described below. However, the layer structures of the second circuit layer 222, the third circuit layer 223, and the fourth circuit layer 224 can correspond to the layer structure of the first circuit layer 221 described below.

[0211] Therefore, in the following description, the first insulating layer 211 will be referred to as an insulating layer, the first circuit layer 221 will be referred to as a circuit layer, and the first through electrode 241 will be referred to as a through electrode.

[0212] Referring to FIG. 9, the circuit board of the first embodiment can be manufactured by the MSAP method.

[0213] In this case, the circuit layer may include a first layer and a second layer.

[0214] The first layer of the circuit layer may refer to the first and second metal layers described below, and the second layer of the circuit layer may refer to the third metal layer described below.

[0215] The following description will focus on the first to third metal layers of the circuit layer.

[0216] On the other hand, the circuit board includes an insulating layer 211 , a circuit layer 221 , and a through electrode 231 .

[0217] The circuit layer 221 may include a first metal layer 221-1 and a second metal layer 221-2.

[0218] The first metal layer 221-1 of the circuit layer 221 may be disposed on the upper surface of the insulating layer 211. The first metal layer 221-1 of the circuit layer 221 may refer to a seed layer of the circuit layer 221.

[0219] At this time, the circuit layer 221 is manufactured by an MSAP process, so that the first metal layer 221-1 of the circuit layer 221 may be composed of a plurality of layers.

[0220] Preferably, the first metal layer 221-1 of the circuit layer 221 may include a 1-1 metal layer 221-1a and a 1-2 metal layer 221-1b.

[0221] The 1-1 metal layer 221-1a of the first metal layer 221-1 of the circuit layer 221 may be disposed on the upper surface of the insulating layer 211. The 2-1 metal layer 221-1a of the first metal layer 221-1 of the circuit layer 221 may refer to a copper foil layer disposed on the upper surface of the insulating layer 211. For example, the 1-1 metal layer 221-1a of the first metal layer 221-1 of the circuit layer 221 may refer to copper foil (Cu foil). The 1-1 metal layer 221-1a of the first metal layer 221-1 of the circuit layer 221 may have a thickness in the range of 2 μm to 5 μm.

[0222] The 1-2 metal layer 221-1b of the first metal layer 221-1 of the circuit layer 221 may be disposed on the 1-1 metal layer 221-1a. For example, the 1-2 metal layer 221-1b of the first metal layer 221-1 of the circuit layer 221 may be formed by performing electroless plating on the 1-1 metal layer 221-1a. Preferably, the 1-2 metal layer 221-1b of the first metal layer 221-1 of the circuit layer 221 may be a chemical copper plating layer. The 1-2 metal layer 221-1b of the first metal layer 221-1 of the circuit layer 221 may have a thickness in the range of 0.2 μm to 2 μm.

[0223] The second metal layer 221-2 of the circuit layer 221 is disposed on the first metal layer 221-1 of the circuit layer 221. For example, the second metal layer 221-2 of the circuit layer 221 is disposed on the 1-2 metal layer 221-1b of the first metal layer 221-1 of the circuit layer 221. For example, the second metal layer 221-2 of the circuit layer 221 may be an electrolytic plating layer formed by electrolytic plating using the 1-2 metal layer 221-1b as a seed layer. The second metal layer 221-2 of the circuit layer 221 may have a thickness in the range of 15 μm to 30 μm. In this case, the second metal layer 221-2 of the circuit layer 221 may be composed of a plurality of layers. For example, the second metal layer 221-2 of the circuit layer 221 may include, but is not limited to, a flash electrolytic copper plating layer and a pattern electrolytic copper plating layer.

[0224] Meanwhile, the through electrode 231 may penetrate the insulating layer 211. For example, the through electrode 231 may be formed by filling a through hole penetrating the insulating layer 211 with a conductive material. In this case, the through electrode 231 may be formed simultaneously with the process of forming the circuit layer 221.

[0225] Preferably, the through electrode 231 includes a first metal layer 231-1 corresponding to the first metal layer 221-1 of the circuit layer 221. Preferably, the first metal layer 231-1 of the through electrode 231 may correspond to a 1-2 metal layer 221-1b of the first metal layer 221-1 of the circuit layer 221.

[0226] Specifically, the 1-2 metal layer 221-1b of the first metal layer 221-1 of the circuit layer 221 and the first metal layer 231-1 of the through electrode 231 may refer to one layer formed by a chemical copper plating process. However, the 1-2 metal layer 221-1b of the first metal layer 221-1 of the circuit layer 221 and the first metal layer 231-1 of the through electrode 231 may be distinguished according to the arrangement position of the chemical copper plating layer.

[0227] For example, the 1-2 metal layer 221-1b of the first metal layer 221-1 of the circuit layer 221 may refer to a portion of one chemical copper plating layer that contacts the 1-1 metal layer 221-1a of the first metal layer 221-1 of the circuit layer 221.

[0228] For example, the first metal layer 231-1 of the through electrode 231 may refer to a portion of one chemical copper plating layer that contacts an inner wall of a through hole penetrating the insulating layer 211.

[0229] Meanwhile, the through electrode 231 may include a second metal layer 231-2. The second metal layer 231-2 of the through electrode 231 may correspond to the second metal layer 221-2 of the circuit layer 221.

[0230] Preferably, the through electrode 231 includes a second metal layer 231-2 corresponding to the second metal layer 221-2 of the circuit layer 221. That is, the second metal layer 221-2 of the circuit layer 221 and the second metal layer 231-2 of the through electrode 231 may refer to a single layer formed by electrolytic plating using the chemical copper plating layer as a seed layer. However, the second metal layer 221-2 of the circuit layer 221 and the second metal layer 231-2 of the through electrode 231 may be distinguished according to the arrangement position of the electrolytic plating layer.

[0231] For example, the second metal layer 231-2 of the through electrode 231 may refer to a portion of one electrolytic plating layer disposed within the through hole of the insulating layer 211. For example, the second metal layer 221-2 of the circuit layer 221 may refer to a portion of one electrolytic plating layer disposed outside the through hole.

[0232] On the other hand, the circuit layers of the circuit board of the second embodiment shown in FIG. 10 may have a different number of layers from the circuit layers of the circuit board of the first embodiment shown in FIG.

[0233] For example, the through electrodes of the circuit board of the second embodiment may have substantially the same structure as the through electrodes of the circuit board of the first embodiment.

[0234] However, the circuit layer 221 of the circuit board of the second embodiment may have a different number of layers than the circuit layers of the circuit board of the first embodiment.

[0235] For example, the circuit layer 221 of the circuit board of the second embodiment includes a first metal layer 221-1 and a second metal layer 221-2.

[0236] At this time, the first metal layer 221-1 of the circuit layer of the circuit board of the first embodiment includes a 1-1 metal layer 221-1a and a 1-2 metal layer 221-1b.

[0237] Alternatively, the first metal layer 221-1 of the circuit layer 221 of the circuit board of the second embodiment may be composed of one layer. For example, the circuit layer 221 of the circuit board of the second embodiment may include only the 1-2 metal layer 221-1b in the first metal layer of the first embodiment.

[0238] That is, the circuit board of the second embodiment can be manufactured by the SAP method. In the process of forming a circuit layer by the SAP method, the copper foil layer or copper foil corresponding to the 1-1 metal layer 221-1a arranged on the surface of the insulating layer can be removed. As a result, the first metal layer corresponding to the seed layer in the circuit board of the second embodiment can include only the 1-2 metal layer 221-1b corresponding to the chemical copper plating layer. In the second embodiment, the first metal layer 221-1 corresponding to the 1-2 metal layer 221-1b can be in direct contact with the upper surface of the insulating layer 211.

[0239] FIG. 11 is a diagram illustrating a semiconductor package according to an embodiment.

[0240] Referring to Fig. 11, a semiconductor package includes a chip mounted on a circuit board of an embodiment. The chip may be at least one. For example, the chip may be at least one processor chip. Alternatively, the chip may include at least two processor chips. Alternatively, the chip may include at least one processor chip and at least one memory chip.

[0241] The semiconductor package includes a first connection portion 310. Specifically, a second circuit layer 222 disposed on the top side of the circuit board includes a pad, and the pad of the circuit layer 222 overlaps with the opening of the first protective layer 251 vertically.

[0242] In this case, a buffer layer may not be formed on the top surface of the circuit layer corresponding to the pad among the second circuit layer 222. Therefore, the first connection part 310 may be disposed directly on the pad.

[0243] The first connection portion 310 is disposed on a pad of the second circuit layer 222 that vertically overlaps with the opening of the first protective layer 251 .

[0244] The first connection part 310 may have a spherical shape. For example, a cross section of the first connection part 310 may have a circular or semicircular shape. For example, a cross section of the first connection part 310 may have a partially or entirely rounded shape. For example, the cross section of the first connection part 310 may have a flat surface on one side and a curved surface on the other side. The first connection part 310 may be, but is not limited to, a solder ball.

[0245] The semiconductor package may include a chip 320 or an element 320 disposed on the first connection portion 310 .

[0246] The chip 320 may be a processor chip, for example, an application processor (AP) chip such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller.

[0247] At this time, the chip 320 may include a terminal 325 on a bottom surface thereof, and the terminal 325 may be electrically connected to the second circuit layer 222 of the circuit board via the first connection part 310 .

[0248] Meanwhile, a semiconductor package may include multiple chips spaced apart horizontally on a single circuit board.

[0249] For example, the chip 320 may include a first chip and a second chip that are spaced apart from each other, and the first chip and the second chip may be different types of application processor (AP) chips.

[0250] Meanwhile, the first chip and the second chip may be spaced apart at a certain distance on the circuit board. For example, the distance between the first chip and the second chip may be 150 μm or less. For example, the distance between the first chip and the second chip may be 120 μm or less. For example, the distance between the first chip and the second chip may be 100 μm or less.

[0251] Preferably, for example, the separation width between the first chip and the second chip may be in the range of 60 μm to 150 μm. For example, the separation width between the first chip and the second chip may be in the range of 70 μm to 120 μm. For example, the separation width between the first chip and the second chip may be in the range of 80 μm to 110 μm. For example, if the separation width between the first chip and the second chip is smaller than 60 μm, a problem may occur in the reliability of the operation of the first chip or the second chip due to mutual interference between the first chip and the second chip. For example, if the separation width between the first chip and the second chip is larger than 150 μm, the signal transmission loss may increase due to the increased distance between the first chip and the second chip.

[0252] Meanwhile, the semiconductor package may include a second connection portion 330. The second connection portion 330 may be disposed on a lower surface of the fourth circuit layer 224. For example, the fourth circuit layer 224 includes at least one pad. The pad of the fourth circuit layer 224 may be vertically overlapped with the opening of the second protective layer 252. The second connection portion 330 may be disposed under the pad of the fourth circuit layer 224 that vertically overlaps with the opening of the second protective layer 252. The second connection portion 330 may be, but is not limited to, a solder ball. The second connection portion 330 may be for coupling the semiconductor package to a main board (or a motherboard) of an external device. The fourth buffer layer 224 may not be formed on the lower surface of the fourth circuit layer 224 on which the second connection portion 330 is disposed.

[0253] 12 to 17 are diagrams showing the process sequence of another method for manufacturing a circuit board according to an embodiment of the present invention.

[0254] 12, an embodiment may perform a process for manufacturing an inner layer of a circuit board. For example, the embodiment may prepare a first insulating layer 211. Then, the embodiment may form a first through electrode 241 penetrating the first insulating layer 211, a first circuit layer 221 disposed on an upper surface of the first insulating layer 211, and a third circuit layer 223 disposed on a lower surface of the first insulating layer 211.

[0255] 13, in an embodiment, the surfaces of the first circuit layer 221 and the third circuit layer 223 may be plasma-treated using nitrogen (N). As a result, a nitride layer containing nitrogen (N) may be formed on the surfaces of the first circuit layer 221 and the third circuit layer 223. For example, functional groups containing nitrogen (N) may be generated on the surfaces of the first circuit layer 221 and the third circuit layer 223. At this time, the functional groups containing nitrogen (N) may be formed not only on the first circuit layer 221 and the third circuit layer 223 but also on the upper and lower surfaces of the first insulating layer 211.

[0256] Next, in the embodiment, a first buffer layer 231 including a first functional group 130a and a second functional group 130c is formed on the first circuit layer 221. In addition, in the embodiment, a third buff layer 233 including a first functional group 130a and a second functional group 130c is formed on the third circuit layer 223.

[0257] Next, referring to FIG. 14, in the embodiment, a second insulating layer 212 is formed on the first insulating layer 211. In addition, in the embodiment, a third insulating layer 213 is formed under the first insulating layer 211. At this time, the second insulating layer 212 may include a functional group that is covalently bonded to the second functional group 130c of the first buffer layer 231. This can ensure adhesion between the second insulating layer 212 and the first circuit layer 221. In addition, in the embodiment, the third insulating layer 213 may include a functional group that is covalently bonded to the second functional group 130c of the third buffer layer 233. This can ensure adhesion between the third circuit layer 223 and the third insulating layer 213.

[0258] Next, referring to FIG. 15, an embodiment may perform a process for forming an outer layer of a circuit board.

[0259] Specifically, the embodiment may perform a process of forming a second through electrode 242 penetrating the second insulating layer 212 and a second circuit layer 222 disposed on an upper surface of the second insulating layer 212. In addition, the embodiment may perform a process of forming a third through electrode 243 penetrating the third insulating layer 213 and a fourth circuit layer 224 disposed on a lower surface of the third insulating layer 213.

[0260] 16, in an embodiment, the surfaces of the second circuit layer 222 and the fourth circuit layer 224 may be plasma-treated using nitrogen (N). As a result, a nitride layer containing nitrogen (N) may be formed on the surfaces of the second circuit layer 222 and the fourth circuit layer 224. For example, functional groups containing nitrogen (N) may be generated on the surfaces of the second circuit layer 222 and the fourth circuit layer 224. At this time, the functional groups containing nitrogen (N) may be formed not only on the second circuit layer 222 and the fourth circuit layer 224 but also on the upper surface of the second insulating layer 212 and the lower surface of the third insulating layer 213.

[0261] Next, the embodiment forms a second buffer layer 232 including the first functional group 130a and the second functional group 130c on the second circuit layer 222. Also, the embodiment forms a fourth buff layer 234 including the first functional group 130a and the second functional group 130c on the fourth circuit layer 224.

[0262] 17, in the embodiment, a first protective layer 251 is formed on the second insulating layer 212. In addition, in the embodiment, a second protective layer 252 is formed on the third insulating layer 213.

[0263] Meanwhile, when the circuit board having the above-mentioned inventive features is used in IT devices and home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when the circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve the problems of leakage current or electrical short circuit between terminals, or electrical open of terminals supplying power to the semiconductor chip. In addition, when it functions as a signal transmission, it can solve the noise problem. As a result, the circuit board having the above-mentioned inventive features can maintain stable functions of IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can form functional unity or technical interrelationship with each other.

[0264] When the circuit board having the above-mentioned features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current or electrical short circuit between terminals, or electrical open of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0265] The features, structures, effects, etc. described in the above-mentioned embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person having ordinary skill in the art to which the embodiment belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiment.

[0266] In addition, although the above description focuses on the embodiments, these are merely illustrative and do not limit the embodiments, and a person having ordinary skill in the art to which the embodiments pertain will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be interpreted as being included in the scope of the embodiments defined in the appended claims.

Claims

1. A first insulating layer; a first circuit layer disposed on the first insulating layer; a first buffer layer disposed on the first circuit layer; a second insulating layer disposed on the first insulating layer and the first buffer layer; The first circuit layer includes: A surface layer containing nitrogen (N), The first buffer is a first functional group that bonds with the surface layer; a second functional group that bonds with the second insulating layer.

2. The circuit board according to claim 1 , wherein the surface layer of the first circuit layer is a nitride layer formed on the surface of the first circuit layer.

3. The circuit board of claim 2 , further comprising a third functional group including nitrogen (N) that coordinates with the first functional group of the first buffer layer, which is the nitride layer of the first circuit layer.

4. 2. The circuit board of claim 1, wherein the first functional group comprises at least one azole group selected from the group consisting of diazole, triazole, tetraazole, benzotriazole, benzothiazole, and nitrotriazole.

5. The circuit board of claim 1 , wherein the second functional group comprises a siloxane group that covalently bonds to the second insulating layer.

6. The circuit board according to claim 1 , wherein the first buffer layer is formed of an organosilane agent including an azole group corresponding to the first functional group.

7. The first insulating layer is a first region overlapping the first circuit layer in a thickness direction; a second region excluding the first region, The circuit board according to claim 1 , wherein a fourth functional group including nitrogen (N) is formed on an upper surface of the second region of the first insulating layer.

8. the first circuit layer includes a first surface in contact with the first buffer layer; 2. The circuit board according to claim 1, wherein the roughness Ra of the first surface of the first circuit layer satisfies a range of 0.1 μm to 0.9 μm.

9. the first circuit layer includes a second surface in contact with the first insulating layer; The circuit board of claim 8 , wherein the second surface of the first circuit layer has a roughness Ra that is different from the roughness Ra of the first surface.

10. The circuit board of claim 8 , wherein a roughness Ra of the first buffer layer corresponds to a roughness Ra of the first surface of the first circuit layer.

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