DRAM Sense Amplifier Architecture with Reduced Power Consumption and Method Related Thereto

Abstract

A dynamic random access memory (DRAM) device may include an array of DRAM cells, each DRAM cell configured to store a high logic voltage and a low logic voltage. The DRAM device may further include a precharge circuit configured to selectively provide a first reference voltage and a second reference voltage to a first line and a second line, respectively, and a sense amplifier including a cross-coupled transistor detection circuit coupled between the first line and the second line. The sense amplifier may include at least one transistor including a superlattice channel. The DRAM device may further include a refresh circuit configured to selectively couple a third reference voltage to a corresponding DRAM cell via the first line based on a voltage difference between the first line and the second line, the third reference voltage being configured to be greater than the high logic voltage of the DRAM cell.

Description

[Technical field]

[0001] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices and related methods. [Background technology]

[0002] One of the key requirements for DRAM (Dynamic Random Access Memory) devices is the ability to retain data during inactivity with minimal power consumption. This power consumption comes from the need to refresh the data stored in the bit cells of selected parts of the memory, and from leakage in the rest of the periphery. This specification is called IDD6. It directly impacts the amount of time that a battery, such as a smartphone or laptop, can be used after a charge. Another important parameter for DRAM devices is latency. Latency refers to the delay between selecting a random location in the memory device and the time that the selected data arrives at the output.

[0003] One particularly advantageous memory device is disclosed in U.S. Patent No. 7,659,539 to Kreps et al., which is assigned to the present assignee and is hereby incorporated by reference in its entirety. This patent discloses a semiconductor device including a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include a superlattice channel including a source region and a drain region spaced apart from one another, and a group of layers stacked on the semiconductor substrate between the source region and the drain region. Each of the group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer disposed thereon, and may include at least one non-semiconductor monolayer constrained within the crystal lattice of an adjacent base semiconductor portion. A floating gate may be adjacent to the superlattice channel, and a control gate may be adjacent to the second gate insulating layer.

[0004] An advantageous DRAM architecture is disclosed in U.S. Patent No. 10,109,342 to Roy. It includes a plurality of memory cells and at least one peripheral circuit connected to the plurality of memory cells and including a superlattice. The superlattice includes a plurality of stacked groups of layers, each of the groups of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within the crystal lattice of an adjacent base semiconductor portion. The semiconductor device further includes a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply source during a first mode of operation, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply source lower than the first voltage supply source during a second mode of operation.

[0005] Despite the advantages of such devices, certain applications may call for further developments in memory technology. Summary of the Invention [Means for solving the problem]

[0006] A dynamic random access memory (DRAM) device includes an array of DRAM cells, each DRAM cell configured to store a high logic voltage and a low logic voltage. The DRAM device may further include a precharge circuit configured to selectively provide a first reference voltage and a second reference voltage to the first line and the second line, respectively, and a sense amplifier including a cross-coupled transistor sensing circuit connected between the first line and the second line. The sense amplifier may include at least one transistor including source and drain regions spaced apart from one another, a superlattice channel extending between the source and drain regions, and a gate overlying the superlattice channel. The superlattice channel includes a group of multiple stacked layers, the group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the crystal lattice of an adjacent base semiconductor portion. The DRAM device further includes a refresh circuit that selectively couples a third reference voltage to a corresponding DRAM cell via the first line based on a voltage difference between the first line and the second line, the third reference voltage being greater than the high logic voltage of the DRAM cell.

[0007] In one embodiment, the at least one transistor in the cross-coupled transistor detection circuit may include all of the transistors in the cross-coupled transistor detection circuit. In another embodiment, the refresh circuit may include at least one transistor including spaced apart source and drain regions, a superlattice channel (such as that briefly described above) extending between the source and drain regions, and a gate overlying the superlattice channel.

[0008] In one embodiment, the precharge circuit may include at least one transistor including spaced apart source and drain regions, a superlattice channel (such as that briefly described above) extending between the source and drain regions, and a gate overlying the superlattice channel. The DRAM device may also include a programming circuit in cooperation with the refresh circuit to selectively couple a third reference voltage to the corresponding DRAM cell. The precharge circuit may include at least one transistor including spaced apart source and drain regions, a superlattice channel (such as that briefly described above) extending between the source and drain regions, and a gate overlying the superlattice channel.

[0009] According to one embodiment, the DRAM device may include another refresh circuit configured to selectively couple a fourth reference voltage to another corresponding DRAM cell via the second line based on a voltage difference between the first line and the second line. In some embodiments, the DRAM memory device may be comprised of multiple stacked DRAM integrated circuits (ICs) including the components described above.

[0010] A related method for fabricating a DRAM device may include forming an array of DRAM cells each having a high logic voltage and a low logic voltage, forming a precharge circuit configured to selectively provide a first reference voltage and a second reference voltage to a first line and a second line, respectively, and forming a sense amplifier including a cross-coupled transistor detection circuit coupled between the first line and the second line. The sense amplifier may include at least one transistor including spaced apart source and drain regions, a superlattice channel (such as briefly described above) extending between the source and drain regions, and a gate overlying the superlattice channel. The method further includes forming a refresh circuit to selectively couple a third reference voltage to a corresponding DRAM cell via the first line based on a voltage difference between the first line and the second line, the third reference voltage being greater than the high logic voltage of the DRAM cell. [Brief description of the drawings]

[0011] [Figure 1] 1 is a greatly enlarged schematic cross-sectional view of a superlattice used in a semiconductor device according to one embodiment; [Diagram 2] FIG. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1. [Diagram 3] 1 is a schematic cross-sectional view of a superlattice according to one embodiment greatly enlarged in another embodiment; [Figure 4A] 3 is a graph of the band structure calculated from the gamma point (G) for both bulk silicon in the prior art and the 4:1 Si:O superlattice shown in FIGS. 1-2. [Figure 4B] 3 is a graph of the band structure calculated from the Z point for both bulk silicon in the prior art and the 4:1 Si:O superlattice shown in FIGS. 1-2. [Figure 4C] 4 is a graph of the band structure calculated from both the gamma and Z points for both bulk silicon in the prior art and the 5:1:3:1:Si:O superlattice shown in FIG. 3 . [Diagram 5] 1 is a schematic block diagram of a typical DRAM architecture in the prior art; [Figure 6] FIG. 6 is a schematic block diagram of the DRAM architecture of FIG. 5, showing the WL pre-decode / decode components in more detail. [Figure 7] 1 is a schematic block diagram of an exemplary DRAM architecture according to one embodiment. [Figure 8] FIG. 1 is a schematic diagram of a minimum sense amplifier in the ideal case of the prior art. [Figure 9] FIG. 9 is a diagram showing activation timing of the sense amplifier of FIG. 8. [Figure 10] FIG. 9 is a diagram showing activation timing in the sense amplifier of FIG. 8. [Figure 11] FIG. 2 is a schematic diagram of another minimal sense amplifier according to the prior art; [Figure 12] 12 is a diagram showing activation timing in the sense amplifier of FIG. 11. [Figure 13] 8 is a schematic diagram of a single-ended sense amplifier according to an exemplary embodiment that may be incorporated into the DRAM of FIG. 7. [Figure 14] FIG. 14 illustrates the timing of an activate read / refresh (stored logic 1) operation in the sense amplifier of FIG. [Figure 15] FIG. 14 illustrates the timing of an activate read / refresh (stored logic 0) operation in the sense amplifier of FIG. [Figure 16] FIG. 14 is a diagram showing the timing of an activate write (logic 1) operation to a bit cell in the sense amplifier of FIG. [Figure 17] FIG. 14 is a diagram showing the timing of an activate write (logic 0) operation to a bit cell in the sense amplifier of FIG. [Figure 18] FIG. 14 is a diagram showing the timing of a read (logic 1) operation of a stored column in the sense amplifier of FIG. [Figure 19] FIG. 14 is a diagram showing the timing of a column read (stored logic 0) operation in the sense amplifier of FIG. 13. [Figure 20] FIG. 14 is a diagram showing the timing of a column write (logic 1) operation in the sense amplifier of FIG. [Figure 21] FIG. 14 is a diagram showing the timing of a column write (logic 0) operation in the sense amplifier of FIG. [Figure 22] 8 is a schematic diagram of an alternative sense amplifier architecture according to an exemplary embodiment that may be used in the DRAM of FIG. 7. [Diagram 23] FIG. 2 is a schematic circuit diagram of a dual sense amplifier configuration in accordance with one embodiment. [Figure 24] FIG. 24 illustrates the activate read / refresh timing for stored logic 1's and logic 0's in the circuit of FIG. 23. [Diagram 25] FIG. 24 illustrates the activate read / refresh timing for stored logic 1's and logic 0's in the circuit of FIG. 23. [Figure 26] FIG. 24 illustrates the activate read / refresh timing for stored logic 1's and logic 0's in the circuit of FIG. 23. [Figure 27] FIG. 24 illustrates the activate read / refresh timing for stored logic 1's and logic 0's in the circuit of FIG. 23. [Figure 28] 1 is a voltage level diagram illustrating the nominal external power supply voltages in a conventional DRAM. [Figure 29] 2 is a voltage level diagram illustrating the nominal external and internal power supply voltages of a DRAM including an MST film in an exemplary embodiment. [Diagram 30] 2 is a voltage level diagram illustrating the nominal external and internal power supply voltages of a DRAM including an MST film in an exemplary embodiment. [Diagram 31] 2 is a voltage level diagram illustrating the nominal external and internal power supply voltages of a DRAM including an MST film in an exemplary embodiment. [Diagram 32] FIG. 1 is a schematic block diagram of a DRAM circuit including a DRAM chip having an MST film in an exemplary embodiment. [Diagram 33] FIG. 1 is a schematic block diagram of a DRAM circuit including a DRAM chip having an MST film in an exemplary embodiment. [Diagram 34] FIG. 2 is a schematic block diagram illustrating an example of a MOSFET including a superlattice channel that may be used in the DRAM device described above. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Exemplary embodiments will now be described in more detail with reference to the accompanying drawings in which exemplary embodiments are shown. However, the embodiments may be implemented in many different forms and should not be construed as being limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like reference numerals refer to like elements throughout, and prime notation is used to indicate like elements in different embodiments.

[0013] Generally, the present disclosure relates to the formation of semiconductor devices utilizing enhanced semiconductor superlattices, which may be referred to in the present disclosure as "MST" layers / films or "MST technology."

[0014] More specifically, MST technology relates to advanced semiconductor materials such as superlattices 25, which are further described below. Applicants theorize, without wishing to be bound thereto, that certain superlattices, such as those described herein, reduce the effective mass of the charge carriers, thereby increasing the mobility of the charge carriers. Effective mass has been described in the literature with various definitions. As a measure of the improvement in effective mass, Applicants use the M e -1 and M h -1 For electrons, we use the inverse conductivity effective mass tensor:

[0015]

number

[0016] and for holes,

[0017]

number

[0018] where f is the Fermi-Dirac distribution, E F is the Fermi energy, T is the temperature, E(k,n) is the energy of the electron in the state corresponding to wave vector k and the nth energy band, the subscripts i and j denote the Cartesian coordinates x, y, z, the integrals are taken in the Brillouin Zone (BZ), and the sums are calculated over the bands with energies above and below the Fermi energy for electrons and holes, respectively.

[0019] Applicant's definition of the inverse conductivity effective mass tensor is that the greater the value of the corresponding component of the inverse conductivity effective mass tensor, the greater the tensor component of the material's conductivity. Applicant also theorizes, without wishing to be bound thereto, that the superlattices described herein set the value of the inverse conductivity effective mass tensor to improve the material's conductive properties, such as the preferred direction of charge carrier transport, typically. The inverse of the appropriate tensor component is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the electron / hole conductive effective mass described above and calculated in the intended direction of carrier transport is used to distinguish improved materials.

[0020] Applicants have identified improved materials or structures for use in semiconductor devices. More specifically, Applicants have identified materials or structures having an energy band structure in which the approximate conductivity effective mass of electrons and / or holes is significantly less than the corresponding values ​​for silicon. In addition to improving mobility properties, these structures can also be formed or used to provide piezoelectric, pyroelectric, and / or ferroelectric properties, which are advantageous for use in various types of devices, as described further below.

[0021] 1 and 2, the material or structure is in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and is formed using known techniques of atomic or molecular layer deposition. The superlattice 25 includes a number of layers 45a-45n arranged in a stacked structure, as may best be understood with particular reference to the schematic cross-sectional view of FIG.

[0022] Each layer group 45a-45n of superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining respective base semiconductor portions 46a-46n and an energy band-modifying layer 50 thereon. Energy band-modifying layer 50 is shown in stippled form in FIG. 1 for clarity.

[0023] The energy band-modifying layer 50 illustratively comprises one non-semiconductor monolayer constrained within the crystal lattice of an adjacent base semiconductor portion. By "constrained within the crystal lattice of an adjacent base semiconductor portion" is meant that at least some of the semiconductor atoms of the opposing base semiconductor portions 46a-46n are chemically bonded via the non-semiconductor monolayer 50 therebetween, as shown in FIG. 2. Generally speaking, this configuration is achieved by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n by atomic layer deposition techniques, as described below, such that not all of the available semiconductor bonding sites are occupied by bonds to non-semiconductor atoms (i.e., coverage is not complete or is less than 100%). Thus, as additional monolayers 46 of semiconductor material are deposited on or over the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will occupy the remaining vacancy bonding sites of the semiconductor atoms located below the non-semiconductor monolayer.

[0024] In other embodiments, there may be more than one such non-semiconductor monolayer. It should be noted that, as used herein, the term non-semiconductor monolayer or semiconducting monolayer means that the material used in the monolayer is non-semiconductor or semiconducting when formed in bulk. That is, a monolayer of a material such as silicon does not necessarily exhibit the same properties as when formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.

[0025] Applicants theorize, without being bound thereto, that the energy band modifying layer 50 and adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower effective conductivity mass for charge carriers in the parallel layer direction than would otherwise be the case. Viewed another way, this parallel direction is perpendicular to the stacking direction. The band modifying layer 50 may also advantageously act as an insulator between vertically upper and lower layers or regions of the superlattice while providing the superlattice 25 with a common energy band structure.

[0026] Additionally, the superlattice structure may also advantageously act as a barrier to diffusion of dopants and / or materials between layers vertically above and below superlattice 25. Thus, these properties may advantageously reduce the diffusion of high-K materials into the channel region, as well as provide an interface in superlattice 25 for a high-K dielectric that reduces unwanted scattering effects and improves device mobility, as will be appreciated by those skilled in the art.

[0027] It is also believed that semiconductor devices including superlattice 25 may enjoy higher charge carrier mobility than other devices due to their lower conductive effective mass. In some embodiments, as a result of the band engineering achieved by the present invention, superlattice 25 may further have a substantially direct energy bandgap, which may be particularly advantageous for optoelectronic devices, for example.

[0028] The superlattice 25 also includes a capping layer 52 on the upper layer group 45n as shown. The capping layer 52 may include a plurality of base semiconductor monolayers 46. By way of example, the capping layer 52 may include 1-100 monolayers 46 of the base semiconductor, more preferably 10-50 monolayers. However, in some applications, the capping layer 52 may be omitted or a thickness of more than 100 monolayers may be used.

[0029] Each of the base semiconductor portions 46a-46n may include a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, as will be appreciated by those skilled in the art, the term Group IV semiconductors includes Group IV-IV semiconductors. More specifically, the base semiconductor may include at least one of silicon and germanium, for example.

[0030] Each energy band modification layer 50 may be composed of a non-semiconductor selected from the group consisting of, for example, oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor is also desirably thermally stable through the deposition of the next layer in order to facilitate its manufacture. In other embodiments, the non-semiconductor may be other inorganic or organic elements or compounds that are compatible with a given semiconductor process, as would be understood by those skilled in the art. More specifically, the base semiconductor may be composed of at least one of, for example, silicon and germanium.

[0031] Note that the term monolayer is meant to include single atomic layers and single molecular layers. Also note that the energy band modification layer 50 provided by a single monolayer may include a monolayer in which not all possible sites are occupied (i.e., the coverage is not complete or less than 100%). For example, referring particularly to the atomic diagram of FIG. 2, a 4-to-1 repeating structure is illustrated for silicon as the base semiconductor material and oxygen as the energy band-modifying material. In the illustrated example, only half of the possible sites of oxygen are occupied.

[0032] In other embodiments and / or with different materials, it is considered that this 50% occupancy ratio does not necessarily apply, as would be understood by those skilled in the art. In fact, as can be seen from this schematic diagram, the individual oxygen atoms in a given monolayer are not exactly aligned along a flat plane, as would be understood by those skilled in atomic deposition. As an example, the preferred range for occupancy is from about one-eighth to one-half of the possible oxygen sites, although other values may be used in specific embodiments.

[0033] Silicon and oxygen are currently widely used in conventional semiconductor processing, and thus manufacturers may readily use these materials as described herein. Atomic layer deposition, or monolayer deposition, is also now widely used. Thus, semiconductor devices incorporating superlattices 25 according to the present invention may be readily adapted and implemented, as will be appreciated by those skilled in the art.

[0034] Applicant theorizes, without being bound thereto, that in the case of a superlattice, such as a Si:O superlattice, it is desirable to have no more than seven silicon monolayers in order to achieve the desired benefits, such that the energy bands of the superlattice are common or relatively uniform throughout. The 4:1 repeating structure of Si:O shown in Figures 1 and 2 has been modeled to show improved mobility of electrons and holes in the X direction. For example, the calculated conductivity effective mass for electrons (isotropic for bulk silicon) is 0.26 and 0.12 in the X direction for a 4:1 SiO superlattice, resulting in a ratio of 0.46. Similarly, the calculations for holes are 0.36 for bulk silicon and 0.16 for a 4:1 Si:O superlattice, resulting in a ratio of 0.44.

[0035] While such directional advantageous features may be desirable in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the layers. As one skilled in the art will appreciate, it may be beneficial to increase the mobility of both electrons and holes, or to increase the mobility of just one of these types of charge carriers.

[0036] The low conductivity effective mass for the 4:1 Si:O embodiment of superlattice 25 can be less than two-thirds the conductivity effective mass otherwise, and this applies to both electrons and holes. Of course, as will be appreciated by those skilled in the art, superlattice 25 may further include at least one conductivity dopant.

[0037] Indeed, with further reference to FIG. 3, another embodiment of a superlattice 25' according to the present invention having different characteristics is now described. In this embodiment, a repeating pattern of 3:1:5:1 is shown. More specifically, the lowest base semiconductor portion 46a' has three monolayers and the second lowest base semiconductor portion 46b' has five monolayers. This pattern is repeated throughout the superlattice 25'. The energy band modifying layers 50' may each include a single monolayer. For such a superlattice 25' including Si vs. O, the charge carrier mobility enhancement is independent of the in-plane orientation of the layers. Other elements not specifically mentioned in FIG. 3 are similar to those previously described with reference to FIG. 1 and need not be described further here.

[0038] In some device embodiments, all of the base semiconductor portions of the superlattice may be the same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In yet other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.

[0039] In Figures 4A-4C we show the band structures calculated using density functional theory (DFT). It is well known to those skilled in the art that DFT underestimates the absolute value of the band gap, and therefore all bands above the gap can be shifted by appropriate "scissors corrections". On the other hand, the shape of the bands is known to be more reliable. The vertical energy axis should be interpreted in this light.

[0040] FIG. 4A shows the calculated band structures from the gamma point (G) for both bulk silicon (represented by continuous lines) and the 4:1 Si:O superlattice 25 shown in FIG. 1 (represented by dotted lines). Although the directions refer to the unit cell of the 4:1 Si:O structure and not to the unit cell of conventional Si, the (001) direction in the figure corresponds to the (001) direction of the conventional Si unit cell and thus indicates the expected location of the minimum in the Si conduction band. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell. Those skilled in the art will appreciate that the Si bands in the figure have been folded to represent the appropriate reciprocal lattice directions of the 4:1 Si:O structure.

[0041] It can be seen that the conduction band minimum of the 4:1 Si:O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction, referred to as the Z point. It is also noted that the curvature of the conduction band minimum of the 4:1 Si:O structure is larger than that of Si, due to the band splitting caused by the perturbation introduced by the additional oxygen layer.

[0042] Figure 4B shows the calculated band structures from the Z point for both bulk silicon (continuous line) and a 4:1 Si:O superlattice 25 (dotted line), which shows an increased curvature of the valence band in the (100) direction.

[0043] FIG. 4C shows the calculated band structures from both the gamma and Z points for both bulk silicon (continuous line) and the 5:1:3:1 Si:O structure of the superlattice 25' of FIG. 3 (dotted line). Due to the symmetry of the 5:1:3:1 Si:O structure, the calculated band structures in the (100) and (010) directions are equivalent. Therefore, the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e., perpendicular to the (001) stacking direction. Note that in the 5:1:3:1 Si:O example, both the conduction band minimum and the valence band maximum are at or near the Z point.

[0044] While an increase in curvature indicates a decrease in effective mass, a suitable comparison or discrimination can be made by calculation of the inverse effective mass tensor of electrical conductivity. From this, applicants further theorize that the 5:1:3:1 superlattice 25' should be substantially direct bandgap. As will be appreciated by those skilled in the art, the appropriate matrix elements for the optical transitions are other indicators of the distinction between direct and indirect bandgap behavior.

[0045] The above-described MST technology for CMOS devices has the ability to operate at significant overdrive voltages compared to standard CMOS devices. As a result, MST-based devices have up to 70% higher performance than standard CMOS technology with correspondingly lower latency. One example of an approach to integrating MST technology into CMOS devices is described in U.S. Patent No. 6,878,576 to Mears et al., which is incorporated herein by reference in its entirety.

[0046] During IDD6 standby, where the data in the array is continually refreshed, it is not necessary to operate at the same speed as during the high-speed active mode made possible by the use of MST technology. The specification for the time that the bit cells can reliably store data (hereafter referred to as the refresh interval) is long enough to fully refresh the entire array at the current performance levels of the Row Activation circuits. As a result, an opportunity arises to operate the Row Activation path of the circuits at a significantly lower voltage while still maintaining a current level clock rate (as opposed to the high-speed levels made possible by overdriven MST technology). By lowering the VDD applied to these circuits, for example from 1.0V to 0.7V, the array can be fully refreshed at the current speed, thus allowing a reduction of this portion of the standby power by approximately 50%, as will be described below. This invention describes a modification of a typical DRAM architecture that allows such a power reduction during IDD6 standby mode.

[0047] A further feature of MST technology is that the high Vt and low Vt devices can be separately optimized on the same chip. The high Vt devices can be optimized to minimize leakage so that they can be used as headers to reduce leakage to the rest of the periphery in standby mode, while the low Vt devices in these paths can be optimized to achieve even greater speeds in active mode than the 70% improvement mentioned above. Further details regarding DRAM memories incorporating MST films to achieve these technical advantages are described in the aforementioned U.S. Pat. No. 10,109,342 and U.S. Pat. No. 10,107,854 to Roy, both of which are incorporated herein by reference in their entireties.

[0048] Referring now to FIG. 5, a typical DRAM architecture 90 is described by way of background. Input enters the chip at block 200 on the left. This represents logic for decoding address information for selected cells, and control information for determining the type of operation to be performed. Part of this information is fed to a word line pre-decode and decode circuit (also called row activation circuit) represented in block 100. The remainder of this information is fed to a read / write decode and control block 300. The terms "read" and "write" refer only to column operations on a previously activated row. This circuit does not operate during refresh-only operations where no data is read or written externally. During read and write operations, the output of this circuit is fed to block 500 which contains column decoders and secondary sense amplifiers (IOSAs) which interface directly to the memory array 400 which contains all the bit cells and primary sense amplifiers. Block 100 containing word line pre-decode and decode circuitry also interfaces directly to the bit cells of the memory array 400. Block 500 also directly interfaces with data in and data out paths, blocks 600 and 700. Since the internal bus width of the DRAM is often much wider than the external interface, the data in and data out paths include serialization (for data out) and deserialization (for data in). Finally, the data in and data out paths are combined in block 800 to provide a bidirectional DQ circuit that interfaces with the outside world.

[0049] Referring now to FIG. 6, an example of a prior art DRAM architecture 90 with typical power supply voltages is shown. Here, the row activation (word line pre-decoding and decoding circuitry) block 100 of FIG. 5 is subdivided into block 130 (WL pre-decoding), block 140 (MWL decoding) and block 160 (SWD, or sub-word driver). Block 160 drives the actual word lines that connect to the bit cells in block 400 (bit cells and primary sense amplifiers). The bit cells and primary sense amplifiers (block 400) are powered by Vddbit, which is typically in the range of 0.9V to 1.0V in both active and standby modes. Similarly, the MWD (main word line decoder, block 140) and SWD (sub-word driver, block 160) are powered by Vddp (approximately 1.8V).

[0050] An exemplary DRAM architecture 91 and associated supply voltages according to an exemplary embodiment are shown in Figure 7. As a first issue, the functional blocks described above generally remain the same, but the inclusion of MST allows Vdd2 to be at a lower value, resulting in significant power savings. Thus, the block number is incremented by 1 compared to Figure 6. An example implementation uses a Vdd2 of 0.7V and a Vddbit of 1.4V, as described further below.

[0051] An example of a minimal prior art sense amplifier (ideal case) 900 and corresponding bitcell 901 is shown in Figure 8. The active timing diagram 902 associated with this sense amplifier is shown in Figure 9 for the idealized case of a nominal bitcell, balanced sense amplifier, and no leakage. Note that the timing diagram 903 in Figure 10 is a zoomed-in area of ​​focus in Figure 9, and that Vddbit is 1V. For a nominal signal at a Vddbit of 1V before leakage is considered:

[0052]

number

[0053] Here, Vcore=Vddbit=1V, and V BLP =0.5V, CB / CS=8, and therefore ΔV=56mV.

[0054] Referring now to FIG. 11, sense amplifier 900' is a modification of the prior art sense amplifier of FIG. 8, which has less precharge to compensate for leakage at the end of the refresh interval (i.e., the non-ideal case). The corresponding activate timing diagram 903' (similar to FIG. 10) is shown in FIG. 12. Again, using equation (1) above with Vcore=Vddbit=1V, CB / CS=8, VBLP will be 0.45V and Vcore(Vcell) will be 0.9V after the refresh interval, giving ΔV=50mV. The refresh interval is the time it takes for a cell to leak from 1V to 0.9V (100mV).

[0055] 13-14, there is shown a single-ended sense amplifier 1000 (and corresponding bit cell 1001) and associated timing diagram 1300 of an activated read refresh (store 1) according to an embodiment. Sense amplifier 1000 includes a cross-coupled transistor sense circuit (transistors 1200-1203), a precharge circuit (transistors 1204-1205), a refresh circuit (transistor 1210), a programming circuit (transistors 1206-1209), and a bit line sense amplifier including bit line transistor 1211. Bit cell 1001 includes transistor 1212 and capacitor 1002. In the sense amplifier of FIG. 13, in some embodiments, the illustrated transistors include an MST layer that defines a channel to provide the mobility enhancement described above, although in other embodiments, some or all of these transistors may not include an MST layer, as discussed further below.

[0056] An example of a transistor configuration (here a planar MOSFET 20) including a channel defined in an MST layer that may be used in one or more of the transistors 1200-1212 described above will now be described with reference to FIG. 34. The illustrated MOSFET 20 includes a substrate 21, source / drain regions 22, 23, source / drain extensions 26, 27, and a channel region therebetween provided by an MST superlattice 25. Source / drain silicide layers 30, 31 and source / drain contacts 32, 33 overlie the source / drain regions, as will be understood by those skilled in the art. The regions indicated by dashed lines 34, 35 are optional residual portions originally formed in the superlattice 25, but which have since been heavily doped. In other embodiments, these residual superlattice regions 34, 35 may not be provided, as will be understood by those skilled in the art. The gate 35 includes a gate insulating layer 37 adjacent the channel provided by the superlattice 25, and a gate electrode layer 36 provided on the gate insulating layer. The illustrated MOSFET 20 also includes sidewall spacers 40, 41. Further details regarding transistors that may include MST channels are described in U.S. Patent No. 6,897,472 to Mears et al., the contents of which are hereby incorporated by reference in their entirety.

[0057] The example shown in Figure 14 illustrates the timing events of an activate read / refresh for the case where a logic 1 is stored with nwell=1V and pwell=0V. At time (1), a rising edge of the external clock (not shown) to the chip occurs. This latches all address and control information for the operation in this clock cycle. It also decodes the SWL address and determines that it is a read activation of a refresh operation, which in turn notifies the control logic for the other signals sequenced in this cycle.

[0058] At time (2), a precharge pulse occurs, turning on the bit line transistor 1211, raising pwell and lowering the Vt of the cross-coupled n-channel for sensing. Specifically, the active side (inti, bit) is precharged to Gnd (0V) and the reference side (intr) is precharged to a reference level Vrefr. Typically, this will be around 50mV. Also, the refresh interval may be longer due to the lower Vtn of the cross-coupled n-channel. Additionally, PCOM may be precharged to Gnd or Vrefr. Precharging to Gnd reduces stress on the Vrefr generator and is therefore considered desirable as long as it does not cause sensing problems due to undershoot levels. The iso signal can be run from the normal Vdd2 (1.1V) as brec pulls the bit up to 1.4V to restore the high level. Vtn may be lowered for sensing as there is a relatively small headroom. In general, a high Vtn is desirable to reduce leakage power when the sense amplifier is storing, ie, not sensing, data.

[0059] At time (3), precharge is stopped and SWL is turned on. At the end of the refresh interval, charge sharing occurs on bit and intl between cells at high level. The final value should have enough margin vs. Vrefr to accurately detect high level under all PVTs and variations.

[0060] At time (4), the sense amplifier 1000 is latched by taking PCOM high and NCOM low. PCOM can either be much lower than Vdd2 to save power or Vdd2 has less overall power penalty. NCOM should be placed below ground to have headroom for sensing the cross-coupled n-channels at low Vrefr level. This can be SWL off level (-100mV) or more negative with capacitive kicking technique.

[0061] At time (5), brec is turned on to pull the bitline to a full high level (e.g., around 1.4V for reliability reasons, possibly higher). Using high voltage devices for iso and BREC allows the sense amplifier 1000 to operate at levels below Vdd2 (1.1V) using higher performance / low Vt thin oxide devices.

[0062] At time (6), the SWL is capacitively kicked high, compressing a full high level into the bitcell. NCOM is also returned to Gnd since the initial detection is over. More specifically, to minimize leakage of the SWL device, which has Vgs=-100mV when off, NCOM may be pulled back to zero so that Gnd is preserved as a low level in the cell. While this may not be necessary in all embodiments, the goal is to not leak the bitline when reading a logic 1 in another SWL on the same physical bitline.

[0063] Time (7) marks the end of the activity where everything is shut off, allowing the cycle time to be extended with little or no impact.

[0064] Referring again to equation (1), if Vcore(Vcell, Vbit)=0.9V, VBLP=0V, and CB / CS=8 after the refresh interval, then ΔV=100mV, which translates to a 50mV signal. The refresh interval here is the time it takes for a cell to leak from 1.4V to 0.9V (500mV). Accordingly, it should be appreciated that the exemplary embodiment provides a 5x voltage drop, and therefore impacts the refresh interval by ≈5x, and impacts the overall standby power by ≈5x. Additionally, since the reference bitline capacitance is eliminated, power consumption is reduced by nearly 2x, resulting in a total reduction of ≈10x. Assuming that the leakage characteristics of the bitcells flatten out at lower voltages (due to weaker electric fields across the depletion region), applicants theorize, but do not wish to be bound, that this number could be significantly higher than 10x, compared to the prior art sense amplifier configuration described above, which was precharged to near Vddbit / 2.

[0065] Previously, DRAMs were not allowed to use error correcting codes (ECC) as part of their redundancy, so the refresh interval was determined by the leakage characteristics of outlier cells that had small defects that could not be repaired. Now that DRAMs can use ECC as part of their redundancy, the above benefits become even more significant, as the refresh interval is now dominated by the bulk (nominal) cells rather than the outliers, and the leakage characteristics are those of completely non-defective bit cells.

[0066] Still referring to FIG. 15, a timing diagram 1301 for activate read / refresh (stored 0) is shown for the sense amplifier 1000 of FIG. 13. The goal is to have no read current requirement for stored 0. In general, Gnd is the most reliable voltage on the chip if noise sources are properly handled (mainly isolated). Vrefr is shown in the timing diagram as nominally 50mV.

[0067] While making the stored logic 0 level in the bit cell slightly negative increases the detection margin of the 0, the tradeoff is that no leakage current from multiple stored 0s on a physical bit line can be tolerated, which can reduce the detection margin when reading a logic 1 from another SWL at the end of the refresh interval. A worst case test for this is to read a logic 1 at high temperature with all (e.g. 255) bit cells on the same physical bit line containing 0s.

[0068] Activation for writing logic 1 and logic 0 to bit cells is shown in timing diagrams 1302, 1303 in Figures 16 and 17, respectively. A read-modify-write (RMW) operation is implemented by a column write to the sense amplifiers of a selected column after the selected SWL is downloaded (read) to the sense amplifiers. Multiple words may be written to the sense amplifiers of a given physical SWL before writing back the full set of sense amplifiers to the bit cells in the SWL. This full set includes the newly written sense amplifiers and the so-called "half cells" located in the SWL that remain during the RMW operation. Therefore, the actual write back operation during this type of activate cycle may skip the read operation. This simplifies the timing and may also speed up the write back activate cycle.

[0069] 18-21, there are shown timing diagrams 1304, 1305, 1306, and 1307 of column read storage logic 1, column read storage logic 0, column write logic 1, and column write logic 0 of the sense amplifier architecture 1000 of FIG. 13. The DRAM sense amplifier is treated similarly to an SRAM bit cell. That is, when a certain Vrefr bias level is close to Gnd, the read operation of the SRAM is inverted compared to a normal SRAM where the NMOS pass gates and bit lines are biased close to Vdd for various reasons. In the SRAM bit cell, there is a trade-off between the writability and the cell stability during read. In this embodiment, by controlling PCOM and NCOM, it is possible to ensure a relatively large stability margin for read as long as PCOM and NCOM are made high impedance during the first sampling of write data from the global line through the SELN transistor in the column write operation.

[0070] Another embodiment of the sense amplifier 1400 is shown in Figure 22. The sense amplifier 1400 includes transistors 1401-1412. This configuration also applies the relatively low Vref technique described above to DRAM. In this configuration, the generation of Vref is based on charge sharing between the active bit line and the reference bit line during precharging.

[0071] Referring again to FIG. 13, as discussed above, the exemplary architecture of sense amplifier 1000 is designed to take advantage of several technical advantages of MST films. One such advantage is Vt mismatch. More specifically, DRAMs have long struggled with statistical mismatch in primitive sense amplifiers. MST provides a relatively clean dielectric surface for the transistors, reducing the Vt mismatch of the differential pair by about a factor of two. For the p-channel pair 1200 / 1201, they can be standard Vt devices since they operate with sufficient overdrive during initial detection. For the n-channel pair 1202 / 1203, the Vt should be as low as possible during initial detection since the advantage of the single-ended approach increases as Vrefr gets lower, such as below 50 mV. The source of this pair can be pushed below ground during initial detection by one of several known techniques, but ideally should be kept at 100-200 mV, well below the forward bias voltage of the S / D diodes.

[0072] Another technical advantage of the MST film that this architecture leverages is that it allows for 200-300mV more of voltage at the drain for the same reliability performance (overdrive). This is important for the sensing scheme because the higher the logic 1 stored in the bitcell, the longer the refresh interval can be. This is primarily driven by the bitcell pass gate 1212. By being able to bump this voltage above Vddp during the last part of the write / restore operation, the amount of bump that can be reliably achieved determines the maximum voltage level that can be written to the cell, which adds directly to the refresh interval. Another advantage is that transistors 1210 and 1211 can be implemented in thin oxide devices (as opposed to the high voltage devices shown), potentially reducing cost by eliminating the thick oxide high voltage devices from the periphery (as 1212 is an entirely different type of transistor than the periphery transistors) if such thick oxide devices are not needed elsewhere (e.g., I / O devices or analog circuitry such as voltage regulators).

[0073] Yet another technical advantage of the MST film exploited by the present architecture is its higher mobility (current drive). That is, the present architecture exploits the capabilities of the MST film to significantly speed up DRAM operations. More specifically, with respect to bitcell passgate 1212, increasing the current drive of this transistor significantly improves both read and write speeds during activation and refresh operations. Additionally, transistors 1204 / 1205 provide a significantly different precharge scheme. That is, because the gate voltage overdrive of the precharge device is limited to Vddbit / 2-Vt in this embodiment relative to Vddbit-Vt, a typical DRAM takes a relatively long time to precharge to approximately Vdd / 2. For standard Vt devices (necessary to minimize leakage), this can be 3-5 times faster, significantly speeding up the precharge portion of the cycle.

[0074] This architecture also leverages the technological ability of the MST film to sustain 200-300mV more voltage on the drain with the same reliable performance (overdrive). As seen in Figure 7, another benefit of the overdrive feature is that Vdd2 can be lowered from 1V to 0.7V throughout the periphery, halving the power of all these blocks. In such applications, an MST film configuration may be chosen that allows lower voltages than 0.7V (short channel, thin oxide), but can be overdriven to 0.7V to match the speed of the 1V baseline transistors.

[0075] Additionally, the technological advantages of MST films, where the implant profile controls the back-gate effect, can also be exploited in this architecture. This is especially true for the NMOS cross-coupled device 1202 / 1203 in the sense amplifier, where it is desirable to sense at a very low Vt due to reduced headroom, but when not sensing, the Vt must be driven much higher to minimize leakage. The cross-coupled p-channel pair 1200 / 1201 can also benefit from this to some extent.

[0076] 23, in another embodiment, the sense amplifier circuit 2300 illustratively includes a left sense amplifier 2301 and a right sense amplifier 2302. More specifically, the sense amplifier circuit 2300 includes transistors 2303-2320. The operation of the left sense amplifier circuit 2301 corresponding to an activate read / refresh of a stored logic 1 will be described with reference to the timing diagram 2400 of FIG. 24. Time 1 corresponds to the rising edge of the external clock to the chip (not shown). This latches all address and control information for the operation in this clock cycle. In addition, it decodes the swl address to determine whether it is a read activation or a refresh operation and notifies the result to the control logic for other signals sequenced in this cycle. At time 2, the precharge is turned off and swl and ISOL are turned on. This allows charge sharing between bit and inti at the cell high level at the end of the refresh interval. The final value should have enough margin with respect to Vref to accurately detect the high level under all PVTs and variations. For example, BRECL pulls the bit up to 1.4V to restore a high level, so ISOL can be run off the normal Vdd2 (1V or less). This may also be desirable to provide some resistive isolation between the sense amp's internal nodes and the bulk capacitor bitline during initial detection.

[0077] At time 3, the sense amplifier is latched by pulling PCOM high and NCOM low. PCOML can be much lower than Vdd2 to save power, or Vdd2 can be used for this with little overall power penalty. NCOML needs to be placed below ground to provide headroom for sensing by the cross-coupled n-channel at low Vrefr levels. This can be the swl off level (-100mV) or even more negative. At time 4, BRECL is turned on, pulling the bitline all the way high (around 1.4V for reliability, and higher if possible). Using high voltage devices for ISOL and BRECL allows the cross-coupled latch of the left sense amplifier 2301 to operate at a higher performance and eliminates low Vt thin oxide devices below the level of Vdd2 (1V or less). This also allows Vdd2 itself to be lower.

[0078] At time 5, after initial detection is ensured, NCOML is abruptly pulled up to Gnd. During this brief time, NCOML is tightly coupled to SWL, which is kicked up a small amount to squeeze out as much charge as possible to write back or restore a 1 level to the bitcell. Also, to minimize leakage from the SWL device, which has Vgs=-100mV when off, NCOML needs to be pulled back to zero so that Gnd is stored as a low level in the cell when writing a zero. More specifically, it is desirable to have no bitline leakage when reading a logic 1 with a different SWL on the same physical bitline.

[0079] At time 6, swl is turned off, and at time 7, BRECL is turned off and precharge is turned on. This causes the sense amplifier circuit 2300 to remain in an "initial" precharge state when not being accessed. The active side (inti, bitl) is precharged to Gnd (0V), and the reference side (intln) is precharged to the reference level Vref (usually 50 to 75 mV).

[0080] With further reference to timing diagram 2500 of FIG. 25, the activate read / refresh of a stored logic 0 is described. The timing is similar to that described above with reference to timing diagram 2400, but no read current requirement is made for a stored 0. In general, Gnd is the most reliable voltage on the chip if noise sources are properly handled (mainly in terms of isolation). In this example, Vref is shown as 50mV. For logic 0 levels stored in bit cells, a slightly negative value increases the detection margin of the zero. However, a trade-off is that leakage current from multiple 0s stored on a physical bit line should not be tolerated, as it may degrade the sensing margin for reading logic 1s from other SWLs at the end of the refresh interval. A worst case test for this is to read a logic 1 at high temperature with 0s stored in all (e.g. 255) bit cells on the same physical bit line.

[0081] An activate write (single ended) to a bitcell for logic 1 and logic 0 is shown in timing diagrams 2600 and 2700 of Figures 26 and 27, respectively.

[0082] An exemplary power supply voltage scheme for a DRAM including the MST film described above will now be described with reference to voltage level diagrams 2800, 2900, 3000, and 3100 in Figures 28-31, respectively. By way of background, diagram 2800 shows typical nominal external power supply levels for a conventional DRAM. In this configuration, lowering Vdd2 during refresh reduces CV 2 Reduces the power at f to 0.81 / 1.21. Noise reduction may play a role in achieving this reduction, but margins may be tighter when measuring IDD6 at low Vdd2.

[0083] For comparison, an example of a nominal external power supply configuration for a DRAM with MST membrane is shown in voltage level diagram 2900. Here, Vddp may be similar to the conventional configuration of the SWL path where this voltage is predominant. If desired, these devices may use similar MST membranes as low voltage MST devices, but different MST membranes may be used depending on the implementation. Meanwhile, the range of Vdd2 achievable due to the evolution of low voltage optimized MST is significantly lower than the conventional configuration. As an example, Vdd2 may be 0.6V, or more specifically, 0.4V or less depending on the configuration. Vdd2 may be binned at a lower voltage (higher cost premium) during testing in some implementations, such as when the channel length of a particular wafer is short and the same performance can be achieved with a lower Vdd2. This supply remains unchanged since the majority of the current for the decode and data paths is sourced from this external supply, and refresh occurs in the background of normal operation.

[0084] The example configuration shown in voltage level diagram 3000 also provides VddTurbo, which has a value of Vdd2+250mV. VddTurbo is rarely used in pre-decoding or datapaths, but may be used in gate array logic or ASIC chips below the DRAM stack. Switching from Vdd2 to VddTurbo may be done "on the fly" for certain logic blocks that can operate in either "normal" or "turbo" mode.

[0085] MST membranes have the ability to maintain or even improve performance at such reduced voltages and power. Nominal CV 2The f power reduction may be at least 0.36 / 1.21 (minus a small overhead for generating additional internal voltages, described below with reference to voltage level diagram 3100) since most of the current is drawn from Vdd2. Examples of devices that may benefit from the inclusion of an MST film include high voltage devices for the SWL path (which may use the same film as the low voltage devices in some embodiments). Similar requirements apply to the baseline, except for brief overvoltage of the SWL during final charge squeeze to the bitcell. Other devices that may benefit from an MST film include high Vt "1V" devices for headers and low leakage situations, and low Vt "0.6V" devices (optimized for Vdd2 levels), but which may be operated with 200-300mV overdrive in "turbo" mode, for example, to increase current drive by 50% or more.

[0086] Further examples of internal power supply ranges are shown in voltage level diagram 3100. Vddgate is used for NMOS pull-up drivers for long lines that require a relatively small amount of current. Vddnwell is selectively used in headers and certain non-speed-sensitive circuits to minimize leakage by raising Vtp (relatively low current). Vrefglobal is used for differential sensing of single-ended long internal data lines (relatively low current). Vrefbit is used to create differential sensing for single-ended bit line sense amplifiers (relatively low current). Vswloff is used to create the off voltage for SWL (relatively low current).

[0087] Vneg is used to provide a large capacitor reservoir for the entire chip, with switches (for noise isolation) to various locations, such as the ncom of the bitline sense amplifier. It may also be used for PMOS gates driving long lines. Vneg draws a moderate current, but spikes are filtered by a large bypass capacitor reservoir. Using a Power Management Integrated Circuit (PMIC) chip in the system (which is relatively low cost) allows for simplification, risk reduction, and power savings for the DRAM chip. Furthermore, this can be achieved while still providing low impedance drive, more flexible voltage levels, and higher accuracy for the "internal" voltages mentioned above.

[0088] 32, an exemplary DRAM assembly includes four MST DRAM chips 3301 (although other numbers of DRAM chips may be used in other embodiments) and a control / interface ASIC 3202. Another example DRAM assembly 3300 is shown in FIG. 33, which also includes four MST DRAM chips 3301, a control / interface ASIC 3302, and a PMIC 3303.

[0089] Numerous modifications and other embodiments will occur to those skilled in the art having the benefit of the teachings herein, and it is understood, therefore, that the disclosure is not limited to the specific exemplary embodiments disclosed herein.

Claims

1. A dynamic random access memory (DRAM) device, comprising: an array of DRAM cells configured such that each DRAM cell stores a high logic voltage and a low logic voltage; a precharge circuit configured to selectively supply a first reference voltage and a second reference voltage to a first line and a second line, respectively; a sense amplifier including a cross-coupled transistor detection circuit coupled between the first line and the second line; a refresh circuit configured to selectively couple a third reference voltage to a corresponding DRAM cell via the first line based on a voltage difference between the first line and the second line, and configured such that the third reference voltage is greater than the high logic voltage of the DRAM cell; wherein the sense amplifier includes at least one transistor including a source region and a drain region spaced apart from each other, a superlattice channel extending between the source region and the drain region, and a gate covering the superlattice channel; wherein the superlattice channel includes a group of a plurality of stacked layers, and each of the groups of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of an adjacent base semiconductor portion, the device.

2. The device according to claim 1, wherein at least one transistor in the cross-coupled transistor detection circuit includes all of the transistors in the cross-coupled transistor detection circuit.

3. The refresh circuit, including a source region and a drain region spaced apart from each other; a superlattice channel extending between the source region and the drain region; and at least one transistor including a gate covering the superlattice channel; wherein the superlattice channel includes a group of a plurality of stacked layers, and each of the groups of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of an adjacent base semiconductor portion, the device according to claim 1.

4. The precharge circuit, including a source region and a drain region spaced apart from each other; a superlattice channel extending between the source region and the drain region; including at least one transistor including a gate covering the superlattice channel, The device according to claim 1, wherein the superlattice channel includes a group of a plurality of stacked layers, and each of the groups of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the crystal lattice of the adjacent base semiconductor portion.

5. The device according to claim 1, further including a programming circuit configured to selectively couple the third reference voltage to the corresponding DRAM cell in cooperation with the refresh circuit.

6. The programming circuit is a source region and a drain region spaced apart from each other, a superlattice channel extending between the source region and the drain region, including at least one transistor including a gate covering the superlattice channel, The device according to claim 5, wherein the superlattice channel includes a group of a plurality of stacked layers, and each of the groups of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the crystal lattice of the adjacent base semiconductor portion.

7. The device according to claim 1, further including another refresh circuit configured to selectively couple a fourth reference voltage to another DRAM cell corresponding thereto via the second line based on a voltage difference between the first line and the second line.

8. A dynamic random access memory (DRAM) device, including a plurality of stacked DRAM integrated circuits (ICs), Each DRAM IC an array of DRAM cells configured such that each DRAM cell stores a high logic voltage and a low logic voltage, a precharge circuit configured to selectively supply a first reference voltage and a second reference voltage to a first line and a second line, respectively, a sense amplifier including a cross-coupled transistor detection circuit coupled between the first line and the second line, configured to selectively couple a third reference voltage to a DRAM cell corresponding thereto via the first line based on a voltage difference between the first line and the second line, and the third reference voltage is configured to be greater than the high logic voltage of the DRAM cell, and including a refresh circuit. The sense amplifier includes at least one transistor including a source region and a drain region arranged at intervals from each other, a superlattice channel extending between the source region and the drain region, and a gate covering the superlattice channel. The superlattice channel includes a group of a plurality of stacked layers, and each of the groups of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the crystal lattice of the adjacent base semiconductor portion.

9. The device according to claim 8, further including a control IC coupled to the plurality of stacked DRAM ICs.

10. The device according to claim 8, further including a power management IC coupled to the plurality of stacked DRAM ICs.

11. At least one transistor in the cross-coupled transistor detection circuit includes all the transistors in the cross-coupled transistor detection circuit. The device according to claim 8.

12. The refresh circuit is a source region and a drain region arranged at intervals from each other, a superlattice channel extending between the source region and the drain region, and at least one transistor including a gate covering the superlattice channel, wherein the superlattice channel includes a group of a plurality of stacked layers, and each of the groups of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the crystal lattice of the adjacent base semiconductor portion. The device according to claim 8.

13. The precharge circuit is a source region and a drain region arranged at intervals from each other, a superlattice channel extending between the source region and the drain region, and at least one transistor including a gate covering the superlattice channel, wherein the superlattice channel includes a group of a plurality of stacked layers, and each of the groups of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the crystal lattice of the adjacent base semiconductor portion. The device according to claim 8.

14. The device according to claim 8, further including a programming circuit that selectively couples the third reference voltage to the corresponding DRAM cell in cooperation with the refresh circuit.

15. wherein the programming circuit includes a source region and a drain region disposed at intervals from each other, a superlattice channel extending between the source region and the drain region, and at least one transistor including a gate covering the superlattice channel, wherein the superlattice channel includes a group of a plurality of stacked layers, and each of the groups of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the crystal lattice of the adjacent base semiconductor portion; the device according to claim 14.

16. The device according to claim 8, further comprising another refresh circuit configured to selectively couple a fourth reference voltage to another DRAM cell corresponding thereto via the second line based on a voltage difference between the first line and the second line.

17. A method of manufacturing a dynamic random access memory (DRAM) device, comprising: forming an array of DRAM cells each configured to store a high logic voltage and a low logic voltage; forming a precharge circuit configured to selectively supply a first reference voltage and a second reference voltage to a first line and a second line, respectively; forming a sense amplifier including a cross-coupled transistor detection circuit coupled between the first line and the second line; forming a refresh circuit configured to selectively couple a third reference voltage to a DRAM cell corresponding thereto via the first line based on a voltage difference between the first line and the second line, and wherein the third reference voltage is configured to be greater than the high logic voltage of the DRAM cell; and wherein the sense amplifier comprises at least one transistor including a source region and a drain region disposed at intervals from each other, a superlattice channel extending between the source region and the drain region, and a gate covering the superlattice channel, wherein the superlattice channel includes a group of a plurality of stacked layers, and each of the groups of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the crystal lattice of the adjacent base semiconductor portion.

18. The method according to claim 17, wherein at least one transistor in the cross-coupled transistor detection circuit includes all the transistors in the cross-coupled transistor detection circuit.

19. The refresh circuit is source regions and drain regions arranged at intervals from each other, a superlattice channel extending between the source region and the drain region, and including at least one transistor including a gate covering the superlattice channel, the superlattice channel includes a group of a plurality of stacked layers, and each of the groups of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the crystal lattice of the adjacent base semiconductor portion, the method according to claim 17.

20. The precharge circuit is source regions and drain regions arranged at intervals from each other, a superlattice channel extending between the source region and the drain region, and including at least one transistor including a gate covering the superlattice channel, the superlattice channel includes a group of a plurality of stacked layers, and each of the groups of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the crystal lattice of the adjacent base semiconductor portion, the method according to claim 17

21. The method according to claim 17, further comprising the step of forming a programming circuit that selectively couples the third reference voltage to the corresponding DRAM cell in cooperation with the refresh circuit.

22. The programming circuit is source regions and drain regions arranged at intervals from each other, a superlattice channel extending between the source region and the drain region, and including at least one transistor including a gate covering the superlattice channel, the superlattice channel includes a group of a plurality of stacked layers, and each of the groups of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the crystal lattice of the adjacent base semiconductor portion, the method according to claim 21.

23. The method of claim 17, further comprising another refresh circuit configured to selectively couple a fourth reference voltage to other DRAM cells corresponding thereto via the second line based on a voltage difference between the first line and the second line.

24. A dynamic random access memory (DRAM) device, comprising: an array of DRAM cells, each DRAM cell being configured to store a high logic voltage and a low logic voltage; a precharge circuit configured to selectively supply a first reference voltage and a second reference voltage to a first line and a second line, respectively; a sense amplifier including a cross-coupled transistor detection circuit coupled between the first line and the second line; a refresh circuit configured to selectively couple a third reference voltage to a DRAM cell corresponding thereto via the first line based on a voltage difference between the first line and the second line, and wherein the third reference voltage is configured to be greater than a high logic voltage of the DRAM cell.

25. The device of claim 24, comprising the step of forming a programming circuit that selectively couples the third reference voltage to the DRAM cell corresponding thereto in cooperation with the refresh circuit.

26. The device of claim 24, further comprising another refresh circuit configured to selectively couple a fourth reference voltage to other DRAM cells corresponding thereto via the second line based on a voltage difference between the first line and the second line.

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