Self-aligned back contact with increased contact area

Abstract

The first source-drain region is adjacent to the first transistor, the second source-drain region is adjacent to the second transistor, the upper source-drain contact is above the first source-drain region, the lower source-drain contact is below the second source-drain region, the lower source-drain contact and the upper source-drain contact are on both sides, and the horizontal plane of the lower source-drain contact is adjacent to the horizontal plane of the dielectric side spacer surrounding the second source-drain region. In an embodiment, the lower source-drain contact surrounds the vertical side surface of the source-drain region. The method includes forming a first nanosheet stack and a second nanosheet stack, forming an upper source-drain contact to the first source-drain region adjacent to the first nanosheet stack, and forming a lower source-drain contact to the lower horizontal plane of the second source-drain region adjacent to the second nanosheet stack.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor manufacturing, and more particularly, to back contacts.

Background Art

[0002] Complementary Metal-oxide-semiconductor (CMOS) technology is generally used in field effect transistors (hereinafter, "FETs") as part of advanced integrated circuits (hereinafter, "ICs") such as central processing units (hereinafter, "CPUs"), memories, and storage devices. Due to the continuous demand to reduce the dimensions of transistor devices, nanosheet FETs help to achieve a reduced footprint of FET devices while maintaining the performance of the FET devices. A nanosheet device includes one or more layers of a semiconductor channel material portion having a vertical thickness that is significantly smaller than the width. A nanosheet FET includes a plurality of stacked nanosheets extending between a pair of source / drain epitaxial regions. This device can be a gate-all-around device or a gate-all-around transistor in which the gate surrounds a portion of the nanosheet channel.

Summary of the Invention

[0003] According to an embodiment, a semiconductor device is provided. The semiconductor device includes a first source / drain region adjacent to a first transistor on a substrate, a second source / drain region adjacent to a second transistor on the substrate, an upper source / drain contact aligned vertically above the first source / drain region and electrically connected to the first source / drain region, and a lower source / drain contact aligned vertically below the second source / drain region and electrically connected to the second source / drain region. The lower source / drain contact and the upper source / drain contact are on both sides of the semiconductor device. A horizontal plane of the lower source / drain contact is adjacent to a horizontal plane of a dielectric side spacer surrounding the second source / drain region, and a width of the lower source / drain contact is wider than a width of the second source / drain.

[0004] According to an embodiment, a semiconductor device is provided. The semiconductor device includes a first source / drain region and a lower source / drain contact aligned vertically below the first source / drain region and electrically connected to the first source / drain region. The lower source / drain contact surrounds a vertical side surface of a second source / drain region.

[0005] According to an embodiment, a method is provided. The method includes forming a first nanosheet stack and a second nanosheet stack on a substrate, forming an upper source / drain contact on an upper horizontal plane of a first source / drain region adjacent to the first nanosheet stack, bonding a carrier wafer to an upper surface of the substrate above the first nanosheet stack and the second nanosheet stack, and forming a lower source / drain contact on a lower horizontal plane of a second source / drain region adjacent to the second nanosheet stack, where the lower source / drain contact and the second source / drain region are aligned vertically. The lower source / drain contact surrounds a vertical side surface of the second source / drain region.

[0006] These and other objects, features, and advantages of the present invention will become apparent from the following detailed description of example embodiments of the invention, read in conjunction with the accompanying drawings. Since each figure is provided to clarify in promoting the understanding of those skilled in the art of the present invention in conjunction with the detailed description, the various features of the drawings are not to scale.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0008] To simplify and clarify the description, it will be understood that the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, reference numerals may be repeated between figures where appropriate to indicate corresponding or similar features.

[0009] Although detailed embodiments of the claimed structures and methods are disclosed herein, it will be understood that the disclosed embodiments are merely examples of the claimed structures and methods that may be embodied in various forms. However, the invention may be embodied in various forms and should not be construed as limited to the exemplary embodiments shown herein. In the description, well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0010] References herein to "one embodiment," "an embodiment," "an exemplary embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Further, such phrases do not necessarily refer to the same embodiment. Also, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0011] When an element is considered to be "on" or "over" another element, such as a layer, region, or substrate, it will be understood that the element can be directly on top of the other element or intervening elements may be present. In contrast, when an element is considered to be "directly on" or "directly over" another element, no intervening elements are present. When an element is considered to be "connected" or "coupled" to another element, it will also be understood that the element can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is considered to be "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0012] To avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and illustration, and in some cases, may not be described in detail. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of the various embodiments of the present invention.

[0013] A nanosheet field effect transistor (hereinafter, "FET") may be formed from alternatingly stacked layers of silicon and silicon germanium, and thereafter, these layers are formed on the stacked nanosheets. A gate all around structure may be formed on all vertical side surfaces and the upper horizontal surface of the cross-section of the nanosheet. Source-drain structures may be formed at both ends of the stacked nanosheet structure.

[0014] Forming a nanosheet FET involves the following steps. A layer of stacked nanosheets is formed on a substrate. To form fins, grooves are formed parallel to each other within the layer of stacked nanosheets, and then sacrificial gates are formed perpendicular to the grooves. Additional grooves are formed between the sacrificial gates perpendicular to the original grooves. In embodiments of the present invention, the grooves may extend into the substrate, and a sacrificial layer is formed in a portion of the grooves within the substrate. These grooves may be formed where back contacts to the source and drain can be formed later. The outer portions of the sacrificial layer of the stacked nanosheets may be removed, and an internal spacer is formed where the outer portions of the sacrificial layer of the stacked nanosheets have been removed. The source and drain regions are formed by spreading out from the exposed channel layer of the nanosheet stack. The source and drain regions may be formed over the grooves. The sacrificial gates are removed, and the remaining portions of the sacrificial layer are removed. A metal gate surrounding the channel layer may be formed where the sacrificial gates and the remaining portions of the sacrificial layer have been removed. Contacts may be formed to the metal gate and to the source and drain, particularly to the source and drain areas without a sacrificial layer under the source and drain. Further formation of the back end of line (BEOL) layer of wiring and vias may be performed.

[0015] Embodiments for forming back contacts may include bonding a carrier substrate to the top surface of a formed nanosheet FET including the BEOL layer, flipping the structure upside down on the BEOL layer, then forming a back opening over the sacrificial layer and removing the sacrificial layer. A self-aligned sacrificial backside contact to the source and drain may be formed within the back opening. Additional layers of lines and vias may be formed over the back contact and may be connected to the back contact.

[0016] Embodiments of forming a backside contact may include using a material different from the material of the bottom dielectric isolation under the nanosheet stack for a dielectric spacer that vertically surrounds the source and drain. When forming the backside opening, a portion of the dielectric spacer may be selectively removed to form a self-aligned sacrificial backside contact that surrounds a portion of the vertical sidewalls of the source and drain and covers the bottom surface of the source and drain.

[0017] Forming self-aligned sacrificial backside contacts has several advantages, including the flexibility to form source-drain contacts either from above or below the structure and the need for fewer contacts overall over the nanosheet device, allowing for larger contact spacing. Having self-aligned contacts is an additional advantage due to the relative alignment accuracy of backside lithography compared to frontside lithography resulting from wafer warpage or thickness non-uniformities. Self-aligned contacts are formed by creating a sacrificial backside contact placeholder under the source-drain epitaxy such that the position of the backside contact is predefined and its formation does not depend on the overlay performance of the backside lithography process.

[0018] The present invention generally relates to the field of semiconductor manufacturing, and more particularly, to backside contacts.

[0019] Embodiments of the present invention disclose a structure, and a method of forming FET nanosheets using self-aligned backside contacts will be described in detail below with reference to the accompanying drawings of FIGS. 1-43 according to the example embodiments.

[0020] Referring now to FIGS. 1, 2, and 3, a semiconductor structure 100 (hereinafter, "the structure") at an intermediate stage of manufacturing is shown in accordance with an exemplary embodiment. FIG. 1 is a top view of the structure 100. FIG. 2 is a cross-sectional view of the structure 100 along the cutting line X-X. FIG. 3 is a cross-sectional view of the structure 100 along the cutting line Y-Y, which is perpendicular to the cutting line X-X. The structure 100 of FIG. 1 may be formed or provided. The structure 100 may include a substrate and a silicon germanium layer 106.

[0021] The substrate may be a silicon-on-insulator (SOI) substrate including a silicon substrate 102, a buried oxide layer 104 (hereinafter, "BOX SiO2") on the silicon substrate 102, and a thin silicon layer 105 on the BOX SiO2 104. In other embodiments, the substrate may be, for example, a bulk substrate made from any of a plurality of known semiconductor materials such as silicon, germanium, silicon germanium alloy, and compound (e.g., group III-V and group II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide, or indium gallium arsenide. Usually, the substrate may be about several 100 microns thick, but is not limited thereto.

[0022] Referring now to FIGS. 4 and 5, the structure 100 is shown in accordance with an exemplary embodiment. FIGS. 4 and 5 are cross-sectional views of the structure 100 along the cutting lines X-X and Y-Y, respectively. FIGS. 4 and 5 are perpendicular to each other. A stack sacrificial layer 108 and a silicon oxide layer 107 are formed from the silicon germanium layer 106 and the thin silicon layer 105.

[0023] The silicon germanium layer 106 may be epitaxially grown to conformally cover the upper surface of the thin silicon layer 105 of the structure 100. The silicon germanium layer 106 may be, for example, silicon germanium having a germanium concentration of about 35 atomic percent to 85 atomic percent, although percentages greater than 85 percent and less than 35 percent may be used.

[0024] The terms "epitaxially grow, or epitaxially deposit, or both" and "epitaxially grown, or epitaxially deposited, or both are performed" mean the growth of a semiconductor material on the deposition surface of a semiconductor material, and the semiconductor material being grown has the same crystal characteristics as the semiconductor material of the deposition surface. In epitaxial film deposition technology, the chemical reactants supplied by the source gas are controlled and the system parameters are set so that the atoms forming the film reach the deposition surface of the semiconductor substrate with sufficient energy, move on the deposition surface, and are oriented in the crystal arrangement of the atoms on the deposition surface. Therefore, an epitaxial semiconductor material has the same crystal characteristics as the deposition surface on which the epitaxial semiconductor material is formed.

[0025] Examples of various epitaxial growth techniques include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature for epitaxial film formation typically ranges from about 550°C to about 900°C. Usually, the higher the temperature, the faster the film formation, but faster film formation may cause crystal defects and film cracks.

[0026] The structure 100 may undergo a thermal oxidation process. This results in the diffusion of germanium from the silicon germanium layer 106 with the thin silicon layer 105, forming the stack sacrificial layer 108 and the silicon oxide layer 107.

[0027] The stack sacrificial layer 108 may be, for example, silicon germanium having a germanium concentration of about 55 atomic percent, but percentages above 55 percent and below 55 percent may be used. Subsequently, as described below, selective removal of the stack sacrificial layer 108 is performed on the remaining alternately overlapping layers. By growing the silicon germanium layer 106 and then following with a silicon germanium enrichment process, the thin silicon layer 105 of the substrate may be converted into the stack sacrificial layer 108.

[0028] Referring now to FIGS. 6 and 7, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 6 and 7 are cross-sectional views of the structure 100 along cut lines X-X and Y-Y, respectively. FIGS. 6 and 7 are perpendicular to each other. The silicon oxide layer 107 may be removed. Stacked nanosheets may be formed on the structure 100.

[0029] The silicon oxide layer 107 may be removed by a method known in the art to expose the top surface of the stack sacrificial layer 108.

[0030] The alternating layers of sacrificial semiconductor material and semiconductor channel material may be collectively referred to as stacked nanosheets.

[0031] The alternating layers of sacrificial semiconductor material and semiconductor channel material may include a sacrificial semiconductor material layer 110 (hereinafter, “sacrificial layer”), which is covered by a semiconductor channel material layer 112 (hereinafter, “channel layer”), which is covered by the sacrificial layer 110, which is covered by the channel layer 112, which is covered by the sacrificial layer 110, which is covered by the channel layer 112, which is covered by the sacrificial layer 110.

[0032] The alternating layers of the sacrificial layer 110 and the channel layer 112 may be formed by sequential epitaxial growth of alternating layers of a first semiconductor material and a second semiconductor material stacked on a substrate. It should be noted that although a limited number of alternating layers are shown, any number of alternating layers may be formed. The epitaxial growth of the first and second semiconductor materials forming the sacrificial semiconductor material layer and the semiconductor channel material layer may be performed using any well-known precursor gas or gas mixture, respectively. Carrier gases such as hydrogen, nitrogen, helium, and argon may be used.

[0033] Each sacrificial layer 110 is made of a first semiconductor material that is different in composition from at least the upper part of the BOX SiO2 104, the channel layer 112, and the stack sacrificial layer 108. In an embodiment, each sacrificial layer 110 may be a silicon germanium semiconductor alloy and may have a germanium concentration of less than 50 atomic percent. In another example, each sacrificial layer 110 may have a germanium concentration ranging from about 20 atomic percent to about 40 atomic percent. Each sacrificial layer 110 can be formed using known film formation techniques or epitaxial growth techniques as described above.

[0034] Each channel layer 112 is made of a second semiconductor material that is different in composition from at least the upper part of the BOX SiO2 104, the sacrificial layer 110, and the stack sacrificial layer 108. Each channel layer 112 has an etching rate different from that of the first semiconductor material of the sacrificial layer 110 and an etching rate different from that of the stack sacrificial layer 108. The second semiconductor material can be, for example, silicon. The second semiconductor material can be formed for each channel layer 112 using known film formation techniques or epitaxial growth techniques as described above.

[0035] The sacrificial layer 110 may have a thickness ranging from about 5 nm to about 15 nm, and the channel layer 112 may have a thickness ranging from about 4 nm to about 12 nm. Each sacrificial layer 110 may have the same or different thickness as the thickness of each channel layer 112. In an embodiment, each sacrificial layer 110 has the same thickness. In an embodiment, each channel layer 112 has the same thickness. The stack sacrificial layer 108 may each have a thickness ranging from about 5 nm to about 12 nm.

[0036] Referring now to FIGS. 8, 9, and 10, a structure 100 is shown according to an exemplary embodiment. FIG. 8 is a top view of the structure 100. FIGS. 9 and 10 are cross-sectional views of the structure 100 along cutting lines X-X and Y-Y, respectively. FIGS. 9 and 10 are perpendicular to each other.

[0037] By removing the unnecessary portions of the nanosheets to form the grooves 114, the active device region is defined. A sacrificial gate 116 and a gate cap 118 may be formed. Cross-section X-X is along the fin of the nanosheet stack, parallel to the adjacent grooves 114, and perpendicular to the sacrificial gate 116. Cross-section Y-Y is between the adjacent sacrificial gates 116, parallel to the sacrificial gates 116, and perpendicular to the fin of the nanosheet stack.

[0038] The stacked sacrificial layer 108 and the layers alternately overlapping the sacrificial layer 110 and the channel layer 112 may be formed on the fin. The fin may have a length perpendicular to the cutting line Y-Y and parallel to the cutting line X-X. The fin may be formed by methods known in the art, which may include steps such as forming a hard mask on the alternately overlapping layers, patterning the hard mask, and subsequent formation of one or more grooves 114 by removal of a portion of each layer of the stacked nanosheets. The grooves 114 may be formed by anisotropic etching techniques that stop at an etching of a portion of the BOX SiO2 104 between each nanosheet stack, such as reactive ion etching (RIE). The BOX SiO2 104 may provide physical and electrical separation between adjacent nanosheet stacks.

[0039] Each fin of the nanosheet stack may include the stacked sacrificial layer 108, which is covered by the sacrificial layer 110, which is covered by the channel layer 112, which is covered by the sacrificial layer 110, which is covered by the channel layer 112, which is covered by the sacrificial layer 110, which is covered by the channel layer 112, which is covered by the sacrificial layer 110, which is covered by the channel layer 112. As an example, three fins are depicted in the drawings of this application, but any number of fins may be formed.

[0040] The material stack that can be employed in the embodiments of the present invention is not limited to the specific embodiments shown in FIGS. 8, 9, and 10. In FIGS. 8, 9, and 10, by way of example only, the nanosheet stack includes three sacrificial layers 110 alternating with three channel layers 112. The nanosheet stack can include any number of sacrificial layers 110 and channel layers 112. The nanosheet stack is used to create a gate-all-around device that includes nanosheets of semiconductor channel material stacked vertically for a p-FET or an n-FET.

[0041] The sacrificial gate 116 and the gate cap 118 are formed perpendicular (at a right angle) to the fin. By way of example, three sacrificial gates 116 are depicted in the drawings of the present application, but any number of sacrificial gates 116 may be formed. The sacrificial gate 116 may include a single sacrificial material or a stack of two or more sacrificial materials. At least one sacrificial material can be formed by forming one or more blanket layers of one material (or various materials) and then patterning the one material (or various materials) by lithography and etching. The sacrificial gate 116 can include any material, including, for example, polysilicon, amorphous silicon, or a combination of these multilayers. In embodiments where amorphous silicon is used as the material for the sacrificial gate 116, a thin layer of SiO2 is first deposited to separate the nanosheet stack from the amorphous silicon. The sacrificial gate 116 can be formed using any film deposition technique, including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin-on techniques. Optionally, the gate cap 118 may be formed as part of the sacrificial gate 116 according to known techniques.

[0042] In an embodiment, the sacrificial gate 116 is formed with a thickness sufficient to fill or substantially fill the space between adjacent nanosheet structures and cover the upper horizontal surface of the top channel layer 112 of the nanosheet stack. The sacrificial gate 116 may be adjacent to the vertical side surfaces of the nanosheet stack or fin. The sacrificial gate 116 may cover the upper horizontal surface of the BOX SiO2 104 between adjacent nanosheet stacks. The height of the sacrificial gate 116 may be considerably thicker than the underlying structure and may have a height of 100 nm to 150 nm around the nanosheet stack. The gate cap 118 may cover the upper horizontal surface of the sacrificial gate 116. Gate patterning may be performed by conventional lithography and etching processes such that a portion of the gate cap 118 and a portion of the sacrificial gate 116 are removed from the subsequently formed source and drain regions.

[0043] Referring now to FIGS. 11 and 12, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 11 and 12 are cross-sectional views of the structure 100 along cut lines X-X and Y-Y, respectively. FIGS. 11 and 12 are perpendicular to each other. The stacked sacrificial layer 108 may be removed. A bottom dielectric isolation 122 (hereinafter, “BDI (bottom dielectric isolation)”) and dielectric spacers 124 may be formed.

[0044] The stacked sacrificial layer 108 may be selectively removed by methods known in the art. For example, dry etching techniques such as using vapor phase HCl dry etching may be used to selectively remove the stacked sacrificial layer 108. Selective removal of the stacked sacrificial layer 108 with respect to the silicon substrate 102, BOX SiO2 104, channel layer 112, sacrificial layer 110, sacrificial gate 116, and gate cap 118 may be performed.

[0045] BDI 122 may be formed where the stacked sacrificial layer 108 has been removed. The BDI 122 may be formed under the bottommost sacrificial layer 110 of the nanosheet stack and on the BOX SiO2 104.

[0046] The dielectric spacer 124 may be formed on the vertical side surfaces of the nano-sheet stack including the vertical side surfaces of the channel layer 112 and the sacrificial layer 112. The dielectric spacer 124 may be formed on the vertical side surfaces of the sacrificial gate 116 and the gate cap 118.

[0047] The BDI 122 and the dielectric spacer 124 may be formed by conformally depositing a dielectric material followed by anisotropic etching. The spacer 124 can be formed by conformal deposition of a dielectric material and an anisotropic RIE process. The BDI 122 and the dielectric spacer 124 may be formed using standard deposition techniques such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin-on techniques, followed by an anisotropic vertical etching process such as reactive ion etching (RIE) or any suitable etching process. In embodiments, the BDI 122 and the dielectric spacer 124 may each include one or more layers. The BDI 122 and the dielectric spacer 124 may each include any dielectric material such as silicon nitride (SiN), silicon boron carbonitride (SiBCN), silicon oxynitride carbide (SiOCN), aluminum oxide (AlOx), SiC, etc., may include a single layer, or may include multiple layers of dielectric materials. The BDI 122 and the dielectric spacer 124 may each include the same material or different materials.

[0048] Referring now to FIGS. 13 and 14, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 13 and 14 are cross-sectional views of the structure 100 along cut lines X-X and Y-Y, respectively. FIGS. 13 and 14 are perpendicular to each other. Source / drain trenches 120 may be formed.

[0049] By methods known in the art, the sacrificial layer 110, the alternately overlapping layers of the channel layer 112, and the BDI 122 may be formed within the nanosheet stack. The source / drain trenches 120 may have a length that is perpendicular to the cut line X-X and parallel to the cut line Y-Y and perpendicular to the fin. The source / drain trenches 120 may be formed between each sacrificial gate 116 surrounded by the dielectric spacer 124 by an anisotropic etching technique that stops at the etching of a portion of the BOX SiO2 104 between each nanosheet stack, such as reactive ion etching (RIE). The BOX SiO2 104 may provide physical and electrical separation between adjacent nanosheet stacks.

[0050] Each nanosheet stack may include a BDI 122, which is covered by the sacrificial layer 110, which is covered by the channel layer 112, which is covered by the sacrificial layer 110, which is covered by the channel layer 112, which is covered by the sacrificial layer 110, which is covered by the channel layer 112, which is covered by the sacrificial layer 110, which is covered by the channel layer 112. On the nanosheet stack, there are the sacrificial gate 116 and the gate cap 118, and the dielectric spacer 124 is on the facing vertical sides. The nanosheet stack may be aligned vertically with respect to the dielectric spacer 124 surrounding the sacrificial gate and the gate cap 118.

[0051] As shown in FIG. 14, a portion of the nanosheet stack may be removed between adjacent sacrificial gates 116, gate caps 118, and dielectric spacers 124. Where the nanosheet stack is removed along the cut line X-X, the dielectric spacer 124 may remain vertically.

[0052] Referring now to FIGS. 15, 16, and 17, a structure 100 is shown in accordance with an exemplary embodiment. FIG. 15 is a top view of the structure 100. FIGS. 16 and 17 are cross-sectional views of the structure 100 along cutting lines X-X and Y-Y, respectively. FIGS. 16 and 17 are perpendicular to each other. Using conventional lithography and etching processes, back contact grooves 134 may be patterned in the BOX SiO2 104. A lithography soft mask, such as an organic planarization layer 130 (hereinafter, “OPL (organic planarization layer)”), may be used in the patterning process.

[0053] The OPL 130 may be formed by blanket deposition using standard film-forming techniques, such as spin-on coating. The OPL 130 can be a self-planarizing organic material that includes carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. The OPL 130 can be a standard C x H y polymer. Non-limiting examples of materials include CHM701B commercially available from Cheil Chemical, HM8006 and HM8014 commercially available from JSR Corporation, and ODL-102 or ODL-401 commercially available from Shin-Etsu Chemical Co., Ltd., but are not limited thereto.

[0054] Dry etching techniques may be used to selectively remove a portion of the OPL 130 that will later be used to form the back contact grooves 134.

[0055] As shown by the cut line X-X in FIG. 12, the back contact groove 134 may be formed between an adjacent pair of the sacrificial gate 116, the gate cap 118, and the dielectric spacers 124 surrounding each sacrificial gate 116, above the adjacent nano-sheet stacks. As shown by the cut line Y-Y in FIG. 13, the back contact groove 134 may be formed between a pair of dielectric spacers 124 where a portion of the nano-sheet stack has been removed between adjacent sacrificial gates 116.

[0056] The back contact groove 134 may be formed by an anisotropic etching technique, such as reactive ion etching (RIE), which removes the aligned portions of the OPL 130 and the BOX SiO2 104 and stops at the etching of a portion of the silicon substrate 102.

[0057] The back contact groove 134 can facilitate the formation of a self-aligned back contact. The back contact groove 134 may be formed within a selected area of the structure 100 where future bottom contacts to the source and drain to be formed later can be formed. There may be one or more back contact grooves 134 in the structure 100.

[0058] Referring now to FIGS. 18 and 19, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 18 and 19 are cross-sectional views of the structure 100 along the cut lines X-X and Y-Y, respectively. FIGS. 18 and 19 are perpendicular to each other. A sacrificial back contact placeholder 136 may be formed.

[0059] A sacrificial back contact placeholder 136 that fills a part of the back contact groove 134 may be formed within the back contact groove 134. The lower surface of the sacrificial back contact placeholder 136 may be adjacent to the upper surface of the silicon substrate 102. The vertical side surfaces of the sacrificial back contact placeholder 136 may be adjacent to the vertical side surfaces of the BOX SiO2 104. A part of the vertical side surfaces of the sacrificial back contact placeholder 136 may be adjacent to a part of the vertical side surfaces of the dielectric spacer 124 surrounding the back contact groove 134. A part of the vertical side surfaces of the sacrificial back contact placeholder 136 may be adjacent to a part of the vertical side surfaces of the BDI 122.

[0060] The sacrificial back contact placeholder 136 may be formed by conformally depositing or growing a sacrificial material, followed by a combination of dry anisotropic etching and wet anisotropic etching, and subsequent etch-back steps. The sacrificial back contact placeholder 136 may be deposited using standard deposition techniques such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin-on techniques, followed by an anisotropic vertical etching process such as reactive ion etching (RIE) or any suitable etching process. The sacrificial placeholder material may also be selectively grown from the substrate 102 by epitaxy, such as a semiconductor material. In an embodiment, the sacrificial back contact placeholder 136 may include one or more layers. In an embodiment, the sacrificial back contact placeholder 136 may include any material that can be a layer that is selectively removed with respect to the BOX SiO2 104, such as SiGe, Ge, III-V semiconductors, silicon oxynitride, silicon nitride, SiBCN, SiOC, SiC, AlOx, TiOx, or any combination of these materials.

[0061] Referring now to FIGS. 20 and 21, a structure 100 is shown according to an exemplary embodiment. FIGS. 20 and 21 are cross-sectional views of the structure 100 along cutting lines X-X and Y-Y, respectively. FIGS. 20 and 21 are perpendicular to each other. The OPL 130 may be removed. The outer portion of the sacrificial layer 110 may be removed. An internal spacer 140 may be formed. A source / drain 144 may be formed.

[0062] A wet etching technique or a dry ashing technique may be used to selectively perform the removal of the OPL 130, which is selective with respect to the silicon substrate 102, the BOX SiO2 104, the sacrificial layer 110, the channel layer 112, the sacrificial gate 116, the gate cap 118, the BDI 122, the dielectric spacer 124, and the sacrificial back contact placeholder 136.

[0063] Using known techniques, the outer portion of the sacrificial layer 110 may be selectively removed. For example, a wet etching process or a dry etching process may be used with an appropriate chemical reaction to remove a portion of each of the sacrificial layer 110. The material used in the etching process may be selective so that the channel layer 112, the sacrificial back contact placeholder 136, the dielectric spacer 124, the BDI 122, the gate cap 118, the sacrificial gate 116, the BOX SiO2 104, and the silicon substrate 102 remain and are not etched. After the etching, a portion of the sacrificial layer 110 covered on both sides by the sacrificial gate 116 may remain as part of the nanosheet stack.

[0064] The internal spacer 140 may be formed by conformally depositing or growing a dielectric material, followed by a combination of dry isotropic etching and wet isotropic etching, and subsequent etch-back steps. The internal spacer 140 may be formed using standard film deposition techniques such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin-on techniques, followed by an isotropic etching process such as a wet etching process or any suitable etching process. In embodiments, the internal spacer 140 may include one or more layers. In embodiments, the internal spacer 140 may include any dielectric material such as silicon oxynitride, silicon nitride, SiBCN, SiOC, or any combination of these materials.

[0065] The internal spacer 140 may completely fill the space between the channel layers 112 where a portion of the sacrificial layer 110 has already been removed.

[0066] The vertical sides of the internal spacer 140 may be aligned with the vertical sides of the channel layers 112, as well as the vertical sides of the dielectric spacers 124 surrounding the sacrificial gate 116 and the gate cap 118.

[0067] Source / drains 144 surrounding the vertical portions of the nanosheet stack on both sides of the sacrificial gate 116 may be epitaxially grown. The bottom surface of the source / drains 144 may be adjacent to the top surface of the sacrificial back contact placeholder 136. The bottom surface of the source / drains 144 may be adjacent to the top surface of the BOX SiO2 104 within an area not including the sacrificial back contact placeholder 136. The vertical sides of the source / drains 144 may be adjacent to the vertical sides of the internal spacer 140, the vertical sides of the BDI 122, and the vertical sides of the channel layers 112. The top surface of the source / drains 144 may be at a distance from the BOX SiO2 104 that is farther than the top surface of the top channel layer 112.

[0068] Referring now to FIGS. 22 and 23, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 22 and 23 are cross-sectional views of the structure 100 along cutting lines X-X and Y-Y, respectively. FIGS. 22 and 23 are perpendicular to each other. An inter-layer dielectric (hereinafter, "ILD (inter-layer dielectric)") 148 may be formed.

[0069] The dielectric material may be conformally deposited or grown, followed by a CMP or etching step, and then the ILD 148 may be formed. The ILD 148 may be formed using standard deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin-on techniques, followed by a planarization process such as CMP or any suitable etching process. In an embodiment, the ILD 148 may include one or more layers. In an embodiment, the ILD 148 may include any dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, SiBCN, SiOC, a low dielectric constant dielectric, or any combination of these materials. The lower surface of the ILD 148 may be adjacent to the upper surface of the source / drain 144. A further lower surface of the ILD 148 may be adjacent to the upper surface of the box 104. The vertical side surfaces of the ILD 148 may be adjacent to the vertical side surfaces of the dielectric spacer 124.

[0070] Chemical mechanical polishing (CMP) techniques may be used to remove excess material, polish the upper surface of the structure 100, remove the gate cap 118, and expose the upper horizontal surface of the sacrificial gate 116. The upper surface of the structure 100 may include the upper horizontal surface of the ILD 148 and the upper horizontal surface of the dielectric spacer 124.

[0071] Referring now to FIGS. 24 and 25, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 24 and 25 are cross-sectional views of the structure 100 along cutting lines X-X and Y-Y, respectively. FIGS. 24 and 25 are perpendicular to each other. The sacrificial gate 116 may be removed. The sacrificial layer 110 may be removed. A high-k metal gate 152 may be formed.

[0072] The sacrificial gate 116 may be removed by methods known in the art. The sacrificial layer 110 is removed selectively with respect to the channel layer 112, the inner spacer 140, the ILD 148, the dielectric spacer 124, the BDI 122, the sacrificial back contact placeholder 136, the BOX SiO2 104, and the silicon substrate 102. For example, a dry etching process such as using vapor phase HCl dry etching may be used to selectively remove the sacrificial layer 110. The upper and lower surfaces of the channel layer 112 may be exposed. The upper surface of the BDI 122 may be exposed.

[0073] According to an exemplary embodiment, in the structure 100, a high-k metal gate 152 may be conformally formed. The high-k metal gate 152 is formed in each cavity surrounding the suspended portion of the channel layer 112 of the nanosheet stack. The high-k metal gate 152 forms a layer surrounding the exposed portion of the nanosheet stack. The high-k metal gate 152 may cover the exposed upper horizontal surface of the BDI 122, the exposed vertical side surface on one side of the side spacer 140, the exposed vertical surface on one side of the dielectric spacer 124, and the exposed upper horizontal surface of the BDI 122. The high-k metal gate 152 may cover the vertical side surface, the upper horizontal surface, and the lower horizontal surface of the channel layer 110. The high-k metal gate 152 may fill the space between the dielectric spacers 124 above the nanosheet stack where the sacrificial gate 116 has been removed.

[0074] The high-k metal gate 152 may be formed using standard film deposition techniques such as atomic layer deposition (ALD), molecular layer deposition (MLD), and chemical vapor deposition (CVD). In an embodiment, the high-k metal gate 152 may include conformal layers of high-k dielectric materials such as two or more layers, for example, HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , SiON, SiN x , these silicates, and alloys thereof. In an embodiment, the work function metal of the p-FET device may include a metal nitride such as titanium nitride or tantalum nitride, titanium carbide, titanium aluminum carbide, or other suitable materials known in the art. In an embodiment, the work function metal of the n-FET device may include, for example, titanium aluminum carbide or other suitable materials known in the art. In an embodiment, the work function metal may include one or more layers to achieve desired device characteristics.

[0075] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the top surface of the structure 100. The top surface of the structure 100 may include the upper horizontal plane of the ILD 148, the upper horizontal plane of the dielectric spacer 124, and the upper horizontal plane of the high-k metal gate 152.

[0076] Referring now to FIGS. 26 and 27, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 26 and 27 are cross-sectional views of the structure 100 along cut lines X-X and Y-Y, respectively. FIGS. 26 and 27 are perpendicular to each other. An interlayer dielectric (hereinafter, “ILD”) 154 may be formed. An upper contact 156 may be formed.

[0077] The ILD 154 may be conformally formed as described with respect to the ILD 148. The lower horizontal plane of the ILD 154 may be adjacent to the upper horizontal plane of the high-k metal gate 152, the upper horizontal plane of the dielectric spacer 124, and the upper horizontal plane of the ILD 148.

[0078] Openings (not shown) may be made in the structure 100 to expose the upper horizontal plane of the source / drain 144 through the ILD 154 and the ILD 148. The upper contact 156 may be formed within the opening (not shown) to form a contact to the source / drain 144. As shown in FIG. 23, there are two upper contacts 156. Any number of upper contacts 156 may be present in the structure 100.

[0079] Upper contacts 156 may be made to the source / drain 144 that do not have the sacrificial back contact placeholder 136 under the source / drain 144. The source / drain 144 having the sacrificial back contact placeholder 136 may have lower contacts as may be formed in subsequent processing steps. Each of the source / drains 144 may have either an upper contact 156 or a lower contact.

[0080] Extra materials may be removed and the upper surface of the structure 100 polished using chemical mechanical polishing (CMP) techniques to expose the upper horizontal surface of the ILD 154 and the upper horizontal surface of the upper contact 156.

[0081] Referring now to FIGS. 28 and 29, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 28 and 29 are cross-sectional views of the structure 100 along cut lines X-X and Y-Y, respectively. FIGS. 28 and 29 are perpendicular to each other. A back end of line (hereinafter, “BEOL”) layer 160 may be formed. A carrier wafer 162 may be bonded to the structure 100.

[0082] The BEOL layer 160 may include layers of wiring and vias formed over existing structures over the contacts 145 and the ILD 154. In an embodiment, the BEOL layer 160 may include 12 or more layers of metal lines and vias. The BEOL layer 160 may be formed using known techniques.

[0083] The carrier wafer 162 may be attached to the upper surface of the BEOL layer 160 and attached to the upper surface of the structure 100. The carrier wafer may be attached using a conventional wafer bonding process, such as a dielectric-to-dielectric bonding process or a copper-to-copper bonding process.

[0084] Referring now to FIGS. 30 and 31, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 30 and 31 are cross-sectional views of the structure 100 along cut lines X-X and Y-Y, respectively. FIGS. 30 and 31 are perpendicular to each other. The structure 100 may be inverted and the silicon substrate 102 removed.

[0085] Here the carrier wafer 162 is shown at the bottom of FIGS. 30 and 31 at the lowest point of the structure, where the structure 100 may be rotated such that the lower surface of the silicon substrate 102 is shown above the structure for further processing.

[0086] The silicon substrate 102 may be selectively removed using a combination of process steps such as wafer grinding, CMP, RIE, and wet etching processes. The final stage of the process may include selectively etching the silicon remaining on the silicon substrate 102 to expose the surface of the BOX SiO2 104 and to expose the sacrificial back contact placeholder 136.

[0087] The silicon substrate 102 may be removed, and the upper horizontal plane of the structure 100 includes the upper horizontal plane of the sacrificial back contact placeholder 136 and the upper horizontal plane of the BOX SiO2 104. Two or more sacrificial back contact placeholders 136 may be present. Each of the sacrificial back contact placeholders 136 may be adjacent to a source / drain 144 that does not have an upper contact 156.

[0088] Referring now to FIGS. 32 and 33, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 32 and 33 are cross-sectional views of the structure 100 along cut lines X-X and Y-Y, respectively. FIGS. 32 and 33 are perpendicular to each other. The sacrificial back contact placeholder 136 may be removed to form a lower contact opening 166.

[0089] Using known techniques, the sacrificial back contact placeholder 136 may be selectively removed to form the lower contact opening 166. For example, a wet etching process or a dry etching process may be used in combination with an appropriate chemical reaction to remove the sacrificial back contact placeholder 136. The material used in the etching process may be selective such that the BDI 122 and the BOX SiO2 104 remain and are not etched.

[0090] Referring now to FIGS. 34 and 35, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 34 and 35 are cross-sectional views of the structure 100 along cutting lines X-X and Y-Y, respectively. FIGS. 34 and 35 are perpendicular to each other. Contact opening enlargement cleaning may be performed.

[0091] Contact opening enlargement cleaning may be performed to enlarge the size of the lower contact opening 166 and remove the native oxide on the source / drain 144. During this process, the horizontal portion of the BOX SiO2 104 and the vertical portion of the BOX SiO2 104 may be etched to increase the size of the lower contact opening 166. Examples of contact opening enlargement cleaning may include a DHF wet cleaning process or a SiCoNi dry cleaning process. Siconi is a trademark of Applied Materials, Inc.

[0092] Contact opening enlargement cleaning may expose a portion of the upper surface of the BDI 122. Contact opening enlargement cleaning may expose a portion of the upper surface and a portion of the vertical surface of a pair of dielectric spacers 124 surrounding the lower contact opening 166. As the lower contact opening 166 is enlarged, the high-k metal gate 152 is separated from the lower contact opening 166 due to the BDI 122. The enlarged lower contact opening 166 is beneficial for forming a larger volume of silicide and metal plugs, which helps to reduce the contact resistance of the contacts formed later in the lower contact opening 166.

[0093] Referring now to FIGS. 36 and 37, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 36 and 37 are cross-sectional views of the structure 100 along cutting lines X-X and Y-Y, respectively. FIGS. 36 and 37 are perpendicular to each other. A lower contact 172 may be formed.

[0094] To form a contact to the source-drain 144, a lower contact 172 may be formed within the lower contact opening 166. As shown in FIGS. 36 and 37, there is one lower contact 172. Any number of lower contacts 172 may be present in the structure 100.

[0095] Forming the lower contact 172 includes filling the lower contact opening 166 with a highly conductive metal material. For clarity, the individual metal materials within the lower contact 172 are not shown. Most of the lower contact 172 includes an elemental metal such as Co, Ru, or Mo to reduce the bulk resistivity, but a metal compound directly adjacent to the semiconductor of the source-drain 144 is selected to reduce the contact resistivity between the lower contact 172 and the semiconductor of the source-drain 144. In one embodiment, the metal compound adjacent to the semiconductor of the source-drain 144 is a metal silicide or germanosilicide. This compound can be created by reacting an elemental metal such as titanium with the semiconductor of the source-drain 144. The metal silicide / germanosilicide is made thin (usually less than 3 nm), but sets the Schottky barrier at the interface between the semiconductor and the metal, and ultimately sets the contact resistivity of this interface. The metal silicide / germanosilicide may be separated from the filling of the elemental metal of the lower contact 172 by a thin conductive metal liner such as a titanium nitride liner. The high concentration of free carriers in the semiconductor of the source-drain 144 and the low Schottky barrier between the metal silicide / germanosilicide and the semiconductor of the source-drain 144 enable a contact resistivity of about 10 -9 W·cm 2 for the back contact structure to both n-type and p-type semiconductors. Compared to the filling of the elemental metal, the additional interfacial compounds and liners are made thin, and the interfacial resistance between each metal is at least one order of magnitude lower than the interfacial resistance at the interface between the semiconductor and the metal, so the presence of multiple metal compounds within the lower contact 172 does not significantly affect the series resistance.

[0096] The contact resistivity of the source / drain 144 to the adjacent metal compound of the lower contact 172 may be 1e-9 ohm cm. 2 It may be as follows. The volume concentration of free electric carriers (electrons or holes) in the source / drain 144 may be 7e20 cm -3 or more.

[0097] In comparison, the contact resistivity of the source / drain 144 to the contact 156 may be 2e-9 ohm cm 2 or more. The volume concentration of free electric carriers (electrons or holes) in the source / drain 144 may be 5e20 cm -3 or less.

[0098] A lower contact 172 may be made to the source / drain 144 without the upper contact 156. The source / drain 144 may have either the upper contact 156 or the lower contact 172. This provides additional options for source / drain contacts. In one example, the source / drains 144 of the n-FET nanosheet stack may each have an upper contact 156, and the source / drains 144 of the p-FET nanosheet stack may each have a lower contact 172. Alternative means are also embodiments.

[0099] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the top surface of the structure 100. The top surface of the structure 100 may include the upper horizontal plane of the BOX SiO2 104 and the upper horizontal plane of the lower contact 172.

[0100] Referring now to FIGS. 38 and 39, a structure 100 is shown in accordance with an exemplary embodiment. FIGS. 38 and 39 are cross-sectional views of the structure 100 along cut lines X-X and Y-Y, respectively. FIGS. 38 and 39 are perpendicular to each other. An interlayer dielectric (hereinafter, "ILD") 176 may be formed. A backside power rail (hereinafter, "BPR (backside power rail)") 178 and a backside power delivery network (hereinafter, "BSPDN (backside power delivery network)") 180 may be formed.

[0101] As described with respect to ILD148, the ILD 176 may be formed by conformally depositing or growing a dielectric material. The bottom surface of the ILD 148 may be adjacent to the upper horizontal surface of the BOX SiO2 104 and the upper horizontal surface of the lower contact 172.

[0102] Using known techniques, the BPR 178 may be formed in an opening (not shown) in the ILD 176. In an embodiment, the BPR 178 may be parallel to the cut line X-X and perpendicular to the cut line Y-Y. The lower horizontal surface of the BPR 178 may be adjacent to the upper horizontal surface of the lower contact 172. As shown in FIG. 39, there are three BPRs 178, but any number of BPRs 178 may be present in the structure 100.

[0103] The BSPDN 180 may be formed on the ILD 176 and the BPR 178. The BSPDN 180 may include additional layers of wiring and vias formed on top of existing structures on the ILD 176 and the BPR 178. In an embodiment, the BSPDN 180 may include three or more layers of lines and vias. The BSPDN 180 may be formed using known techniques.

[0104] The resulting structure 100 includes a FET nanosheet, along with a self-aligned back contact (lower contact 172), provides a contact having an enlarged size without shorting to the high-k metal gate 152, and enables an additional option for forming the lower contact 172 to the FET nanosheet on the back surface of the structure.

[0105] Referring now to FIGS. 40 and 41, a structure 101 is shown in accordance with an exemplary embodiment. FIGS. 40 and 41 are cross-sectional views of the structure 101 along cut lines X-X and Y-Y, respectively. FIGS. 40 and 41 are perpendicular to each other. The structure 101 is an alternative embodiment of the structure 100. The structure 101 may be formed as described with respect to the structure 100 and is an alternative embodiment showing the processing steps after the processing steps shown in FIGS. 34 and 35. All parts having similar names may be formed as described with respect to FIGS. 1-39.

[0106] The openings 166 as shown in FIGS. 34 and 35 may be increased by selective removal of a portion of the dielectric spacer 124 surrounding the source / drain 144 of the opening 166. In this embodiment, the dielectric spacer 124 is a material different from the BDI 122 and may be selectively etched. In an embodiment, the dielectric spacer 124 may include SiN, SiBCN, or SiOCN, and the BDI may include SiC.

[0107] The lower contact 173 may be formed within the opening 166 having an increased volume here. The lower contact 173 may surround a portion of the side surface of the source / drain 144.

[0108] To form a contact to the source / drain 144, the lower contact 173 may be formed within the lower contact opening 166. As shown in FIGS. 40 and 41, one lower contact 173 is present. Any number of lower contacts 173 may be present in the structure 101.

[0109] Lower contacts 173 may be made to source / drain 144 without upper contacts 156. The source / drain 144 may have either upper contacts 156 or lower contacts 173. This provides additional options for source / drain contacts. In one example, the source / drain 144 of the n-FET nanosheet stack may each have upper contacts 156, and the source / drain 144 of the p-FET nanosheet stack may each have lower contacts 173. Alternative means are also embodiments.

[0110] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the top surface of the structure 101. The top surface of the structure 101 may include the upper horizontal plane of the BOX SiO2 104 and the upper horizontal plane of the lower contacts 173.

[0111] Referring now to FIGS. 42 and 43, a structure 101 is shown according to an example embodiment. FIGS. 42 and 43 are cross-sectional views of the structure 101 along cut lines X-X and Y-Y, respectively. FIGS. 42 and 43 are perpendicular to each other. An interlayer dielectric (hereinafter, "ILD") 176 may be formed. A backside power rail (hereinafter, "BPR") 178 and a backside power supply distribution network (hereinafter, "BSPDN") 180 may be formed.

[0112] As described with respect to the ILD 148, the ILD 176 may be formed by conformally depositing or growing a dielectric material. The bottom surface of the ILD 148 may be adjacent to the upper horizontal plane of the BOX SiO2 104 and the upper horizontal plane of the lower contacts 173.

[0113] Using known techniques, BPR178 may be formed in an opening (not shown) within ILD176. In an embodiment, BPR178 may be parallel to cutting line X-X and perpendicular to cutting line Y-Y. The lower horizontal plane of BPR178 may be adjacent to the upper horizontal plane of lower contact 173. As shown in FIG. 43, there are three BPR178s, but any number of BPR178s may be present in structure 100.

[0114] BSPDN180 may be formed on ILD176 and BPR178. BSPDN180 may include additional layers of wiring and vias formed on top of existing structures on ILD176 and BPR178. In an embodiment, BSPDN180 may include three or more layers of lines and vias. BSPDN180 may be formed using known techniques.

[0115] The resulting structure 101 includes a FET nanosheet with a self-aligned back contact (contact 173) and provides a contact having an enlarged size compared to contact 172 of structure 100. Contact 172 is formed by spreading within an area where a portion of dielectric spacer 124 surrounding source / drain 144 is removed, forming a wraparound contact surrounding source / drain 144 that does not short-circuit with high-k metal gate 152. This provides an additional option for forming contact to the FET nanosheet on the back surface of the structure.

[0116] An advantage of structure 101 compared to structure 100 is that lower contact 173 has contact to source / drain 144 of structure 101 with a larger surface area than lower contact 172 of structure 100. This has the advantage of reducing contact resistance with a specific contact resistivity of the materials used.

[0117] The descriptions of the various embodiments of the present invention are presented for illustrative purposes, but are not intended to be exhaustive and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the present invention. The terms used herein are selected to best explain the principles of the embodiments, actual applications, or technological improvements over the technologies found in the marketplace, or to enable other skilled artisans to understand the embodiments disclosed herein.

[0118] In a preferred embodiment of the invention described herein, there is provided a semiconductor device comprising a first source-drain region and a lower source-drain contact aligned vertically below the first source-drain region and electrically connected to the first source-drain region, the lower source-drain contact surrounding a vertical side surface of a second source-drain region. The lower source-drain contact may comprise a vertical side surface adjacent to a vertical side surface of a lower dielectric isolation region below a second nanosheet stack. The lower source-drain contact may comprise a horizontal surface adjacent to a horizontal surface of a liner surrounding the first source-drain region. The device may further comprise a backside power rail connected to the lower source-drain contact below the lower source-drain contact. The device may further comprise a backside power supply network below the embedded power rail.

Claims

1. A first source-drain region adjacent to a first transistor on a substrate, a second source-drain region adjacent to a second transistor on the substrate, an upper source-drain contact vertically aligned on the first source-drain region and electrically connected to the first source-drain region, a lower source-drain contact vertically aligned under the second source-drain region and electrically connected to the second source-drain region A semiconductor device comprising: wherein the lower source-drain contact and the upper source-drain contact are on both sides of the semiconductor device, a horizontal plane of the lower source-drain contact is adjacent to a horizontal plane of a dielectric side spacer surrounding the second source-drain region, a width of the lower source-drain contact is wider than a width of the second source-drain, Semiconductor device.

2. The semiconductor device according to claim 1, wherein the lower source-drain contact comprises a vertical side adjacent to a vertical side of a lower dielectric isolation region under the second transistor.

3. The semiconductor device according to claim 1, wherein the lower source-drain contact comprises a part of an upper horizontal plane adjacent to a part of a lower horizontal plane of a lower isolation region between the substrate and the second transistor.

4. The semiconductor device according to claim 1, further comprising a backside power rail connected to the lower source-drain contact under the lower source-drain contact.

5. The semiconductor device according to claim 1, further comprising a backside power supply network under the embedded power rail.

6. Forming a first nanosheet stack and a second nanosheet stack on a substrate, Forming an upper source-drain contact on an upper horizontal plane of a first source-drain region adjacent to the first nanosheet stack, Bonding a carrier wafer to an upper surface of the substrate above the first nanosheet stack and the second nanosheet stack, Forming a lower source-drain contact to a lower horizontal surface of a second source-drain region adjacent to the second nanosheet stack, the lower source-drain contact and the second source-drain region being vertically aligned; A method comprising: A method in which the lower source-drain contact surrounds a vertical side surface of the second source-drain region. **Claim 7** The method of claim 6, wherein the lower source-drain contact comprises a vertical side surface adjacent to a vertical side surface of a lower dielectric isolation region under the second nanosheet stack. **Claim 8** The method of claim 7, wherein the lower source-drain contact comprises a vertical side surface adjacent to a vertical side surface of a liner of the second source-drain, the liner of the second source-drain being between the second source-drain and a gate work function metal of the second nanosheet stack. **Claim 9** The method of claim 6, further comprising an epitaxial region between the lower source-drain contact and the second source-drain region. **Claim 10** The method of claim 9, wherein a lower horizontal surface of the epitaxial region is below a lower horizontal surface of a lower dielectric isolation region under the second nanosheet stack. **Claim 11** An embedded power rail above the lower source-drain contact and connected to the lower source-drain contact; A backside power supply network above the embedded power rail The method of claim 6, further comprising. **Claim 12** The method of claim 6, further comprising a lower dielectric isolation region under the first nanosheet stack and under the second nanosheet stack. **Claim 13** The first nanosheet stack comprises alternatingly overlapping layers of a work function metal and a semiconductor channel material vertically aligned and stacked; The method of claim 6, wherein the second nanosheet stack comprises alternatingly overlapping layers of a work function metal and the semiconductor channel material vertically aligned and stacked. **Claim 14** The method of claim 6, further comprising an undoped silicon buffer epitaxial region between the lower source-drain contact and the first source-drain region. **Claim 15** The method according to claim 6, further comprising vertical spacers on both sides of the first source / drain region.

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