Self-aligned back contact having an increased contact area

Abstract

The first and second source-drain regions, with an upper source-drain contact connected to the first source-drain region and a lower source-drain contact connected to the second source-drain region, a dielectric spacer surrounding the facing vertical sides of the lower source-drain contact, the dielectric spacer overlapping the vertical sides and the lower horizontal plane of the lower isolation region. The width of the lower source-drain contact is wider than the width of the second source-drain. Undoped silicon buffer epitaxy is formed between the first nanosheet stack and the second nanosheet stack and within the lower opening, forming a contact to the first source-drain adjacent to the first source-drain, removing the undoped silicon buffer epitaxy under the second source-drain between the first nanosheet stack and the second nanosheet stack, forming a lower contact to the second source-drain, and the width of the lower contact being wider than the width of the second source-drain.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor manufacturing, and more particularly, to back contacts.

Background Art

[0002] Complementary Metal-oxide-semiconductor (CMOS) technology is generally used in field effect transistors (hereinafter, "FETs") as part of advanced integrated circuits (hereinafter, "ICs") such as central processing units (hereinafter, "CPUs"), memories, and storage devices. Due to the continuing demand to reduce the dimensions of transistor devices, nanosheet FETs help to achieve a reduced footprint of FET devices while maintaining the performance of the FET devices. A nanosheet device includes one or more layers of a semiconductor channel material portion having a vertical thickness that is significantly smaller than the width. A nanosheet FET includes a plurality of stacked nanosheets extending between a pair of source / drain epitaxial regions. This device can be a gate-all-around device or a gate-all-around transistor in which the gate surrounds a portion of the nanosheet channel.

Summary of the Invention

[0003] According to an embodiment, a semiconductor device is provided. This semiconductor device includes a first source-drain region, a second source-drain region, an upper source-drain contact aligned vertically above the first source-drain region and electrically connected to the first source-drain region, and a lower source-drain contact aligned vertically below the second source-drain region and electrically connected to the second source-drain region. The lower source-drain contact and the upper source-drain contact are on both sides of the semiconductor device. A dielectric spacer surrounds the opposing vertical side surfaces of the lower source-drain contact, and the dielectric spacer overlaps the vertical side surfaces and the lower horizontal surface of the lower isolation region.

[0004] According to an embodiment, a semiconductor device is provided. This semiconductor device includes a first source-drain region, a second source-drain region, an upper source-drain contact aligned vertically above the first source-drain region and electrically connected to the first source-drain region, and a lower source-drain contact aligned vertically below the second source-drain region and electrically connected to the second source-drain region. The lower source-drain contact and the upper source-drain contact are on both sides of the semiconductor device. A dielectric spacer surrounds the opposing vertical side surfaces of the lower source-drain contact, the dielectric spacer overlaps the vertical side surfaces and the lower horizontal surface of the lower isolation region, and the width of the lower source-drain contact is wider than the width of the second source-drain.

[0005] According to an embodiment, a method is provided. The method includes forming a double nanosheet stack on a substrate, forming a shallow trench isolation between adjacent double nanosheet stacks, splitting the double nanosheet stack into a first nanosheet stack and a second nanosheet stack, forming a shallow trench isolation within the split double nanosheet stack, forming an undoped silicon buffer epitaxy between the first nanosheet stack and the second nanosheet stack and within an opening thereunder, forming an upper source-drain contact to an upper horizontal plane of a first source-drain region adjacent to the first nanosheet stack, bonding a carrier wafer to an upper surface of the substrate over the first nanosheet stack and the second nanosheet stack, removing the undoped silicon buffer epitaxy under a second source-drain region between the first nanosheet stack and the second nanosheet stack, and forming a lower source-drain contact to a lower horizontal plane of the second source-drain region, wherein the lower source-drain contact and the second source-drain region are vertically aligned, and the width of the lower source-drain contact is wider than the width of the second source-drain region.

[0006] These and other objects, features, and advantages of the present invention will become apparent from the following detailed description of example embodiments of the present invention, read in conjunction with the accompanying drawings. For the purpose of clarity in facilitating understanding by those skilled in the art of the present invention, in combination with the detailed description, the various features of the drawings are not to scale.

Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0008] For the sake of simplicity and clarity of explanation, it will be understood that the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some of the elements may be exaggerated compared to other elements for clarity. Further, when considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or similar features.

[0009] Although detailed embodiments of the claimed structures and methods are disclosed herein, it can be understood that the disclosed embodiments are merely examples of the claimed structures and methods that may be embodied in various forms. However, the present invention may be embodied in various forms and should not be construed as limited to the example embodiments shown herein. In the description, well-known features and technical details may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0010] References to "one embodiment", "an embodiment", "an example embodiment", etc. in this specification do not necessarily mean that all such references are to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. That is, while the described embodiments may include a particular feature, structure, or characteristic, not all embodiments necessarily can include that particular feature, structure, or characteristic. Also, such phrases do not necessarily refer to the same embodiment.

[0011] When an element is considered to be "on" or "over" another element as a layer, region, or substrate, it will be understood that the element can be directly on the other element or intervening elements may be present. In contrast, when an element is considered to be "directly on" or "directly over" another element, no intervening elements are present. When an element is considered to be "connected" or "coupled" to another element, it will also be understood that the element can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is considered to be "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0012] To avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined together for purposes of presentation and illustration and, in some cases, may not be described in detail. In other instances, some processing steps or operations known in the art may not be described at all. It should be understood that the following description is rather focused on the distinct features or elements of the various embodiments of the present invention.

[0013] A nanosheet field effect transistor (hereinafter, “FET”) can be formed. A layer of stacked nanosheets is formed on a substrate, and in the layer of stacked nanosheets, grooves are formed parallel to each other to form double-width fins and shallow trench isolation regions formed between the double-width fins. To divide the double-width fins into two fins, grooves are formed in each double-width fin, and shallow trench isolation regions are formed between the two fins. Next, a sacrificial gate is formed perpendicular to the grooves. Additional grooves are formed between the sacrificial gates perpendicular to the original grooves. Dielectric spacers may be formed surrounding the nanosheet stack and the underlying isolation region formed under the nanosheet stack. The outer portion of the sacrificial layer of the stacked nanosheets may be removed, and an internal spacer is formed where the outer portion of the sacrificial layer of the stacked nanosheets has been removed. In an embodiment of the present invention, the grooves may extend into the substrate, and the sacrificial layer is formed in a part of the grooves in the substrate. This groove may be formed where a back contact to the source / drain can be formed later. Undoped silicon buffer epitaxy may be formed between adjacent nanosheet stacks. Source / drain regions of either a positive FET (p-FET) or a negative FET (n-FET) extending out from the exposed channel layer of the nanosheet stack are formed. The sacrificial gate is removed, and the remaining portion of the sacrificial layer is removed. Where the sacrificial gate and the remaining portion of the sacrificial layer have been removed, a metal gate surrounding the channel layer may be formed. Contacts may be formed to the metal gate and to each source / drain, particularly to the source / drain area having no sacrificial layer under the source / drain. Further formation of a back end of line (BEOL) layer of wiring and vias may be performed.

[0014] Embodiments for forming a backside contact may include bonding a carrier substrate to the top surface of a formed nanosheet FET including a BEOL layer, flipping the structure upside down on the BEOL layer, then forming a backside opening over a sacrificial layer and removing the sacrificial layer. A self-aligned sacrificial backside contact to the source / drain through the backside opening may be formed within the opening. Additional layers of wires and vias may be formed over and connected to the backside contact.

[0015] Forming a self-aligned sacrificial backside contact has several advantages, including the flexibility to form source / drain contacts either from above or below the structure and the ability to form contacts with a greater pitch because fewer contacts are required overall over the nanosheet device. Having self-aligned contacts is an additional advantage due to the relative alignment accuracy of backside lithography compared to frontside lithography resulting from wafer warping or thickness non-uniformities. Self-aligned contacts are formed by creating a sacrificial backside contact placeholder under the source / drain epitaxy such that the position of the backside contact is predefined and formation is independent of the overlay performance of the backside lithography process.

[0016] The present invention generally relates to the field of semiconductor manufacturing and, more particularly, to backside contacts.

[0017] Referring now to FIGS. 1, 2, and 3, a semiconductor structure 200 (hereinafter, the "structure") at an intermediate stage of manufacture is shown in accordance with an exemplary embodiment. FIG. 1 is a top view of the structure 200. FIG. 2 is a cross-sectional view of the structure 200 taken along cut line X-X. FIG. 3 is a cross-sectional view of the structure 200 taken along cut line Y-Y, which is perpendicular to cut line X-X. The structure 200 of FIG. 1 may be formed or provided.

[0018] The structure 200 may include a substrate 202, a silicon germanium layer 204 on the substrate 202, and a thin silicon layer 206 on the silicon germanium layer 204.

[0019] The substrate 202 can be made of any of a plurality of known semiconductor materials, such as, for example, silicon, germanium, silicon germanium alloy, and compound (e.g., group III-V and group II-VI) semiconductor materials, and may be, for example, a bulk substrate. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide, or indium gallium arsenide. Typically, the substrate 202 may be about a few hundred microns thick, but is not limited thereto.

[0020] The silicon germanium layer 204 may be epitaxially grown to conformally cover the upper surface of the substrate 202 of the structure 200. The silicon germanium layer 204 may be, for example, silicon germanium having a germanium concentration of about 30 atomic percent, but percentages greater than 30 percent and less than 30 percent may be used.

[0021] The terms "epitaxially grow, or epitaxially deposit, or both" and "epitaxially grown, or epitaxially deposited, or both are performed" mean the growth of a semiconductor material on the deposition surface of a semiconductor material, and the semiconductor material being grown has the same crystal characteristics as the semiconductor material of the deposition surface. In epitaxial film deposition technology, the chemical reactants supplied by the source gas are controlled and the system parameters are set so that the atoms forming the film reach the deposition surface of the semiconductor substrate with sufficient energy, move on the deposition surface, and are oriented in the crystal arrangement of the atoms on the deposition surface. Therefore, an epitaxial semiconductor material has the same crystal characteristics as the deposition surface on which the epitaxial semiconductor material is formed.

[0022] Examples of various epitaxial growth techniques include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature for epitaxial film formation generally ranges from about 550°C to about 900°C. Usually, the higher the temperature, the faster the film formation, but faster film formation may cause crystal defects and film cracks.

[0023] The thin silicon layer 206 may be epitaxially grown to conformally cover the upper surface of the silicon germanium layer 206.

[0024] Referring now to FIGS. 4 and 5, a structure 200 is shown in accordance with an exemplary embodiment. FIGS. 4 and 5 are cross-sectional views of the structure 200 along cutting lines X-X and Y-Y, respectively. FIGS. 4 and 5 are perpendicular to each other. A stack sacrificial layer 208 may be formed, and stacked nanosheets may be formed.

[0025] The stack sacrificial layer 208 may be, for example, silicon germanium having a germanium concentration of about 55 atomic percent, although percentages greater than 55 percent and less than 55 percent may be used. The stack sacrificial layer 208 may be epitaxially grown in the structure 200.

[0026] Layers in which a sacrificial semiconductor material and a semiconductor channel material alternately overlap may be collectively referred to as stacked nanosheets. Layers in which a sacrificial semiconductor material and a semiconductor channel material alternately overlap may include a sacrificial semiconductor material layer 210 (hereinafter, “sacrificial layer”), and this sacrificial layer 210 is covered by a semiconductor channel material layer 212 (hereinafter, “channel layer”), and this semiconductor channel material layer 212 is covered by the sacrificial layer 210, and this sacrificial layer 210 is covered by the channel layer 212, and this channel layer 212 is covered by the sacrificial layer 210, and this sacrificial layer 210 is covered by the channel layer 212.

[0027] Layers in which the sacrificial layer 210 and the channel layer 212 alternately overlap may be formed by sequential epitaxial growth of layers in which a first semiconductor material and a second semiconductor material alternately overlap, stacked on a substrate. Note that although a limited number of alternately overlapping layers are shown, any number of alternately overlapping layers may be formed. The epitaxial growth of the first and second semiconductor materials forming the sacrificial semiconductor material layer and the semiconductor channel material layer may be performed using any well-known precursor gas or gas mixture, respectively. Carrier gases such as hydrogen, nitrogen, helium, and argon may be used.

[0028] Each sacrificial layer 210 is made of a first semiconductor material that is different in composition from at least the upper portion of the thin silicon layer 206, the channel layer 212, and the stack sacrificial layer 208. In an embodiment, each sacrificial layer 210 may be a silicon germanium semiconductor alloy and may have a germanium concentration of less than 50 atomic percent. In another example, each sacrificial layer 210 may have a germanium concentration ranging from about 20 atomic percent to about 40 atomic percent. Each sacrificial layer 210 may be formed using known film formation techniques or epitaxial growth techniques as described above.

[0029] Each channel layer 212 is made of a second semiconductor material that is different in composition from at least the upper portion of the thin silicon layer 206, the sacrificial layer 210, and the stacked sacrificial layer 208. Each channel layer 212 has an etching rate different from that of the first semiconductor material of the sacrificial layer 210 and a different etching rate from that of the stacked sacrificial layer 208. The second semiconductor material can be, for example, silicon. The second semiconductor material can be formed for each channel layer 212 using known film formation techniques or epitaxial growth techniques as described above.

[0030] The sacrificial layer 210 may have a thickness ranging from about 5 nm to about 15 nm, and the channel layer 212 may have a thickness ranging from about 4 nm to about 12 nm. Each sacrificial layer 210 may have the same or different thicknesses as the thickness of each channel layer 212. In an embodiment, each sacrificial layer 210 has the same thickness. In an embodiment, each channel layer 212 has the same thickness. The stacked sacrificial layers 208 may each have a thickness ranging from about 5 nm to about 12 nm.

[0031] Each channel layer 212 is made of a second semiconductor material that is different in composition from at least the upper portion of the thin silicon layer 206, the silicon germanium layer 204, the sacrificial layer 210, and the stacked sacrificial layer 208. Each channel layer 212 has an etching rate different from that of the first semiconductor material of the sacrificial layer 210 and a different etching rate from that of the stacked sacrificial layer 208.

[0032] Referring now to FIGS. 6 and 7, a structure 200 is shown according to an exemplary embodiment. FIGS. 6 and 7 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 6 and 7 are perpendicular to each other. A hard mask 214 may be formed. A groove 216 may be formed that separates the structure 200 into regions 201 and 203.

[0033] The hard mask 214 may be conformally formed on the structure 200 by methods known in the art. By methods known in the art, the stack sacrificial layer 208 and the alternately overlapping layers of the sacrificial layer 210 and the channel layer 212 may be formed into fins of double width. In subsequent processing steps, the fins of double width may be further divided into two separate fins. The fins of double width may have a length perpendicular to the cutting line Y-Y and parallel to the cutting line X-X. The fins may be formed by methods known in the art, which may include steps such as forming a hard mask on the alternately overlapping layers, patterning the hard mask, and subsequent formation of one or more grooves 216 by removal of a portion of each layer of the stacked nanosheets. The grooves 216 may be formed in the nanosheet stack into fins of double width by anisotropic etching techniques that stop at the etching of a portion of the thin silicon layer 206 between each nanosheet stack, such as reactive ion etching (RIE).

[0034] Each fin of double width of the nanosheet stack may include the stack sacrificial layer 208, which is covered by the sacrificial layer 210, which is covered by the channel layer 212, which is covered by the sacrificial layer 210, which is covered by the channel layer 212, which is covered by the sacrificial layer 210, which is covered by the channel layer 212, which is covered by the sacrificial layer 210, which is covered by the channel layer 212, which is covered by the hard mask 214. By way of example, two fins of double width are depicted in the drawings of the present application, although any number of fins may be formed.

[0035] The material stack that can be employed in the embodiments of the present invention is not limited to the specific embodiments shown in FIGS. 6 and 7. In FIGS. 6 and 7, by way of example only, the nanosheet stack includes three sacrificial layers 210 alternating with three channel layers 212. The nanosheet stack can include any number of sacrificial layers 210 and channel layers 212. The nanosheet stack is used to generate a gate-all-around device that includes nanosheets of semiconductor channel material stacked vertically for a p-FET or an n-FET.

[0036] In an embodiment, fins that are twice as wide as the region 201 may be formed on the p-FET nanosheets, while fins that are twice as wide as the region 203 may be formed on the n-FET nanosheets. The groove 216 may separate the p-FET nanosheets from the n-FET nanosheets. Alternatively, the groove 216 may separate adjacent p-FET nanosheets or adjacent n-FET nanosheets.

[0037] Referring now to FIGS. 8 and 9, a structure 200 is shown according to an example embodiment. FIGS. 8 and 9 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 8 and 9 are perpendicular to each other. A liner 218 may be formed and the groove 216 may be increased.

[0038] In the structure 200, the liner 218 may be conformally formed, and then, anisotropic etching techniques continue to deepen the groove 216 until the horizontal portion of the liner 218 is removed and etched into the substrate 202. The liner 218 may cover the vertical surface of the hard mask 214, as well as the vertical side surfaces of the channel layer 212, the sacrificial layer 210, and a part of the vertical side surface of the stacked sacrificial layer 206. The liner 218 may be formed using standard film deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and spin-on techniques. In an embodiment, the liner 218 may include SiO2, SiN, SiC, AlOx, TiN, TiOx, etc. In an embodiment, the liner 218 may have a thickness in the range of about 2 nm to 20 nm and the range therebetween, although thicknesses less than 2 nm and greater than 20 nm may be acceptable.

[0039] The liner 218 may protect the sacrificial layer 210 and the channel layer 212 of the nanosheet stack from being damaged later. The groove 216 may be increased by removing a vertically aligned portion of the thin silicon layer 206, the silicon germanium layer 204, and a part of the substrate 202. The groove 216 may be increased by methods known in the art. In an embodiment, the groove 216 may be increased by anisotropic etching techniques, such as reactive ion etching (RIE).

[0040] Referring now to FIGS. 10 and 11, a structure 200 is shown according to an example embodiment. FIGS. 10 and 11 are cross-sectional views of the structure 200 along cutting lines X-X and Y-Y, respectively. FIGS. 10 and 11 are perpendicular to each other. The silicon germanium layer 204 may be recessed.

[0041] The silicon germanium layer 204 may be recessed by methods known in the art. For example, dry etching techniques may be used, such as using vapor phased HCl dry etch, to selectively remove a portion of the silicon germanium layer 204. The recessing of the silicon germanium layer 204 may be performed selectively with respect to the substrate 202, the thin silicon layer 206, the channel layer 212, the sacrificial layer 210, the stack sacrificial layer 208, and the liner 218.

[0042] Referring now to FIGS. 12 and 13, a structure 200 is shown in accordance with an exemplary embodiment. FIGS. 12 and 13 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 12 and 13 are perpendicular to each other. The liner 218 may be removed. A liner 222 may be formed. A shallow trench isolation (hereinafter, "STI") 224 may be formed.

[0043] The liner 218 may be removed using methods known in the art. The removal of the liner 218 may be performed selectively with respect to the hard mask 218, the channel layer 212, the sacrificial layer 210, the stack sacrificial layer 208, the thin silicon layer 206, the silicon germanium layer 204, and the substrate 202.

[0044] The liner 222 may be conformally formed with the structure 200. The liner 222 may cover the upper and vertical surfaces of the hard mask 214, as well as the vertical side surfaces of the channel layer 212, the sacrificial layer 210, the thin silicon layer 206, the silicon germanium layer 204, and the stack sacrificial layer 208, a part of the vertical side surface and the lower horizontal surface of the thin silicon layer 206, and the vertical side surface and the upper horizontal surface of the silicon germanium layer 204. The liner 222 may be formed by using standard film deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and spin-on techniques. In an embodiment, the liner 222 may include SiN, SiBCN, SiOCN, SiOC, etc. In an embodiment, the liner 222 may have a thickness in the range of about 3 nm to 20 nm and thicknesses less than 3 nm and greater than 20 nm may be acceptable.

[0045] The STI 224 may be conformally formed with the structure 200. The STI 224 may fill the space between adjacent double-width fins of the structure 200. The STI may fill the space between the liners 222, and the liners 222 cover the double-width fins.

[0046] STI224 may be a dielectric material and may be formed using known film formation techniques, planarization techniques, and etching techniques. STI224 may be formed by conformally depositing a dielectric material and then following with a combination of dry anisotropic etching and wet anisotropic etching, as well as a recess step. STI224 may use standard film formation techniques such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin-on techniques, followed by an anisotropic vertical etching process such as reactive ion etching (RIE) or any suitable etching process. In an embodiment, STI224 may include one or more layers respectively. STI224 may include any dielectric material such as SiO2 respectively. The lower horizontal plane of STI224 may be below a part of the upper horizontal plane of the substrate 202.

[0047] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of the structure 200 to expose the upper horizontal planes of the hard mask 214, the liner 222, and the STI224.

[0048] Referring now to FIG. 14, a structure 200 is shown according to an exemplary embodiment. FIG. 14 is a cross-sectional view of the structure 200 along the cutting line Y - Y. FIG. 12 remains unchanged with respect to this process step. By repeating the process steps of FIGS. 6 - 13 using another lithography mask, the double-width fins may be separated. The remaining portion of the silicon germanium layer 204 may be removed.

[0049] Vertical grooves (not shown) may be formed within the fins of double width. A liner 222 may be formed within the grooves (not shown). STI 224 may be formed within the liner 222. CMP may be performed. The structure 200 may not include fins of double width. The structure 200 may include fins of a nanosheet stack separated from each other by STI 224.

[0050] Referring now to FIGS. 15 and 16, a structure 200 is shown in accordance with an exemplary embodiment. FIGS. 15 and 16 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 15 and 16 are perpendicular to each other. A portion of the liner 222 and a portion of the STI 224 are removed. The hard mask 214 is removed.

[0051] The removal of a portion of the liner 222 and a portion of the STI 224, selective to the hard mask 214, the channel layer 212, the sacrificial layer 210, the stack sacrificial layer 208, and the thin silicon layer 206, is performed selectively. A portion of the liner 222 and a portion of the STI 224 may be selectively removed by methods known in the art. For example, an isotropic wet etching process or an isotropic dry etching process. A portion of the vertical sides of the channel layer 212, the sacrificial layer 210, the stack sacrificial layer 208, and the thin silicon layer 206 may be exposed. In an embodiment, the top surface of the liner 222 and the top surface of the STI 224 may coincide with the top surface of the thin silicon layer 206. The STI 224 and the STI liner 222 remain within the thin silicon layer 206 between adjacent nanosheet stacks, providing physical and electrical separation between adjacent nanosheet stacks.

[0052] Region 201 shows two p-FET nanosheet fins and region 203 shows two n-FET nanosheet fins. Any number of nanosheet fins may be present in either region 201 or region 203.

[0053] Referring now to FIG. 17, a structure 200 is shown in accordance with an exemplary embodiment. FIG. 17 is a cross-sectional view of the structure 200 along the cut line X-X. FIG. 16 remains unchanged with respect to this process step. A sacrificial gate 226 and a gate cap 228 may be formed.

[0054] The sacrificial gate 226 and the gate cap 228 are formed orthogonally (at a right angle) to the fin. By way of example, three sacrificial gates 226 are depicted in the drawings of the present application, although any number of sacrificial gates 226 may be formed. The sacrificial gate 226 may include a single sacrificial material or a stack of two or more sacrificial materials. At least one sacrificial material may be formed by forming one (or more) blanket layer(s) of one material (or various materials) and then patterning the one material (or various materials) by lithography and etching. The sacrificial gate 226 can include any material, for example, polysilicon, amorphous silicon, or a combination of these multilayers. In embodiments where amorphous silicon is used as the material of the sacrificial gate 226, a thin layer of SiO2 is first deposited to separate the nanosheet stack from the amorphous silicon. The sacrificial gate 226 may be formed using any film formation technique, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin-on techniques. Optionally, the gate cap 228 may be formed as part of the sacrificial gate 226 in accordance with known techniques.

[0055] In an embodiment, the sacrificial gate 226 is formed with a thickness sufficient to fill or substantially fill the space between adjacent nanosheet structures and to cover the upper horizontal surface of the top channel layer 212 of the nanosheet stack. The sacrificial gate 226 may be adjacent to the vertical side surfaces of the nanosheet stack or fin. The sacrificial gate 226 may cover the upper horizontal surface of the BOX SiO2 104 between adjacent nanosheet stacks. The height of the sacrificial gate 226 may be considerably thicker than the underlying structure and may have a height of 100 nm to 150 nm above the nanosheet stack. The gate cap 228 may cover the upper horizontal surface of the sacrificial gate 226. Gate patterning may be performed by conventional lithography and etching processes such that a portion of the gate cap 228 and a portion of the sacrificial gate 226 are removed from the subsequently formed source and drain regions.

[0056] Referring now to FIGS. 18 and 19, a structure 200 is shown in accordance with an example embodiment. FIGS. 18 and 19 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 18 and 19 are perpendicular to each other. The stacked sacrificial layer 208 may be removed. A bottom dielectric isolation 234 (hereinafter, “BDI (bottom dielectric isolation)”) and dielectric spacers 232 may be formed.

[0057] The stacked sacrificial layer 208 may be selectively removed by methods known in the art. For example, dry etching techniques, such as using vapor phase HCl dry etching, may be used to selectively remove the stacked sacrificial layer 208. Selective removal of the stacked sacrificial layer 208 may be performed with respect to the substrate 202, the thin silicon layer 206, the channel layer 212, the sacrificial layer 210, the sacrificial gate 226, and the gate cap 228.

[0058] BDI 234 may be formed where the stack sacrificial layer 208 has been removed. BDI 234 may be formed under the bottom sacrificial layer 210 of the nanosheet stack and above the thin silicon layer 206. This formation may be achieved by first conformally depositing a BDI dielectric liner and then anisotropically etching the dielectric liner.

[0059] Dielectric spacer 232 may be formed on the vertical sidewalls of the nanosheet stack that include the vertical sidewalls of the channel layer 210 and the vertical sidewalls of the sacrificial layer 212. Dielectric spacer 232 may be formed on the vertical sidewalls of the sacrificial gate 226 and the gate cap 228.

[0060] BDI 234 and dielectric spacer 232 may be formed by conformally depositing a dielectric material followed by a combination of dry anisotropic etching and wet anisotropic etching, as well as a recess step. BDI 234 and dielectric spacer 232 may be formed simultaneously or sequentially. BDI 234 and dielectric spacer 232 may be deposited using standard deposition techniques such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin-on techniques, followed by an anisotropic vertical etching process such as reactive ion etching (RIE) or any suitable etching process. In embodiments, BDI 234 and dielectric spacer 232 may each include one or more layers. BDI 234 and dielectric spacer 232 may each include any dielectric material such as silicon nitride (SiN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), aluminum oxide (AlOx), SiC, etc., may include a single layer, or may include multiple layers of dielectric materials. BDI 234 and dielectric spacer 232 may each include the same material or different materials.

[0061] Referring now to FIGS. 20 and 21, a structure 200 is shown in accordance with an exemplary embodiment. FIGS. 20 and 21 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 20 and 21 are perpendicular to each other. Source / drain trenches 236 may be formed. An internal spacer 240 may be formed.

[0062] By methods known in the art, a sacrificial layer 210, alternating layers of a channel layer 212, and a BDI 234 may be formed within the nanosheet stack. The source / drain trenches 236 may have a length that is perpendicular to cut line X-X and parallel to cut line Y-Y and perpendicular to the fins. The source / drain trenches 236 may be formed between each sacrificial gate 226 surrounded by a dielectric spacer 232 by an anisotropic etching technique that stops at a portion of a thin silicon layer 206 between each nanosheet stack, such as reactive ion etching (RIE).

[0063] Each nanosheet stack may include a BDI 234, which is covered by a sacrificial layer 210, which is covered by a channel layer 212, which is covered by a sacrificial layer 210, which is covered by a channel layer 212, which is covered by a sacrificial layer 210, which is covered by a channel layer 212, which is covered by a sacrificial layer 210, which is covered by a channel layer 212. On top of the nanosheet stack are sacrificial gates 226 and a gate cap 228, which are on opposite vertical sides of the dielectric spacer 232. The nanosheet stack may be aligned vertically with respect to the dielectric spacer 232 surrounding the sacrificial gates 226 and the gate cap 228.

[0064] As shown in FIG. 20, a portion of the nanosheet stack may be removed between adjacent sacrificial gates 226, gate caps 228, and dielectric spacers 232. Where the nanosheet stack is removed along cut line X-X, the dielectric spacers 232 may remain vertically.

[0065] Using known techniques, the outer portion of the sacrificial layer 210 may be selectively removed. For example, a wet-etching process or a dry-etching process may be used, along with an appropriate chemical reaction, to remove a portion of each of the sacrificial layers 210. The channel layer 212, BDI 234, dielectric spacer 232, gate cap 228, sacrificial gate 226, thin silicon layer 206, and substrate 202 remain and the materials used in the etching process may be selective so that they are not etched. After etching, a portion of the sacrificial layer 210 covered on both sides by the sacrificial gate 226 may remain as part of the nanosheet stack.

[0066] The inner spacer 240 may be formed by conformally depositing or growing a dielectric material and then subsequent dry isotropic etching and wet isotropic etching, as well as a recess step. The inner spacer 240 may be formed using standard deposition techniques such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin-on techniques, followed by an isotropic etching process such as a wet-etching process or any appropriate etching process. In embodiments, the inner spacer 240 may include one or more layers. In embodiments, the inner spacer 240 may include any dielectric material such as silicon oxynitride, silicon nitride, SiBCN, SiOC, or any combination of these materials.

[0067] The inner spacer 240 may completely fill the space between the channel layers 212 where a portion of the sacrificial layer 210 has already been removed.

[0068] The vertical sides of the inner spacer 240 may be aligned with the vertical sides of the channel layer 212, as well as the vertical sides of the dielectric spacer 232 surrounding the sacrificial gate 226 and the gate cap 228.

[0069] Referring now to FIGS. 22 and 23, a structure 200 is shown in accordance with an exemplary embodiment. FIGS. 22 and 23 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 22 and 23 are perpendicular to each other. A liner 244 may be formed. A lithography soft mask, such as an organic planarization layer 246 (hereinafter, "OPL (organic planarization layer)") that can be used in a patterning process may be formed. A back contact groove 248 may be formed.

[0070] The liner 244 may be conformally formed on the structure 200. The liner 244 may cover the upper horizontal surfaces of the gate cap 228 and the dielectric spacer 232. The liner 244 may cover the vertical side surfaces of the dielectric spacer 232, the channel layer 212, the sacrificial layer 210, the thin silicon layer 206, the silicon germanium layer 204, and a part of the vertical side surface and the lower horizontal surface of the stacked sacrificial layer 208, as well as the vertical side surface and the upper horizontal surface of the silicon germanium layer 204. The liner 222 may be formed using standard film deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and spin-on techniques. In an embodiment, the liner 222 may include materials such as SiO2, SiN, SiOC, SiC, etc. In an embodiment, the liner 222 may have a thickness in the range of about 3 nm to 20 nm and values therebetween, although thicknesses less than 3 nm and greater than 20 nm may be acceptable.

[0071] OPL246 may be formed by blanket deposition using standard film - forming techniques such as spin - on coating. OPL246 can be a self - planarizing organic material containing carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. OPL246 can be a standard CxHy polymer. Non - limiting examples of materials include CHM701B commercially available from Cheil Chemical, HM8006 and HM8014 commercially available from JSR Corporation, and ODL - 102 or ODL - 401 commercially available from Shin - Etsu Chemical Co., Ltd., but are not limited thereto.

[0072] Dry - etching techniques may be used to selectively remove the portion of OPL246 aligned in the vertical direction to form the back - contact groove 248. Wet - etching techniques or dry - ashing techniques may be used to selectively remove OPL246 selectively with respect to the substrate 202, the thin silicon layer 206, the sacrificial layer 210, the channel layer 212, the sacrificial gate 226, the gate cap 228, BDI234, the internal spacer 240, and the dielectric spacer 232. The bottom surface and the vertical side surface of the sacrificial back - contact placeholder 136 may be the dielectric spacer 232.

[0073] Referring now to FIGS. 24 and 25, the structure 200 is shown in accordance with an exemplary embodiment. FIGS. 24 and 25 are cross - sectional views of the structure 200 along cutting lines X - X and Y - Y, respectively. FIGS. 24 and 25 are perpendicular to each other. The back - contact groove 248 may be increased.

[0074] As shown by the cut line X-X in FIG. 24, the back contact groove 248 may be formed between adjacent pairs of the sacrificial gate 226, the gate cap 228, and the dielectric spacers 232 surrounding each sacrificial gate 226, above the adjacent nano-sheet stacks. As shown by the cut line Y-Y in FIG. 25, the back contact groove 248 may be formed between pairs of dielectric spacers 232 where a portion of the nano-sheet stack has been removed between adjacent sacrificial gates 226.

[0075] The back contact groove 248 may be formed by an anisotropic etching technique, such as reactive ion etching (RIE), that removes the aligned portion of the liner 244 and stops at an etching of a portion of the thin silicon layer 206.

[0076] The back contact groove 248 can facilitate the formation of self-aligned back contacts. The back contact groove 248 may be formed within a selected area of the structure 200 where future bottom contacts to the source and drain to be formed later can be formed. There may be one or more back contact grooves 248 in the structure 200.

[0077] Referring now to FIGS. 26 and 27, the structure 200 is shown in accordance with an exemplary embodiment. FIGS. 26 and 27 are cross-sectional views of the structure 200 along the cut lines X-X and Y-Y, respectively. FIGS. 26 and 27 are perpendicular to each other. A sacrificial layer, such as a sacrificial silicon germanium epitaxy 249, may be formed in a portion of the back contact groove 248.

[0078] A sacrificial silicon germanium epitaxy 249 that fills a part of the back contact groove 248 may be formed in the back contact groove 248. The lower surface of the sacrificial silicon germanium epitaxy 249 may be adjacent to the upper surface of the thin silicon layer 206. The vertical side surfaces of the sacrificial silicon germanium epitaxy 249 may be adjacent to the vertical side surfaces of the thin silicon layer 206. A part of the vertical side surfaces of the sacrificial silicon germanium epitaxy 249 may be adjacent to a part of the vertical side surfaces of the dielectric spacer 232 surrounding the back contact groove 248.

[0079] The sacrificial silicon germanium epitaxy 249 may be formed by epitaxial growth. In an embodiment, the sacrificial silicon germanium epitaxy 249 can be SiGe, a III-V semiconductor, or other materials that can be formed by film deposition and recession, such as AlOx, TiOx, SiC.

[0080] Referring now to FIGS. 28 and 29, a structure 200 is shown according to an exemplary embodiment. FIGS. 28 and 29 are cross-sectional views of the structure 200 along cutting lines X-X and Y-Y, respectively. FIGS. 28 and 29 are perpendicular to each other. The OPL 246 and the liner 244 may be removed. An undoped silicon buffer epitaxy 250 may be formed. A p-FET source drain epitaxy 252 may be formed. An n-FET source drain epitaxy 254 may be formed.

[0081] Wet etching techniques or dry ashing techniques may be used to selectively remove the OPL 246 and the liner 244 selectively with respect to the substrate 202, the thin silicon layer 206, the STI liner 222, the STI 224, the dielectric spacer 232, the channel layer 212, the sacrificial layer 210, the internal spacer 240, the BDI 234, and the sacrificial silicon germanium epitaxy 249.

[0082] An undoped silicon buffer epitaxy 250 may be epitaxially grown to surround the vertical portions of the nanosheet stack on both sides of the sacrificial gate 226 and fill a portion of the back contact groove 248. The lower surface of the undoped silicon buffer epitaxy 250 may be adjacent to the upper surface of the thin silicon layer 206. The lower surface of the undoped silicon buffer epitaxy 250 may be adjacent to the upper surface of the sacrificial silicon germanium epitaxy 249. The vertical side surfaces of the undoped silicon buffer epitaxy 250 may be adjacent to the vertical side surfaces of the internal spacer 240, the vertical side surfaces of the BDI 234, and the vertical side surfaces of the channel layer 212. The undoped silicon buffer epitaxy 250 may not be doped. The upper surface of the undoped silicon buffer epitaxy 250 may be at a distance from the upper surface of the thin silicon layer 206 that is farther than the upper surface of the BDI 234.

[0083] An n-FET source-drain epitaxy 254 may be epitaxially grown to surround the vertical portions of the nanosheet stack on both sides of the sacrificial gate 226 and fill a portion of the opening 248 within the region 203. The lower surface of the n-FET source-drain epitaxy 254 may be adjacent to the upper surface of the undoped silicon buffer epitaxy 250. The vertical side surfaces of the n-FET source-drain epitaxy 254 may be adjacent to the vertical side surfaces of the internal spacer 240, the vertical side surfaces of the BDI 234, and the vertical side surfaces of the channel layer 212. The upper surface of the n-FET source-drain epitaxy 254 may be at a distance from the thin silicon layer 206 that is farther than the upper surface of the top channel layer 212.

[0084] The p-FET source-drain epitaxy 252 may be epitaxially grown to surround the vertical portions of the nanosheet stack on both sides of the sacrificial gate 226 and fill a part of the opening 248 within the region 201. The lower surface of the p-FET source-drain epitaxy 252 may be adjacent to the upper surface of the undoped silicon buffer epitaxy 250. The vertical side surfaces of the p-FET source-drain epitaxy 252 may be adjacent to the vertical side surfaces of the internal spacer 240, the vertical side surfaces of the BDI 234, and the vertical side surfaces of the channel layer 212. The upper surface of the p-FET source-drain epitaxy 252 may be at a distance from the thin silicon layer 206 that is farther than the upper surface of the top channel layer 212.

[0085] The advantage of forming the undoped silicon buffer epitaxy 250 under both the p-FET source-drain epitaxy 252 and the n-FET source-drain epitaxy 254 is that it enables the selective removal of the sacrificial silicon germanium epitaxy 249 from the back surface of the wafer at a subsequent stage of manufacturing without damaging either the p-FET source-drain epitaxy 252 or the n-FET source-drain epitaxy 254, especially the p-FET source-drain epitaxy 252 which may contain similar silicon germanium without damaging it.

[0086] Referring now to FIGS. 30 and 31, a structure 200 is shown in accordance with an exemplary embodiment. FIGS. 30 and 31 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 30 and 31 are perpendicular to each other. An inter-layer dielectric (hereinafter, "ILD (inter-layer dielectric)") 260 may be formed. The gate cap 228 and the sacrificial gate 226 may be removed. The sacrificial layer 210 may be removed. A high-k metal gate 264 may be formed.

[0087] The ILD260 may be formed by conformally depositing or growing a dielectric material. The ILD260 may be deposited using standard deposition techniques such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin-on techniques, followed by a planarization process such as CMP or any suitable etching process. In embodiments, the ILD260 may include one or more layers. In embodiments, the ILD260 may include any dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, SiBCN, SiOC, low-k dielectrics, or any combination of these materials. The bottom surface of the ILD260 may be adjacent to the top surfaces of the p-FET source / drain epitaxy 252 and the n-FET source / drain epitaxy 254. A further bottom surface of the ILD260 may be adjacent to the top surface of the STI224. The vertical side surfaces of the ILD260 may be adjacent to the vertical side surfaces of the dielectric spacers 232.

[0088] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the top surface of the structure 200 to remove the gate cap 228 and expose the upper horizontal surface of the sacrificial gate 226. The top surface of the structure 200 may include the upper horizontal surface of the ILD260 and the upper horizontal surface of the dielectric spacers 232.

[0089] The sacrificial gate 226 may be removed by methods known in the art. The sacrificial layer 210 is removed selectively with respect to the channel layer 212, the internal spacers 240, the ILD260, the dielectric spacers 232, the BDI234, the sacrificial back contact placeholder 249, the thin silicon layer 206, the silicon germanium layer 204, and the substrate 202. For example, a dry etching process such as using vapor phase HCl dry etching may be used to selectively remove the sacrificial layer 210. The top and bottom surfaces of the channel layer 212 may be exposed. The top surface of the BDI234 may be exposed.

[0090] According to an example embodiment, in the structure 200, a high-k metal gate 264 may be conformally formed. The high-k metal gate 264 is formed in each cavity surrounding the suspended portion of the channel 212 in the nanosheet stack. The high-k metal gate 264 forms a layer surrounding the exposed portion of the nanosheet stack. The high-k metal gate 264 may cover the exposed vertical side on one side of the side spacer 240, the exposed vertical surface on one side of the dielectric spacer 232, and the exposed upper horizontal surface of the BDI 234. The high-k metal gate 264 may cover the vertical side, the upper horizontal surface, and the lower horizontal surface of the channel layer 210. The high-k metal gate 264 may fill the space between the dielectric spacers 232 above the nanosheet stack from which the sacrificial gate 226 has been removed.

[0091] The high-k metal gate 264 may be formed using standard film deposition techniques such as atomic layer deposition (ALD), molecular layer deposition (MLD), and chemical vapor deposition (CVD). In an embodiment, the high-k metal gate 264 is composed of two or more layers such as HfO 2 、ZrO 2 、La 2 O 3 、Al 2 O 3 、TiO 2 、SrTiO 3 、LaAlO 3 、Y 2 O 3 、HfO x N y 、ZrO x N y 、La 2 O x N y 、Al 2 O x N y 、TiO x N y 、SrTiO x N y 、LaAlO x N y 、Y 2 O x N y 、SiON、SiN x, may include a conformal layer of a high dielectric constant dielectric material such as these silicates and these alloys. In an embodiment, the work function metal of the p-FET device in region 201 may include a metal nitride, such as titanium nitride or tantalum nitride, titanium carbide, titanium aluminum carbide, or other suitable materials known in the art. In an embodiment, the work function metal of the n-FET device in region 203 may include, for example, titanium aluminum carbide or other suitable materials known in the art. In an embodiment, the work function metal may include one or more layers to achieve desired device characteristics.

[0092] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the top surface of the structure 200. The top surface of the structure 200 may include the upper horizontal plane of the ILD260, the upper horizontal plane of the dielectric spacer 232, and the upper horizontal plane of the high-k metal gate 264.

[0093] Referring now to FIGS. 32 and 33, a structure 200 is shown in accordance with an example embodiment. FIGS. 32 and 33 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 32 and 33 are perpendicular to each other. An upper contact 266 may be formed. A back end of line (hereinafter, "BEOL") layer 268 may be formed. A carrier wafer 270 may be bonded to the structure 200.

[0094] An opening (not shown) through the ILD260 that exposes the upper horizontal plane of either the p-FET source / drain epitaxy 252 or the n-FET source / drain epitaxy 254 may be made in the structure 200. An upper contact 266 may be formed within the opening (not shown) to form a contact to either the p-FET source / drain epitaxy 252 or the n-FET source / drain epitaxy 254. As shown in FIG. 33, there are three upper contacts 266. Any number of upper contacts 266 may be present in the structure 200.

[0095] An upper contact 266 may be made to either a p-FET source-drain epitaxy 252 or an n-FET source-drain epitaxy 254 that does not have a sacrificial back contact placeholder 249 under either the p-FET source-drain epitaxy 252 or the n-FET source-drain epitaxy 254. The p-FET source-drain epitaxy 252 or the n-FET source-drain epitaxy 254 having the sacrificial back contact placeholder 249 may have a lower contact formed in a subsequent processing step. Each of the p-FET source-drain epitaxy 252 and the n-FET source-drain epitaxy 254 may have either the upper contact 266 or the lower contact.

[0096] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the top surface of the structure 200 to expose the upper horizontal surface of the ILD 260 and the upper horizontal surface of the upper contact 266.

[0097] The BEOL layer 268 may include layers of wiring and vias formed over the upper contact 266 and the existing structures over the ILD 260. In an embodiment, the BEOL layer 268 may include 12 or more layers of metal lines and vias. The BEOL layer 268 may be formed using known techniques.

[0098] A carrier wafer 270 may be attached to the top surface of the BEOL layer 268 and may be attached to the top surface of the structure 200. The carrier wafer may be attached using a conventional wafer bonding process, such as a dielectric-to-dielectric bonding process or a copper-to-copper bonding process.

[0099] Referring now to FIGS. 34 and 35, a structure 200 is shown according to an exemplary embodiment. FIGS. 34 and 35 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 34 and 35 are perpendicular to each other. The structure 200 may be inverted and the substrate 202 may be removed.

[0100] Here, the carrier wafer 270 is shown at the bottom of FIGS. 34 and 35 at the lowest point of the structure, and the structure 200 may be rotated such that the lower surface of the substrate 202 is shown above the structure for further processing.

[0101] The substrate 202 may be selectively removed using a combination of process steps such as wafer grinding, CMP, RIE, and wet etching processes. The final stage of the process may include selectively etching the silicon remaining on the substrate 202 to expose the surface of the STI liner 222. The continuous STI liner 222 protects the thin silicon layer 206 from damage during the removal process of the substrate 202.

[0102] Referring now to FIGS. 36 and 37, the structure 200 is shown according to an exemplary embodiment. FIGS. 36 and 37 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 36 and 37 are perpendicular to each other. An interlayer dielectric (hereinafter, "ILD") 274 may be formed. An opening 276 may be formed.

[0103] The ILD 274 may be formed as described with respect to the ILD 260. The lower surface of the ILD 274 may be adjacent to the upper surface of the STI liner 222. The vertical side surfaces of the ILD 260 may be adjacent to the vertical side surfaces of the STI liner 222. Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of the structure 200.

[0104] The opening 276 may be formed using known techniques such as, for example, following a conventional lithography process with an anisotropic etching technique such as reactive ion etching (RIE). The opening 276 may be formed by removing an aligned portion of the ILD 274, a portion of the STI liner 222, a portion of the STI 224, and a portion of the thin silicon layer 206.

[0105] The opening 276 may expose the top surface of the sacrificial silicon germanium epitaxy 249 (here). The sacrificial silicon germanium epitaxy 249 may be referred to as a sacrificial back contact placeholder. There may be two or more sacrificial back contact placeholders. Each of the sacrificial back contact placeholders may be adjacent to an undoped silicon buffer epitaxy 250 that is adjacent to either a p-FET source / drain epitaxy 252 or an n-FET source / drain epitaxy 254 that does not have an upper contact 266.

[0106] The formation of the back contact may have a larger overlay error than the formation of the upper contact. In order to compensate for the larger overlay error in the alignment and exposure of the sacrificial back contact placeholder, a relatively larger opening must be made compared to the opening of the upper contact.

[0107] Referring now to FIGS. 38 and 39, a structure 200 is shown in accordance with an exemplary embodiment. FIGS. 38 and 39 are cross-sectional views of the structure 200 along cutting lines X-X and Y-Y, respectively. FIGS. 38 and 39 are perpendicular to each other. The sacrificial silicon germanium epitaxy 249 may be selectively removed by increasing the opening 276.

[0108] Referring now to FIGS. 40 and 41, a structure 200 is shown in accordance with an exemplary embodiment. FIGS. 40 and 41 are cross-sectional views of the structure 200 along cutting lines X-X and Y-Y, respectively. FIGS. 40 and 41 are perpendicular to each other. The opening 276 may be further increased by selective etching around the thin silicon layer 206 and the undoped silicon buffer epitaxy 250.

[0109] The material used in the etching process to increase the opening 276 may be selective to remove the exposed portion of the thin silicon layer 206 and a portion of the undoped silicon buffer epitaxy 250, and may be selective with respect to the ILD 274, the STI liner 222, the STI 224, the remaining portion of the thin silicon layer 206, the p-FET source / drain epitaxy 252, and the n-FET source / drain epitaxy 254. There may be a remaining portion of the undoped silicon buffer epitaxy 250 over the n-FET source / drain epitaxy 254.

[0110] Referring now to FIGS. 42 and 43, a structure 200 is shown in accordance with an exemplary embodiment. FIGS. 42 and 43 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 42 and 43 are perpendicular to each other. An internal spacer 280 may be formed.

[0111] The internal spacer 280 may be formed along the sidewalls of the opening 276. The internal spacer 280 may be formed as described for the dielectric spacer 232.

[0112] Referring now to FIGS. 44 and 45, a structure 200 is shown in accordance with an exemplary embodiment. FIGS. 44 and 45 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 44 and 45 are perpendicular to each other. The opening 276 may be increased to expose the upper surface of the n-FET source / drain epitaxy 254, and the remaining portion of the undoped silicon buffer epitaxy 250 may be removed.

[0113] The remaining portion of the undoped silicon buffer epitaxy 250 may be selectively removed. The ILD 274, STI liner 222, STI 224, thin silicon layer 206, p-FET source / drain epitaxy 252, n-FET source / drain epitaxy 254, and dielectric spacer 232 remain, and the materials used in the etching process may be selective so as not to be etched. The bottom surface of the undoped silicon buffer epitaxy 250 may be exposed over the n-FET source / drain epitaxy 254.

[0114] Referring now to FIGS. 46 and 47, a structure 200 is shown in accordance with an exemplary embodiment. FIGS. 46 and 47 are cross-sectional views of the structure 200 along cut lines X-X and Y-Y, respectively. FIGS. 46 and 47 are perpendicular to each other. A lower contact 282 may be formed.

[0115] To form a contact to the n-FET source / drain epitaxy 254, the lower contact 282 may be formed within the opening 276. As shown in FIGS. 46 and 47, one lower contact 282 is present. Any number of lower contacts 282 may be present in the structure 200.

[0116] Forming the lower contact 282 includes filling the opening 276 with a highly conductive metal material. For clarity, the individual metal materials within the lower contact 282 are not shown. Most of the lower contact 282 includes an elemental metal such as Co, Ru, or Mo to reduce the bulk resistivity, but to reduce the contact resistance between the lower contact 282 and the semiconductor of the n-FET source / drain epitaxy 254 (or the semiconductor of the p-FET source / drain epitaxy 252), a metal compound directly adjacent to the semiconductor of the n-FET source / drain epitaxy 254 (or the semiconductor of the p-FET source / drain epitaxy 252) is selected. In one embodiment, the metal compound adjacent to the semiconductor of the n-FET source / drain epitaxy 254 (or the semiconductor of the p-FET source / drain epitaxy 252) is a metal silicide or germanosilicide. This compound can be created by reacting an elemental metal such as titanium with the semiconductor of the n-FET source / drain epitaxy 254 (or the semiconductor of the p-FET source / drain epitaxy 252). The metal silicide / germanosilicide is made thin (usually less than 3 nm), but sets the Schottky barrier at the interface between the semiconductor and the metal, and ultimately sets the contact resistivity at this interface. The metal silicide / germanosilicide may be separated from the filling of the elemental metal of the lower contact 282 by a thin conductive metal liner such as a titanium nitride liner. The high concentration of free carriers within the semiconductor of the n-FET source / drain epitaxy 254 (or the semiconductor of the p-FET source / drain epitaxy 252) and the low Schottky barrier between the metal silicide / germanosilicide and the semiconductor of the n-FET source / drain epitaxy 254 (or the semiconductor of the p-FET source / drain epitaxy 252) enable a low contact resistivity of about 10 -9 Ω·cm2 for the back contact structure to both n-type and p-type semiconductors. Compared to the filling of the elemental metal, the additional interfacial compounds and liners are made thin, and the interfacial resistance between each metal is at least one order of magnitude lower than the interfacial resistance at the interface between the semiconductor and the metal, so the presence of multiple metal compounds within the lower contact 282 does not significantly affect the series resistance.

[0117] The contact resistivity of the n-FET source / drain epitaxy 254 (or the semiconductor of the p-FET source / drain epitaxy 252) to the adjacent metal compound of the lower contact 282 may be 1e-9 ohm cm2 or less. The volume concentration of free electric carriers (electrons or holes) of the n-FET source / drain epitaxy 254 (or the semiconductor of the p-FET source / drain epitaxy 252) may be 7e20 cm-3 or more.

[0118] In comparison, the contact resistivity of the n-FET source / drain epitaxy 254 (or the semiconductor of the p-FET source / drain epitaxy 252) to the contact 282 may be 2e-9 ohm cm2 or more. The volume concentration of free electric carriers (electrons or holes) of the n-FET source / drain epitaxy 254 (or the semiconductor of the p-FET source / drain epitaxy 252) may be 5e20 cm-3 or less.

[0119] A lower contact 282 may be made to the n-FET source / drain epitaxy 254 or the p-FET source / drain epitaxy 252 without the upper contact 266. The n-FET source / drain epitaxy 254 or the p-FET source / drain epitaxy 252 may have either the lower contact 282 or the upper contact 266. This provides additional options for source / drain contacts. In one example, the n-FET source / drain epitaxy 254 of the n-FET nanosheet stack may each have the upper contact 266, and the p-FET source / drain epitaxy 252 of the p-FET nanosheet stack may each have the lower contact 282. Alternative means are also embodiments.

[0120] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of the structure 200. The upper surface of the structure 200 may include the upper horizontal surface of the lower contact 282, the upper horizontal surface of the internal spacer 280, and the upper horizontal surface of the ILD 274.

[0121] Referring to FIGS. 48 and 49 here, a structure 200 is shown according to an exemplary embodiment. FIGS. 48 and 49 are cross-sectional views of the structure 200 along cutting lines X-X and Y-Y, respectively. FIGS. 48 and 49 are perpendicular to each other. An interlayer dielectric (hereinafter, "ILD") 286 may be formed. A backside power rail (hereinafter, "BPR (backside power rail)") including power rails Vss290 and Vdd288, and a backside power delivery network (hereinafter, "BSPDN (backside power delivery network)") 292 may be formed.

[0122] As described with respect to ILD260, ILD286 may be formed by conformally depositing or growing a dielectric material. The lower surface of ILD286 may be adjacent to the upper horizontal surface of ILD274, the upper horizontal surface of internal spacer 280, and the upper horizontal surface of lower contact 282. Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of the structure 200.

[0123] Using known techniques, Vss290 and Vdd288 may be formed in openings (not shown) in ILD286. In an embodiment, Vss290 and Vdd288 may be parallel to cutting line X-X and perpendicular to cutting line Y-Y. The lower horizontal surface of Vdd288 may be adjacent to the upper horizontal surface of lower contact 282. As shown in FIG. 49, one Vss290 and one Vdd288 are present, but any number of Vss290 and Vdd288 may be present in the structure 200.

[0124] BSPDN292 may be formed in ILD286 and BPR. BSPDN292 may include additional layers of wiring and vias formed on top of existing structures on ILD286 and BPR. In an embodiment, BSPDN292 may include 12 or more layers of lines and vias. BSPDN292 may be formed using known techniques.

[0125] The resulting structure 200 includes FET nanosheets, along with self-aligned backside groove epitaxy that provides a low contact resistivity to the contacts, enabling additional options for forming contacts to the FET nanosheets on the backside of the structure.

[0126] Advantages of the structure 200 can include an enlarged backside contact area for the contacts 282 by selective lateral etching of the thin silicon layer 206 that does not short to the gate.

[0127] The description of the various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the present invention. The terms used herein have been chosen to best explain the principles of the embodiments, the practical application, or a technical improvement over technologies found in the marketplace, or to enable other skilled artisans to understand the embodiments disclosed herein.

[0128] In a preferred embodiment of the invention described in this specification, there is provided a semiconductor device including a first source-drain region, a second source-drain region, an upper source-drain contact aligned vertically above the first source-drain region and electrically connected to the first source-drain region, and a lower source-drain contact aligned vertically below the second source-drain region and electrically connected to the second source-drain region. The lower source-drain contact and the upper source-drain contact are on both sides of the semiconductor device. A dielectric spacer surrounds the opposing vertical side surfaces of the lower source-drain contact, and the dielectric spacer overlaps the vertical side surfaces and the lower horizontal surface of the lower isolation region. The width of the lower source-drain contact is wider than the width of the second source-drain. The lower dielectric isolation region may be under the nanosheet stack of the semiconductor device. The dielectric spacer may be between the shallow trench isolation region and the lower source-drain contact. The device may further include a backside power rail connected to the lower source-drain contact under the lower source-drain contact. The device may further include a backside power supply network under the backside power rail.

Claims

1. a first source-drain region, a second source-drain region, an upper source-drain contact aligned vertically above the first source-drain region and electrically connected to the first source-drain region, a lower source-drain contact aligned vertically below the second source-drain region and electrically connected to the second source-drain region A semiconductor device comprising: wherein the lower source-drain contact and the upper source-drain contact are on opposite sides of the semiconductor device, a dielectric spacer surrounding the opposing vertical sides of the lower source-drain contact, wherein the dielectric spacer overlaps the vertical side and the lower horizontal plane of the lower isolation region, Semiconductor device.

2. The semiconductor device according to claim 1, wherein the lower isolation region is below a nanosheet stack of the semiconductor device.

3. The semiconductor device according to claim 1, wherein the dielectric spacer is between a shallow trench isolation region and the lower source-drain contact.

4. The semiconductor device according to claim 1, further comprising a backside power rail connected to the lower source-drain contact below the lower source-drain contact.

5. The semiconductor device according to claim 4, further comprising a backside power supply network below the backside power rail.

6. forming a double nanosheet stack on a substrate; forming a shallow trench isolation between adjacent double nanosheet stacks; dividing the double nanosheet stack into a first nanosheet stack and a second nanosheet stack; forming a shallow trench isolation within the divided double nanosheet stack; forming an undoped silicon buffer epitaxy within the openings between and below the first nanosheet stack and the second nanosheet stack; forming an upper source-drain contact on the upper horizontal surface of a first source-drain region adjacent to the first nanosheet stack; bonding a carrier wafer to the upper surface of the substrate above the first nanosheet stack and the second nanosheet stack; Removing the undoped silicon buffer epitaxy under the second source-drain region between the first nanosheet stack and the second nanosheet stack, Forming a lower source-drain contact to a lower horizontal plane under the second source-drain region, wherein the lower source-drain contact and the second source-drain region are vertically aligned, A method comprising: The method wherein the width of the lower source-drain contact is wider than the width of the second source-drain region. **Claim 7** The method according to claim 6, wherein the lower source-drain contact comprises a vertical side adjacent to a vertical side of a lower dielectric isolation region under the second nanosheet stack. **Claim 8** The method according to claim 7, wherein the lower source-drain contact comprises a vertical side adjacent to a vertical side of a liner of the second source-drain, and the liner of the second source-drain is between the second source-drain and the gate work function metal of the second nanosheet stack. **Claim 9** The method according to claim 6, further comprising an epitaxial region between the lower source-drain contact and the second source-drain region. **Claim 10** The method according to claim 9, wherein a lower horizontal plane of the epitaxial region is below a lower horizontal plane of a lower dielectric isolation region under the second nanosheet stack. **Claim 11** An embedded power rail connected to the lower source-drain contact above the lower source-drain contact, and A backside power supply network above the embedded power rail The method according to claim 6, further comprising. **Claim 12** The method according to claim 6, further comprising a lower dielectric isolation region under the first nanosheet stack and under the second nanosheet stack. **Claim 13** The first nanosheet stack comprises alternatingly stacked layers of work function metal and semiconductor channel material vertically aligned and stacked, The method according to claim 6, wherein the second nanosheet stack comprises alternatingly stacked layers of work function metal and the semiconductor channel material vertically aligned and stacked. **Claim 14** The method according to claim 6, further comprising an undoped silicon buffer epitaxial region between the lower source-drain contact and the first source-drain region.

15. The method according to claim 6, further comprising vertical spacers on both sides of the first source-drain region.

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