Comparator circuit having a speed control element

Abstract

This specification discloses a comparator circuit having a speed control element. The speed control element may include a variable voltage source and one or more transistors. Using the voltage supplied by the variable voltage source, the one or more transistors may control the swing of a clock signal to provide the clock signal with a controlled swing to an amplification portion of the comparator circuit. The clock with a controlled swing for the amplification portion of the comparator circuit may be used to control the speed of the comparator circuit (e.g., an amplification stage, etc.) based on the noise level of the comparator circuit. The clock with a controlled swing may further be used to match the switching voltage of a downstream logic cell (e.g., an inverter, etc.) connected to the comparator circuit and the output common voltage of the comparator circuit.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims priority based on U.S. Patent Application No. 17 / 745,756, filed on May 16, 2022, entitled "Comparator Circuit with a Speed Control Element", under 35 USC 120, and the entire content thereof is incorporated herein by reference.

[0002] [Technical Field] The present disclosure generally relates to clocked comparator circuits, and more specifically, to an improved clocked comparator circuit with a speed control element.

Background Art

[0003] A clock comparator is a component used in various applications such as analog - to - digital converters (ADCs), serializers / deserializers (SERDES), and high - speed communication circuits. The reliability, sensitivity, and accuracy of the comparator's decision also greatly depend on the thermal noise generated by the comparator itself. Since the noise and decision speed of the comparator are correlated, for example, improving the performance of the comparator by reducing the noise level (such as by spending more time on integration) will slow down the operation of the comparator. Comparators are generally evaluated in terms of speed and accuracy (noise). In the case of advanced node processes, the variation between speed and noise becomes more significant due to the spread of process, voltage, and temperature (PVT). However, conventional comparators do not have a mechanism to control their own speed.

[0004] This proposal is to balance between these two parameters according to each process. By controlling the speed on the fly (depending on the situation), it is possible to operate the comparator at the optimal operating point. Summary of the Invention

[0005] The multiple embodiments disclosed in this specification solve the technical problems mentioned above and, similarly, can provide other technical solutions. In some of the multiple exemplary embodiments, a speed control element may be provided for the comparator circuit. The speed control element may include a variable voltage source and one or more transistors. Using the voltage supplied by the variable voltage source, one or more transistors may control a swing of a clock signal to provide a swing controlled clock signal to the amplification portion of the comparator circuit. The swing controlled clock for this purpose may be used to control the speed of the comparator circuit (e.g., an amplification phase, etc.) based on the noise level of the comparator circuit. The swing controlled clock may further be used to align the switching voltages of downstream logic cells (e.g., inverters, etc.) connected to the comparator circuit with an output common voltage of the amplifier based comparator circuit.

[0006] In one exemplary embodiment, a speed control element for a comparator circuit may include a variable voltage source configured to supply a variable voltage to one or more transistors, the one or more transistors receiving a clock signal and controlling the swing of the clock signal based on the variable voltage supplied by the variable voltage source to generate a clock signal with a controlled swing, providing the clock signal with a controlled swing to control a speed of an amplification phase of the comparator circuit.

[0007] In other embodiments, the comparator circuit may include a speed control element, the speed control element may include a variable voltage source configured to supply a variable voltage to one or more transistors, the one or more transistors receiving a clock signal and controlling the swing of the clock signal based on the variable voltage supplied by the variable voltage source to generate a clock signal with a controlled swing, providing the clock signal with a controlled swing to control the speed of the amplification phase of the comparator circuit.

[0008] In yet another embodiment, a method of controlling the speed of a comparator circuit may include supplying a variable voltage to one or more transistors of a speed control element of the comparator circuit by a variable voltage source of the speed control element; receiving a clock signal by the one or more transistors; controlling, by the one or more transistors, a swing of the clock signal based on the variable voltage supplied by the variable voltage source to generate a clock signal with a controlled swing; and controlling, by the one or more transistors, the speed of an amplification phase of the comparator circuit by providing the clock signal with a controlled swing. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To enable a more detailed understanding of the features described above in this disclosure, a more specific description of the disclosure, briefly summarized above, can be obtained by referring to a plurality of embodiments, some of which are illustrated in the accompanying drawings. On the one hand, the accompanying drawings illustrate only typical embodiments of this disclosure. Therefore, it should be noted that since this disclosure can admit other equally effective embodiments, those accompanying drawings are not considered to limit its scope.

[0010]

Figure 1

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Figure 5

[0011] For ease of understanding, where possible, the same reference numbers are used to designate the same elements common to multiple drawings. It is contemplated that a plurality of elements disclosed in one embodiment may be beneficially utilized in a plurality of other embodiments without specific description.

DETAILED DESCRIPTION OF THE INVENTION

[0012] The various embodiments disclosed herein generally relate to an improved comparator design. More specifically, the various embodiments disclosed herein generally relate to an improved comparator design that utilizes a speed control element to help reduce comparator noise.

[0013] Several attempts have been made to reduce comparator noise. For example, conventional systems have attempted to reduce comparator noise by controlling the capacitance of multiple internal nodes (e.g., by adding capacitors). However, adding such capacitors increases a constant parasitic capacitance that affects variations across PVT. Another attempt to reduce comparator noise is by changing the input common mode. However, such an approach typically requires adaptation from a previous stage.

[0014] To understand the noise mechanism and the impact of noise on comparator operation, an introduction to the comparator is described below. As one example, the StrongARM comparator is introduced below. As will be appreciated by those skilled in the art, such an architecture is exemplary and is not intended to limit the types of comparators that can utilize a speed control element.

[0015] FIG. 1 is a schematic circuit diagram of a StrongARM comparator 100 ("comparator 100") having an additional speed control element 101 in accordance with several exemplary embodiments.

[0016] As shown, comparator 100 may include a plurality of switches S1 - S4 and a plurality of transistors M0 - M6 (which may be formed using transistors in some of the embodiments). The plurality of transistors M0 - M6 may include a clocked differential pair M1 and M2, a first cross - coupled pair M3 and M4, and a second cross - coupled pair M5 and M6. Comparator 100 may further include nodes P and Q. In operation, comparator 100 experiences several stages.

[0017] The first phase may refer to a reset phase. In the reset phase, the clock (clk) signal is at a low level (e.g., such that the state of the clk signal is at the "0" logic level). Thus, in the reset phase, the swing controlled clk signal is also at a low level and controls the gate terminal of M0, so M0 turns off. In this stage (where clk is at a low level), since S1 - S4 are PMOS devices and are compared with M0 which is an NMOS device, S1 - S4 are conducting. Turning M0 off and S1 - S4 on charges the internal nodes (such as P, Q, Out, Out, etc.) to the "1" logic level of V dd up to the "1" logic level of V p up to the "1" logic level of V n up to the "1" logic level of V

[0018] The second phase may refer to the amplification phase. In the amplification phase, the clk signal and the "swing controlled clk" are at a high level ("1" logic level). Thus, in the amplification phase, M0 may turn on, pulling its drain towards ground and letting the input pair M1-M2 conduct. The current in each of those input pairs M1-M2 is proportional to their (input signal vin p and the input signal vin n When the input signal vin p and the input signal vin n are differential and not necessarily equal, the currents flowing through M1 and M2 are different, and the differential input signal vin p and vin n generates amplification of the differential input signals vin p and vin n ). This discharge (or amplification) process occurs when P and Q are connected to V dd -V t reaches its "on" voltage, turning on transistors M3 and M4, which then (depending on the differential input signal) p And Out n (ph2.b in Fig. 3). The result of this step is the input signal vin p and the input signal vin n and the amplified signal Out p And Out n Generate.

[0019] The third stage starts when either Out p or Out n reaches the "on" voltage (V dd -V t voltage level) of the cross-coupled transistors M5 or M6 and turns on one of the cross-coupled transistors M5 / M6. When one of those cross-coupled transistors M5 / M6 turns on, the associated output net is pulled up, enabling positive feedback of back-to-back inverters (such as M3-M6 as shown in Fig. 3). For example, the back-to-back inverter can charge the output (Out dd and V ss up to V p Out n ).

[0020] Typically, the most noise-sensitive stage is the amplification phase. During the amplification phase, a voltage difference is generated between node P and node Q, and as a result, between Out p and Out n of the comparator 100, so the amplification phase can be particularly sensitive to noise. Noise in the amplification stage generated by this process or from other sources can result in a flip of the stage output and lead to an incorrect decision by the comparator. Additionally, since noise is integrated during the amplification phase, reducing the speed of this stage using the speed control element 101 will reduce the input reference noise of the comparator 100. The speed control element 101 can reduce the noise to a desired noise level for amplification during the amplification phase by controlling the speed.

[0021] Due to the correlation between the speed and noise of comparator 100, it is possible to slow down the comparator in noisy PVTs using speed control element 101 while meeting the speed requirements (the speed requirements). This speed limit is stronger in low-speed PVTs and it is possible to reduce noise, thus there is no need to slow down the speed.

[0022] The speed control element 101 may be configured to control the speed of the comparator 100 by restricting the current flowing through M0. As shown, the speed control element 101 may include transistor M7, transistor M8, and variable voltage source 102. The speed control element 101 may restrict the current flowing through M0 by changing the voltage level of the clock signal applied to the M0 gate. To restrict the current flowing through M0, the speed control element 101 may use transistor M7, transistor M8, and variable voltage source 102 to control the supply of M0’s driver (i.e., the gate voltage of M0). In other words, the power supply voltage (V DD ) of transistors M7 and M8 and the applied DC voltage V DC of variable voltage source 102 control the swing. In addition to controlling the speed, by reducing the swing of the gate voltage of M0, M0 can operate more in the saturation region, thus it is possible to increase the gain and improve the common mode rejection ratio (CMRR).

[0023] As shown, a part of the speed control element 101 is emphasized within circle 105. The portion 105 surrounded by the circle of the speed control element 101 indicates that the polarities of the gate signals of S1 - S4 are the same as that of M0, but since the original clock signal (i.e., the clock signal whose swing is not controlled) is used for S1 - S4, the power supply is constant.

[0024] FIG. 2 is a schematic circuit diagram of an amplifier-based comparator 200 ("comparator 200") having a speed control element 201 according to a plurality of exemplary embodiments.

[0025] As shown, comparator 200 may include a plurality of switches S10 - S11 and a plurality of transistors M10 - M14 (which may be formed using transistors in some of the embodiments). Transistors M10 - M14 may include a clocked differential pair M11 and M12 and a cross-coupled pair M13 and M14. Further, inverter 202 and inverter 204 may follow comparator 200. Inverter 202 and inverter 204, or any other logic cells, may be used to open the signal toward rail to rail, which may be achieved after one or few logic cell stages.

[0026] Regarding comparator 200, for example, it may be desirable to align the comparator 200’s output common voltage with the next (or downstream) logic cells’ switching point (such as inverters 202 and 204 in the illustrated embodiment, although other logic cells may also be used). For example, if these voltages are not aligned, the output of the logic cell may not change independently of the comparator's decision. To align the output common voltage with the switching point of the next logic cell, comparator 200 may use speed control element 201 in addition to the purpose of noise reduction.

[0027] The speed control element 201 may include transistor M15, transistor M16, and variable voltage source 206. The speed control element 201 may limit the current flowing through M10 by changing the voltage level of the clock signal applied to the M10 gate, and in addition, may be configured to align the output common voltage with the next logic cell by changing the voltage swing of M10. For example, controlling the voltage swing of the gate of M10 using the speed control element 201 may be used to adjust the between the output common voltage and the switching point of the next logic cell (such as inverters 202 and 204 in FIG. 2).

[0028] As shown, a part of the speed control element 201 is emphasized within the circle 205. The part surrounded by the circle of the speed control element 201 emphasizes that the polarity of the gate signal of S10 - S11 is the same as that of M0, but since the original clock signal (i.e., the clock signal whose swing is not controlled) is used for S10 - S11, the power supply is constant.

[0029] Figure 3 is a chart 300 illustrating the operating phases of a comparator (e.g., a StrongARM comparator without a speed control element 101) according to a plurality of exemplary embodiments. As shown, chart 300 shows the output Out (at reference number "302") p , the output Out (at reference number "304") n , the output voltage over time at node P (at reference number "306") and node Q (at reference number "308"). First, following the output Out n , the output voltage of comparator 100 at Out n remains stable during stage 1 until it begins to drop during stage 2. The output voltage of comparator 100 at Out n continues to drop until it reaches zero during stage 3. Second, following the output of Out p , the output voltage at Out p follows a similar drop from stage 1 to stage 2, but due to amplification, a differential voltage is developed between Out n and Out p during stage 2. As a result, during stage 3, one output drops to zero (as Out n of chart 300) and one output rises to V p (as Out dd of chart 300).

[0030] Figure 4 is a chart 400 illustrating a comparison between the outputs of a comparator with a speed control element (e.g., comparator 100 with a speed control element 101) according to a plurality of exemplary embodiments and a comparator (e.g., a StrongARM comparator) being compared. As can be shown, in the current comparator with a speed control element, the integration operation is slower, so a significant differential voltage occurs earlier in the conventional comparator compared to the currently disclosed comparator.

[0031] For example, as shown, chart 400 shows the Out of a comparator without a speed control element (e.g., "outp orig" corresponding to reference numeral 402, etc.). p The Out of a comparator without a speed control element (e.g., "outn orig" corresponding to reference numeral 404, etc.). n The Out of a comparator with a speed control element (e.g., "outp proposed" corresponding to reference numeral 406, etc.). p And the Out of a comparator with a speed control element (e.g., "outn proposed" corresponding to reference numeral 408, etc.). n are shown.

[0032] FIG. 5 is a chart 500 illustrating a comparison between the differential output of a conventional StrongARM comparator compared to the differential output of a comparator with a speed control element (e.g., comparator 100 having a speed control element 101, etc.) according to a plurality of exemplary embodiments. For example, reference numeral 502 may correspond to the differential output of the conventional StrongARM comparator, and reference numeral 504 may correspond to the differential output of a comparator with a speed control element. As shown, by including the speed control element 101, the amplification stage (e.g., the second stage, etc.) may be extended beyond the amplification stage that was originally possible.

[0033] Those skilled in the art will understand that the plurality of examples described above are illustrative and not limiting. By reading this specification and examining the drawings, all such substitutions, enhancements, equivalents, and improvements to those plurality of examples will be apparent to those skilled in the art and are intended to be included within the true spirit and scope of the present disclosure. Accordingly, the following appended claims are intended to include all such modifications, substitutions, and equivalents that fall within the true spirit and scope of these teachings.

Claims

1. A speed control element for a comparator circuit, the speed control element comprising: a variable voltage source configured to supply a variable voltage to one or more transistors; the one or more transistors receive a clock signal, control the swing of the clock signal based on the variable voltage supplied by the variable voltage source to generate a clock signal with a controlled swing, provide the clock signal with a controlled swing to control the speed of the amplification stage of the comparator circuit. configured as a speed control element.

2. The speed control element according to claim 1, wherein during the reset stage of the comparator circuit, the one or more transistors are configured to provide clock logic with a controlled swing to turn off other transistors of the comparator circuit.

3. The speed control element according to claim 1, wherein during the amplification stage of the comparator circuit, the one or more transistors are configured to provide clock logic with a controlled swing to turn on other transistors of the comparator circuit.

4. The speed control element according to claim 1, wherein the one or more transistors are configured to provide the clock signal with a controlled swing to other transistors of the comparator circuit based on a predefined level of noise for the amplification stage.

5. The speed control element according to claim 1, wherein the one or more transistors are configured to provide the clock signal with a controlled swing to other transistors of the comparator circuit based on the alignment between the switching point of a downstream logic cell connected to the comparator circuit and the output common voltage of the comparator circuit.

6. The speed control element according to claim 5, wherein at least one of the downstream logic cells includes an inverter.

7. The speed control element according to claim 1, wherein the variable voltage source includes a DC voltage source.

8. A comparator circuit, the comparator circuit comprising: a speed control element, the speed control element comprising: a variable voltage source configured to supply a variable voltage to one or more transistors; the one or more transistors receive a clock signal, control the swing of the clock signal based on the variable voltage supplied by the variable voltage source to generate a clock signal with a controlled swing, Providing a clock signal whose swing is controlled to control the speed of the amplification stage of the comparator circuit, configured as follows, Comparator circuit.

9. During the reset stage of the comparator circuit, the one or more transistors are configured to provide clock logic with a controlled swing to turn off other transistors of the comparator circuit, the comparator circuit according to claim 8.

10. During the amplification stage of the comparator circuit, the one or more transistors are configured to provide clock logic with a controlled swing to turn on other transistors of the comparator circuit, the comparator circuit according to claim 8.

11. The one or more transistors are configured to provide the clock signal with a controlled swing to other transistors of the comparator circuit based on a predefined level of noise for the amplification stage, the comparator circuit according to claim 8.

12. The one or more transistors are configured to provide the clock signal with a controlled swing to other transistors of the comparator circuit based on the alignment between the switching point of a downstream logic cell connected to the comparator circuit and the output common voltage of the comparator circuit, the comparator circuit according to claim 8.

13. At least one of the downstream logic cells includes an inverter, the comparator circuit according to claim 12.

14. The variable voltage source includes a DC voltage source, the comparator circuit according to claim 8.

15. A method for controlling the speed of a comparator circuit, the method comprising: Supplying a variable voltage to one or more transistors of the speed control element by a variable voltage source of the speed control element of the comparator circuit; Receiving a clock signal by the one or more transistors; Controlling the swing of the clock signal based on the variable voltage supplied by the variable voltage source by the one or more transistors to generate a clock signal with a controlled swing; Controlling the speed of the amplification stage of the comparator circuit by providing the clock signal with a controlled swing by the one or more transistors, Method.

16. The step of providing the clock signal with a controlled swing is, The method according to claim 15, comprising the step of providing clock logic with a controlled swing by the one or more transistors to turn off other transistors of the comparator circuit during a reset phase of the comparator circuit.

17. The step of providing the clock signal with a controlled swing The method according to claim 15, comprising the step of providing clock logic with a controlled swing by the one or more transistors to turn on other transistors of the comparator circuit during an amplification phase of the comparator circuit.

18. The step of providing the clock signal with a controlled swing The method according to claim 15, comprising the step of providing the clock signal with a controlled swing to other transistors of the comparator circuit by the one or more transistors based on a predefined level of noise for the amplification phase.

19. The step of providing the clock signal with a controlled swing The method according to claim 15, comprising the step of providing the clock signal with a controlled swing to other transistors of the comparator circuit by the one or more transistors based on the alignment between a switching point of a downstream logic cell connected to the comparator circuit and an output common voltage of the comparator circuit.

20. The method according to claim 15, wherein the variable voltage source includes a DC voltage source.

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