Growth of Epitaxial Silicon Channel

Abstract

The three-dimensional NAND flash memory structure may include a solid channel core of epitaxial silicon that grows directly from a silicon substrate reference. Alternating oxide and nitride material layers may be formed as a stack. Channel holes extending downward to the silicon substrate may be etched through the material layers. A tunnel layer may be formed around the channel holes so as to contact the alternating material layers. The epitaxial silicon core may grow from the silicon substrate to the channel holes. In some embodiments, a support structure may be formed within the channel holes or within the slits of the memory array to provide physical support while the epitaxial silicon core grows through the channels.

Description

Technical Field

[0001] Cross - reference to related applications

[0001] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 343,437, filed on May 18, 2022, entitled "EPITAXIAL SILICON CHANNEL GROWTH", the entire disclosure of which is incorporated herein by reference as if fully set forth herein for all purposes.

[0002]

[0002] This disclosure generally describes memory cells comprising an epitaxial silicon channel core. More specifically, this disclosure describes techniques for manufacturing a 3D NAND flash memory structure comprising an epitaxial channel core grown from a silicon substrate.

Background Art

[0003]

[0003] Memory designs known as NAND memory are non - volatile flash memory storage architectures that do not require power to maintain stored data. NAND flash memory is used in many products such as solid - state devices and portable electronic devices. To increase the density and reduce the size of NAND memory, conventional two - dimensional NAND architectures are migrating to three - dimensional NAND stacks. Unlike 2D planar NAND technology where individual memory cells are stacked on separate horizontal substrates, 3D NAND is vertically stacked using multiple layers in which conductive and dielectric materials are alternately arranged, and vertical channels intersect.

Summary of the Invention

[0004]

[0004] In some embodiments, a three-dimensional (3D) NAND memory structure may include a silicon substrate and a plurality of alternating material layers arranged in a stacked body perpendicular to the silicon substrate. Channel holes may extend through the plurality of alternating material layers to the silicon substrate. The channel holes may be perpendicular to the plurality of alternating material layers. The memory structure may also include a channel within the channel holes that includes a tunnel layer surrounding the inside of the channel holes in contact with the plurality of alternating material layers, and an epitaxial silicon core inside the tunnel layer in contact with the silicon substrate.

[0005]

[0005] In some embodiments, a method of manufacturing a 3D NAND memory structure may include forming a plurality of alternating material layers arranged in a stacked body perpendicular to a silicon substrate, etching channel holes that extend through the plurality of alternating material layers to the silicon substrate, forming a tunnel layer in contact with the plurality of alternating material layers around the channel holes, and epitaxially growing an epitaxial silicon core from the silicon substrate through the channel holes inside the tunnel layer.

[0006]

[0006] In some embodiments, a 3D NAND memory array may include a silicon substrate and a plurality of alternating material layers arranged in a stacked body perpendicular to the silicon substrate. A plurality of channel holes may extend through the plurality of alternating material layers. Further, the memory array may include a plurality of support structures that extend through the plurality of alternating material layers into the silicon substrate.

[0007]

[0007] In any embodiment, any and all of the following features may be implemented in any combination, without limitation. The silicon substrate may include single-crystalline silicon in which an epitaxial silicon core grows through a channel hole. The alternating material layers may include alternating layers of an oxide material and a nitride material. The alternating material layers may include alternating layers of an oxide material and a metal. Here, the metal may form a gate electrode for individual memory cells within the memory structure. The epitaxial silicon core may extend into the silicon substrate. The memory structure may also include an epitaxial silicon layer that extends across the channel hole. Here, the epitaxial silicon layer may be between the silicon substrate and the plurality of alternating material layers. The epitaxial silicon layer may connect the epitaxial silicon core to a plurality of other channels within the memory structure. The memory structure may also include a support structure that extends into the silicon substrate through the plurality of alternating material layers and the epitaxial silicon layer. In the memory structure that extends into a sacrificial nitride layer above the silicon substrate through the plurality of alternating material layers, a slit may be etched. The sacrificial nitride layer may be subjected to an etching process configured to selectively etch the sacrificial nitride layer. A portion of the tunnel layer exposed after removing the sacrificial nitride layer may be removed. An epitaxial silicon layer may epitaxially grow from the silicon substrate to replace the sacrificial nitride layer. A second channel hole may be etched that extends into the silicon substrate through the plurality of alternating material layers. The second channel hole may be filled with a gap filling material as a support structure. The plurality of support structures may include a metal that fills one or more of the plurality of channel holes. The plurality of support structures may include a gap filling material within a slit in the memory array. By arranging the slits in the memory array alternately, the support structure may be formed. The plurality of support structures may include a combination of a gap filling material within one or more slits in the memory array and / or a metal that fills one or more of the plurality of channel holes.

[0008]

[0008] A further understanding of the nature and advantages of the various embodiments can be realized by referring to the remainder of this specification and the drawings. In the drawings, like reference numerals are used throughout several views to refer to like components. In some instances, a sub-label is associated with the reference numeral to indicate one of a plurality of like components. When a reference to a reference numeral is made without designation to an existing sub-label, it is intended to refer to all such plurality of like components.

Brief Description of the Drawings

[0009]

Figure 1

[0009] FIG. shows a top view of one embodiment of a processing system of a deposition chamber, an etching chamber, a baking chamber, and a curing chamber according to some embodiments.

Figure 2A

[0010] FIG. shows an incremental stage for generating an array of 3D NAND flash memory cells with epitaxial silicon channels according to some embodiments.

Figure 2B

Figure 2C

Figure 2D

Figure 2E

Figure 2F

Figure 2G

Figure 2H

Figure 2I

Figure 2J

Figure 2K

Figure 2L

Figure 2M

Figure 2N

Figure 2O

Figure 2P

Figure 3A

[0011] Shows a portion of a memory array, according to some embodiments.

Figure 3B

[0012] Shows a portion of a memory array when some of the channels are used in a support structure to facilitate an epitaxial silicon channel core, according to some embodiments.

Figure 4A

[0013] Shows incremental steps in a manufacturing process for a memory structure that uses slits to separate memory blocks for a support structure when growing epitaxial silicon channels for individual memory cells, according to some embodiments.

Figure 4B

Figure 4C

Figure 4D

Figure 4E

Figure 4F

Figure 4G

Figure 4H

Figure 4I

Figure 4J

Figure 4K

Figure 4L

Figure 5

[0014] Shows a top view of a portion of a memory array, according to some embodiments.

Figure 6A

[0015] Shows progressive steps for forming a laminate including support structures in both channel holes and slits, according to some embodiments.

Figure 6B

Figure 6C

Figure 6D

Figure 6E

Figure 6F

Figure 6G

Figure 6H

Figure 7

[0016] Shows a top view of a part of a memory array, according to some embodiments.

Figure 8

[0017] Shows a flowchart of a method for manufacturing a 3D NAND memory structure, according to some embodiments.

Embodiments for Carrying Out the Invention

[0010]

[0018] Conventional three-dimensional (3D) NAND flash memory structures use channel cores made from oxide materials or polycrystalline silicon. However, epitaxial silicon exhibits much higher mobility than polycrystalline silicon or other similar materials. The present disclosure describes a 3D NAND flash memory structure that uses an epitaxial silicon core grown directly from a silicon substrate reference. Alternating oxide and nitride material layers can be formed as a stack. Channel holes extending downward to the silicon substrate can be etched through the material layers. A tunnel layer can be formed around the channel holes to contact the alternating material layers. The epitaxial silicon core can grow from the silicon substrate to the channel holes. In some embodiments, a support structure can be formed within the channel holes or within the slits of the memory array to provide physical support while the epitaxial silicon core grows through the channel.

[0011]

[0019] FIG. 1 shows a top view of one embodiment of a processing system 100 of a deposition chamber, an etching chamber, a baking chamber, and a curing chamber, according to some embodiments. In this figure, a pair of front-opening unified pods 102 supply substrates of various sizes. These substrates are received by a robotic arm 104, placed in a low-pressure holding area 106, and then disposed in one of the substrate processing chambers 108a-f within tandem sections 109a-c. A second robotic arm 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and vice versa. Each substrate processing chamber 108a-f can be equipped to perform a number of substrate processing steps, including dry etching processes described herein, in addition to cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma processing, degassing, orientation, and other substrate processes.

[0012]

[0020] The substrate processing chambers 108a - f can include one or more system components for depositing, annealing, curing, and / or etching a material film on a substrate or wafer. In one configuration, two pairs of processing chambers, such as 108c - d and 108e - f, are used to deposit material on a substrate, and a third pair of processing chambers, such as 108a - b, can be used to cure, anneal, or process the deposited film. In another configuration, all three pairs of chambers, such as 108a - f, can be configured to deposit and cure a film on a substrate. Any one or more of the processes described can be performed in additional chambers separate from the manufacturing systems shown in different embodiments. It will be appreciated that the processing system 100 contemplates additional configurations of deposition chambers, etching chambers, annealing chambers, and curing chambers for material films. Additionally, any number of other processing systems may be utilized with this technology, and these processing systems can incorporate chambers for performing any of the specific steps. In some embodiments, a chamber system that can provide access to multiple processing chambers while maintaining a vacuum environment in various sections such as the aforementioned holding area and transfer area can enable operations to be performed within multiple chambers while maintaining a specific vacuum environment between individual processes.

[0013]

[0021] The processing system 100, more specifically the chambers incorporated into the processing system 100 or other processing systems, can be used to manufacture structures according to some embodiments of this technology. For example, the processing system 100 can be used to manufacture a memory array by performing processes such as deposition, etching, sputtering, polishing, cleaning, etc. in various substrate processing chambers 108.

[0014]

[0022] Figures 2A - 2P show incremental stages for generating an array of 3D NAND flash memory cells with an epitaxial silicon channel, according to some embodiments. FIG. 2A shows a partial stack of alternating oxide - nitride layers that can be formed for a 3D NAND flash array. In each layer shown in FIG. 2A, one layer can be formed step - by - step on top of the previous layer using any deposition or layer - formation technique. In this example, layers can be formed on a substrate 200 of a silicon material such as an epitaxial silicon or single - crystal silicon wafer. A silicon oxide layer 202 is formed on the substrate 200, and subsequently a silicon nitride layer 204 can be formed. In some embodiments, the silicon oxide layer 202 and the silicon nitride layer 204 represent the first layers on the substrate 200, and these layers can be thicker than the alternating oxide - nitride layers formed thereon. Next, alternating layers of silicon oxide 206 and silicon nitride 208 can be formed in a stacked manner.

[0015]

[0023] The progressive formation of the substrate 200, the silicon oxide layer 206, the silicon nitride layer 208, and other materials described below with reference to FIGS. 2A - 2P can be collectively referred to as the laminate 224. As shown in FIG. 2A, the laminate 224 can initially have a limited height. For example, the completed laminate can have a very large number of layers (e.g., 128 pairs of alternating oxide and nitride layers). However, if all of these layers are initially formed, the aspect ratio can be too high, resulting in a laminate 224 in which narrow channel holes and other vias that penetrate the entire laminate 224 cannot be reliably formed. Thus, the laminate 224 can be initially formed partially. Next, the partial laminate can have channel holes etched therein. Additional alternating oxide and nitride layers may be added on top of the partial laminate, and those additional layers can be etched in the same positions to form channel holes that continue with a more uniform width through all of the alternating oxide and nitride layers. Thus, a high aspect ratio is maintained without over - angling the sidewalls of the channel holes.

[0016]

[0024] Figure 2B shows a method of etching a partial laminate to form a hole 203 that penetrates alternating silicon oxide layers 206 and silicon nitride layers 208. To remove the material exposed by the mask, a mask can be overlaid on the partial laminate and the etching process can be executed to form the hole 203. Any etching process, such as dielectric etching, may be used. Generally, the depth of the hole 203 can be controlled based on the number of silicon oxide layers 206 and the number of silicon nitride layers 208 to be etched. For example, the time allowed for the execution of the etching process can be determined by the number of silicon oxide layers 206 and the number of silicon nitride layers 208, and the thickness of these layers. Instead of stopping the etching process after reaching the final silicon oxide layer 202, in some embodiments, the etching process can be continued so that the hole 203 extends into the substrate 200. This additional etching, which is directed at the bottom of the hole and is referred to herein as "bottom punch" etching, can expose the silicon material of the substrate 200 at the bottom of the hole 203. The bottom punch etching can represent an etching different from the etching used to form the hole, or can be an extension of this etching until reaching a depth inside the substrate. The exposed silicon material of the substrate 200 can be used in a later step to epitaxially grow silicon through a channel that forms a 3D NAND flash memory cell.

[0017]

[0025] FIG. 2C shows how stack 224 can be extended by adding additional silicon oxide layer 207 and silicon nitride layer 209 on a partial stack according to some embodiments. These additional layers can be formed stepwise on the partial stack. Alternatively, these layers can be formed separately and placed on the partial stack. It should be understood that the partial stacks shown in these figures are greatly simplified for clarity. In reality, the stack includes a number of layers, a number of channel holes, and can be used to form hundreds of 3D NAND flash memory cells. However, these figures are simplified to show the formation of a single epitaxial silicon channel and adjacent support structures or slits within the memory array. For example, an actual stack can include thousands of channels, over 100 alternating oxide and nitride layers, as well as multiple slits and support structures. These layers are formed in multiple processes, and the etching process can be performed stepwise for each batch of layers as the layers are added to the partial stack. Thus, although FIG. 2C shows only two partial stacks being combined, it will be understood that a number of additional partial stacks may be stacked and etched to form holes 203 through stack 224. For example, in some embodiments, a combination of two partial stacks each including about 128 alternating oxide-nitride layers can be included, for a total of 256 alternating oxide-nitride layers.

[0018]

[0026] FIG. 2D shows stack 224 formed from a plurality of partial stacks each etched individually according to some embodiments. After adding additional silicon oxide layer 207 and silicon nitride layer 209 of the second partial stack, holes 211, 219 can be etched in these layers as shown. Note that these holes 211, 219 can be formed using a mask similar to that previously used to etch holes 203 in the first partial stack. By etching this set of layers stepwise, a very high aspect ratio can be achieved despite the depth of holes 211, 219 in the complete stack 224.

[0019]

[0027] FIG. 2E shows a support feature 210 that can be formed in one of the holes to provide support during subsequent steps of the process, according to some embodiments. The support feature 210 can be selectively deposited in one of the holes to form a rigid structure. For example, some embodiments can use a metal such as tungsten to form the support feature 210. Some embodiments can use a dielectric fill such as SiOx or a metal-aluminum oxide-nitride-oxide-silicon (MANOS) stack for the support feature 210. Any deposition process can be used to form the support feature 210. Note that the support feature 210 can extend below the substrate 200 due to the above-described etching process that overshoots the last silicon oxide layer 202. As will become apparent later in the present disclosure, the support feature 210 prevents the layers of the laminate 224 from collapsing when the sacrificial nitride layer 204 is removed. Further, by extending the support feature 210 below the substrate 200, the upper layers of the laminate 224 are optionally prevented from moving when the nitride layer 204 is removed later.

[0020]

[0028] FIG. 2F shows a first layer of epitaxial silicon 212 formed in one of the holes 219, according to some embodiments. As described above, due to the additional depth of the bottom punch etching into the substrate 200, the silicon material of the substrate 200 is exposed to the channel holes 219. Since the single crystal silicon of the substrate 200 is exposed, the layer of epitaxial silicon 212 can grow within the channel holes using a process such as silicon epitaxial deposition or epitaxy that grows a thin layer of single crystal silicon on top of the single crystal silicon substrate 200. For example, some embodiments may perform an epitaxy process through chemical vapor deposition. To form the epitaxial silicon 212 growing on the substrate 200 in stages, materials such as silicon tetrachloride, trichlorosilane, dichlorosilane, silane, and other chemical sources of silicon may be supplied to the deposition chamber. The height of the epitaxial silicon 212 may be above the silicon oxide layer 202, but may be below the next silicon oxide layer in the stack 224. For example, the height of the epitaxial silicon 212 may be within the sacrificial nitride layer 204.

[0021]

[0029] FIG. 2G shows the deposition of the tunnel layer 214 within the hole 219, according to some embodiments. Since the hole 219 can now be used to form the channel of the vertical column of 3D NAND memory cells, the hole 219 may also be referred to herein as the channel hole 219. The tunnel layer 214 can be formed by depositing a blocking dielectric or oxide, a charge trap nitride (e.g., silicon nitride), and a tunnel dielectric or oxide. These three layers may be collectively referred to as the "tunnel layer" 214 in the present disclosure. The oxide layer within the tunnel layer 214 may provide an offset to the conduction band and valence band of the transistor device of the memory cell.

[0022]

[0030] For example, the silicon nitride layer can be surrounded by inner and outer layers of silicon oxide. The various layers of the tunnel layer 214 can be formed using atomic layer deposition. Thus, the layers of the tunnel layer 214 can be relatively thin compared to the alternating oxide / nitride layers of the stack 224. By this process, the tunnel layer 214 can grow on the sidewalls of the channel holes 219, on the epitaxial silicon 212, and along the bottom of the channel holes. It should be noted that since the epitaxial silicon 212 stops before the alternately stacked silicon oxide layers 206 and silicon nitride layers 208, the interior of the channels of the 3D NAND memory cells can be covered by the tunnel layer 214.

[0023]

[0031] FIG. 2H shows how the channel holes 219 can be filled with a sacrificial gap fill material 216 according to some embodiments. For the purpose of protecting the tunnel layer 214 during subsequent etching processes, the channel holes 219 can be filled with a sacrificial gap fill material 216 such as carbon.

[0024]

[0032] FIG. 2I shows a slit 218 that can be etched within a laminate 224 according to some embodiments. The slit 218 may represent a relatively long trench etched within the laminate 224 so as to be adjacent to a plurality of individual channel holes along the length of the slit 218. Refer to FIG. 2R below for a top view of the slit with respect to the channel holes in the memory array. In contrast to the etching process used to form the channel holes, the slit 218 can be etched using a single process that penetrates all layers of the laminate 224. Since the width of the slit 218 can be wider than the channel holes, a single process can be used. Thus, the aspect ratio is smaller and can therefore be achieved with a single process. In some embodiments, a carbon liner 220 can be deposited inside the slit 218 to protect the internal silicon oxide layer 206 and silicon nitride layer 208 from subsequent chemical etching processes using the slit 218. For example, the carbon liner 220 can be deposited on the sidewalls and bottom of the slit 218, and subsequent etching can be used to remove the carbon liner 220 from the bottom of the slit 218 to expose the silicon nitride layer 204. The slit 218 can be used in two different memory blocks of the memory array. In a later process, the slit 218 can provide access to all nitride layers within the laminate 224 so that these nitride layers can be removed and replaced with tungsten (or any other conductive material) to form a conductive path for each memory cell. These conductive paths can later form the word lines or gate electrodes of the memory cells. For example, wet etching using hot phosphoric acid can be used to remove the nitride layer from the laminate 224. Thereafter, the slit 218 can provide access to the precursors so that an atomic layer deposition process can be used to grow tungsten within the voids left from the removed nitride layer.

[0025]

[0033] Figure 2J shows the selective removal of the nitride layer 204 according to some embodiments. To grow epitaxial silicon 212 within the channel holes, the nitride layer 204 may be removed for the purpose of exposing a portion of the tunnel layer 214 that needs to be removed so that the epitaxial silicon 212 is again exposed to the channel holes. In this example, wet etching such as high-temperature phosphoric acid chemical etching may be used. The wet etching can access the nitride layer 204 through the slit 218 and selectively remove the nitride layer 204. The carbon liner 212 may protect the inner nitride layer from the etching process. Other embodiments may use dry etching or other processes configured to selectively remove the nitride layer 204.

[0026]

[0034] Figure 2K shows the selective removal of the tunnel layer 214 from the bottom of the channel holes according to some embodiments. The above-described wet / dry etching process may be used for the removal of the nitride layer of the tunnel layer 214. Similar processes may be used to selectively remove the dielectric layer or oxide layer of the tunnel layer 214. Note that the gap 230 left by the removal of the nitride layer 204 is lined on the top and bottom by oxide layers. These oxide layers (e.g., oxide layer 202) may be formed to be slightly thicker than the other oxide layers within the stack 224. However, since the oxide layer and nitride layer of the tunnel layer 214 may be formed as atomic layer deposition layers, these layers will be relatively thin so that they can be removed without removing a significant portion of the other oxide layers that may be exposed to the etching process.

[0027]

[0035] Figure 2L shows the removal of the sacrificial gap filling material 216 from the channel holes 219 according to some embodiments. Note that when the sacrificial gap filling material 216 is removed, the channel holes 219 are lined by the tunnel layer 214 and are exposed to the epitaxial silicon 212.

[0028]

[0036] FIG. 2M shows the growth of epitaxial silicon 212 according to some embodiments. The epitaxy process can be performed as described above. However, since the slit 218 and the channel holes 219 are exposed to the epitaxial silicon 212, a layer of epitaxial silicon 236 can be grown to fill the gap 230 and start filling the channel holes 219. To prevent the slit 218 from being filled with epitaxial silicon, the growth of the layer of epitaxial silicon 236 can stop when it reaches the bottom of the channel holes 219.

[0029]

[0037] FIG. 2N shows the selective removal of a portion of the layer of epitaxial silicon 236 at the bottom of the slit 218. A portion of the epitaxial silicon layer 236 can be removed using an etching process to perform a bottom "punch" as described above. This etching can remove the portion of the epitaxial silicon layer 236 up to the bottom oxide layer 202 as shown in FIG. 2N. Alternatively, the etching can penetrate into the substrate 200 through under the bottom oxide layer 202.

[0030]

[0038] FIG. 2O shows the deposition of a sacrificial gap filling material 240 within the slit 218 according to some embodiments. The sacrificial gap filling material 214 can be deposited within the slit 218 such that the epitaxial silicon layer 236 grows within the channel holes 219 without filling the slit 218.

[0031]

[0039] FIG. 2P shows the epitaxial growth of epitaxial silicon layer 236 up to channel hole 219 according to some embodiments. Up to this point, the previous steps of this process have been performed to provide a channel hole in which epitaxial silicon can be grown as the channel core of a 3D NAND flash memory cell. For example, by the steps described above, a reference layer of epitaxial silicon is formed at the bottom of channel hole 219 grown from substrate 200 itself. To grow epitaxial silicon layer 236 up to channel hole 219, the epitaxy process can be performed as described above. The resulting structure can include a stack 224 having a channel hole filled with an epitaxial silicon core 242, rather than an oxide core or a polycrystalline silicon core as seen in the conventional "macaroni" structure of 3D NAND flash memory cells. Thus, the embodiments described herein can be at least partially distinguished from conventional 3D NAND flash memory cells by the physical connection between epitaxial silicon core 242 and substrate 200, and by the epitaxial silicon core 242 used for the channel, along with the angled walls of the channel and the channel hole.

[0032]

[0040] Referring to FIG. 2P, a 3D NAND memory structure can include a silicon substrate 200 that can be formed of single crystal silicon. The memory structure can also include a plurality of alternating material layers 275 arranged in a stacked manner perpendicular to the silicon substrate 200. The alternating material layers 275 can include alternating layers of an oxide material and a nitride material (e.g., silicon oxide and silicon nitride). At a later stage of the manufacturing process, the alternating material layers 275 can alternatively include alternating layers of an oxide material and a metal such as tungsten. For example, to form the gate electrodes of individual memory cells within the memory structure, the nitride material can be selectively removed and replaced with a metal.

[0033]

[0041] The alternating material layer 275 may define channel holes 277 that extend through the plurality of alternating material layers 275 to the silicon substrate 200. The channel holes 277 may be formed using any of the processes described throughout this disclosure. As illustrated, the channel holes 277 may be substantially perpendicular to the plurality of alternating material layers 275. The memory structure may also include channels inside the channel holes 277. The channels may include a tunnel layer 214 around (and thus outside the perimeter of) the inside of the channel hole using the layers described above. The channels may also include an epitaxial silicon core 242 inside the tunnel layer that contacts the silicon substrate 200. In some cases, the epitaxial silicon core 242 may extend into the silicon substrate 200. Thus, the epitaxial silicon core 242 starts epitaxial growth below the top level of the silicon substrate 200.

[0034]

[0042] The memory structure may also include a layer of epitaxial silicon 236 that extends across the channel holes. The layer of epitaxial silicon 236 may be parallel to the plurality of alternating material layers 275. It will be recalled that FIG. 2P shows only one of the many channels in the memory structure. Thus, the epitaxial silicon layer 236 may connect the epitaxial silicon cores 242 of the illustrated channels to a plurality of other channels within the memory structure. For example, the epitaxial silicon cores of each channel connected by the epitaxial silicon layer 236 may grow simultaneously from the epitaxial silicon layer 236 during the same epitaxy process.

[0035]

[0043] The process described above may be used to selectively grow the epitaxial silicon core 242 using the single crystal silicon of the substrate 200. 3D NAND flash memory cells using the epitaxial silicon core 242 exhibit better performance than similar memory cells using an oxide core. For example, the mobility of polycrystalline silicon is 10 to 20 times lower than the mobility of epitaxial silicon.

[0036]

[0044] To complete the memory array, additional processes may be performed later on the laminate 224. These processes are outside the scope of the present disclosure but may include removing the sacrificial gap filling material 240 from the slit, removing the nitride layer in the laminate 224, depositing a conductive metal (e.g., tungsten) instead of the nitride layer to form the gate electrode, performing staircase etching on the laminate, and the like.

[0037]

[0045] FIG. 3A shows a portion of a memory array 300 according to some embodiments. This portion of the memory array 300 may represent a single memory block having an offset row of channels 256. The slits 250, 252 may be used to separate this memory block from other memory blocks. In this example, 24 channels are used in the offset column between the slits 250, 252. This portion of the memory array 300 may use a conventional oxide or polycrystalline silicon core for the channels. Thus, no support structure is required and each channel hole may be used to implement the memory cell.

[0038]

[0046] In comparison, FIG. 3B shows a portion of the memory array 301 when a portion of the channel is used in the support structure to facilitate an epitaxial silicon channel core, according to some embodiments. As described above, the process for growing an epitaxial silicon channel for the memory cells within the memory array 301 uses a process in which some of the channel holes are used in the support structure 254 to prevent the memory array 301 from collapsing when the sacrificial nitride layer is removed to create space for the epitaxial silicon layer. These support structures 254 can be spaced throughout the memory array to provide appropriate support to the stack of layers within the array during the manufacturing process. Note that the spacing shown in FIG. 3B is provided by way of example and is not intended to be limiting. In this example, the spacing of the support structures 254 is approximately every four channel holes and every other row. In this configuration, by using some of the channel holes used for the memory cells for the support structure 254, the bit density per area within the memory array 301 is slightly reduced.

[0039]

[0047] As described above, some embodiments may use channel holes to provide a support structure during the manufacturing process. The advantage of using channel holes for the support structure is that the spacing of the support structure can be increased or decreased as needed. However, some embodiments may instead form the same epitaxial silicon channel by using slits instead of channel holes to provide the support structure. These embodiments represent a trade-off of reducing the number of supports provided throughout the memory block in exchange for an increase in channel density.

[0040]

[0048] Figures 4A - 4L illustrate progressive stages in a manufacturing process for a memory structure that uses slits to separate memory blocks for a support structure when growing epitaxial silicon channels for individual memory cells, according to some embodiments. Figure 4A shows channel holes 401 in a stack 400 having epitaxial silicon 406 grown from a substrate 400, according to some embodiments. The channel holes 401 and the epitaxial silicon 406 can be formed using the processes described above in connection with Figures 2A - 2F. In this example, instead of using one of the channel holes 401 for a support structure, each of the channel holes 401 can be used to form a channel for a memory cell. Figure 4B shows the channel holes 401 after a tunnel layer 408 has been lined. The tunnel layer can be formed as described in detail above in connection with Figure 2G. Figure 4C shows the channel holes 401 filled with a sacrificial gap fill material 410, which can be formed as described in detail above in connection with Figure 2H.

[0041]

[0049] FIG. 4D shows slits 412, 413 that can be formed on both sides of a memory block according to some embodiments. Although only two channel holes are shown in FIG. 4D, it should be understood that there may be many additional channels between slits 412, 413. For example, slits 412, 413 can surround a memory block with a block width of 24 channels. These channels can be arranged in a honeycomb pattern of two columns offset by 12 channels each. A plurality of pairs of these offset columns of 24 channels can be present within the block. Typically, slits 412, 413 are etched only up to a depth above substrate 400 but below the first oxide layer 417 in the alternating material layers forming the memory cells. For example, slit 213 is below the first oxide level 417 and is etched to a depth within the sacrificial nitride layer 415. However, the slits can undergo additional or extended etching processes so that their depth increases to provide a support structure when subsequently manufacturing the epitaxial silicon layer and channel core. For example, slit 412 can be etched to a depth below the upper surface of substrate 400 using bottom punch etching. Thereby, slit 412 can function as a support structure that is fixed to substrate 400 rather than floating above the substrate.

[0042]

[0050] FIG. 4E shows slit 412 designated to function as a support structure filled with a gap filling material 414 according to some embodiments. In this example, alternating slits can be used as a support structure for the memory array. Thus, slit 413 can remain shallower in depth. On the other hand, slit 412 is etched to a depth below substrate 400 and filled with gap filling material 414 and can function as a support structure during the growth of the epitaxial silicon layer.

[0043]

[0051] FIG. 4F shows the removal of the sacrificial nitride layer 415 according to some embodiments. As described above in connection with FIG. 2J, to selectively remove the sacrificial nitride layer 415, the sacrificial nitride layer 415 can be exposed to an etching process through the slit 413. Although not shown explicitly in FIG. 4F, to prevent the etching process from removing the nitride layer from the alternating material layers that are later used to form the memory cells, a protective liner material (e.g., carbon) may be coated on the sidewalls of the slit 413. Additional bottom punch etching can be applied to remove the protective liner from the bottom of the slit 213 so that the sacrificial nitride layer 415 is exposed to the etching process.

[0044]

[0052] FIG. 4G shows the removal of the tunnel layer 408 from the bottom portion of the channel according to some embodiments. For example, the layer used for the tunnel layer 408 can be selectively removed by a wet etching process and / or a dry etching process as described above. After removing the exposed portion of the tunnel layer 408 at the bottom of the channel hole, the gap filling material 414 can expose the gap 416 between the substrate 400 and the first oxide layer 417, and then provide a support structure to the stack 400 so that the stack 400 does not collapse.

[0045]

[0053] FIG. 4H shows the removal of the sacrificial gap filling material 410 from the channel hole 401 using selective etching. FIG. 4I shows the epitaxial growth of the epitaxial silicon layer 420 in the gap 416. As described above, the epitaxial silicon layer 420 can grow until it begins to fill the channel hole 401. FIG. 4J shows the formation of a hole 422 in the epitaxial silicon layer 420 to expand the slit 413 using a bottom punch etching process. FIG. 4K shows the slit 413 filled with the gap filling material 424. FIG. 4L shows the growth of the epitaxial silicon core 426 in each channel within the memory block. Each of these steps can be performed as described in detail above in connection with FIGS. 2A - 2P.

[0046]

[0054] The channels in the stack 400 resulting from the result shown in FIG. 4L are substantially the same as the channels in the stack 224 resulting from the result shown in FIG. 2P, with the tunnel layer 408 stretched and having alternating material layers 475 and channel holes 477 filled with epitaxial silicon core 426. However, in the memory structure including this stack 400, there is no need to secure any channels as a support structure. Instead, by using slits as a support structure during the manufacturing process, a maximum channel density can be achieved. As described above, additional process steps beyond the scope of the present disclosure, such as removal of alternating nitride layers, formation of a conductive layer (e.g., tungsten layer) for forming gate electrodes, and execution of staircase etching, can then be performed on the stack 400 to complete the manufacture of the memory structure.

[0047]

[0055] FIG. 5 shows a top view of a portion of a memory array 500 according to some embodiments. In this example, all of the channel holes 456 can be used to form channels for memory cells. The alternating slits 550 can be used to provide a support structure during the manufacturing process. On the other hand, the remaining slits 552 can be used to provide access to the sacrificial nitride layer during the manufacturing process as described above. Note that the use of the alternating slits 550 is for illustrative purposes only and is not intended to be limiting. Depending on the block width of each memory block, other embodiments can use every third slit, every fourth slit, etc., based on the number of channels per block and the amount of support needed for anti-collapse.

[0048]

[0056] Instead of using only channel holes for the support structure or only slits for the support structure, some embodiments can use a combination of slits and channel holes to provide the support structure. This can make the spacing of the support structure very flexible. By using slits, the number of channel holes sacrificed for the support structure can be minimized while leaving room to provide additional support structures to as many channel holes as needed.

[0049]

[0057] Figures 6A - 6H illustrate progressive steps for forming a laminate 600 that includes support structures in both channel holes and slits, according to some embodiments. Figure 6A shows the laminate 600 having channel holes filled with a support structure 604. Additional channel holes with support structures may also be present within the laminate 600 but are not explicitly shown in Figure 6A. The laminate 600 may also include channel holes filled with a gap filling material 602 and a tunnel layer 603 that separates the gap filling material 602 from epitaxial silicon 611 growing from a substrate 601. It should be noted that although not visible in Figure 6A, there may be many additional channel holes in the laminate 600. The laminate 600 may also include a slit 606 that is etched downward to a level above the substrate 601 and has a liner that contacts a sacrificial nitride layer 610. Another slit may be filled with a gap filling material 608 and may extend downward into the substrate 601 to function as a support structure.

[0050]

[0058] The remaining steps for growing epitaxial silicon within the channels of the laminate 600 can be performed as detailed above. For example, Figure 6B shows the removal of the sacrificial nitride layer 610 to expose a gap 612 while the laminate 600 is supported by the support structure. Figure 6C shows the removal of a portion of the tunnel layer 603 that is exposed in the gap 612. Figure 6D shows the removal of the gap filling material 602 within the channel hole 614. Figure 6E shows the growth of an epitaxial silicon layer 616 in the gap 612. Figure 6F shows the result of a bottom punch etch to expand a hole 618 through the epitaxial silicon layer 616 for the slit 606. Figure 6G shows the gap filling material 620 within the slit 606. Figure 6H shows the growth of an epitaxial silicon core 622 within the channel hole 614.

[0051]

[0059] FIG. 7 shows a top view of a portion of a memory array 700 according to some embodiments. In this example, most of the channel holes can be used to form channels for memory cells. The alternating slits 750 can be used to provide a support structure during the manufacturing process. On the other hand, the remaining slits 752 can be used to provide access to the sacrificial nitride layer during the manufacturing process, as described above. Instead of using only slits for the support structure, in this hybrid example, a combination of slits and channel holes 756 is used to provide the support structure as described. This allows the spacing of the support structures to be set very flexibly. By using slits, many channel holes are still allowed to provide additional support structures as needed while minimizing the number of channel holes sacrificed for the support structure.

[0052]

[0060] As shown in this embodiment, the processes described herein can be used to form a 3D NAND memory array 700 that includes a silicon substrate and a plurality of alternating material layers disposed in a stacked configuration perpendicular to the silicon substrate. A plurality of channel holes can extend through the alternately arranged material layers. A plurality of support structures extending into the silicon substrate through the plurality of alternating material layers can provide support during the manufacture of the memory array 700. The support structure can include a metal that fills one or more of the channel holes 756. The support structure can also include a gap fill material that fills the slits 750 of the memory array 700. Some embodiments can use metal-filled channel holes and / or gap fill materials, in any combination, without limitation, within one or more slits.

[0053]

[0061] FIG. 8 shows a flowchart 800 of a method for manufacturing a 3D NAND memory structure according to some embodiments. This method can be performed in various processing chambers within a semiconductor processing system, as shown in FIG. 1. The method can include forming a plurality of alternating material layers disposed in a vertical stack on a silicon substrate (802). The alternating layers can include nitride and oxide layers formed in a stacked manner as described above with reference to FIGS. 2A-2D. The method can also include etching channel holes extending through the plurality of alternating material layers to the silicon substrate (804). The channel holes can be etched using a bottom punch etch to penetrate the silicon substrate, as described above with reference to FIG. 2D.

[0054]

[0062] The method can further include forming a tunnel layer in contact with the plurality of alternating material layers around the channel holes (806). The tunnel layer within the channel holes can be formed as described above with reference to FIGS. 2G-2K by depositing a tunnel oxide including the layers described above and selectively removing a portion of the tunnel layer exposed to an etching process at the bottom of the channel.

[0055]

[0063] The method can further include epitaxially growing a silicon core from the silicon substrate through the channel holes within the tunnel layer (808). The epitaxial silicon core can be grown using the steps described throughout this disclosure. For example, growing the epitaxial silicon core can include etching a slit of the memory structure extending into a sacrificial nitride layer on top of the silicon substrate through the plurality of alternating material layers, as shown in FIG. 2I. The sacrificial nitride layer can be exposed to an etching process configured to selectively etch the sacrificial nitride layer, as shown in FIGS. 2J-2L. As shown in FIG. 2M, an epitaxial silicon layer can epitaxially grow from the silicon substrate to replace the sacrificial nitride layer. In some embodiments, a support structure can be formed by etching a second channel hole extending through the plurality of alternating material layers into the silicon substrate and filling the second channel hole with a gap filling material as a support structure.

[0056]

[0064] It should be understood that the specific steps shown in FIG. 8 provide a specific method for manufacturing a 3D NAND memory structure according to various embodiments. Also, other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments may perform the above steps in a different order. Further, the individual steps shown in FIG. 8 may include a plurality of sub-steps that may be performed in various sequences suitable for the individual steps. Additionally, depending on the particular application, additional steps may be added or removed. Many variations, modifications, and alternatives are also within the scope of the present disclosure.

[0057]

[0065] As used herein, the terms “about” or “approximately” or “substantially” may be construed to be within the range expected by one of ordinary skill in the art in light of this disclosure.

[0058]

[0066] In the above description, for the sake of convenience of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the various embodiments. However, it will be apparent that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0059]

[0067] The above description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the above description of the various embodiments provides a possible disclosure for implementing at least one embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of some embodiments recited in the appended claims.

[0060]

[0068] Specific details are given in the above description to provide a complete understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may sometimes be shown as components in block diagram form in order not to obscure the embodiments with unnecessary details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may sometimes be shown without unnecessary detail in order to avoid obscuring the embodiments.

[0061]

[0069] Also, note that individual embodiments have been described as a process, shown as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. A flowchart may describe the operations as a sequential process, but many of the operations may be performed in parallel or simultaneously. Further, the order of the operations may be rearranged. A process terminates when its operations are completed, but it may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination may correspond to the return of the function to the calling function or the main function.

[0062]

[0070] The term "computer-readable medium" includes, without limitation, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction can represent any combination of a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or instruction, data structure, or program statement. A code segment can be coupled to another code segment or hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. can be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0063]

[0071] Furthermore, embodiments can be implemented by hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments for performing the necessary tasks can be stored in a machine-readable medium. One or more processors can perform the necessary tasks.

[0064]

[0072] In the foregoing specification, features have been described with reference to specific embodiments thereof, but it should be appreciated that not all embodiments are limited thereto. The various features and aspects of some embodiments can be used individually or together. Furthermore, embodiments can be utilized in any number of environments and applications other than those described herein without departing from the broader spirit and scope of this specification. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

[0065]

[0073] Furthermore, for purposes of explanation, the methods have been described in a particular order. It should be understood that in alternative embodiments, the methods may be performed in a different order than that described. It should also be understood that the methods described above may be implemented by hardware components or may be embodied as a sequence of machine-executable instructions that can be used to cause a machine, such as a general or special purpose processor or logic circuits programmed with instructions, to perform the methods. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy disk, a ROM, a RAM, an EPROM, an EEPROM, a magnetic or optical card, a flash memory, or other type of machine-readable media suitable for storing electronic instructions. Alternatively, the methods may be implemented by a combination of hardware and software.

Claims

1. A silicon substrate, A plurality of alternating material layers arranged in a stacked body perpendicular to the silicon substrate, wherein channel holes extend through the plurality of alternating material layers to the silicon substrate, and the channel holes are perpendicular to the plurality of alternating material layers, the plurality of alternating material layers, A channel inside the channel hole, A tunnel layer around the inner periphery of the channel hole that contacts the plurality of alternating material layers, and An epitaxial silicon core inside the tunnel layer that contacts the silicon substrate Including, a channel Comprising a three-dimensional (3D) NAND memory structure.

2. The 3D NAND memory structure according to claim 1, wherein the silicon substrate includes single-crystalline silicon on which the epitaxial silicon core grows through the channel hole.

3. The 3D NAND memory structure according to claim 1, wherein the alternating material layers include alternating layers of an oxide material and a nitride material.

4. The 3D NAND memory structure according to claim 1, wherein the alternating material layers include alternating layers of an oxide material and a metal, and the metal forms a gate electrode for individual memory cells in the memory structure.

5. The 3D NAND memory structure according to claim 1, wherein the epitaxial silicon core extends into the silicon substrate.

6. An epitaxial silicon layer extending beyond the channel hole, the epitaxial silicon layer being between the silicon substrate and the plurality of alternating material layers, and the epitaxial silicon layer connecting the epitaxial silicon core to a plurality of other channels in the memory structure, the epitaxial silicon layer Further comprising the 3D NAND memory structure according to claim 1.

7. A support structure extending into the silicon substrate through the plurality of alternating material layers and the epitaxial silicon layer Further comprising the 3D NAND memory structure according to claim 6.

8. A method of manufacturing a three-dimensional (3D) NAND memory structure, comprising: Forming a plurality of alternating material layers arranged in a stacked body perpendicular to a silicon substrate; Etching channel holes extending through the plurality of alternating material layers to the silicon substrate; Forming a tunnel layer contacting the plurality of alternating material layers around the channel holes; Epitaxially growing an epitaxial silicon core from the silicon substrate through the channel holes inside the tunnel layer A method comprising the above. **Claim 9** Etching the slits in the memory structure that extend into the sacrificial nitride layer on the silicon substrate through the plurality of alternating material layers The method according to claim 8, further comprising the above. **Claim 10** Exposing the sacrificial nitride layer to an etching process configured to selectively etch the sacrificial nitride layer The method according to claim 9, further comprising the above. **Claim 11** Removing a part of the tunnel layer that is exposed after removing the sacrificial nitride layer The method according to claim 10, further comprising the above. **Claim 12** Epitaxially growing an epitaxial silicon layer from the silicon substrate to replace the sacrificial nitride layer The method according to claim 10, further comprising the above. **Claim 13** Etching a second channel hole that extends into the silicon substrate through the plurality of alternating material layers, and Filling the second channel hole with a gap filling material as a support structure The method according to claim 8, further comprising the above. **Claim 14** A silicon substrate, A plurality of alternating material layers arranged in a stacked body perpendicular to the silicon substrate, wherein a plurality of channel holes extend through the plurality of alternating material layers, and A plurality of support structures extending into the silicon substrate through the plurality of alternating material layers A three-dimensional (3D) NAND memory array comprising the above. **Claim 15** The 3D NAND memory array according to claim 14, wherein the plurality of support structures include a metal filling one or more of the plurality of channel holes. **Claim 16** The 3D NAND memory array according to claim 14, wherein the plurality of support structures include a gap filling material in the slits within the memory array. **Claim 17** The 3D NAND memory array according to claim 16, wherein the alternating slits within the memory array form the support structures. **Claim 18** The plurality of support structures, A gap filling material within one or more slits within the memory array, and A metal filling one or more of the plurality of channel holes The 3D NAND memory array according to claim 14, comprising a combination of the above. **Claim 19** Further comprising a plurality of channels inside the plurality of channel holes, and The plurality of channels, A tunnel layer around the interior of the channel holes, which contacts the plurality of alternating material layers, and An epitaxial silicon core within the tunnel layer, which contacts the silicon substrate The 3D NAND memory array according to claim 14, comprising

20. An epitaxial silicon layer between the silicon substrates within the plurality of alternating material layers The 3D NAND memory array according to claim 19, further comprising, wherein the epitaxial silicon layer connects the epitaxial silicon cores of the plurality of channels

Images