Growth of Epitaxial Silicon Channel

Abstract

The three-dimensional NAND flash memory structure can include a solid channel core of epitaxial silicon that grows directly from a silicon substrate reference. Alternating oxide and nitride material layers can be formed as a stack. Channel holes extending downward to the silicon substrate can be etched through the material layers. A tunnel layer can be formed around the channel holes so as to contact the alternating material layers. The epitaxial silicon core can grow from the silicon substrate to the channel holes. In some embodiments, a support structure can be formed within the channel holes or within the slits of the memory array to provide physical support while the epitaxial silicon core grows through the channels.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application is filed on September 23, 2022, and claims priority to U.S. Provisional Patent Application 63 / 409,697 titled "EPITAXIAL SILICON CHANNEL GROWTH", which is incorporated herein by reference. This application also claims priority to U.S. Provisional Patent Application 63 / 343,437 titled "EPITAXIAL SILICON CHANNEL GROWTH" filed on May 18, 2022, and is incorporated herein by reference.

[0002]

[0002] This disclosure generally describes a memory cell comprising an epitaxial silicon channel core. More specifically, this disclosure describes techniques for manufacturing a 3D NAND flash memory structure comprising an epitaxial channel core grown from a silicon substrate.

Background Art

[0003]

[0003] A memory design known as NAND memory is a non - volatile flash memory storage architecture that does not require power to maintain stored data. NAND flash memory is used in many products such as solid - state devices and portable electronic devices. To increase the density and reduce the size of NAND memory, the conventional two - dimensional NAND architecture has migrated to three - dimensional NAND stacks. Different from 2D planar NAND technology where individual memory cells are stacked on separate horizontal substrates, 3D NAND is vertically stacked using multiple layers in which conductive and dielectric materials are alternately arranged, and vertical channels intersect.

Summary of the Invention

[0004]

[0004] In some embodiments, a three-dimensional (3D) NAND memory structure may include a silicon substrate and a plurality of alternating material layers disposed in a stacked configuration perpendicular to the silicon substrate. Channel holes may extend through the plurality of alternating material layers to the silicon substrate. The channel holes may be perpendicular to the plurality of alternating material layers. The memory structure may also include a channel within the channel holes that includes a tunnel layer surrounding the inside of the channel holes in contact with the plurality of alternating material layers, and an epitaxial silicon core within the tunnel layer in contact with the silicon substrate.

[0005]

[0005] In some embodiments, a method of manufacturing a 3D NAND memory structure may include forming a plurality of alternating material layers disposed in a stacked configuration perpendicular to a silicon substrate, etching channel holes that extend through the plurality of alternating material layers to the silicon substrate, forming a tunnel layer in contact with the plurality of alternating material layers around the channel holes, and epitaxially growing an epitaxial silicon core from the silicon substrate through the channel holes within the tunnel layer.

[0006]

[0006] In some embodiments, a 3D NAND memory array may include a silicon substrate and a plurality of alternating material layers disposed in a stacked configuration perpendicular to the silicon substrate. A plurality of channel holes may extend through the plurality of alternating material layers. The memory array may also include a plurality of support structures that extend through the plurality of alternating material layers into the silicon substrate.

[0007]

[0007] In some embodiments, a 3D NAND memory structure may include a layer on a silicon substrate and an oxide layer above the silicon substrate. Holes may be etched through the oxide layer to expose the oxide layer. The structure may also include epitaxial silicon growing from the substrate through the holes in the oxide layer, and a nitride layer covering the oxide layer and the epitaxial silicon.

[0008]

[0008] In some embodiments, a method of manufacturing a 3D NAND memory structure may include forming a layer on a silicon substrate. The method may also include etching holes through the layer to expose the silicon substrate. The method may additionally include epitaxially growing epitaxial silicon for channels through the holes from the silicon substrate. The method may further include forming a 3D NAND memory structure above the layer and the substrate such that channel holes within the 3D NAND memory structure include an epitaxial silicon core grown from the epitaxial silicon.

[0009]

[0009] In any embodiment, any and all of the following features may be implemented without limitation in any combination. The silicon substrate may include single-crystalline silicon in which an epitaxial silicon core grows through a channel hole. The alternating material layer may include an alternating layer of an oxide material and a nitride material. The alternating material layer may include an alternating layer of an oxide material and a metal. Here, the metal may form a gate electrode for individual memory cells within the memory structure. The epitaxial silicon core may extend into the silicon substrate. The memory structure may also include an epitaxial silicon layer that extends across the channel hole. Here, the epitaxial silicon layer may be between the silicon substrate and the plurality of alternating material layers. The epitaxial silicon layer may connect the epitaxial silicon core to a plurality of other channels within the memory structure. The memory structure may also include a support structure that extends into the silicon substrate through the plurality of alternating material layers and the epitaxial silicon layer. In the memory structure that extends into a sacrificial nitride layer on top of the silicon substrate through the plurality of alternating material layers, a slit may be etched. The sacrificial nitride layer may be subjected to an etching process configured to selectively etch the sacrificial nitride layer. A portion of the tunnel layer exposed after removing the sacrificial nitride layer may be removed. An epitaxial silicon layer may grow epitaxially from the silicon substrate to replace the sacrificial nitride layer. A second channel hole may be etched that extends into the silicon substrate through the plurality of alternating material layers. The second channel hole may be filled with a gap filling material as a support structure. The plurality of support structures may include a metal that fills one or more of the plurality of channel holes. The plurality of support structures may include a gap filling material within a slit in the memory array. By arranging the slits in the memory array alternately, a support structure may be formed. The plurality of support structures may include a combination of a gap filling material within one or more slits in the memory array and / or a metal that fills one or more of the plurality of channel holes.

[0010]

[0010] When an epitaxial silicon plug is formed instead before alternating material layers, such as by growing epitaxial silicon above the upper surface of a silicon oxide layer above a silicon substrate, the 3D NAND memory structure can be formed on the epitaxial silicon. For example, this method may also include forming a nitride layer on the layer and the epitaxial silicon, and polishing the nitride layer to remove surface variations caused by the height difference between the layer and the epitaxial silicon. The method further may include forming a plurality of alternating nitride and oxide layers above the layer and the substrate, etching a channel hole through the plurality of alternating nitride and oxide layers to expose the epitaxial silicon, and epitaxially growing the epitaxial silicon to the channel hole to form an epitaxial silicon core of the channel hole. The epitaxial silicon may extend above the upper surface of the oxide layer. The upper surface of the nitride layer may be planarized so that there is no surface variation due to the height difference between the oxide layer and the epitaxial silicon, and the upper surface of the nitride layer is flat. The hole may extend below the upper surface of the silicon substrate so that the epitaxial silicon extends into the silicon substrate. The plurality of alternating material layers may be arranged in a vertical stack on the nitride layer. The channel hole may extend through the plurality of alternating material layers to the epitaxial silicon.

[0011]

[0011] A further understanding of the nature and advantages of various embodiments can be realized by referring to the remainder of this specification and the drawings. In the drawings, like reference numerals are used throughout several drawings to refer to like components. In some instances, a sub-label is associated with the reference numeral to indicate one of a plurality of like components. When reference is made to the reference numeral without designation of an existing sub-label, it is intended to refer to all such plurality of like components.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2A

[0013] FIG. 2 shows an incremental stage for generating an array of 3D NAND flash memory cells with an epitaxial silicon channel according to some embodiments.

Figure 2B

Figure 2C

Figure 2D

Figure 2E

Figure 2F

Figure 2G

Figure 2H

Figure 2I

Figure 2J

Figure 2K

Figure 2L

Figure 2M

Figure 2N

Figure 2O

Figure 2P

Figure 2Q

Figure 3A

[0014] Shows a portion of a memory array, according to some embodiments.

Figure 3B

[0015] Shows a portion of a memory array when some of the channels are used in a support structure to facilitate an epitaxial silicon channel core, according to some embodiments.

Figure 4A

[0016] Shows the progressive steps in a manufacturing process for a memory structure that uses slits to separate memory blocks for a support structure when growing an epitaxial silicon channel for individual memory cells, according to some embodiments.

Figure 4B

Figure 4C

Figure 4D

Figure 4E

Figure 4F

Figure 4G

Figure 4H

Figure 4I

Figure 4J

Figure 4K

Figure 4L

Figure 5

[0017] Shows a top view of a portion of a memory array, according to some embodiments.

Figure 6A

[0018] Shows progressive steps for forming a laminate including a support structure in both a channel hole and a slit, according to some embodiments.

Figure 6B

Figure 6C

Figure 6D

Figure 6E

Figure 6F

Figure 6G

Figure 6H

Figure 7

[0019] Shows a top view of a part of a memory array, according to some embodiments.

Figure 8

[0020] Shows a flowchart of a method for manufacturing a 3D NAND memory structure, according to some embodiments.

Figure 9A

[0021] Shows the steps in a process for forming channel holes with epitaxial silicon at the base of the channel holes before the channel holes are formed within a layer of alternating oxide / nitride layers, according to some embodiments.

Figure 9B

Figure 9C

Figure 9D

Figure 9E

Figure 9F

Figure 9G

Figure 9H

Figure 9I

Figure 10

[0022] A flowchart 1000 of a method for manufacturing a 3D NAND memory structure according to some embodiments is shown.

Embodiments for Carrying Out the Invention

[0013]

[0023] Conventional three-dimensional (3D) NAND flash memory structures use channel cores made from oxide materials or polycrystalline silicon. However, epitaxial silicon exhibits much higher mobility than polycrystalline silicon or other similar materials. The present disclosure describes a 3D NAND flash memory structure that uses an epitaxial silicon core grown directly from a silicon substrate reference. Alternating oxide and nitride material layers can be formed as a stack. Channel holes extending downward to the silicon substrate can be etched through the material layers. A tunnel layer can be formed around the channel holes to contact the alternating material layers. The epitaxial silicon core can grow from the silicon substrate to the channel holes. In some embodiments, a support structure can be formed within the channel holes or within the slits of the memory array to provide physical support while the epitaxial silicon core grows through the channel.

[0014]

[0024] FIG. 1 shows a top view of one embodiment of a processing system 100 of a deposition chamber, an etching chamber, a baking chamber, and a curing chamber according to some embodiments. In this figure, a pair of front-opening unified pods 102 supply substrates of various sizes. These substrates are received by a robotic arm 104, placed in a low-pressure holding area 106, and then placed in one of the substrate processing chambers 108a-f within the tandem sections 109a-c. A second robotic arm 110 may be used to transfer the substrate wafers to and from the holding area 106 to the substrate processing chambers 108a-f. Each substrate processing chamber 108a-f can be equipped to perform a number of substrate processing steps, including the dry etching processes described herein, in addition to periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma processing, degassing, orientation, and other substrate processes.

[0015]

[0025] The substrate processing chambers 108a - f may include one or more system components for depositing, annealing, curing, and / or etching a material film on a substrate or wafer. In one configuration, two pairs of processing chambers, such as 108c - d and 108e - f, are used to deposit material on the substrate, and a third pair of processing chambers, such as 108a - b, may be used to cure, anneal, or process the deposited film. In another configuration, all three pairs of chambers, such as 108a - f, may be configured to deposit and cure a film on the substrate. Any one or more of the processes described may be performed in additional chambers separate from the manufacturing systems shown in different embodiments. It will be understood that the processing system 100 contemplates additional configurations of deposition chambers, etching chambers, annealing chambers, and curing chambers for material films. Additionally, any number of other processing systems may be utilized with this technology, and these processing systems may incorporate chambers for performing any of the specific steps. In some embodiments, a chamber system that can provide access to multiple processing chambers while maintaining a vacuum environment in various sections such as the aforementioned holding area and transfer area can enable operations to be performed within multiple chambers while maintaining a specific vacuum environment between individual processes.

[0016]

[0026] The processing system 100, more specifically, the chambers incorporated into the processing system 100 or other processing systems, may be used to manufacture structures according to some embodiments of this technology. For example, the processing system 100 may be used to manufacture a memory array by performing processes such as deposition, etching, sputtering, polishing, and cleaning in various substrate processing chambers 108.

[0017]

[0027] Figures 2A - 2Q illustrate incremental stages for generating an array of 3D NAND flash memory cells with epitaxial silicon channels according to several embodiments. Figure 2A shows a partial stack of alternating oxide - nitride layers that can be formed for a 3D NAND flash array. For each layer shown in Figure 2A, one layer can be incrementally formed on top of the previous layer using any deposition or layer - forming technique. In this example, layers can be formed on a substrate 200 of a silicon material such as an epitaxial silicon or single - crystal silicon wafer. A silicon oxide layer 202 can be formed on the substrate 200, followed by a silicon nitride layer 204. In some embodiments, the silicon oxide layer 202 and the silicon nitride layer 204 represent the first layers on the substrate 200, and these layers can be thicker than the alternating oxide - nitride layers formed thereon. Next, alternating layers of silicon oxide 206 and silicon nitride 208 can be formed in a stacked manner.

[0018]

[0028] The progressive formation of the substrate 200, the silicon oxide layer 206, the silicon nitride layer 208, and other materials described later in Figures 2A - 2Q can be collectively referred to as the stack 224. As shown in Figure 2A, the stack 224 can initially have a limited height. For example, a completed stack can have a very large number of layers (e.g., 128 pairs of alternating oxide and nitride layers). However, if all of these layers are formed first, the aspect ratio can be too high, resulting in a stack 224 in which narrow channel holes and other vias that penetrate the entire stack 224 cannot be reliably formed. Thus, the stack 224 can initially be partially formed. Next, the partial stack can have channel holes etched therein. Additional alternating oxide and nitride layers can be added on top of the partial stack, and those additional layers can be etched at the same position to form channel holes that continue with a more uniform width through all of the alternating oxide and nitride layers. Thus, a high aspect ratio is maintained without over - angling the sidewalls of the channel holes.

[0019]

[0029] Figure 2B shows a method of etching a partial laminate to form holes 203 that penetrate alternating silicon oxide layers 206 and silicon nitride layers 208. To remove the material exposed by the mask, a mask can be overlaid on the partial laminate and the etching process can be executed to form holes 203. Any etching process can be used. Some embodiments can use dielectric etching. The etching through the alternating silicon oxide layers 206 and silicon nitride layers 208 can benefit from dielectric etching. This is because the desired aspect ratio of the holes 203 for the device channel is relatively high (i.e., the vertical depth of the holes 203 is relatively large compared to the horizontal width of the holes 203). Generally, the depth of the holes 203 can be controlled based on the number of silicon oxide layers 206 and the number of silicon nitride layers 208 to be etched. For example, the time allowed for the execution of the etching process can be determined by the number of silicon oxide layers 206, the number of silicon nitride layers 208, and the thickness of these layers. For example, some embodiments can etch the holes 203 down to the silicon nitride layer 204. Other embodiments can etch the holes 203 down to the silicon oxide layer 202 or down to the upper surface of the substrate 200. The example shown in Figure 2B stops the etching at the upper part of the silicon nitride layer 204.

[0020]

[0030] FIG. 2C shows how bottom punch etching can be used to penetrate the substrate 200 to expose the silicon of the substrate 200, according to some embodiments. The dielectric etching used in FIG. 2B can stop the channel hole etching before the etching penetrates the substrate 200. Some embodiments may then perform a second etching process such that the hole 203 extends down into the substrate 200. This additional etching can be a directional etching oriented in a vertical direction towards the bottom of the hole 203. This may be referred to herein as "bottom punch" etching. The bottom punch etching can expose the silicon material of the substrate 200 at the bottom of the hole 203. The bottom punch etching can represent an etching different from the etching used to form the hole. For example, the bottom punch etching can be performed in a conductor etching chamber instead of a dielectric etching chamber. This conductor etching chamber can have better critical dimension uniformity and profile control than the dielectric etching used to initially form the hole 203 for the device channel. Thus, the bottom punch can extend the hole 203 down into the substrate 200 to expose the silicon material. For example, the bottom punch etching can extend to the top surface of the substrate 200 or penetrate into the substrate 200 below the top surface of the substrate 200. Alternatively, other embodiments can etch the entire length of the hole 203 down into the substrate 200 using a single etching process. Thus, the results of FIGS. 2B-2C are combined in a single processing step. The exposed silicon material of the substrate 200 can be used in a later step to epitaxially grow silicon through a channel forming a 3D NAND flash memory cell.

[0021]

[0031] Figure 2D shows how laminate 224 can be extended by adding additional silicon oxide layer 207 and silicon nitride layer 209 on a partial laminate according to some embodiments. These additional layers can be formed progressively on the partial laminate. Alternatively, these layers can be formed separately and placed on the partial laminate. It should be understood that the partial laminates shown in these figures are greatly simplified for clarity. In reality, the laminate includes a number of layers, a number of channel holes, and can be used to form hundreds of 3D NAND flash memory cells. However, these figures are simplified to show the formation of a single epitaxial silicon channel and adjacent support structures or slits within the memory array. For example, an actual laminate can include thousands of channels, over 100 alternating oxide and nitride layers, as well as multiple slits and support structures. These layers are formed in multiple processes, and the etching process can be performed progressively for each batch of layers as they are added to the partial laminate. Thus, although Figure 2D shows only two partial laminates being combined, it will be understood that a number of additional partial laminates may be stacked and etched to form holes 203 through laminate 224. For example, in some embodiments, a combination of two partial laminates each including about 128 alternating oxide-nitride layers can be included, for a total of 256 alternating oxide-nitride layers.

[0022]

[0032] Figure 2E shows laminate 224 formed from a plurality of partial laminates each etched individually according to some embodiments. After adding additional silicon oxide layer 207 and silicon nitride layer 209 of the second partial laminate, holes 211, 219 can be etched in these layers as shown. Note that these holes 211, 219 can be formed using a mask similar to that previously used to etch holes 203 in the first partial laminate. By etching this set of layers progressively, a very high aspect ratio can be achieved despite the depth of holes 211, 219 in the complete laminate 224.

[0023]

[0033] Figure 2F shows a support feature 210 that can be formed in one of the holes to provide support during subsequent steps of the process, according to some embodiments. The support feature 210 can be selectively deposited in one of the holes to form a rigid structure. For example, some embodiments can use a metal such as tungsten to form the support feature 210. Some embodiments can use a dielectric fill such as SiOx or a metal-aluminum oxide-nitride-oxide-silicon (MANOS) stack for the support feature 210. Any deposition process can be used to form the support feature 210. It should be noted that the support feature 210 can extend below the substrate 200 due to the above-described etching process that overshoots the last silicon oxide layer 202. As will become apparent later in the present disclosure, the support feature 210 prevents the layers of the laminate 224 from collapsing when the sacrificial nitride layer 204 is removed. Further, by extending the support feature 210 below the substrate 200, it prevents the upper layers of the laminate 224 from optionally moving when the nitride layer 204 is removed later.

[0024]

[0034] FIG. 2G shows a first layer of epitaxial silicon 212 formed in one of the holes 219, according to some embodiments. As described above, due to the additional depth of the bottom punch etching into the substrate 200, the silicon material of the substrate 200 is exposed in the channel holes 219. Since the single-crystalline silicon of the substrate 200 is exposed, the layer of epitaxial silicon 212 can grow in the channel holes using a process such as silicon epitaxial deposition or epitaxy that grows a thin layer of single-crystalline silicon on top of the single-crystalline silicon substrate 200. For example, some embodiments may perform an epitaxy process through chemical vapor deposition. To gradually form the epitaxial silicon 212 growing on the substrate 200, materials such as silicon tetrachloride, trichlorosilane, dichlorosilane, silane, and other chemical precursors of silicon can be supplied to the deposition chamber. The height of the epitaxial silicon 212 can be above the silicon oxide layer 202, but can be below the next silicon oxide layer in the stack 224. For example, the height of the epitaxial silicon 212 can be within the sacrificial nitride layer 204.

[0025]

[0035] At this stage shown in FIG. 2G, the channel holes 219 are formed in a plurality of layers of alternating nitride / oxide layers such that the channel holes 219 extend downward to expose the substrate 200. Thereafter, after the channel holes 219 are formed in the device stack 224, the epitaxial silicon 212 grows. However, alternative embodiments may instead first expose the silicon of the substrate 200 and form the epitaxial silicon 212 before forming subsequent layers and etching the channel holes. This alternative process will be described in detail in FIGS. 9A-9I below. This alternative process can be freely substituted for the process described in FIGS. 2A-2G to form the same structure.

[0026]

[0036] FIG. 2H shows the deposition of the tunnel layer 214 within the hole 219, according to some embodiments. Since the hole 219 can now be used to form the channel of the vertical column of 3D NAND memory cells, the hole 219 may also be referred to herein as the channel hole 219. The tunnel layer 214 can be formed by depositing a blocking dielectric or oxide, a charge trap nitride (e.g., silicon nitride), and a tunnel dielectric or oxide. These three layers may be collectively referred to as the "tunnel layer" 214 in the present disclosure. The oxide layer within the tunnel layer 214 can provide an offset to the conduction band and valence band of the transistor device of the memory cell.

[0027]

[0037] For example, a layer of silicon nitride can be surrounded by inner and outer layers of silicon oxide. The various layers of the tunnel layer 214 can be formed using atomic layer deposition. Thus, the layers of the tunnel layer 214 can be relatively thin compared to the alternating oxide / nitride layers of the stack 224. By this process, the tunnel layer 214 can grow on the sidewalls of the channel hole 219, on the epitaxial silicon 212, and along the bottom of the channel hole. Note that since the epitaxial silicon 212 stops before the alternating silicon oxide layer 206 and silicon nitride layer 208 are deposited, the interior of the channel of the 3D NAND memory cell can be covered by the tunnel layer 214.

[0028]

[0038] FIG. 2I shows how the channel hole 219 can be filled with a sacrificial gap fill material 216, according to some embodiments. The channel hole 219 can be filled with a sacrificial gap fill material 216, such as carbon, for the purpose of protecting the tunnel layer 214 during subsequent etching processes.

[0029]

[0039] FIG. 2J shows a slit 218 that can be etched within the laminate 224 according to some embodiments. The slit 218 may represent a relatively long trench etched within the laminate 224 so as to be adjacent to a plurality of individual channel holes along the length of the slit 218. For a top view of the slit with respect to the channel holes in the memory array, see FIGS. 3A - 3B below. In contrast to the etching process used to form the channel holes, the slit 218 can be etched using a single process that penetrates all layers of the laminate 224. Since the width of the slit 218 can be wider than the channel holes, a single process can be used. Thus, the aspect ratio is smaller and can therefore be achievable with a single process. In some embodiments, a carbon liner 220 can be deposited inside the slit 218 to protect the internal silicon oxide layer 206 and silicon nitride layer 208 from subsequent chemical etching processes using the slit 218. For example, the carbon liner 220 can be deposited on the sidewalls and bottom of the slit 218, and subsequent etching can be used to remove the carbon liner 220 from the bottom of the slit 218 to expose the silicon nitride layer 204. The slit 218 can be used in two different memory blocks of the memory array. In a later process, the slit 218 can provide access to all nitride layers within the laminate 224 so that these nitride layers can be removed and replaced with tungsten (or any other conductive material) to form a conductive path for each memory cell. These conductive paths can later form the word lines or gate electrodes of the memory cells. For example, wet etching using hot phosphoric acid can be used to remove the nitride layer from the laminate 224. Then, the slit 218 can provide access to the precursors so that an atomic layer deposition process can be used to grow tungsten within the voids left from the removed nitride layer.

[0030]

[0040] FIG. 2K shows the selective removal of the nitride layer 204 according to some embodiments. To grow epitaxial silicon 212 within the channel holes, the nitride layer 204 may be removed for the purpose of exposing the portion of the tunnel layer 214 that needs to be removed so that the epitaxial silicon 212 is again exposed to the channel holes. In this example, wet etching such as high-temperature phosphoric acid chemical etching may be used. The wet etching can access the nitride layer 204 through the slit 218 and selectively remove the nitride layer 204. The carbon liner 212 can protect the inner nitride layer from the etching process. Other embodiments may use dry etching or other processes configured to selectively remove the nitride layer 204.

[0031]

[0041] FIG. 2L shows the selective removal of the tunnel layer 214 from the bottom of the channel holes according to some embodiments. The above-described wet / dry etching processes may be used for the removal of the nitride layer of the tunnel layer 214. Similar processes may be used to selectively remove the dielectric layer or oxide layer of the tunnel layer 214. Note that the gap 230 left by the removal of the nitride layer 204 is lined on the top and bottom by oxide layers. These oxide layers (e.g., oxide layer 202) may be formed to be slightly thicker than the other oxide layers within the stack 224. However, since the oxide layer and nitride layer of the tunnel layer 214 may be formed as atomic layer deposition layers, these layers will be relatively thin so that they can be removed without removing a significant portion of the other oxide layers that may be exposed to the etching process.

[0032]

[0042] FIG. 2M shows the removal of the sacrificial gap fill material 216 from the channel holes 219 according to some embodiments. Note that when the sacrificial gap fill material 216 is removed, the tunnel layer 214 lines the channel holes 219 and is exposed to the epitaxial silicon 212.

[0033]

[0043] FIG. 2N shows the growth of epitaxial silicon 212 according to some embodiments. The epitaxy process can be performed as described above. However, since the slit 218 and the channel holes 219 are exposed to the epitaxial silicon 212, a layer of epitaxial silicon 236 can be grown to fill the gap 230 and begin to fill the channel holes 219. To prevent the slit 218 from being filled with epitaxial silicon, the growth of the layer of epitaxial silicon 236 can stop when it reaches the bottom of the channel holes 219.

[0034]

[0044] FIG. 2O shows the selective removal of a portion of the layer of epitaxial silicon 236 at the bottom of the slit 218. A portion of the epitaxial silicon layer 236 can be removed using an etching process to perform a bottom "punch" as described above. This etching can remove the portion of the epitaxial silicon layer 236 up to the bottom oxide layer 202 as shown in FIG. 2O. Alternatively, the etching can penetrate through the bottom oxide layer 202 and into the substrate 200.

[0035]

[0045] FIG. 2P shows the deposition of a sacrificial gap filling material 240 within the slit 218 according to some embodiments. The sacrificial gap filling material 214 can be deposited within the slit 218 such that the epitaxial silicon layer 236 grows within the channel holes 219 without filling the slit 218.

[0036]

[0046] Figure 2Q shows the epitaxial growth of the epitaxial silicon layer 236 up to the channel hole 219 according to some embodiments. Up to this point, the previous steps of this process have been performed to provide channel holes in which epitaxial silicon can be grown as the channel core of the 3D NAND flash memory cell. For example, by the steps described above, a reference layer of epitaxial silicon is formed at the bottom of the channel hole 219 grown from the substrate 200 itself. To grow the epitaxial silicon layer 236 up to the channel hole 219, the epitaxy process can be performed as described above. The resulting structure can include a stack 224 having channel holes filled with an epitaxial silicon core 242, rather than an oxide core or a polycrystalline silicon core as seen in the conventional "macaroni" structure of 3D NAND flash memory cells. Thus, the embodiments described herein can be at least partially distinguished from conventional 3D NAND flash memory cells by the physical connection between the epitaxial silicon core 242 and the substrate 200, and by the epitaxial silicon core 242 used for the channel, along with the angled walls of the channel and the channel hole.

[0037]

[0047] Referring to Figure 2Q, the 3D NAND memory structure can include a silicon substrate 200 that can be formed of single-crystalline silicon. The memory structure can also include a plurality of alternating material layers 275 arranged in a stacked manner perpendicular to the silicon substrate 200. The alternating material layers 275 can include alternating layers of an oxide material and a nitride material (e.g., silicon oxide and silicon nitride). At a later stage of the manufacturing process, the alternating material layers 275 can alternatively include alternating layers of an oxide material and a metal such as tungsten. For example, to form the gate electrodes of the individual memory cells within the memory structure, the nitride material can be selectively removed and replaced with a metal.

[0038]

[0048] The interleave material layer 275 may define channel holes 277 that extend through the plurality of interleave material layers 275 to the silicon substrate 200. The channel holes 277 may be formed using any of the processes described throughout this disclosure. As illustrated, the channel holes 277 may be substantially perpendicular to the plurality of interleave material layers 275. The memory structure may also include channels inside the channel holes 277. The channels may include a tunnel layer 214 around the inside of the channel holes (and thus around the outside of the channels) using the layers described above. Also, the channels may include an epitaxial silicon core 242 inside the tunnel layer that contacts the silicon substrate 200. In some cases, the epitaxial silicon core 242 may extend into the silicon substrate 200. Thus, the epitaxial silicon core 242 starts epitaxial growth below the top level of the silicon substrate 200.

[0039]

[0049] The memory structure may also include a layer of epitaxial silicon 236 that extends across the channel holes. The layer of epitaxial silicon 236 may be parallel to the plurality of interleave material layers 275. It will be recalled that FIG. 2Q shows only one of the many channels in the memory structure. Thus, the epitaxial silicon layer 236 may connect the epitaxial silicon cores 242 of the illustrated channels to a plurality of other channels within the memory structure. For example, the epitaxial silicon cores of each channel connected by the epitaxial silicon layer 236 may grow simultaneously from the epitaxial silicon layer 236 during the same epitaxy process.

[0040]

[0050] The process described above may be used to selectively grow the epitaxial silicon core 242 using the single crystal silicon of the substrate 200. 3D NAND flash memory cells using the epitaxial silicon core 242 exhibit better performance than similar memory cells using an oxide core. For example, the mobility of polycrystalline silicon is 10 to 20 times lower than the mobility of epitaxial silicon.

[0041]

[0051] To complete the memory array, additional processes may be performed later on the stack 224. These processes are outside the scope of the present disclosure, but may include removing the sacrificial gap filling material 240 from the slit, removing the nitride layer in the stack 224, depositing a conductive metal (e.g., tungsten) instead of the nitride layer to form the gate electrode, performing staircase etching on the stack, and the like.

[0042]

[0052] FIG. 3A shows a portion of a memory array 300 according to some embodiments. This portion of the memory array 300 may represent a single memory block having an offset row of channels 256. Slits 250, 252 may be used to separate this memory block from other memory blocks. In this example, 24 channels are used in the offset column between slits 250, 252. This portion of the memory array 300 may use a core of conventional oxide or polycrystalline silicon in the channels. Thus, no support structure is required and each channel hole may be used to implement the memory cell.

[0043]

[0053] In comparison, FIG. 3B shows a portion of the memory array 301 when a portion of the channel is used in the support structure to facilitate an epitaxial silicon channel core, according to some embodiments. As described above, the process for growing an epitaxial silicon channel for the memory cells within the memory array 301 uses a process in which some of the channel holes are used in the support structure 254 to prevent the memory array 301 from collapsing when the sacrificial nitride layer is removed to create space for the epitaxial silicon layer. To provide a suitable support for the stack of layers within the array during the manufacturing process, these support structures 254 can be spaced throughout the memory array. Note that the spacing shown in FIG. 3B is provided by way of example and is not intended to be limiting. In this example, the spacing of the support structures 254 is approximately every four channel holes and every other row. In this configuration, by using some of the channel holes used for the memory cells for the support structure 254, the bit density per area within the memory array 301 is slightly reduced.

[0044]

[0054] As described above, some embodiments can use channel holes to provide a support structure during the manufacturing process. An advantage of using channel holes for the support structure is that the spacing of the support structures can be increased or decreased as needed. However, some embodiments can alternatively form the same epitaxial silicon channel by using slits instead of channel holes to provide the support structure. These embodiments represent a trade-off of reducing the number of supports provided throughout the memory block in exchange for an increase in channel density.

[0045]

[0055] Figures 4A - 4L show progressive stages in a manufacturing process for a memory structure that uses slits to separate memory blocks for a support structure when growing an epitaxial silicon channel for individual memory cells, according to some embodiments. Figure 4A shows a channel hole 401 within a stack 400 having epitaxial silicon 406 grown from a substrate 400. The channel hole 401 and the epitaxial silicon 406 can be formed using the processes described above in connection with Figures 2A - 2G. In some embodiments, the epitaxial silicon 406 can be formed after the channel hole 401 is formed within a first set of oxide / nitride layers and before a set of oxide / nitride layers above it is formed and etched to extend the channel hole 401. For example, returning to Figure 2C, after the channel hole 203 is etched and bottom punch etching is used to extend the channel hole 203 into the substrate 200, at this stage, epitaxial silicon 406 can grow into the channel hole 203 from the exposed substrate 200. After the epitaxial silicon 406 is formed within the hole 203, the number of device layers and the depth of the channel hole 203 can be increased, and the upper alternating layers of oxide 207 and nitride 209 can be added and etched to ultimately form the structure shown in Figure 4A. Alternatively, the epitaxial silicon 406 can grow after the channel hole 401 is completely formed or at any stage after the silicon of the substrate 400 is exposed.

[0046]

[0056] In this example, instead of using one of the channel holes 401 for a support structure, each of the channel holes 401 can be used to form a channel for a memory cell. Figure 4B shows the channel hole 401 after a tunnel layer 408 is lined. The tunnel layer can be formed as described in detail above in connection with Figure 2H. Figure 4C shows the channel hole 401 filled with a sacrificial gap fill material 410, which can be formed as described in detail above in connection with Figure 2I.

[0047]

[0057] Figure 4D shows slits 412, 413 that can be formed on both sides of a memory block according to some embodiments. Although only two channel holes are shown in Figure 4D, it should be understood that there can be many additional channels between slits 412, 413. For example, slits 412, 413 can surround a memory block with a block width of 24 channels. These channels can be arranged in a honeycomb pattern of two columns offset by 12 channels each. Multiple pairs of these offset columns of 24 channels can exist within the block. Typically, slits 412, 413 are etched only up to a depth above substrate 400 but below the first oxide layer 417 in the alternating material layers forming the memory cells. For example, slit 213 is below the first oxide level 417 and is etched to a depth within the sacrificial nitride layer 415. However, the slits can undergo additional or extended etching processes so that their depth increases to provide a support structure when later manufacturing the epitaxial silicon layer and channel core. For example, slit 412 can be etched to a depth below the upper surface of substrate 400 using bottom punch etching. Thereby, slit 412 can function as a support structure fixed to substrate 400 rather than floating above the substrate.

[0048]

[0058] Figure 4E shows slit 412 designated to function as a support structure filled with gap filling material 414 according to some embodiments. In this example, alternating slits can be used as a support structure for the memory array. Thus, slit 413 can remain shallower in depth. On the other hand, slit 412 is etched to a depth below substrate 400 and filled with gap filling material 414 to function as a support structure during the growth of the epitaxial silicon layer.

[0049]

[0059] FIG. 4F shows the removal of the sacrificial nitride layer 415 according to some embodiments. As described above in connection with FIG. 2K, the sacrificial nitride layer 415 can be exposed to an etching process through the slit 413 to selectively remove the sacrificial nitride layer 415. Although not explicitly shown in FIG. 4F, in order to prevent the etching process from removing the nitride layer from the alternating material layers that will be used later to form the memory cells, a protective liner material (e.g., carbon) may be applied to the sidewalls of the slit 413. Additional bottom punch etching can be applied to remove the protective liner from the bottom of the slit 213 so that the sacrificial nitride layer 415 is exposed to the etching process.

[0050]

[0060] FIG. 4G shows the removal of the tunnel layer 408 from the bottom portion of the channel according to some embodiments. For example, the layer used for the tunnel layer 408 can be selectively removed by a wet etching process and / or a dry etching process as described above. After removing the exposed portion of the tunnel layer 408 at the bottom of the channel hole, the gap filling material 414 can provide a support structure to the stack 400 so that the stack 400 does not collapse after exposing the gap 416 between the substrate 400 and the first oxide layer 417.

[0051]

[0061] FIG. 4H shows the removal of the sacrificial gap filling material 410 from the channel hole 401 using selective etching. FIG. 4I shows the epitaxial growth of the epitaxial silicon layer 420 in the gap 416. As described above, the epitaxial silicon layer 420 can grow until it begins to fill the channel hole 401. FIG. 4J shows the formation of a hole 422 in the epitaxial silicon layer 420 to expand the slit 413 using a bottom punch etching process. FIG. 4K shows the slit 413 filled with the gap filling material 424. FIG. 4L shows the growth of the epitaxial silicon core 426 in each channel within the memory block. Each of these steps can be performed as described in detail above in connection with FIGS. 2A - 2Q.

[0052]

[0062] The channels in the stack 400 resulting from the results shown in FIG. 4L are substantially the same as the channels in the stack 224 resulting from the results shown in FIG. 2Q, with the tunnel layer 408 stretched and having alternating material layers 475 and channel holes 477 filled with epitaxial silicon core 426. However, in the memory structure including this stack 400, there is no need to secure any channels as a support structure. Instead, by using slits as a support structure during the manufacturing process, a maximum channel density can be achieved. As described above, additional process steps beyond the scope of the present disclosure, such as removal of alternating nitride layers, formation of a conductive layer (e.g., tungsten layer) for forming gate electrodes, and performing staircase etching, can then be performed on the stack 400 to complete the manufacture of the memory structure.

[0053]

[0063] FIG. 5 shows a top view of a portion of a memory array 500 according to some embodiments. In this example, all of the channel holes 456 can be used to form channels for memory cells. The alternating slits 550 can be used to provide a support structure during the manufacturing process. On the other hand, the remaining slits 552 can be used to provide access to the sacrificial nitride layer during the manufacturing process as described above. Note that the use of the alternating slits 550 is for illustrative purposes only and is not intended to be limiting. Depending on the block width of each memory block, other embodiments can use every third slit, every fourth slit, etc., based on the number of channels per block and the amount of support needed for anti-collapse.

[0054]

[0064] Instead of using only channel holes for the support structure or only slits for the support structure, some embodiments can use a combination of slits and channel holes to provide the support structure. This allows the spacing of the support structures to be very flexible. By using slits, the number of channel holes sacrificed for the support structure can be minimized while leaving room to provide additional support structures to as many channel holes as needed.

[0055]

[0065] Figures 6A - 6H show progressive steps for forming a laminate 600 that includes support structures in both channel holes and slits, according to some embodiments. Figure 6A shows the laminate 600 having channel holes filled with a support structure 604. Additional channel holes with support structures may also be present within the laminate 600 but are not explicitly shown in Figure 6A. The laminate 600 may also include channel holes filled with a gap filling material 602 and a tunnel layer 603 that separates the gap filling material 602 from epitaxial silicon 611 grown from a substrate 601. It should be noted that although not visible in Figure 6A, there may be many additional channel holes in the laminate 600. The laminate 600 may also include a slit 606 that is etched downward to a level above the substrate 601 and has a liner that contacts a sacrificial nitride layer 610. Another slit may be filled with a gap filling material 608 and may extend downward into the substrate 601 to function as a support structure.

[0056]

[0066] The remaining steps for growing epitaxial silicon within the channels of the laminate 600 can be carried out as detailed above. For example, Figure 6B shows the removal of the sacrificial nitride layer 610 to expose a gap 612 while the laminate 600 is supported by the support structure. Figure 6C shows the removal of a portion of the tunnel layer 603 that is exposed in the gap 612. Figure 6D shows the removal of the gap filling material 602 within the channel hole 614. Figure 6E shows the growth of an epitaxial silicon layer 616 in the gap 612. Figure 6F shows the result of a bottom punch etch to expand a hole 618 through the epitaxial silicon layer 616 for the slit 606. Figure 6G shows the gap filling material 620 within the slit 606. Figure 6H shows the growth of an epitaxial silicon core 622 in the channel hole 614.

[0057]

[0067] FIG. 7 shows a top view of a portion of a memory array 700 according to some embodiments. In this example, most of the channel holes can be used to form channels for the memory cells. The alternating slits 750 can be used to provide a support structure during the manufacturing process. On the other hand, the remaining slits 752 can be used to provide access to the sacrificial nitride layer during the manufacturing process as described above. Instead of using only slits for the support structure, in this hybrid example, a combination of slits and channel holes 756 is used to provide the support structure as described. This allows the spacing of the support structures to be set very flexibly. By using slits, the number of channel holes sacrificed for the support structure can be minimized while leaving room to provide additional support structures to as many channel holes as necessary.

[0058]

[0068] As shown in this embodiment, the processes described herein can be used to form a 3D NAND memory array 700 that includes a silicon substrate and a plurality of alternating material layers disposed in a stacked configuration perpendicular to the silicon substrate. A plurality of channel holes can extend through the alternatingly disposed material layers. A plurality of support structures extending into the silicon substrate through the plurality of alternating material layers can provide support during the manufacture of the memory array 700. The support structures can include metal filling one or more of the channel holes 756. The support structures can also include a gap filling material filling the slits 750 of the memory array 700. Some embodiments can use metal filled channel holes and / or gap filling materials, in any combination, without limitation, within one or more of the slits.

[0059]

[0069] FIG. 8 shows a flowchart 800 of a method for manufacturing a 3D NAND memory structure according to some embodiments. This method can be performed in various processing chambers within a semiconductor processing system, as shown in FIG. 1. The method can include forming a plurality of alternating material layers arranged in a vertical stack on a silicon substrate (802). The alternating layers can include nitride and oxide layers formed in a stacked manner as described above with reference to FIGS. 2A-2E. The method can also include etching channel holes extending through the plurality of alternating material layers to the silicon substrate (804). The channel holes can be etched using bottom punch etching to penetrate the silicon substrate, as described above with reference to FIG. 2E.

[0060]

[0070] The method can further include forming a tunnel layer in contact with the plurality of alternating material layers around the channel holes (806). The tunnel layer within the channel holes can be formed as described above with reference to FIGS. 2H-2L by depositing a tunnel oxide including the layers described above and selectively removing a portion of the tunnel layer exposed to an etching process at the bottom of the channel.

[0061]

[0071] The method can further include epitaxially growing a silicon core from the silicon substrate through the channel holes within the tunnel layer (808). The epitaxial silicon core can be grown using the steps described throughout this disclosure. For example, growing the epitaxial silicon core can include etching a slit of the memory structure extending into a sacrificial nitride layer on top of the silicon substrate through the plurality of alternating material layers, as shown in FIG. 2J. The sacrificial nitride layer can be exposed to an etching process configured to selectively etch the sacrificial nitride layer, as shown in FIGS. 2K-2M. As shown in FIG. 2N, an epitaxial silicon layer can epitaxially grow from the silicon substrate to replace the sacrificial nitride layer. In some embodiments, a second channel hole extending through the plurality of alternating material layers into the silicon substrate can be etched, and a support structure can be formed by filling the second channel hole with a gap filling material as a support structure.

[0062]

[0072] It should be understood that the specific steps shown in FIG. 8 provide a specific method for manufacturing a 3D NAND memory structure according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the above steps in a different order. Further, the individual steps shown in FIG. 8 may include a plurality of sub-steps that may be performed in various sequences suitable for the individual steps. Further, additional steps may be added or removed depending on the specific application. Many variations, modifications, and alternatives are also included within the scope of the present disclosure.

[0063]

[0073] In the above embodiment, at least a portion of the channel hole was first formed into an alternating nitride / oxide layer downward toward the substrate before epitaxial silicon was formed at the bottom of the channel hole. However, another method for forming epitaxial silicon at the bottom of the channel hole at an early stage of the manufacturing process may also be used.

[0064]

[0074] FIGS. 9A-9I show steps in a process for forming a channel hole with epitaxial silicon at the base of the channel hole before the channel hole is formed within a layer of alternating oxide / nitride layers, according to some embodiments. FIG. 9A shows a silicon substrate 902 that may be formed as described above. An oxide layer 904, such as a silicon oxide layer, may be formed on the substrate 902.

[0065]

[0075] Figure 9B shows how the bottom portion of channel hole 905 can be etched into silicon substrate 902 before forming subsequent oxide and / or nitride layers within the device stack. Since the aspect ratio is very low, any etching process can be used to form the bottom of channel hole 905. For example, since the vertical depth of channel hole 905 is very small, dielectric etching may be used to form channel hole 905 instead of the bottom punch etching described above. The bottom portion of channel hole 905 is shown only with respect to oxide layer 904 and substrate 902, but in other embodiments, other layers may be present on top of oxide layer 904. As described with the alternative process above, the bottom of channel hole 905 can be etched to a depth that exposes the silicon of substrate 902. For example, channel hole 905 can be etched at least to the upper surface of substrate 902, or can be etched below the upper surface of substrate 902 such that the bottom of channel hole 905 penetrates substrate 902.

[0066]

[0076] Figure 9C shows how epitaxial silicon 906 can be formed on the bottom portion of channel hole 905. Epitaxial silicon 906 can grow epitaxially from the crystal structure of the exposed silicon of substrate 902. Epitaxial silicon 906 can grow above the upper surface of substrate 902, or can grow above the upper surface of oxide layer 904. Epitaxial silicon 906 is shown as a rectangular shape growing straight from the sidewalls of channel hole 905 for clarity, but in an actual implementation, expansion can begin when epitaxial silicon 906 is no longer bounded by channel hole 905. For example, when epitaxial silicon 906 grows beyond the upper surface of oxide layer 904, it can form a "mushroom" shape. This horizontal expansion is allowed because there is a significant gap remaining between adjacent channel holes in the device layout.

[0067]

[0077] FIG. 9D shows how the bottom nitride layer 908 can be formed on the epitaxial silicon 906. As described above, the bottom nitride layer 908 can be thicker than other nitride layers in the device stack. The bottom nitride layer 908 can be formed on the oxide layer 904 and the epitaxial silicon 906 using any of the processes described above. However, since the epitaxial silicon 906 can grow above the upper surface of the oxide layer 904, the bottom nitride layer 908 may not be formed with a flat upper surface. As shown in FIG. 9D, since the bottom nitride layer 908 protrudes above the upper part of the oxide layer 904, it can conform to the shape and contour of the epitaxial silicon 906. Therefore, the upper part of the bottom nitride layer 908 may have unevenness on the surface after formation.

[0068]

[0078] FIG. 9E shows how the bottom nitride layer 908 can be processed to planarize the upper surface of the nitride layer 908. For example, after the bottom nitride layer 908 is formed, a polishing process such as a chemical mechanical polishing process can be used to planarize the upper surface of the wafer. This polishing process can remove a part of the bottom nitride layer 908 until the upper surface of the bottom nitride layer 908 becomes substantially flat. By planarizing the bottom nitride layer 908, a flat and stable surface can be provided on which the remaining alternating nitride / oxide layers in the device stack can be formed.

[0069]

[0079] FIG. 9F shows how the alternating nitrate / oxide layers 910 can be formed on the bottom nitride layer 908. These alternating nitrate / oxide layers 910 can be formed using any of the processes described above. FIG. 9F shows a single layer of the alternating nitride / oxide layer 910 formed on the bottom nitride layer 908. After the channel holes are etched, additional layers can be formed on this first layer.

[0070]

[0080] FIG. 9G shows how the channel holes 912 can be etched within the alternating nitride / oxide layers 910. Instead of etching the channel holes 912 downward into the silicon substrate 902, this etching process can etch downward onto the epitaxial silicon 906. The channel holes 912 can be etched using dielectric etching. Thus, this process may eliminate the need to transfer the wafer to a conductor etching chamber to perform bottom punch etching that expands the channel holes 912 downward into the silicon substrate 902. By forming the epitaxial silicon 906 at an early stage of the process before the alternating nitride / oxide layers 910 are formed, the depth of the channel hole etching is reduced, and as a result, the etching process can be simplified.

[0071]

[0081] FIG. 9H shows how subsequent layers of the alternating nitride / oxide layers 914 can be formed on top of the first layer of the alternating nitride / oxide layers 910. FIG. 9I shows how the alternating nitride / oxide layers 914 in the second layer can then be etched to expand the channel holes 912 downward to the first layer of the alternating nitride / oxide layers 910.

[0072]

[0082] This alternative process illustrated in FIGS. 9A - 9I can be freely substituted for the process described above in FIGS. 2A - 2G to form epitaxial silicon at the bottom of the channel holes.

[0073]

[0083] FIG. 10 shows a flowchart 1000 of a method for manufacturing a 3D NAND memory structure according to some embodiments. This method can be performed as part of the method described above and shown in FIG. 8 to form the first epitaxial silicon used to grow an epitaxial silicon core for the device. For example, in step 804, instead of etching the channel holes completely downward into the silicon substrate, the channel holes can be etched downward through a plurality of alternating material layers onto the epitaxial silicon formed using the method of flowchart 1000.

[0074]

[0084] The method may include forming a layer on a silicon substrate (1002). The silicon substrate may be formed from any of the silicon materials described above. This layer may include a first oxide layer such as a silicon oxide layer. The method may also include etching a hole extending through the layer to expose the silicon substrate (1004). A pattern corresponding to the position of the channel holes of the 3D NAND memory structure may be introduced on the layer. As described above, this hole may be etched downward to expose the silicon substrate. For example, the hole may be etched to expose the upper surface of the silicon substrate, or the hole may be etched to penetrate below the upper surface of the silicon substrate. This etching may be performed using a conductor etching process, a dielectric etching process, or other types of etching processes.

[0075]

[0085] The method may further include epitaxially growing epitaxial silicon for a channel through the hole from the silicon substrate (1006). The epitaxial silicon may form a silicon plug that fills the hole in the silicon substrate and the layer. In some embodiments, the epitaxial silicon may grow to a level above the upper surface of the semiconductor substrate and below the upper surface of the layer. Also, the epitaxial silicon may grow above the upper surface of the layer such that the upper portion of the epitaxial silicon is higher than the upper portion of the layer.

[0076]

[0086] The method may further include forming a 3D NAND memory structure (1008) above the layer and the substrate such that the channel holes in the 3D NAND memory structure include an epitaxial silicon core grown from epitaxial silicon. For example, a bottom nitride layer such as a silicon nitride layer may be formed on the layer and the epitaxial silicon. The upper portion of this nitride layer is not smooth and may have a surface profile affected by the height difference between the layer and the underlying epitaxial silicon. Next, the upper surface of this nitride layer may be planarized by subjecting the nitride layer to a polishing process to form a smooth surface for growing subsequent device layers. Next, the method may include forming a plurality of alternating material layers, such as alternating nitride and oxide layers, on the substrate and the layer. Thereafter, channel holes may be etched through the plurality of alternating nitride and oxide layers to expose the underlying epitaxial silicon. Then, this epitaxial silicon may be used to epitaxially grow an epitaxial silicon core through the channel holes.

[0077]

[0087] It should be understood that the specific steps shown in FIG. 10 provide a specific method of manufacturing a 3D NAND memory structure according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps described above in a different order. Further, each individual step shown in FIG. 10 may include a plurality of sub-steps that may be performed in various sequences suitable for the individual steps. Further, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also within the scope of the present disclosure.

[0078]

[0088] As used herein, the terms “about” or “approximately” or “substantially” may be construed to be within the range expected by one of ordinary skill in the art in light of this disclosure.

[0079]

[0089] In the above description, for the sake of convenience of explanation, numerous specific details have been described to provide a complete understanding of various embodiments. However, it will be apparent that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0080]

[0090] The above description provides only exemplary embodiments and does not limit the scope, applicability, or configuration of the present disclosure. Rather, the foregoing description of various embodiments will provide a realizable disclosure for implementing at least one embodiment. It should be understood that various changes may be made to the functions and arrangements of elements without departing from the spirit and scope of some embodiments, as set forth in the appended claims.

[0081]

[0091] Specific details have been given in the above description to provide a complete understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form so as not to obscure the embodiments with unnecessary details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail so as not to obscure the embodiments.

[0082]

[0092] Note also that individual embodiments have been described as processes, which may be shown as flowcharts, flow diagrams, data flow diagrams, structure diagrams, or block diagrams. Although steps may be described in a flowchart as sequential processes, many of the steps may be executed in parallel or simultaneously. Further, the order of the steps may be rearranged. A process may terminate when the steps are completed, but there may be additional steps not included in the figure. A process may correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the return of the function to the calling function or the main function.

[0083]

[0093] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction may represent any combination of procedures, functions, subprograms, programs, routines, subroutines, modules, software packages, classes, or instructions, data structures, or program statements. A code segment may be connected to another code segment or hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, transferred, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0084]

[0094] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or code segments for performing the necessary tasks may be stored on a machine-readable medium. One or more processors may perform the necessary tasks.

[0085]

[0095] In the above specification, features are described with reference to specific embodiments, but it should be recognized that not all embodiments are limited thereto. The various features and aspects of some embodiments can be used individually or in combination. Further, the embodiments can be utilized in any number of environments and applications other than those described herein without departing from the broader spirit and scope of this specification. Accordingly, this specification and the drawings should be regarded as illustrative rather than restrictive.

[0086]

[0096] Furthermore, for purposes of explanation, methods have been described in a particular order. In alternative embodiments, it should be understood that the methods may be performed in an order different from that described. Also, the methods described above may be performed by hardware components or embodied in a sequence of machine-executable instructions that may be used to cause a machine, such as a general or special purpose processor, or a logic circuit programmed with the instructions, to perform the methods. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy disk, a ROM, a RAM, an EPROM, an EEPROM, a magnetic or optical card, a flash memory, or other type of machine-readable media suitable for storing electronic instructions. Alternatively, the methods may be implemented by a combination of hardware and software.

Claims

1. A three-dimensional (3D) NAND memory structure comprising: a layer on a silicon substrate; an oxide layer above the silicon substrate, wherein holes are etched through the oxide layer to expose the silicon substrate; epitaxial silicon growing from the substrate through the holes in the oxide layer; and a nitride layer covering the oxide layer and the epitaxial silicon. A 3D NAND memory structure.

2. The 3D NAND memory structure according to claim 1, wherein the epitaxial silicon extends above the upper surface of the oxide layer.

3. The 3D NAND memory structure according to claim 1, wherein the upper surface of the nitride layer is planarized so that there is no surface variation due to the height difference between the oxide layer and the epitaxial silicon.

4. The 3D NAND memory structure according to claim 1, wherein the holes extend below the upper surface of the silicon substrate so that the epitaxial silicon extends into the silicon substrate.

5. A plurality of alternating material layers arranged in a stacked body perpendicular to the nitride layer. The 3D NAND memory structure according to claim 1, further comprising.

6. Channel holes extending through the plurality of alternating material layers to the epitaxial silicon. The 3D NAND memory structure according to claim 5, further comprising.

7. A channel inside the channel holes, the channel comprising: a tunnel layer around the inner circumference of the channel holes in contact with the plurality of alternating material layers, and an epitaxial silicon core inside the tunnel layer in contact with the epitaxial silicon and growing from the epitaxial silicon. The 3D NAND memory structure according to claim 6, further comprising. The 3D NAND memory structure according to claim 6, further comprising.

8. The 3D NAND memory structure according to claim 1, wherein the silicon substrate comprises single-crystalline silicon on which the epitaxial silicon grows.

9. The 3D NAND memory structure according to claim 1, further comprising a plurality of alternating material layers arranged in a stacked body perpendicular to the nitride layer and including alternating layers of an oxide material and a metal, wherein the metal forms a gate electrode for individual memory cells in the memory structure.

10. An epitaxial silicon layer extending across the channel holes. Further comprising, wherein the epitaxial silicon layer is between the silicon substrate and the plurality of alternating material layers, and the epitaxial silicon layer connects an epitaxial silicon core to a plurality of other channels in the memory structure, the 3D NAND memory structure according to claim 9.

11. A support structure extending into the silicon substrate through the plurality of alternating material layers and the epitaxial silicon layer Further comprising, the 3D NAND memory structure according to claim 10.

12. A method of manufacturing a three-dimensional (3D) NAND memory structure, comprising: Forming a layer on a silicon substrate; Etching a hole extending through the layer to expose the silicon substrate; Epitaxially growing epitaxial silicon for a channel through the hole from the silicon substrate; Forming the 3D NAND memory structure above the layer and the substrate such that a channel hole in the 3D NAND memory structure includes an epitaxial silicon core grown from the epitaxial silicon Including, the method.

13. The method according to claim 12, wherein the epitaxial silicon grows above an upper surface of the layer.

14. The method according to claim 12, wherein the layer includes a silicon oxide layer.

15. Forming the 3D NAND memory structure above the layer and the substrate includes: Forming a nitride layer above the layer and the epitaxial silicon Including, the method according to claim 12.

16. Forming the 3D NAND memory structure above the layer and the substrate includes: Polishing the nitride layer to remove surface variations caused by a height difference between the layer and the epitaxial silicon Further including, the method according to claim 15.

17. Forming the 3D NAND memory structure above the layer and the substrate includes: Forming a plurality of alternating nitride and oxide layers above the layer and the substrate Including, the method according to claim 12.

18. Forming the 3D NAND memory structure above the layer and the substrate includes: Etching a channel hole through the plurality of alternating nitride and oxide layers to expose the epitaxial silicon To form the epitaxial silicon core of the channel hole, epitaxially growing the epitaxial silicon until it reaches the channel hole The method according to claim 17, further comprising.

19. Forming the 3D NAND memory structure above the layer and the substrate comprises Forming a plurality of alternating material layers arranged in a vertical stack on a silicon substrate, Etching a channel hole that extends through the plurality of alternating material layers to the epitaxial silicon, Forming a tunnel layer in contact with the plurality of alternating material layers around the channel hole, Epitaxially growing an epitaxial silicon core from the epitaxial silicon through the channel hole inside the tunnel layer The method according to claim 12, comprising.

20. Etching a slit in the memory structure that extends into the layer through the plurality of alternating material layers, Subjecting the layer to an etching process configured to selectively etch the layer, Removing a part of the tunnel layer exposed after removing the layer The method according to claim 19, further comprising.

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