Array substrate and display panel

Abstract

Embodiments of the present application disclose an array substrate and a display panel. The array substrate includes a base substrate, an active layer, a first electrode layer, a first insulating layer, and a second electrode layer that are sequentially arranged. The sum of the orthographic projections of the first electrode layer and the second electrode layer on the base substrate covers the orthographic projection of the active layer on the base substrate. In the present application, the first electrode layer and the second electrode layer jointly protect the active layer, thereby avoiding the influence of external light on the active layer and ensuring the stability of the array substrate.

Description

Technical Field

[0001] This application relates to the display field, and more specifically to an array substrate and a display panel.

Background Art

[0002] With the development of display technology, the research on the stability of the active layer in the array substrate has been increasingly emphasized. Among them, metal oxide thin film transistors (MO-TFTs), especially indium gallium zinc oxide (IGZO) TFTs, have advantages such as excellent uniformity, high mobility, low drain current, and suitability for large-scale industrial manufacturing, and thus are widely applied in the flat panel display industry. However, in the current manufacturing process of the array substrate, IGZO is easily affected by external light irradiation, resulting in instability of the active layer, and thereby the operating performance of the array substrate becomes unstable in an environment where external light exists.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of this application provide an array substrate and a display panel that can solve the problem of low stability of conventional array substrates in an environment where external light exists.

Means for Solving the Problems

[0004] Embodiments of this application provide an array substrate, which includes a base substrate, an active layer disposed on the base substrate, a first electrode layer disposed on a side of the active layer away from the base substrate, wherein the first electrode layer and the active layer are partially overlapped and connected, a first insulating layer disposed on a side of the first electrode layer away from the active layer, A second electrode layer disposed on a side of the first insulating layer away from the first electrode layer, wherein a positive projection of the second electrode layer on the base substrate at least partially covers a positive projection of the active layer on the base substrate, and a sum of positive projections of the first electrode layer and the second electrode layer on the base substrate covers a positive projection of the active layer on the base substrate, and includes a second electrode layer.

[0005] Preferably, in some embodiments of the present application, a positive projection of the second electrode layer on the base substrate covers a positive projection of the active layer on the base substrate.

[0006] Preferably, in some embodiments of the present application, a sum of a light-shielding area of the second electrode layer with respect to the active layer and a light-shielding area of the first electrode layer with respect to the active layer is equal to an area of a positive projection of the active layer on the base substrate.

[0007] Preferably, in some embodiments of the present application, the first electrode layer includes a first electrode, the first electrode is connected in an overlapping manner with one end of the active layer, a first opening is formed in the first insulating layer, the first opening exposes the other end of the active layer, the second electrode layer includes a second electrode, and the second electrode is connected in an overlapping manner with the other end of the active layer through the first opening.

[0008] Preferably, in some embodiments of the present application, the first electrode is a drain, and the second electrode is a source.

[0009] Preferably, in some embodiments of the present application, the first electrode is a source, and the second electrode is a drain.

[0010] Preferably, in some embodiments of the present application, the first electrode layer includes a source and a drain connected in an overlapping manner with the active layer, the second electrode layer includes a light-shielding electrode, and a positive projection of the light-shielding electrode on the base substrate covers a positive projection of the active layer on the base substrate.

[0011] Preferably, in some embodiments of the present application, the array substrate is a gate layer disposed between the base substrate and the active layer, the gate layer including a gate disposed corresponding to the active layer, and a positive projection of the gate on the base substrate covering a positive projection of the active layer on the base substrate, and a second insulating layer disposed between the gate layer and the active layer, the second insulating layer further including a second insulating layer covering the gate layer.

[0012] Preferably, in some embodiments of the present application, the array substrate is a third insulating layer disposed on a side of the second electrode layer away from the first insulating layer, a second opening being formed in the third insulating layer, the second opening penetrating the third insulating layer and the first insulating layer along the thickness direction of the array substrate, and the second opening exposing the first electrode, and a pixel electrode layer disposed on a side of the third insulating layer away from the second electrode layer, the pixel electrode layer including a pixel electrode, and the pixel electrode being electrically connected to the first electrode through the second opening.

[0013] Preferably, in some embodiments of the present application, the array substrate is a third insulating layer disposed on a side of the second electrode layer away from the first insulating layer, a third opening being formed in the third insulating layer, and the third opening exposing the second electrode, and a pixel electrode layer disposed on a side of the third insulating layer away from the second electrode layer, the pixel electrode layer including a pixel electrode, and the pixel electrode being electrically connected to the second electrode through the third opening.

[0014] Preferably, in some embodiments of the present application, the second electrode layer further includes a common electrode, the pixel electrode layer further includes a connection electrode, a fourth aperture is formed at a position corresponding to the common electrode on the third insulating layer, and the connection electrode is electrically connected to the common electrode through the fourth aperture.

[0015] Preferably, in some embodiments of the present application, the second electrode layer further includes a common electrode, the pixel electrode layer further includes a connection electrode, a fourth aperture is formed at a position corresponding to the common electrode on the third insulating layer, and the connection electrode is electrically connected to the common electrode through the fourth aperture.

[0016] Preferably, in some embodiments of the present application, the material of the second electrode layer is a non-translucent conductive material.

[0017] Accordingly, embodiments of the present application further provide a display panel, and the display panel includes the array substrate described in any one of the above items.

[0018] Accordingly, embodiments of the present application further provide an array substrate, and this substrate includes a base substrate, an active layer disposed on the base substrate, a first electrode layer disposed on a side of the active layer away from the base substrate, the first electrode layer being partially overlapped and connected with the active layer, a first insulating layer disposed on a side of the first electrode layer away from the active layer, a second electrode layer disposed on a side of the first insulating layer away from the first electrode layer, the second electrode layer having a positive projection on the base substrate covering a positive projection of the active layer on the base substrate. Here, the first electrode layer includes a first electrode, the first electrode is overlapped and connected to one end of the active layer, a first opening is formed in the first insulating layer, the first opening exposes the other end of the active layer, the second electrode layer includes a second electrode, and the second electrode is overlapped and connected to the other end of the active layer through the first opening.

[0019] Preferably, in some embodiments of the present application, the first electrode is a drain, and the second electrode is a source.

[0020] Preferably, in some embodiments of the present application, the first electrode is a source, and the second electrode is a drain.

[0021] Preferably, in some embodiments of the present application, the array substrate is a gate layer disposed between the base substrate and the active layer, the gate layer includes a gate disposed corresponding to the active layer, and a positive projection of the gate on the base substrate covers a positive projection of the active layer on the base substrate. and a second insulating layer disposed between the gate layer and the active layer, the second insulating layer covering the gate layer.

[0022] Preferably, in some embodiments of the present application, the array substrate is a third insulating layer disposed on a side of the first insulating layer away from the second electrode layer, a second opening is formed in the third insulating layer, the second opening penetrates the third insulating layer and the first insulating layer along the thickness direction of the array substrate, and the second opening exposes the first electrode. and a pixel electrode layer disposed on a side of the third insulating layer away from the second electrode layer, the pixel electrode layer includes a pixel electrode, and the pixel electrode is electrically connected to the first electrode through the second opening.

[0023] Preferably, in some embodiments of the present application, the array substrate is a third insulating layer disposed on a side of the second electrode layer away from the first insulating layer, wherein a third opening is formed in the third insulating layer, and the third opening exposes the second electrode; a pixel electrode layer disposed on a side of the third insulating layer away from the second electrode layer, wherein the pixel electrode layer includes a pixel electrode, and the pixel electrode is electrically connected to the second electrode through the third opening.

Advantages of the Invention

[0024] In the embodiments of the present application, the array substrate includes a base substrate, an active layer, a first electrode layer, a first insulating layer, and a second electrode layer. The active layer is disposed on the base substrate, the first electrode layer is disposed on a side of the active layer away from the base substrate, the first electrode layer and the active layer are partially overlapped and connected, the first insulating layer is disposed on a side of the first electrode layer away from the active layer, the second electrode layer is disposed on a side of the first insulating layer away from the first electrode layer, a positive projection of the second electrode layer on the base substrate at least partially covers a positive projection of the active layer on the base substrate, and a sum of positive projections of the first electrode layer and the second electrode layer on the base substrate covers a positive projection of the active layer on the base substrate. By arranging the sum of the positive projections of the first electrode layer and the second electrode layer on the base substrate to cover the positive projection of the active layer on the base substrate, the first electrode layer and the second electrode layer can jointly protect the active layer, avoid the influence of external light on the active layer, and thereby ensure the stability of the array substrate.

Brief Description of the Drawings

[0025] To more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments are briefly described below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0026]

Figure 1

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Figure 3

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Figure 9

Embodiments for Carrying Out the Invention

[0027] Hereinafter, with reference to the drawings in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of them. Based on the embodiments in the present application, all other embodiments that can be conceived by those skilled in the art without creative efforts all belong to the protection scope of the present application. It should be understood that the specific embodiments described here are only for explaining and interpreting the present application, not for limiting the present application. In the present application, unless otherwise stated, the directional terms used, such as "upper" and "lower", generally refer to the upper and lower in the actual use or operating state of the device, specifically the paper surface direction in the figure, and "inner" and "outer" are the directions with respect to the contour of the device.

[0028] Embodiments of the present application provide an array substrate, a display panel, and a method for manufacturing an array substrate, which will be described in detail below. Note that the order of description of the following embodiments does not limit the preferred order of the embodiments.

[0029] First, embodiments of the present application provide an array substrate. As shown in FIGS. 1 to 3, the array substrate 100 includes a base substrate 110. The base substrate 110 is used as a support structure of the array substrate 100 to support other functional structure layers of the array substrate 100 and ensure the structural stability of the array substrate 100. Here, the base substrate 110 may be a glass substrate or other types of materials, and is not particularly limited herein.

[0030] The array substrate 100 includes an active layer 140. The active layer 140 is disposed on the base substrate 110. The active layer 140 is used as an important component of a thin film transistor to form a conductive trench. By controlling the conductive trench in the active layer 140, the conduction state of the thin film transistor can be controlled.

[0031] The array substrate 100 includes a first electrode layer 150. The first electrode layer 150 is disposed on the side of the active layer 140 away from the base substrate 110, and the first electrode layer 150 and the active layer 140 are partially overlapped and connected. By installing the first electrode layer 150 and the active layer 140 to overlap and connect, the transmission of the input signal on the array substrate 100 between the active layer 140 and the first electrode layer 150 can be realized, and further the normal use of the array substrate 100 can be realized.

[0032] The array substrate 100 includes a first insulating layer 160. The first insulating layer 160 is disposed on the side of the first electrode layer 150 away from the active layer 140, thereby isolating the first electrode layer 150 from the subsequent functional layers, preventing the first electrode layer 150 and the subsequent functional layers from directly overlapping and connecting to cause mutual interference, and further avoiding affecting the normal use of the array substrate 100.

[0033] Here, the first insulating layer 160 includes a passivation layer 162 and a planarization layer 163 that are stacked and installed. The passivation layer 162 mainly functions as insulation. When forming the first electrode layer 150, since a patterning process needs to be performed on the first electrode layer 150, the flatness of the surface after forming the passivation layer 162 becomes low. By forming an additional planarization layer 163 on the passivation layer 162, it helps to improve the flatness of the entire surface, thereby facilitating the manufacturing of subsequent film layers and ensuring the structural stability of the entire array substrate 100.

[0034] The array substrate 100 further includes a second electrode layer 170. The second electrode layer 170 is installed on the side of the first insulating layer 160 away from the first electrode layer 150, and the orthographic projection of the second electrode layer 170 on the base substrate 110 at least partially covers the orthographic projection of the active layer 140 on the base substrate 110. The sum of the orthographic projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110, that is, when the first electrode layer 150 and the active layer 140 are overlapped and connected, it partially covers the active layer 140. The second electrode layer 170 is installed such that its orthographic projection on the base substrate 110 at least partially covers the orthographic projection of the active layer 140 on the base substrate 110, and the sum of the orthographic projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110. By doing so, the first electrode layer 150 and the second electrode layer 170 can protect the active layer 140, avoid the influence of external light on the active layer 140, and thereby ensure the stability of the array substrate 100.

[0035] In the embodiment of the present application, the array substrate 100 includes a base substrate 110, an active layer 140, a first electrode layer 150, a first insulating layer 160, and a second electrode layer 170 that are sequentially arranged. The first electrode layer 150 and the active layer 140 are partially overlapped and connected. The orthographic projection of the second electrode layer 170 on the base substrate 110 at least partially covers the orthographic projection of the active layer 140 on the base substrate 110. The sum of the orthographic projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110. The present application is arranged such that the orthographic projection of the second electrode layer 170 on the base substrate 110 at least partially covers the orthographic projection of the active layer 140 on the base substrate 110, and the sum of the orthographic projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110, so that the first electrode layer 150 and the second electrode layer 170 can jointly exert a protective effect on the active layer 140, avoid the influence of external light on the active layer 140, and thereby ensure the stability of the array substrate 100.

[0036] Preferably, the orthographic projection of the second electrode layer 170 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110, that is, when forming the second electrode layer 170 and performing a patterning process on the second electrode layer 170, the orthographic projection of the portion of the second electrode layer 170 corresponding to the active layer 140 on the base substrate 110 can directly cover the orthographic projection of the active layer 140 on the base substrate 110. Thereby, it is not necessary to consider the light-shielding area of the first electrode layer 150 with respect to the active layer 140, and the second electrode layer 170 itself can realize light shielding with respect to the active layer 140, which helps to simplify the patterning design of the second electrode layer 170.

[0037] In other embodiments, when forming the second electrode layer 170 and performing a patterning process on the second electrode layer 170, the area of the active layer 140 and the light-shielding area of the first electrode layer 150 with respect to the active layer 140 may be associated such that the orthographic projection of the portion of the second electrode layer 170 corresponding to the active layer 140 on the base substrate 110 covers only the portion of the active layer 140 that is not shielded by the first electrode layer 150. That is, the light-shielding area of the second electrode layer 170 with respect to the active layer 140 and the light-shielding area of the first electrode layer 150 are equal to the area of the orthographic projection of the active layer 140 on the base substrate 110, thereby maximizing the use of the light-shielding effects of the first electrode layer 150 and the second electrode layer 170, further saving the use of the second electrode layer 170, reducing the weight of the entire array substrate 100, and achieving a lightweight design of the array substrate 100.

[0038] Here, the specific design form of the second electrode layer 170 can be adjusted according to actual design requirements, ensuring that the installation of the first electrode layer 150 and the second electrode layer 170 can achieve light shielding for the active layer 140 and avoiding the influence of external light on the active layer 140, thereby ensuring the stability of the array substrate 100. It is not particularly limited here.

[0039] In some embodiments, as shown in FIG. 1, the first electrode layer 150 includes a first electrode 151. The first electrode 151 overlaps and is connected to one end of the active layer 140. A first opening 161 is formed in the first insulating layer 160. The first opening 161 exposes the other end of the active layer 140. The second electrode layer 170 includes a second electrode 171. The second electrode 171 overlaps and is connected to the other end of the active layer 140 through the first opening 161. That is, the first electrode 151 and the second electrode 171 are components of the thin film transistor, and the first electrode 151 and the second electrode 171 overlap and are connected to both ends of the active layer 140 respectively, so that charge carriers flow between the first electrode 151 and the second electrode 171 through the conductive trench in the active layer 140, thereby realizing the normal use of the array substrate 100. At the same time, the second electrode 171 can further block light from the active layer 140, thereby avoiding the influence of external light on the active layer 140, and ensuring the stability of the array substrate 100.

[0040] Here, the first electrode 151 is the drain, and the second electrode 171 is the source, or the first electrode 151 is the source, and the second electrode 171 is the drain. The definitions of the source and the drain can be adjusted according to actual design requirements and are not particularly limited herein. By controlling the conduction or interruption between the source and the drain, the control of the conduction or interruption of the thin film transistor can be realized.

[0041] In some other embodiments, as shown in FIG. 3, the first electrode layer 150 includes a source 152 and a drain 153 that overlap and are connected to the active layer 140. The second electrode layer 170 includes a light-shielding electrode 172. The orthographic projection of the light-shielding electrode 172 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110. That is, the first electrode layer 150 simultaneously forms the source 152 and the drain 153 of the thin-film transistor. The portion of the second electrode layer 170 corresponding to the active layer 140 only serves to shield light, thereby avoiding the influence of external light on the active layer 140 and ensuring the stability of the array substrate 100. By such an installation method of the structure, the use of the thin-film transistor and the light-shielding electrode 172 become independent of each other, avoiding the interference of the light-shielding electrode 172 on the use of the thin-film transistor, and thereby ensuring the stability during the use of the array substrate 100.

[0042] It should be noted that the material of the second electrode layer 170 is a non-translucent conductive material, thereby simultaneously satisfying the light-shielding effect of the second electrode layer 170 on the active layer 140 and the purpose of overlapping and connecting the corresponding second electrode 171 and the active layer 140 in the embodiments shown in FIGS. 1 and 2, and realizing the transmission of control signals in the array substrate 100.

[0043] Preferably, the array substrate 100 includes a gate layer 120. The gate layer 120 is disposed between the base substrate 110 and the active layer 140. The gate layer 120 includes a gate 121 disposed corresponding to the active layer 140, and the orthographic projection of the gate 121 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110. Here, as a component of the thin-film transistor, when a control signal is input to the gate 121, sensitive charges are generated in the active layer 140 to form a conductive trench, thereby realizing conduction between the source and the drain in the thin-film transistor. By arranging the orthographic projection of the gate 121 on the base substrate 110 to cover the orthographic projection of the active layer 140 on the base substrate 110, the gate 121 can simultaneously shield the side facing the base substrate 110 of the active layer 140, thereby realizing light shielding on both sides of the active layer 140, further avoiding the influence of external light on the active layer 140, and ensuring the stability of the array substrate 100.

[0044] The array substrate 100 further includes a second insulating layer 130. The second insulating layer 130 is disposed between the gate layer 120 and the active layer 140, and the second insulating layer 130 covers the gate layer 120 to isolate the gate layer 120 from the active layer 140, avoiding interference between the gate layer 120 and the active layer 140, thereby ensuring the normal operation of the thin-film transistor.

[0045] Preferably, the array substrate 100 further includes a third insulating layer 180 and a pixel electrode layer 190. The third insulating layer 180 is disposed on the side away from the first insulating layer 160 of the second electrode layer 170, and the pixel electrode layer 190 is disposed on the side away from the second electrode layer 170 of the third insulating layer 180. The third insulating layer 180 is used to isolate the second electrode layer 170 from the pixel electrode layer 190 to avoid mutual interference between the pixel electrode layer 190 and the second electrode layer 170, thereby ensuring the normal use of the array substrate 100.

[0046] In some embodiments, as shown in FIG. 1, a second opening 181 is formed in the third insulating layer 180. The second opening 181 penetrates the third insulating layer 180 and the first insulating layer 160 along the thickness direction of the array substrate 100, exposes the first electrode 151. The pixel electrode layer 190 includes a pixel electrode 191, and the pixel electrode 191 is electrically connected to the first electrode 151 through the second opening 181. The first electrode 151, as part of the thin film transistor, can realize the electrical connection between the pixel electrode 191 and the thin film transistor by electrically connecting the pixel electrode 191 and the first electrode 151. During the use of the array substrate 100, by controlling the conduction and cutoff of the thin film transistor, the conduction status of the signal on the pixel electrode 191 can be controlled, and further the control of the light emission mode of the light-emitting pixel can be realized, thereby satisfying various display requirements.

[0047] In some other embodiments, as shown in FIG. 2, a third opening 182 is formed in the third insulating layer 180. The third opening 182 exposes the second electrode 171. The pixel electrode layer 190 includes a pixel electrode 191, and the pixel electrode 191 is electrically connected to the second electrode 171 through the third opening 182. The second electrode 171, as part of the thin film transistor, can realize the electrical connection between the pixel electrode 191 and the thin film transistor by electrically connecting the pixel electrode 191 and the second electrode 171. During the use of the array substrate 100, by controlling the conduction and cutoff of the thin film transistor, the conduction status of the signal on the pixel electrode 191 can be controlled, and further the control of the light emission mode of the light-emitting pixel can be realized, thereby satisfying various display requirements.

[0048] During the use of the array substrate 100, the pixel electrode 191 is electrically connected to the drain of the thin film transistor. When the pixel electrode 191 is electrically connected to the first electrode 151, the first electrode 151 is the drain. When the pixel electrode 191 is electrically connected to the second electrode 171, the second electrode 171 is the drain.

[0049] Preferably, the second electrode layer 170 further includes a common electrode 173, that is, when forming the second electrode layer 170 and performing a patterning process on the second electrode layer 170, the second electrode 171 and the common electrode 173 can be formed simultaneously, or the light-shielding electrode 172 and the common electrode 173 can be formed simultaneously, thereby saving the process of manufacturing the photomask of the common electrode 173 alone, further simplifying the process steps of the array substrate 100, and reducing the production cost.

[0050] The pixel electrode layer 190 further includes a connection electrode 192, that is, when forming the pixel electrode layer 190 and performing a patterning process on the pixel electrode layer 190, the pixel electrode 191 and the connection electrode 192 can be formed simultaneously, thereby saving the process of manufacturing the photomask of the connection electrode 192 alone, further simplifying the process steps of the array substrate 100, and reducing the production cost.

[0051] Here, a fourth opening 183 is formed at a position corresponding to the common electrode 173 on the third insulating layer 180, and the connection electrode 192 is electrically connected to the common electrode 173 through the fourth opening 183. In addition, a common electrode line (not shown) is further installed on the array substrate 100, and the common electrode line can be installed in the same layer as the gate 121, that is, when forming the gate layer 120 and performing a patterning process on the gate layer 120, the gate 121 and the common electrode line can be formed simultaneously, thereby simplifying the process steps of the array substrate 100.

[0052] In addition to being electrically connected to the common electrode 173, the connection electrode 192 is further electrically connected to the common electrode line simultaneously, that is, during the use of the array substrate 100, a corresponding control signal is input on the common electrode line, and the control signal is transmitted to the common electrode 173 through the connection electrode 192, thereby realizing the control of the light-emitting mode of the corresponding light-emitting pixel and meeting various display requirements.

[0053] Next, the embodiments of the present application provide a display panel, which includes an array substrate. For the specific structure of the array substrate, reference may be made to the above embodiments. Since this display panel adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and the description thereof is omitted here.

[0054] As shown in FIG. 9, the display panel 10 includes an array substrate 100, a light-emitting device 200, and a packaging assembly 300. Here, the light-emitting device 200 is installed on the array substrate 100, and the array substrate 100 is electrically connected to the light-emitting device 200 to control the light-emitting mode of the light-emitting device 200, thereby controlling the display mode of the entire display panel 10. The packaging assembly 300 is installed on the light-emitting device 200 to protect the internal structures of the light-emitting device 200 and the array substrate 100, and avoid external moisture or oxygen from entering and eroding the internal structures of the light-emitting device 200 or the array substrate 100, thereby guaranteeing the overall performance and display effect of the display panel 10.

[0055] It should be noted that the application scope of the display panel 10 in the embodiments of the present application is very wide, including various display devices such as televisions, computers, mobile phones, foldable and rollable displays, and lighting, as well as wearable devices such as smart bracelets and smart watches, all of which are included within the scope of the application fields to which the display panel 10 in the embodiments of the present application belongs.

[0056] Finally, the embodiments of the present application further provide a method for manufacturing an array substrate. As shown in FIG. 4, the method for manufacturing an array substrate mainly includes the following steps.

[0057] S100, provide a base substrate 110.

[0058] When manufacturing the array substrate 100, first, a base substrate 110 is provided. It is necessary to clean the base substrate 110 to remove the dirt on the base substrate 110, thereby facilitating the manufacturing of subsequent film layers. The base substrate 110 is used as a support structure for the array substrate 100 to support other functional structure layers of the array substrate 100 and ensure the structural stability of the array substrate 100. Here, the base substrate 110 may be a glass substrate or other types of materials, and is not particularly limited here.

[0059] S200. Form an active layer 140 on the base substrate 110.

[0060] After the base substrate 110 is prepared, a layer of the active layer 140 is deposited on the base substrate 110, and a patterning process is performed on the active layer 140. The active layer 140 is used as an important component of the thin film transistor in the array substrate 100 to form a conductive trench. By controlling the conductive trench in the active layer 140, the conduction state of the thin film transistor can be controlled.

[0061] S300. Sequentially form a first electrode layer 150, a first insulating layer 160, and a second electrode layer 170 on the side of the active layer 140 away from the base substrate 110. The first electrode layer 150 and the active layer 140 are partially overlapped and connected, and the orthographic projection of the second electrode layer 170 on the base substrate 110 at least partially covers the orthographic projection of the active layer 140 on the base substrate 110, so that the sum of the orthographic projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110.

[0062] After the active layer 140 is manufactured, a single-layer first electrode layer 150, a first insulating layer 160, and a second electrode layer 170 are sequentially deposited on the side of the active layer 140 away from the base substrate 110. By performing patterning processes on the first electrode layer 150 and the second electrode layer 170 respectively, the first electrode layer 150 and the active layer 140 are partially overlapped and connected, and the orthographic projection of the second electrode layer 170 on the base substrate 110 at least partially covers the orthographic projection of the active layer 140 on the base substrate 110, and the sum of the orthographic projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110.

[0063] Here, by arranging the first electrode layer 150 and the active layer 140 to be overlapped and connected, the transmission of the input signal on the array substrate 100 between the active layer 140 and the first electrode layer 150 can be realized, and further the normal use of the array substrate 100 can be realized. The first insulating layer 160 is used to isolate the first electrode layer 150 and the second electrode layer 170, so as to avoid the first electrode layer 150 and the second electrode layer 170 directly overlapping and connecting to cause mutual interference and further affecting the normal use of the array substrate 100. The first insulating layer 160 includes a passivation layer 162 and a planarization layer 163 which are stacked. The passivation layer 162 mainly functions as insulation. When forming the first electrode layer 150, since it is necessary to perform a patterning process on the first electrode layer 150, the flatness of the surface after forming the passivation layer 162 becomes low. By forming an additional planarization layer 163 on the passivation layer 162, it helps to improve the flatness of the entire surface, thereby facilitating the manufacturing of subsequent film layers and ensuring the structural stability of the entire array substrate 100.

[0064] Note that when the first electrode layer 150 is connected in overlap with the active layer 140, it partially covers the active layer 140. Due to the combined action of the first electrode layer 150 and the second electrode layer 170, the orthographic projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 jointly cover the orthographic projection of the active layer 140 on the base substrate 110, protecting the active layer 140 and avoiding the influence of external light on the active layer 140, thereby ensuring the stability of the array substrate 100.

[0065] In some embodiments, as shown in FIG. 5, step S300 mainly includes the following content.

[0066] S310a: Form the first electrode layer 150 on the side of the active layer 140 away from the base substrate 110, and perform a patterning process on the first electrode layer 150 to form a first electrode 151 that is connected in overlap with one end of the active layer 140.

[0067] S320a: Form the first insulating layer 160 on the side of the first electrode layer 150 away from the active layer 140, and form a first aperture 161 in the first insulating layer 160 to expose the other end of the active layer 140.

[0068] S330a: Form the second electrode layer 170 on the side of the first insulating layer 160 away from the first electrode layer 150, and perform a patterning process on the second electrode layer 170 to form a second electrode 171 that is connected in overlap with the other end of the active layer 140, such that the orthographic projection of the second electrode 171 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110.

[0069] As shown in FIG. 6, in the process of manufacturing the array substrate 100, the first electrode layer 150 is patterned to form the first electrode 151, the second electrode layer 170 is patterned to form the second electrode 171, the first electrode 151 and the second electrode 171 are used as components of the thin film transistor, and the first electrode 151 and the second electrode 171 are respectively overlapped and connected to both ends of the active layer 140, so that charge carriers flow between the first electrode 151 and the second electrode 171 through the conductive trench in the active layer 140, thereby realizing the normal use of the array substrate 100. At the same time, by arranging the second electrode 171 so that the orthographic projection on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110, the second electrode 171 can further shield the active layer 140 from light, avoiding the influence of external light on the active layer 140, thereby ensuring the stability of the array substrate 100.

[0070] Here, the first electrode 151 is the drain, the second electrode 171 is the source, or the first electrode 151 is the source and the second electrode 171 is the drain. The definitions of the source and the drain can be adjusted according to actual design requirements and are not particularly limited herein. By controlling the conduction or interruption between the source and the drain, the control of the conduction or interruption of the thin film transistor can be realized.

[0071] In some other embodiments, as shown in FIG. 7, step S300 mainly includes the following.

[0072] S310b. Form the first electrode layer 150 on the side of the active layer 140 away from the base substrate 110, and pattern the first electrode layer 150 to form the source 152 and the drain 153 that are overlapped and connected to the active layer 140.

[0073] S320b. Form the first insulating layer 160 on the side of the first electrode layer 150 away from the active layer 140.

[0074] Form a second electrode layer 170 on the side of the first electrode layer 150 of the first insulating layer 160 away from the first electrode layer 150, perform a patterning process on the second electrode layer 170 to form a light-shielding electrode 172, and ensure that the orthographic projection of the light-shielding electrode 172 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110.

[0075] As shown in FIG. 8, in the process of manufacturing the array substrate 100, a source 152 and a drain 153 that overlap and are connected to the active layer 140 are formed by performing a patterning process on the first electrode layer 150, and a light-shielding electrode 172 is formed by performing a patterning process on the second electrode layer 170. As a result, the first electrode layer 150 simultaneously forms the source 152 and the drain 153 of the thin-film transistor, and the portion of the second electrode layer 170 corresponding to the active layer 140 only serves as a light-shielding function to avoid the influence of external light on the active layer 140, thereby ensuring the stability of the array substrate 100. By such an installation method of the structure, the use of the thin-film transistor and the light-shielding electrode 172 become independent of each other, avoiding the interference of the light-shielding electrode 172 on the use of the thin-film transistor, and thereby ensuring the stability during the use of the array substrate 100.

[0076] Preferably, in the process of manufacturing the array substrate 100, before manufacturing the active layer 140, first deposit a gate layer 120 and a second insulating layer 130 on the base substrate 110 in sequence, perform a patterning process on the gate layer 120 to form a gate 121 corresponding to the active layer 140, and ensure that the orthographic projection of the gate 121 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110.

[0077] By installing the gate 121 such that the orthographic projection of the gate 121 on the base substrate 110 covers the orthographic projection of the active layer 140 on the base substrate 110, the gate 121 can simultaneously shield the side facing the base substrate 110 of the active layer 140, thereby realizing light shielding on both sides of the active layer 140, further avoiding the influence of external light on the active layer 140, and ensuring the stability of the array substrate 100. The second insulating layer 130 is installed between the gate layer 120 and the active layer 140, and the second insulating layer 130 covers the gate layer 120 to isolate the gate layer 120 from the active layer 140 and avoid interference between the gate layer 120 and the active layer 140, thereby ensuring the normal operation of the thin film transistor.

[0078] Preferably, after the second electrode layer 170 is manufactured, the manufacturing method of the array substrate 100 further includes the following. On the side of the second electrode layer 170 away from the first insulating layer 160, a layer of the third insulating layer 180 and the pixel electrode layer 190 are sequentially deposited. In the third insulating layer 180, a second opening 181 for exposing the first electrode 151 is opened, and the pixel electrode layer 190 is patterned to form a pixel electrode 191 connected to the first electrode 151.

[0079] Here, the third insulating layer 180 is used to isolate the second electrode layer 170 from the pixel electrode layer 190 and avoid mutual interference between the pixel electrode layer 190 and the second electrode layer 170, thereby ensuring the normal use of the array substrate 100. By electrically connecting the pixel electrode 191 and the first electrode 151, the electrical connection between the pixel electrode 191 and the thin film transistor can be realized. During the use of the array substrate 100, by controlling the conduction and cutoff of the thin film transistor, the conduction status of the signal on the pixel electrode 191 can be controlled, and further the control of the light emission mode of the light emitting pixel can be realized, thereby meeting various display requirements.

[0080] When patterning the second electrode layer 170, the second electrode 171 and the common electrode 173 can be formed simultaneously, or the light-shielding electrode 172 and the common electrode 173 can be formed simultaneously, thereby omitting the process of manufacturing the photomask of the common electrode 173 alone, further simplifying the manufacturing process of the array substrate 100, and reducing the production cost.

[0081] As described above, the array substrate, the display panel, and the method for manufacturing the array substrate according to the embodiments of the present application have been introduced in detail. In this specification, specific examples are used to describe the principle and embodiments of the present application. However, the description of the above embodiments is only for understanding the method of the present application and its core idea. Those skilled in the art should understand that based on the idea of the present application, it is possible to change the specific embodiments and the scope of application. In short, the content of this specification is not intended to limit the present application.

Claims

1. An array substrate, comprising: a base substrate; an active layer disposed on the base substrate; a first electrode layer disposed on a side of the active layer away from the base substrate, wherein the first electrode layer and the active layer are partially overlapped and connected; a first insulating layer disposed on a side of the first electrode layer away from the active layer; a second electrode layer disposed on a side of the first insulating layer away from the first electrode layer, wherein a front projection of the second electrode layer on the base substrate at least partially covers a front projection of the active layer on the base substrate, and a sum of front projections of the first electrode layer and the second electrode layer on the base substrate covers the front projection of the active layer on the base substrate.

2. The array substrate according to claim 1, wherein a front projection of the second electrode layer on the base substrate covers a front projection of the active layer on the base substrate.

3. The array substrate according to claim 1, wherein a sum of a light-shielding area of the second electrode layer with respect to the active layer and a light-shielding area of the first electrode layer with respect to the active layer is equal to an area of a front projection of the active layer on the base substrate.

4. The array substrate according to claim 1, wherein the first electrode layer includes a first electrode, the first electrode is overlapped and connected with one end of the active layer, a first opening is formed in the first insulating layer, the first opening exposes the other end of the active layer, the second electrode layer includes a second electrode, and the second electrode is overlapped and connected with the other end of the active layer through the first opening.

5. The array substrate according to claim 4, wherein the first electrode is a drain and the second electrode is a source.

6. The array substrate according to claim 4, wherein the first electrode is a source and the second electrode is a drain.

7. The array substrate according to claim 1, wherein the first electrode layer includes a source and a drain overlapped and connected with the active layer, the second electrode layer includes a light-shielding electrode, and a front projection of the light-shielding electrode on the base substrate covers a front projection of the active layer on the base substrate.

8. The array substrate further comprises: A gate layer disposed between the base substrate and the active layer, the gate layer including a gate disposed corresponding to the active layer, a projection of the gate on the base substrate covering a projection of the active layer on the base substrate, and A second insulating layer disposed between the gate layer and the active layer, the second insulating layer further including a second insulating layer covering the gate layer, the array substrate according to claim 1.

9. The array substrate is A third insulating layer disposed on a side of the second electrode layer away from the first insulating layer, a second opening being formed in the third insulating layer, the second opening penetrating the third insulating layer and the first insulating layer along a thickness direction of the array substrate, the second opening exposing the first electrode, and A pixel electrode layer disposed on a side of the third insulating layer away from the second electrode layer, the pixel electrode layer including a pixel electrode, the pixel electrode being electrically connected to the first electrode through the second opening, the array substrate according to claim 4.

10. The array substrate is A third insulating layer disposed on a side of the second electrode layer away from the first insulating layer, a third opening being formed in the third insulating layer, the third opening exposing the second electrode, and A pixel electrode layer disposed on a side of the third insulating layer away from the second electrode layer, the pixel electrode layer including a pixel electrode, the pixel electrode being electrically connected to the second electrode through the third opening, the array substrate according to claim 4.

11. The second electrode layer further includes a common electrode, the pixel electrode layer further includes a connection electrode, a fourth opening being formed at a position on the third insulating layer corresponding to the common electrode, the connection electrode being electrically connected to the common electrode through the fourth opening, the array substrate according to claim 9.

12. The second electrode layer further includes a common electrode, the pixel electrode layer further includes a connection electrode, a fourth opening being formed at a position on the third insulating layer corresponding to the common electrode, the connection electrode being electrically connected to the common electrode through the fourth opening, the array substrate according to claim 10.

13. The material of the second electrode layer is a non-translucent conductive material, the array substrate according to claim 1.

14. A display panel including the array substrate according to Claim 1.

15. An array substrate, comprising: a base substrate; an active layer disposed on the base substrate; a first electrode layer disposed on a side of the active layer away from the base substrate, wherein the first electrode layer and the active layer are partially overlapped and connected; a first insulating layer disposed on a side of the first electrode layer away from the active layer; a second electrode layer disposed on a side of the first insulating layer away from the first electrode layer, wherein a positive projection of the second electrode layer on the base substrate covers a positive projection of the active layer on the base substrate. Here, the first electrode layer includes a first electrode, the first electrode is overlapped and connected with one end of the active layer, a first opening is formed in the first insulating layer, the first opening exposes the other end of the active layer, the second electrode layer includes a second electrode, and the second electrode is overlapped and connected with the other end of the active layer through the first opening.

16. The array substrate according to Claim 15, wherein the first electrode is a drain and the second electrode is a source.

17. The array substrate according to Claim 15, wherein the first electrode is a source and the second electrode is a drain.

18. The array substrate further comprises: a gate layer disposed between the base substrate and the active layer, the gate layer includes a gate disposed corresponding to the active layer, and a positive projection of the gate on the base substrate covers a positive projection of the active layer on the base substrate; a second insulating layer disposed between the gate layer and the active layer, the second insulating layer covers the gate layer.

19. The array substrate further comprises: a third insulating layer disposed on a side of the second electrode layer away from the first insulating layer, a second opening is formed in the third insulating layer, the second opening penetrates the third insulating layer and the first insulating layer along a thickness direction of the array substrate, and the second opening exposes the first electrode. A pixel electrode layer disposed on a side of the third insulating layer away from the second electrode layer, the pixel electrode layer including a pixel electrode, the pixel electrode being electrically connected to the first electrode through the second opening, and further including the pixel electrode layer according to claim 15.

20. The array substrate is A third insulating layer disposed on a side of the second electrode layer away from the first insulating layer, a third opening being formed in the third insulating layer, the third opening exposing the second electrode, and the third insulating layer A pixel electrode layer disposed on a side of the third insulating layer away from the second electrode layer, the pixel electrode layer including a pixel electrode, the pixel electrode being electrically connected to the second electrode through the third opening, and further including the pixel electrode layer according to claim 15.

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