Substrate with vias and related manufacturing method

Abstract

The present invention relates to a substrate comprising a first layer (30) based on a semiconductive material and a second layer (31) on top of the first layer. The substrate (3) comprises a plurality of embedded hollow vias (32) extending from the second layer (31) over a part of the first layer (30). The present invention further relates to a method for manufacturing the substrate and a method for manufacturing a microelectronic device using the substrate. The substrate comprises hollow vias for later use, and the manufacture of the vias is facilitated.

Description

Technical Field

[0001] The present invention relates to the field of substrates intended for manufacturing electronic devices, and more particularly, microelectronic devices. These substrates ultimately enable electrical and mechanical connections of the electrical components. The present invention has advantageous applications, although not limited to, when manufacturing microelectronic devices, for example, microelectronic devices for computing applications.

Background Art

[0002] For example, as shown in FIG. 1, in order to be able to interconnect these components on the front surface 3a and the back surface 3b of the substrate 3 to obtain the microelectronic device 4, there is an interest in manufacturing an assembly of components 4' on a substrate 3 provided with vias 32 for forming through contacts. Thus, the component 4' can be connected to a printed circuit, for example, through the casing 5. These substrates 3 can specifically be, for example, semiconductive substrates of the semiconductor-on-insulator type, specifically the silicon-on-insulator (SOI) type.

[0003] Etching and filling of these vias (generally called TSVs (Through-Silicon-Vias)) with a conductive or semiconductive material are very specific process steps and are often performed in the premises of the assembler rather than the manufacturer (generally called OSAT (Outsourced Semi-conductor Assembly and Test)).

[0004] Two types of vias are distinguished according to the time of their manufacture in the production line of microelectronic devices. The so-called "TSV middle" vias are generally manufactured in the middle of the process after the component pattern has been manufactured during the front-end-of-line (FEOL), but before the metal layers of the back-end-of-line (BEOL) are deposited. This generally requires the transfer of the substrate and components from the fabricator to the assembler to manufacture the vias, then a return to the fabricator for the BEOL steps, and finally a transfer to the assembler to complete the process. These manufacturing steps are very limited in terms of planarity and contamination, which are highly incompatible with the back-and-forth movement between the fabricator and the assembler.

[0005] "TSV last" vias can be manufactured at the end of the process after the FEOL and BEOL steps. This generally requires only a single transfer from the fabricator to the assembler after the BEOL steps. However, the via shapes that can be achieved thereby are limited. Specifically, the achievable via density is limited. This is particularly limiting for certain applications, such as for calculations.

[0006] Therefore, there is a need to obtain these structures without relying on other manufacturing steps of the line.

Summary of the Invention

Problems to be Solved by the Invention

[0007] Therefore, an object of the present invention is to facilitate the manufacture of vias in microelectronic devices.

[0008] Other objects, features, and advantages of the present invention will become apparent from the following description and the accompanying drawings. It is understood that other advantages may be incorporated.

Means for Solving the Problems

[0009] To achieve this object, according to an embodiment, - a first base layer, preferably made of a semiconductive material, and - a second layer on top of the first layer are provided with a substrate.

[0010] Advantageously, the substrate comprises a plurality of embedded hollow vias extending from the second layer over a portion of the first layer, each via being defined by a side wall, a bottom wall, and an upper wall opposite the bottom wall.

[0011] Thus, the substrate comprises non-open hollow vias for subsequent filling with a conductive or semiconductive member. This makes it possible to provide hollow vias independently of other steps in manufacturing microelectronic devices. A substrate with embedded hollow vias can be used, for example, for depositing layers such as FEOL or BEOL, whereby the hollow vias can be opened to produce a desired conductive or semiconductive member, such as an electrical interconnection. Furthermore, since the vias are manufactured in advance, the shape of the vias is not limited.

[0012] This has several advantages. These hollow vias are compatible with FEOL steps performed at high temperatures, in contrast to current solutions implementing metallized vias made of, for example, copper or tungsten.

[0013] Therefore, it is understood that manufacturing the vias is facilitated, specifically with respect to other steps in manufacturing microelectronic devices. Manufacturing vias filled with a conductive or semiconductive member is made more specifically easier.

[0014] According to an example, at least the bottom wall and the side walls are made of a dielectric material. Due to the walls of the dielectric material being formed in advance, these walls enable good insulation of the vias once they are filled with a conductive or semiconductive material, while being compatible with FEOL steps, or steps of temporarily mounting a support. This is particularly advantageous when the aspect ratio of the vias is 10 or more, as it is easier to fabricate these walls before manufacturing the microelectronic device.

[0015] A second aspect is a method for manufacturing a substrate according to the first aspect, comprising: - providing a support sub-substrate based on a semiconductive material, preferably made of a semiconductive material and having an exposed surface; - etching a plurality of vias such that the vias extend from the exposed surface across a portion of the first layer, each via being defined by side walls and a bottom wall; - providing a donor sub-substrate comprising a surface layer having an exposed surface; - assembling the support sub-substrate and the donor sub-substrate by their exposed surfaces such that each via is defined by a side wall, a bottom wall, and an upper wall opposite the bottom wall; and relates to a method including the above steps.

[0016] Thus, this method enables the production of embedded hollow vias in a substrate. This method has the effects and advantages described with respect to the first aspect.

[0017] A third aspect is a method for manufacturing a microelectronic device, comprising: - providing a substrate according to the first aspect, or a substrate manufactured by the method according to the second aspect, the substrate having a front exposed surface and a rear exposed surface; - Forming at least one layer portion of the device on the pre-exposed surface of the substrate by deposition of said portion and / or etching the pre-exposed surface of the substrate configured to form said portion; - Etching in at least one via with the post-exposed surface of the substrate, wherein the wall of at least one of the upper and bottom walls of the at least one via is etched to open into the via to form a cavity and then etching is continued until reaching at least one layer portion of the device; - Depositing a conductive or semiconductive member to fill the cavity A method comprising.

[0018] Accordingly, the provided substrate enables the formation of microelectronic devices, thereby enabling the opening of embedded hollow vias to fabricate a desired conductive or semiconductive member. This can be done in an easy manner related to current solutions.

[0019] The objects, goals, features and advantages of the present invention are best clarified from the detailed description of the embodiments of the present invention shown by the following attached drawings.

Brief Description of the Drawings

[0020]

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[0021] The drawings are provided by way of example and not limitation of the invention. The drawings constitute schematic diagrams of the principles intended to facilitate understanding of the invention and are not necessarily to scale for practical applications. Specifically, the relative dimensions of the layers, vias, and sub-substrate and substrate of the walls do not represent reality.

[0022] Before beginning a detailed examination of embodiments of the present invention, optional features that may be used optionally in connection with or as an alternative are described below.

[0023] According to an example, the second layer is a base layer, preferably made of a material selected from a dielectric material, such as an oxide, a semiconductive material, or a piezoelectric material.

[0024] According to an example, the second layer is an embedded dielectric material layer, such as an oxide, on which a third layer based on a material selected from a semiconductive material or a piezoelectric material is located. The substrate can be of the "semiconductor on insulator" type, for example, of the "silicon on insulator" type.

[0025] According to an example, all cross-sectional dimensions of each via are substantially 30 μm or less.

[0026] According to an example, each via has at least one cross-sectional dimension, such as a diameter, substantially between 1 μm and 30 μm. According to an example, all cross-sectional dimensions of each via are between 1 μm and 30 μm.

[0027] According to an example, at least some of the vias have a shape factor of 10 or more of the longer dimension oriented along the dimensions in the thickness of the first and second layers. This shape factor is specifically adapted to obtain a large via density on the substrate, in particular in combination with the pitch value range described above.

[0028] According to an example, the plurality of vias comprises at least three vias, preferably at least five vias.

[0029] According to an example, the plurality of vias forms a periodic matrix. Thus, the substrate comprises a hollow via matrix that can be selected to achieve the desired interconnections. Therefore, an overall substrate comprising these vias enables, specifically by being adaptable to different microelectronic devices, to facilitate the manufacture of the vias and of conductive or semiconductive members.

[0030] According to an example, the vias are separated in pairs by a constant pitch along at least one direction of the main extension planes of the first layer and the second layer.

[0031] According to an example, the pitch is substantially between 50 μm and 300 μm, preferably between 100 μm and 200 μm. This pitch enables a better density of the hollow vias in the substrate. Thus, a greater interconnect density is possible. Further, the compatibility of the substrate to different microelectronic devices is improved.

[0032] According to an example, the vias are parallel to each other.

[0033] According to an example, the vias have a longitudinal dimension that is oriented along the dimension in the thickness of the first layer and the second layer.

[0034] According to an example, the vias extend along a direction parallel to the perpendicular to the main extension planes of the first layer and the second layer.

[0035] According to an example, the vias are cylindrical. Thus, the bottom wall of the vias is more homogeneous than a non-cylindrical shape, for example, a square where the corners become shallower than the center after etching of the vias. The cylindrical shape minimizes this effect. Further, the mechanical stress is smaller for cylindrical vias that do not have angular singularities. It is advantageous for the heat treatment during the manufacturing of the circuit.

[0036] According to an example, the second layer is on top of the first layer by being in direct contact with the first layer.

[0037] According to an example, and as is apparent from the figures attached to the present application, at least some of the vias, preferably each via, have a cross-section in a plane substantially parallel to the main extension planes of the first layer and the second layer, and the ratio of the maximum dimension to the minimum dimension of the cross-section is 3 or less, preferably 2 or less. Thus, the vias are absolutely distinguishable from other structures such as trenches.

[0038] According to an example, at least one via, preferably each via, is completely surrounded by a groove extending from a second layer over a portion of the first layer over at least a portion of the longitudinal dimension of the via. The grooves make it possible to improve the electrical insulation between the vias. Thus, the grooves are pre-fabricated and fabricated independently from other steps of manufacturing the microelectronic device. Thus, the grooves are compatible with FEOL steps performed at high temperatures. Furthermore, since the grooves are pre-fabricated, the shape of the grooves is not limited by other steps of manufacturing the microelectronic device.

[0039] According to an example, each groove is not filled with a solid material. Each groove is preferably filled with an electrically insulating gas atmosphere such as air, nitrogen, or argon, optionally at a pressure below ambient pressure.

[0040] According to an example, each groove is defined by a bottom wall, side walls, and an upper wall opposite the bottom wall. For at least one groove, preferably for each groove, at least a portion of the side walls and the bottom wall can be made of the same material as the material of the first layer. The insulation of the vias is actually sufficient thanks to the insulating atmosphere contained in the grooves. Alternatively, for at least one groove, preferably for each groove, at least a portion of the side walls and the bottom wall can be made of a dielectric material such as the same dielectric material as the wall of the via. Thus, the electrical insulation of the vias can also be improved.

[0041] According to an example, the grooves are concentric with the vias. This specifically makes it possible to reduce the interference ability between the vias and the substrate and to increase the breakdown voltage.

[0042] According to an example, the grooves extend from the second layer to the first layer, preferably by plus or minus 5 μm, over a longitudinal dimension that is less than or equal to the longitudinal dimension of the via. Thus, the grooves surround the via over at least a portion, preferably substantially over the entire longitudinal dimension.

[0043] According to an example, the substrate further comprises markers configured to enable alignment of the substrate. This also makes it possible to facilitate the manufacture of microelectronic devices by facilitating alignment of the substrate, and specifically, also makes it possible to facilitate the manufacture of microelectronic devices in terms of performing photolithography steps necessary for FEOL and BEOL structures and thus via opening.

[0044] According to an example, the semiconducting material is selected from the group consisting of silicon Si, germanium Ge, SiGe, group III-V materials (e.g., GaN, InN, InGaAs, GaP, InP, InAs, AsGa, etc.), group II-VI materials, e.g., wide bandgap materials greater than 3 eV.

[0045] According to an example, the semiconducting material includes silicon and is preferably silicon.

[0046] According to an example, the piezoelectric material is lithium tantalate (LiTaO 3 ), lithium niobate (LiNbO 3 ), potassium sodium niobate (K X Na 1-X NbO 3 or KNN), barium titanate (BaTiO 3 ), quartz, lead zirconate titanate (PZT), a compound of magnesium lead and lead titanate niobate (PMN-PT), zinc oxide (ZnO), aluminum nitride (AlN), or aluminum scandium nitride (AlScN).

[0047] According to an example, the dielectric material is a semiconducting oxide and is preferably silica of chemical formula SiO 2 .

[0048] According to an example, following the etching of a plurality of vias, preferably before the assembly of the support sub-substrate and the donor sub-substrate, the method includes, for each via, forming a dielectric material at least on the bottom wall and the side walls. Thus, the hollow vias formed in the substrate have a dielectric layer at least on the bottom wall and the side walls of the vias before using the substrate in a method for manufacturing microelectronic devices.

[0049] According to an example, forming a dielectric material at least on the bottom wall and the side walls of at least a plurality of vias comprises - a thermal oxidation that oxidizes a first layer of semiconductive material at least on the bottom wall and the side walls, and / or - a deposition of a dielectric material at least on the bottom wall and the side walls and includes.

[0050] These techniques, and in particular clearly, thermal oxidation makes it possible to obtain a good adhesion of the dielectric material to the walls. The adhesion of the thermal oxidation makes it possible to obtain an oxide with a high density and a uniform thickness on the bottom wall and the side walls. Therefore, thermal oxidation is particularly advantageous in synergy with a high via form factor. Regarding deposition, thermal oxidation further makes it possible to smooth the etched via walls and suppress the presence of defects between the first layer of semiconductive material and the dielectric.

[0051] According to an example, when the bottom wall is made of a dielectric material, the bottom walls of the plurality of vias have a transverse dimension that is substantially between 50 nm and 600 nm, preferably substantially equal to 400 nm.

[0052] According to an example, when at least the bottom wall and the side walls are made of a dielectric material, the side walls of the plurality of vias have a transverse dimension that is substantially between 50 nm and 600 nm, preferably substantially equal to 400 nm.

[0053] According to an example, the surface layer of the donor sub-substrate is a layer based on a material selected from a dielectric material, such as an oxide, a semiconductive material, or a piezoelectric material, preferably a layer made of such a material.

[0054] According to an example, - The support sub-substrate is a dielectric material, for example, a surface layer based on an oxide, on the first layer (10), preferably further comprising a surface layer made of such a dielectric material, the surface layer having an exposed surface, and / or - The surface layer of the donor sub-substrate is a layer of a dielectric material, for example, a layer based on an oxide, on a layer based on a material selected from a semiconductive material or a piezoelectric material, preferably a layer made of such a dielectric material.

[0055] Therefore, it is understood that the embedded oxide layer of the substrate can come from the donor sub-substrate and / or the support sub-substrate.

[0056] According to an example, the surface layer of the donor substrate is based on one of a semiconductive material or a dielectric material, preferably made of one of a semiconductive material or a dielectric material. According to this, it is understood that the upper wall of the via, and optionally the upper wall of the groove, are based on a semiconductive material or a dielectric material, or made of a semiconductive material or a dielectric material, as the surface layer is based on a semiconductive material or a dielectric material.

[0057] According to an example, the etching of the plurality of vias is configured to form a periodic matrix. Therefore, the effects and advantages described with respect to the via matrix are obtained.

[0058] According to an example, the method for manufacturing a substrate further includes etching a groove that completely surrounds at least one via in at least a portion of the longitudinal dimension of the via, the groove extending from the surface layer to the first layer, before the assembly of the support sub-substrate and the donor sub-substrate. Therefore, the effects and advantages described with respect to the groove are obtained.

[0059] According to an example, the method includes forming a brittle region at the depth of the surface of the surface layer of the donor substrate and then separating the donor substrate in the brittle region.

[0060] According to an example, a method for manufacturing a microelectronic device includes, before etching by a back-exposed surface of a substrate, - applying a mask having an opening positioned vertically aligned with at least one via to be etched on the back-exposed surface of the substrate; and - etching a first layer to reach the wall of at least one via to be etched including selecting at least one via to be etched from among a plurality of vias.

[0061] Thus, it is possible to select the via to be etched from the existing vias.

[0062] Thus, the method can be adapted according to a desired microelectronic device configuration. This selection is particularly advantageous in synergistic effect with the feature that the vias form a via matrix.

[0063] According to an example, selecting at least one via to be etched includes applying a mask and then etching a first layer through the opening of the mask. Thus, potential embrittlement of the wall of the via to be etched is avoided. Thus, this etching etches the first layer on the right side of at least one via to be etched until it opens into at least one via to be etched.

[0064] According to an example, selecting at least one via to be etched includes etching a first layer to reach the wall of at least one via to be etched and then applying a mask. Thus, the sidewalls of the dielectric material can exist all along the longitudinal dimension of the cavity formed. It is not necessary to insulate a part of the cavity to complete the wall of the dielectric material of the via. The first layer is etched more clearly across all of its main extension plane.

[0065] According to an example, the deposition of a conductive or semiconductive member is configured to further cover at least a portion of the rear exposed surface of the substrate with a conductive or semiconductive layer.

[0066] According to an example, the method includes creating a pattern in a conductive or semiconductive rear layer.

[0067] According to an example, the method includes passivating the rear exposed surface of the substrate.

[0068] According to an example, a method for manufacturing a microelectronic device is - mounting a support on the front exposed surface of the substrate between forming at least one layer portion of the device and etching by the rear exposed surface of the substrate, - removing the support after depositing a conductive or semiconductive member to fill an electrical cavity and including.

[0069] Thus, the support makes it possible to facilitate the handling of the substrate.

[0070] By a microelectronic device, this means any type of device fabricated by microelectronic means. These devices specifically include not only devices with purely electronic purposes, microelectromechanical devices, or electromechanical devices, but also optical devices or optoelectronic devices. A microelectronic device can be intended to ensure electronic functions, optical functions, mechanical functions, etc. A microelectronic device can be an intermediate product that is only intended to fabricate other microelectronic devices. A microelectronic device can be a passive electrical interconnection structure.

[0071] It is clearly stated that within the scope of the present invention, the terms "on" or "above" do not necessarily mean "in contact with". Thus, for example, the deposition of a layer on another layer does not necessarily mean that the two layers are in direct contact with each other, but rather that one of the layers at least partially covers the other layer, either by being in direct contact with the other layer or by being separated from the other layer by a film, another layer, or other element.

[0072] Furthermore, a layer can consist of a plurality of sub-layers of the same or different materials.

[0073] An element "based on" material A, or an A-based element, means an element that contains only this material A, or an element that contains this material A and an optional other material.

[0074] In the following detailed description, terms such as "longitudinal" and "transverse" may be used. These terms must be interpreted with respect to the substrate or with respect to the dimensions in the thickness of the device. Thus, the longitudinal dimension, height, depth, or thickness of an element or layer means the dimension along the thickness of the substrate that supports the element or layer, or the substrate that contains the element or layer. The width, cross-sectional dimension, or transverse dimension means the dimension perpendicular to the thickness of the substrate.

[0075] Certain components of the substrate or device of the present invention can have an electrical function. Some are used for conductivity and, by conduction or equivalently, mean an element formed from at least one material having sufficient conductivity to perform the desired function in the application. On the contrary, other components are used for electrical insulation, and all materials having sufficient resistance to achieve this insulation are considered, specifically called dielectric or electrically insulating.

[0076] The term "dielectric" more precisely qualifies materials whose conductivity is low enough to serve as an insulator in a given application. In the present invention, the dielectric material preferably has a relative permittivity of less than 4.

[0077] By "direct bonding", this consists, for example, of the contact between those surfaces, achieved under ambient atmosphere at atmospheric temperature, to create an adhesion between relatively smooth surfaces (typically with a root mean square (RMS) of less than 5 Å), meaning a bond without adding an adhesive material (specifically of the adhesive or polymer type). -10 By "direct bonding", this consists, for example, of the contact between those surfaces, achieved under ambient atmosphere at atmospheric temperature, to create an adhesion between relatively smooth surfaces (typically with a root mean square (RMS) of less than 5 Å), meaning a bond without adding an adhesive material (specifically of the adhesive or polymer type).

[0078] According to an embodiment, the direct bonding of two substrates means that the bond is obtained by a chemical bond established between two contacting surfaces. These chemical bonds can be, for example, van der Waals bonds and / or, specifically, strong covalent chemical bonds when the bond is enhanced by plasma activation or when a strengthening heat treatment (typically 200 - 1200 °C over 1 hour) follows.

[0079] Direct bonding can be obtained without the need to apply a significant pressure to the structure to be assembled. Only some pressure may be applied to initiate the bonding. Thermal annealing may further be performed to strengthen the bond.

[0080] By a parameter "substantially equal to / greater than / smaller than" a given value, this means that this parameter is equal to / greater than / smaller than the given value within plus or minus 10%, and even plus or minus 5% of the given value.

[0081] Substrate 3 is described according to some examples of embodiments with reference to FIGS. 2A - 3C.

[0082] For example, as shown by FIG. 2A, the substrate 3 comprises a first layer 30 based on or made of a semiconductive material. According to an example, the semiconductive material includes silicon and is preferably silicon. It is noted that other semiconductive materials may be considered as described later. The first layer 30 has a thickness L that is, for example, substantially between 100 μm and 800 μm 30 and has.

[0083] The substrate 3 further comprises a second layer 31. As shown by FIG. 2A, the second layer 31 can be based on or made of a dielectric material. According to an example, the dielectric material includes a semiconductive oxide, for example, silica of the formula SiO 2 and is preferably such a semiconductive oxide. The second layer 31 is preferably on the first layer 30 by being in direct contact with the first layer 30. As shown by FIG. 2B, alternatively, the second layer 31 can be based on or made of a semiconductive material or a piezoelectric material that is preferably a single crystal. The second layer 31 can have a thickness L of, for example, 10 nm or more, preferably 100 nm 31 and can have. The thickness L 31 can be 3000 nm or less. The second layer 31 of the substrate 3 preferably does not have a metal portion. The second layer 31 is preferably continuous in the main extension plane of the substrate 3.

[0084] According to an example that can be shown by FIG. 2A, on the second layer 31 there is preferably a third layer 33 based on or made of a semiconductive material or a piezoelectric material that is preferably a single crystal. According to an example, the semiconductive material includes silicon and is preferably silicon. In this case, it is also noted that other semiconductive materials may be considered as described later. The third layer 33 has a thickness L that is, for example, substantially between 10 nm and 1000 nm 33It has. Therefore, the substrate 3 may have a semiconductor-on-insulator type, specifically a silicon-on-insulator (SOI) type structure. It should be noted that it can be provided that there is no third semiconductive layer on the second layer 31. The third layer 33 of the substrate 3 preferably has no metal portion. The third layer 33 is preferably continuous in the main extension plane of the substrate 3.

[0085] According to an example, the materials based on which the layers 30, 31, 33 are formed are preferably continuous in the extension plane of the layers. At least one, preferably each of the layers 30, 31, 33 is preferably continuous over at least 80%, preferably over at least 90%, and even more preferably over the whole of the main extension plane of the substrate 3.

[0086] The first layer 30 and / or the second layer 31 is preferably monolithic. The first layer 30 is preferably monolithic at least over the portion where the via 32 extends.

[0087] Hereinafter, unless explicitly stated otherwise, it is considered in a non-limiting manner that the substrate 3 is an SOI substrate, the first layer 30 is made of single-crystalline silicon, the second layer is made of SiO 2 and the third layer is made of single-crystalline silicon.

[0088] The substrate 3 comprises a hollow via 32 extending from the second layer 31 to the first layer 30. In a technique known to those skilled in the art, the via is an interconnecting hole in the substrate. Therefore, the via is absolutely distinguished from other structures such as trenches. The vias 32 can be parallel to each other. The via 32 preferably has a longitudinal dimension L oriented in the thickness direction of the first layer 30 and the second layer 31 32extends across. The via 32 is embedded in the substrate 3, that is, it does not open on either one or the other of the exposed surfaces 3a, 3b of the substrate 3. Therefore, the via 32 defines a closed volume, and more specifically, as is apparent from the figure, each via 32 defines a closed volume. The vias 32 do not communicate with each other, as is apparent from the figure. Since the via 32 is hollow, it is not filled with solid material. The via 32 is preferably filled with a gas atmosphere such as air, nitrogen, and / or argon at a pressure optionally below ambient pressure.

[0089] Therefore, the substrate 3 comprises hollow vias 32 for later filling. This makes it possible to provide hollow vias independently of other steps of fabricating the microelectronic device 4, as will be described later with reference to a method for manufacturing microelectronic devices.

[0090] Longitudinal dimension L 32 can be selected to extend over at least a portion of the thickness L of the second layer, for example, as shown in FIG. 2A, over only a portion of the thickness L of the first layer 30 31 can be selected to extend. In a variation, the via 32 can be flush with the surface of the first layer 30, for example, as shown in FIG. 2C. 30 The via 32 is defined by a side wall 320, a bottom wall 321, and an upper wall 322 opposite the bottom wall 321. The bottom wall 321 is arranged facing the rear surface 3b of the substrate 3, and the upper wall 322 is arranged facing the front surface 3a of the substrate 3.

[0091] Of these walls, at least the bottom wall 321 and the side wall 320 are SiO 2

[0092] 2It can be made of a dielectric material such as. Therefore, when the via 32 is filled with a conductive or semiconductive material, it will be electrically insulated from the first layer 30 and other vias 32. As shown in FIG. 2A, all the walls of the via 32 can be made of a dielectric material. According to a variation, for example, as shown in FIG. 9A which will be described in detail later in relation to the method for manufacturing the substrate 3, the upper wall 322 can be made of the same material as the third layer 33.

[0093] In a variation, for example, as shown by FIG. 2C, the walls of the via 32 can be made of a semiconductive material, and more specifically, can be made of the same material as the material of the first layer 30. Then, the electrical insulation of the via 32 can be carried out during the method for manufacturing the microelectronic device from the substrate 3 which will be described later.

[0094] The via has a transverse dimension D that is substantially 30 μm or less, preferably substantially between 1 μm and 30 μm, more preferably substantially between 5 μm and 15 μm, and even more preferably between 8 μm and 12 μm 32 , for example, can have a diameter. Therefore, the transverse dimension D 32 is smaller than the typical dimensions of TSV-last, which enables having a larger number of vias 32, i.e., a higher density of vias 32, for the same surface of the substrate 3 in the main extension plane of the first layer 30 and the second layer 31. The longitudinal dimension L of the via 32 can be approximately the thickness L of the layer 30 30 , and the via 32 is not open. L 32 can be made to be substantially 200 μm or less, preferably substantially between 50 μm and 150 μm, and can be equal to, for example, substantially 100 μm. These length ranges enable facilitating the formation of through-interconnections through the conductive or semiconductive through-members of the substrate 3, such as the via 32, during the manufacture of the microelectronic device 4.

[0095] The via 32 can have a form factor that is substantially 5 or greater, preferably 10 or greater. By form factor, this means the ratio between the longest dimension and the shortest dimension. In this case, the form factor F is F = L 32 / D 32 and so on. This form factor enables, during the manufacture of the device, a synergistic effect with the formation of conductive or semiconductive through - members, e.g., through - interconnects by vias 32, and the pitch separating the vias 32, to increase the density of vias 32 in the substrate.

[0096] According to an example that can be shown by FIG. 2B, the vias 32 form a periodic matrix, i.e., the vias 32 form a periodic matrix that is arranged at regular intervals in the main extension planes of the first layer 30 and the second layer 31. Thus, the substrate 3 can be an inclusive substrate including a via matrix, and the vias 32' to be etched and filled will be selected according to the conductive or semiconductive members to be formed, as described in more detail later.

[0097] For this purpose, the vias 32 can be separated in pairs by a first pitch A along a first direction included in the main extension planes of the first layer 30 and the second layer 31. The vias 32 can be separated in pairs by a second pitch B along a second direction included in the main extension planes of the first layer 30 and the second layer 31 and different from the first direction. Preferably, these first and second directions are orthogonal. One or the other of these pitches A and B can be substantially between 50 μm and 300 μm, preferably between 100 μm and 200 μm. These pitches can be different from each other or equal to each other along the desired matrix shape. This pitch is measured from center to center between two directly successive vias 32. The pitch A and / or B is preferably constant, i.e., substantially the same for each repetition of the pattern.

[0098] According to a preferred example, the substrate 3 comprises a pattern 32b of only one via 32, preferably having only one via 32. According to this example, each via 32 is separated from adjacent vias 32 by pitches A and B that are substantially the same for each repetition of the pattern. The pitches A and B are preferably equal to each other.

[0099] The vias 32 can be repeated over at least 80% of the dimension of the substrate 3 in this direction / these directions, preferably along the direction of the main extension planes of the first layer 30 and the second layer 31, preferably along the above two different directions. The vias 32 are preferably repeated in the main extension plane of the first layer 30 over at least 80%, preferably at least 90%, even more preferably at least 95% of the main extension plane of the first layer 30. The vias 32 are even more preferably repeated in the main extension plane of the substrate 3 over at least 80%, preferably at least 90%, even more preferably at least 95% of the main extension plane of the substrate 3. Thus, the comprehensive substrate 3 comprises one or more comprehensive matrices of vias 32 over most of its surface to facilitate the manufacture of microelectronic devices as described in detail later. These vias 32 can specifically be selected according to the desired architecture by a comprehensive substrate 3 that can be adapted to manufacture different microelectronic devices.

[0100] According to an example, at least some of the vias 32, preferably each via, extend over a height of 50% or more of the thickness of the substrate 3, preferably 70% or more of the thickness of the substrate 3.

[0101] According to an example that can be shown by FIGS. 3A and 3B, the substrate 3 can comprise at least one, preferably more, grooves 35 configured to improve the electrical insulation of the vias 32. Thus, the substrate 3 can be adapted, specifically, for high-frequency applications and / or instead of high-resistance substrates required by the application. For this purpose, at least one via 32, preferably each via 32, has a cross-section that is completely surrounded by a groove 35 taken in the main extension plane of the first layer 30 and the second layer 31. The groove 35 can surround the via 32 over at least a part of its longitudinal dimension L 32 The groove 35 can surround the via 32 over at least a part of its longitudinal dimension L. The grooves 35 are preferably arranged to insulate the vias 32 from each other and preferably surround only one via 32. The grooves 35 preferably do not contact each other. The grooves 35 can extend more clearly from a part of the second layer 31 to the first layer 30.

[0102] Each groove 35 is preferably embedded, that is, it does not open on one or the other of the exposed surfaces 3a, 3b of the substrate 3. Therefore, each groove 35 defines a closed volume. Each groove 35 is preferably hollow and not filled with solid material. Each groove 35 is preferably filled with a gas atmosphere such as air, nitrogen, or argon, optionally at a pressure below ambient pressure.

[0103] Each groove 35 is defined by a side wall 350, a bottom wall 351, and an upper wall 352 opposite the bottom wall 351. The bottom wall 351 is arranged facing the rear surface 3b of the substrate, and the upper wall 352 is arranged facing the front surface 3a of the substrate 3. Of these walls, at least the bottom wall 351 and the side wall 350 are SiO 2It can be made of a dielectric material such as. As shown in FIG. 3A, all the walls can be made of a dielectric material. According to a variation not depicted in the drawings, the upper wall 352 can be made of the same material as the second layer 31. It can also be provided that the groove 35 is flush with the surface of the first layer 30, like the via 32 shown in FIG. 2C. According to another variation that can be shown, for example, by FIG. 3B, all the walls can be made of the same material as the layer in which the walls extend or extend in contact with, and can be made of a dielectric or semiconductive material depending on the layer under consideration.

[0104] For example, as shown by FIG. 3A, each groove 35 is substantially the depth L of the via 32 hereinafter, and by way of example, is equal to plus or minus 5 μm, the longitudinal dimension L 35 , or equivalently, the depth L 35 can have.

[0105] As shown, for example, by FIGS. 3A and 3B, each groove 35 is substantially 50 μm or less, preferably substantially between 20 μm and 30 μm, the transverse dimension D taken on both sides of the via 32 35 , for example, can have a diameter. Each groove 35 can have a width that is substantially 5 μm or less and substantially between 2 μm and 4 μm. Thus, similar to the dimensions of the via 32, it is possible to obtain a high density of large vias 32 while obtaining an improvement in electrical insulation. Synergistically, for cases of a high density of vias 32 in the substrate 3, using these grooves 35 is particularly advantageous when the vias 32 are close to each other. Due to the high density, for example, the pitch A and / or B is 100 μm or less. It can be provided that the grooves 35 have equal dimensions or different dimensions between different grooves 35.

[0106] According to the dimensions of the grooves 35 in the main extension plane of the first layer 30 and the second layer 31, the pitch can be adapted so that the grooves 35 are different from each other. Each groove 35 can be made cylindrical and preferably can be concentric with the via 32 surrounded by the groove 35.

[0107] For example, as shown in FIGS. 2A to 3C, the substrate 3 can comprise at least one mark, or equivalently a marker 34, which enables alignment of the substrate 3 with other elements. Thus, the placement of the vias 32 during the method for manufacturing the microelectronic device is made more reliable. This marker 34 can be formed by one or more dielectric material layer portions of the first layer 30 and / or the second layer 31. A person skilled in the art can of course consider other variations of the marker, such as markings arranged on the front face 3a or the rear face 3b of the substrate 3.

[0108] Here, a method for manufacturing the substrate 3 will be described with reference to FIGS. 4A to 9B.

[0109] The method includes providing a secondary substrate 1. The secondary substrate 1 comprises at least one first layer 10 intended to form the first layer 30 of the resulting substrate 3, as shown for example in FIGS. 4A and 4B. The secondary substrate 1 can further comprise a surface layer 11 intended to at least partially form the second layer 31 of the substrate 3, as shown by FIG. 4A for example. The surface layer 11 is preferably based on, or made of, a dielectric material. The secondary substrate 1 further has an exposed surface 1a in the first layer 10 or the surface layer 11.

[0110] For example, as shown by FIGS. 5 and 6A and 6C, via 32 can be formed by etching, preferably by deep reactive ion etching (DRIE). To form via 32, the etching step may include applying a mask 12 having an opening 120 through which via 32 is etched, as shown in FIG. 5 for example. Mask 12 is preferably a resin mask. The mask being hard can be provided, for example, by applying a resin mask 12 and then etching the surface layer 11, removing this mask, and etching the first layer 10 thanks to the so-called "hard" oxide mask thus formed. It is noted that the surface layer 11 can be removed after etching via 32, and via 32 is then electrically insulated by subsequent deposition of a dielectric layer.

[0111] Etching is preferably configured to obtain the features of via 32 described above, specifically to obtain the dimensions of via 32 and the pitch separating via 32. For example, the dimensions of mask 12 and / or the etching time and etching rate are adjusted for this purpose.

[0112] Therefore, to form via 32, the method may include forming a dielectric material at least at the bottom wall 321 and the side wall 320, as shown in FIG. 6B for example.

[0113] This formation can be carried out by thermal oxidation, for example, at a temperature of substantially 1050°C in an atmosphere containing oxygen.

[0114] In a variant or complement, a dielectric material, for example, silica SiO 2 can be deposited on at least the walls 320, 321 of via 32. This deposition can be carried out, for example, using a precursor gas containing oxides and silicon, optionally combined with dioxygen, for example, tetraethyl orthosilicate (TEOS) or the chemical formula SiH 4It can be chemical vapor deposition (CVD) from a silane. The deposition is, for example, sub-atmospheric pressure CVD (SACVD) or plasma enhanced chemical vapor deposition (PECVD).

[0115] Preferably, mask 12 is removed before the formation of the walls of these dielectric materials. When layer 11 serves as a hard mask, it is also preferable to remove layer 11.

[0116] Preferably, the formation of walls 320, 321 is configured such that the dielectric walls 320, 321 have dimensions substantially between 50 nm and 600 nm, preferably substantially equal to 400 nm. For side wall 320, this dimension is the transverse dimension. For bottom wall 321, this dimension is the longitudinal dimension. For example, the thermal oxidation time or deposition time and / or deposition rate can be adjusted for this purpose.

[0117] The method can include the step of forming marker 34 simultaneously with or together with the etching of via 32 and, if necessary, simultaneously with or together with the formation of the walls of the dielectric material. For this purpose, the mask can further comprise an opening, not depicted in this case, for etching an opening 34' in the second layer 31 down to the first layer 30 as shown, for example, in FIG. 6A. The opening 34' can be filled with a dielectric material during the formation of the walls. The formation of marker 34 can be separate from these steps of etching and filling the opening 34', for example, by the application of a mask specific to this marker 34. When the formation of marker 34 is separate from these steps, it is advantageously performed beforehand to serve as a marker for the positioning of via 32.

[0118] Figures 7A - 7C show an example where a groove 35 is formed around a via 32. Only one groove is depicted to simplify the figure. The formation of the groove 35 can include the same steps with respect to the etching of the via 32 and, if necessary, can include the same steps with respect to the formation of the walls of the dielectric material. The groove 35 can be formed simultaneously with the via 32, and thus the mask 12 comprises an opening corresponding to the groove 35 to be etched. The groove 35 can alternatively be etched before or after the etching of the via 32, such as by the application of a mask and etching specific to the groove 35. According to an example, when the groove 35 and the via 32 are etched, a dielectric material can be formed at the walls 350, 351, 320, 321 as described above. Alternatively, the groove 35 can be formed after the formation of the dielectric material at the walls 320 and 321. According to the method described above, other formations of the dielectric material can be provided at the walls 350, 351. The etching of the groove 35 may not be followed by the formation of the dielectric material at the walls 350 and 351, as shown for example in Figure 7C. The groove 35 and the via 32 may, according to a variation not shown, not have walls of dielectric material.

[0119] Following the formation of the via 32 and, if necessary, the formation of the groove 35, these structures can be covered so as to be embedded during the assembly of the substrate 1 with the donor substrate 2. Thus, the method can include providing a donor substrate 2 having an exposed surface 2a.

[0120] As shown by Figures 8A - 9C, the support substrate 1 and the donor substrate 2 can be assembled by contact through the direct bonding of their respective surfaces 1a, 2a. Thus, the donor substrate 2 can be thinned, for example, by cutting by a method known as Smart - Cut®.

[0121] For this purpose, the assembly may include forming a embrittled region 22 at a non-zero depth from the surface 2a of the donor sub-substrate 2 before the contact of the surfaces 1a, 2a. This embrittled region 22 is formed, for example, by ion implantation such as hydrogen and / or helium ions. It is noted that any other technique for forming an embrittled region, specifically any other technique used in the SOI type stack development method, can be considered.

[0122] Following the assembly of the support sub-substrate 1 and the donor sub-substrate 2, the method may include separating the surface layer from the donor sub-substrate 2 in the embrittled region 22, as in the example shown in FIGS. 8B and 9B. This separation can be carried out thermally or mechanically by steps known to those skilled in the art.

[0123] After the separation, the resulting surface 3a may be irregular and damaged. Polishing of the surface 3a, chemical smoothing, chemical, mechanical, and / or thermal hardening, or ion beam hardening based on atomic clusters or monomers can be performed so that the surface 3a has a crystalline quality and roughness compatible with other subsequent methods. Any chemical mechanical polishing (CMP) or thermal polishing method intended to smooth a semiconductor-based surface, specifically a silicon-based surface, can be considered.

[0124] According to an example, the donor sub-substrate 2 comprises a layer 20 based on or made of a semiconductive material, for example made of silicon, more specifically single crystal silicon or a piezoelectric material. The donor sub-substrate 2 may further comprise a layer 21 based on or made of a dielectric material, for example made of silica SiO 2 and made of.

[0125] According to an example that can be shown by FIGS. 8A and 8B, layer 21 can form the surface layer of the donor sub-substrate 2. Specifically, a semiconductive oxide, for example, silicon oxide for the semiconductive oxide, for example, direct bonding of the semiconductive oxide can be performed. Following their assembly, layer 21 and layer 11 will form the second layer 31 of the substrate 3. Therefore, the respective thicknesses of those layers can be selected to obtain a desired thickness L 31 It will be understood that, according to this example, the upper wall 322 of the via 32 and, if necessary, the upper wall 352 of the groove 35 can be formed from a dielectric material. The upper wall 322 of the via 32 and, if necessary, the upper wall 352 of the groove 35 can have a thickness, for example, substantially between 1 nm and 600 nm.

[0126] According to an example that can be shown by FIGS. 9A and 9B, layer 20 can form the surface layer of the donor sub-substrate 2. A semiconductive oxide, for example, silicon oxide for the semiconductor, specifically, direct bonding of silicon can be performed. Following their assembly, only layer 11 will form the second layer 31 of the substrate 3. Therefore, the thickness of that layer can be selected to obtain a desired thickness L 31 It will be understood that, according to this example, the upper wall 322 of the via 32 and, if necessary, the upper wall 352 of the groove 35 can be formed from a semiconductive material.

[0127] According to an example that can be shown by FIG. 9C, layer 20 can form the surface layer of the donor sub-substrate 2. A direct bonding of a semiconductive or piezoelectric, specifically silicon, to the semiconductor can be performed when layer 20 is based on a semiconductive material or a piezoelectric material. A direct bonding of a semiconductive oxide to the semiconductor, specifically silicon, can be performed when layer 20 is based on a dielectric material, specifically an oxide. Following their assembly, layer 20 will form the second layer 31 of the substrate 3. Therefore, the thickness of that layer can be selected to obtain a desired thickness L 31 to obtain.

[0128] Regarding assembly, it is noted that in order to avoid the occurrence of defects, it is preferable to have a thickness of at least 10 nm of a dielectric material, specifically an oxide thickness, at the bonding interface.

[0129] Here, a method for manufacturing the microelectronic device 4 will be described with reference to FIGS. 10 to 17.

[0130] In this method, the vias 32 can be used to establish interconnections. The vias 32 can be used alternatively or complementarily to form part of a microelectronic device that does not necessarily have metal interconnections, such as in a MEMS device. The vias can be intended to be filled with a semiconducting material, such as poly-Si.

[0131] The method can include providing a substrate 3. The method can include depositing a layer of components 4', such as transistors, diodes, memory points (shown in FIG. 1). This deposition can include, for example, FEOL steps.

[0132] As shown, for example, in FIG. 10, the method can include depositing at least one layer portion 40, also referred to as a device portion 40, on the front surface 3a of the substrate 3. In the following, it is considered in a non-limiting manner that several portions 40 can be deposited. Alternatively or complementarily, the device portion can be etched on the pre-exposed surface 3a of the substrate 3.

[0133] These portions can be made of metal 40, specifically, metal interconnect lines can be formed. Typically, these metal portions 40 can be used to redistribute electrical signals. These metal portions can also be called metallization levels. There can be several metal portions 40 by means of interconnections between these portions. This deposition can include, for example, BEOL steps.

[0134] In the following, it is considered in a non-limiting manner that these portions 40 are metallic and that the etched vias 32 serve to establish the interconnections. The following steps are of course applicable when a portion 40 of the non-metallic device 4 is deposited and / or etched and / or when a semiconductive member 45 is fabricated at the via 32.

[0135] To facilitate the handling of the substrate 3, the method may include mounting a support 41 on the side of the pre-exposed surface 3a of the substrate 3, for example through a bonding 410 performed in a prior deposition as shown by way of example in FIG. 11. This further enables protecting the deposition performed on the front face 3a of the substrate 3.

[0136] After the deposition of the metallic portion 40, and if necessary after the mounting of the support 41, the method includes etching at least one via 32 in order to achieve at least one interconnection with one of the metallic portions 40. For this purpose, several examples are possible and are described here. In the following, it is considered in a non-limiting manner that several vias 32 are etched and filled.

[0137] According to a first example as shown by FIGS. 12A, 12E, and 12F, from the rear face 3b of the substrate 3, the first layer 30 can be etched until it is flush with the bottom wall 321 of the via 32 or beyond the bottom wall 321. Thus, the bottom wall 321 of the via 32 is exposed. For this purpose, the first layer 30 can be thinned and etched by a selective etching of the material of the first layer 30 with respect to the dielectric material of the walls 320, 321. According to the example shown in FIG. 12A, the etching is, for example, a reactive ion etching using a precursor such as SF 6 such as silica SiO in reactive ion etching using a precursor such as SF 2It can be a selective etching of silicon with respect to [substrate]. By "selective etching of material A with respect to material B", this means that the etching rate of material A is 10 times greater, preferably 100 times greater, than the etching rate of material B. It can be considered to perform a partial mechanical thinning of the substrate 3 that ends with selective plasma or chemical etching.

[0138] Therefore, the dielectric material walls can be selectively etched with respect to the material of the first layer 30 in order to open to the vias 32.

[0139] Specifically, when the substrate 3 is an inclusive substrate having a matrix of vias 32 and some of the vias 32 are considered to be etched and then filled, the method can include selecting the vias 32' to be etched. For example, as shown by FIGS. 12B and 12G, a mask 42 can be deposited on the back surface 3b of the substrate 3. This mask 42 can include an opening 420 positioned vertically aligned with the vias 32' to be etched. Therefore, the wall 321 can be etched by the opening in order to open to the vias 32.

[0140] Regardless of whether all or some of the vias 32 are etched, the etching can be continued to form at least one cavity 43, for example, an electrically connecting cavity 43 that extends from the vias 32 to a portion 40 positioned below the vias 32 as shown by FIGS. 12C and 12G. In the following, the formation of several cavities 43 is considered in a non-limiting manner. For example, the etching of the dielectric material in the wall 321 can be reactive ion etching. The etching of the semiconductive material in the wall 321 can be similar to that performed to etch the layer 30.

[0141] When the walls of the vias 32' to be etched are not made of a dielectric material, the method may include forming a dielectric layer at least on the sidewalls 320, according to the method described above with reference to the method for manufacturing the substrate 3. This example can be illustrated by FIG. 12H.

[0142] When the cavity 43 is formed, the method may include a conductive or semiconductive member 45. This member 45 may be based on a metal material 45, such as electrolytic copper or CVD tungsten, or may be made from such a metal material 45. Alternatively, this member 45 may be based on a semiconductive material, such as poly-Si, or may be made from such a semiconductive material. The deposition may be configured to fill these cavities 43 with a metal material to form electrical interconnections or device portions 40, as shown, for example, by FIG. 12D. The deposition may be further configured to cover at least a portion of the post-exposed surface 3b of the substrate 3 with a metal or semiconductive layer 46.

[0143] During the formation of the cavity 43 and the deposition of the member 45, the method may include at least one of the following. - Removal of the mask 42. - Passivation of the post-exposed surface 3b of the substrate 3 by forming a dielectric material layer 44, also referred to as a passivation layer 44, for example. This formation can be performed by depositing a dielectric material as described above, for example. - Etching of the cavity 43 to remove an optional oxide layer formed at the bottom of the cavity, specifically during the formation of the passivation layer 44. This optional oxide layer can actually limit the electrical re-contact in the portion 40.

[0144] According to a second example shown by FIGS. 13A to 13C, the mask 42 can be first deposited on the rear surface 3b of the substrate 3. This mask 42 can include an opening 420 positioned vertically aligned with the via 32. Specifically, when the substrate 3 is a comprehensive substrate including a matrix of vias 32, when it is considered that some of the vias 32 are only etched and then metallized, the selection of the vias 32' to be etched can be performed according to the arrangement of the opening 420 above the vias 32' to be etched.

[0145] The first layer 30 can be etched by the opening 420 until it is flush with the bottom wall 321 of the via and even beyond the bottom wall 321. The etching can be continued to form at least one cavity 43 extending from the via 32 to the metal part 40 positioned below the via 32, as shown in FIG. 13B for example. In this case, the formation of several cavities 43 is considered in a non-limiting manner. This etching step can be reactive ion etching.

[0146] Next, the subsequent steps can be performed as previously described, as shown in FIG. 13C for example. Thus, the layer 44 also passivates the upper part of the cavity 43 in the continuation of the side wall 320.

[0147] The example of the embodiment is also applicable when the via 32' does not have a wall of a dielectric material. As previously described, the method can include forming a dielectric layer at least on the side wall 320 after the opening of the via 32' to be etched.

[0148] When the substrate 3 includes the groove 35, the two examples described above can be applicable. FIGS. 14A to 14F show the first example described above. According to one or the other of these examples, in order not to fill the groove of the conductive or semiconductive member, the opening 420 of the mask 42 can be arranged so as not to enable the etching of the groove 35. More specifically, the mask can cover the rear surface 3b of the substrate arranged in a vertical direction with the groove 35, as shown in FIG. 14D for example. During the steps following the formation of the cavity 43, the groove 35 preferably remains closed and thus is not filled with the member 45.

[0149] Following the deposition of the metal layer 46 on the rear surface 3b of the substrate, even in the example of the throat of the embodiment described above, the method may include fabricating a pattern 46' in this metal layer 46, for example, to define different interconnections. This can be shown by way of example in FIG. 15. This patterning can be performed by masking, and for example, ion etching, ion beam etching, or wet etching follows.

[0150] The method may include passivating 47 the rear surface 3b of the substrate, for example, as shown in FIG. 16, as an alternative or complement to this fabrication of the pattern 46'. This passivation can be performed by the deposition of an organic compound such as a photosensitive structural resin, for example, a polymer type of polyimide or benzocyclobutene.

[0151] For example, as shown in FIG. 16, the method can further include so-called UBM (under bump metallization) to connect the obtained electrical interconnections with the casing 5 shown in FIG. 1.

[0152] When the manufacturing steps performed on the rear surface 3b of the substrate 3 are completed, the support 41 can be removed as shown by the transition from FIG. 16 to FIG. 17.

[0153] In view of the above, it becomes clearly apparent that the present invention proposes a substrate that enables the manufacturing of vias in microelectronic devices in such a manner, a method for manufacturing the same, and a method for manufacturing microelectronic devices.

[0154] The present invention is not limited to the embodiments described above, but extends to all embodiments encompassed by the present invention. The present invention is not limited to the examples described above. Many other modifications of the embodiments are possible without departing from the scope of the present invention, for example, by combining the above features. Furthermore, the features described with respect to an aspect of the present invention can be combined with other aspects of the present invention. Specifically, the substrate can have any feature resulting from its manufacturing method, and vice versa, and this method can include any step configured to obtain a feature of the substrate. The method for manufacturing a microelectronic device can implement any feature of the substrate.

[0155] In the examples described, the semiconducting material is silicon. The present invention can of course also be applied to other single-crystalline or polycrystalline semiconductors that are optionally doped, specifically, Si, Ge, SiGe, SiC, group III-V materials (e.g., AlN, GaN, InN, InGaAs, GaP, InP, InAs, AsGa, etc.), and group II-VI semiconductor materials. The dielectric material can be an oxide or a semiconducting nitride such as SiO 2 , SiN, Al 2 O 3 etc. The piezoelectric material is, for example, lithium tantalate (LiTaO 3 ), lithium niobate (LiNbO 3 ), potassium sodium niobate (K X Na 1-X NbO 3 or KNN), barium titanate (BaTiO 3) can be selected from quartz, lead zirconate titanate (PZT), a compound of magnesium lead and lead titanate niobate (PMN-PT), zinc oxide (ZnO), aluminum nitride (AlN), or aluminum scandium nitride (AlScN). Of course, other materials can also be considered.

Description of Reference Numerals

[0156] 1 Support sub-substrate 1a Exposed surface, surface 2 Donor sub-substrate 2a Exposed surface, surface 3 Substrate 3a Front exposed surface 3b Rear exposed surface 4 Microelectronic device, non-metallic device 4’ Component 5 Casing 10 First layer 11 Surface layer 12 Mask 20 Layer based on semiconductive material, layer made of semiconductive material 21 Layer based on dielectric material, layer made of dielectric material 22 Brittleness region 30 First layer 31 Second layer 32 Via 32’ Etched via 32b Pattern 33 Third layer 34 Mark, marker 35 Groove 40 Device part, layer part, metal part 41 Support 42 Mask 43 Cavity 44 Dielectric material layer, passivation layer 45 Conductive or semiconductive member, metal material 46 Metal or semiconductive layer 46’ Pattern 47 Passivation 120 Opening 320 Side wall 321 Bottom wall 322 Top wall 350 Side wall 351 Bottom wall 352 Top wall 410 Joining 420 Opening A First pitch B Second pitch D 32 Transverse dimension, horizontal dimension L 30 Thickness of the first layer 30 L 31 Thickness of the second layer 31 L 32 Longitudinal dimension, depth of via 32 L 33 Thickness of the third layer 33 L 35 Longitudinal dimension, depth of groove 35 D 35 Transverse dimension, diameter of groove 35

Claims

1. A substrate (3) comprising a first layer (30) based on a semi-conductive material, and a second layer (31) on top of said first layer, wherein said substrate (3) comprises a plurality of embedded vias (32) extending from said second layer (31) over a part of said first layer (30), each via (32) being defined by a side wall (320), a bottom wall (321), and an upper wall (322) opposite to said bottom wall (321), and each via (32) having at least one transverse dimension of 30 μm or less, characterized in that it is a substrate (3).

2. The substrate according to claim 1, wherein at least said bottom wall (321) and said side wall (320) are made of a dielectric material.

3. The substrate according to claim 1 or 2, wherein said second layer (31) is a layer based on a material selected from a dielectric material, such as an oxide, a semi-conductive material, or a piezoelectric material, and preferably is a layer made of such a material.

4. The substrate according to any one of claims 1 to 3, wherein said second layer (31) is an embedded dielectric material layer, such as an oxide, on which there is a third layer (33) based on a material selected from a semi-conductive material or a piezoelectric material.

5. The substrate according to any one of claims 1 to 4, wherein each via (32) has at least one transverse dimension between 1 μm and 30 μm.

6. The substrate according to any one of claims 1 to 5, wherein at least some of said vias (32), preferably each via (32), have an aspect ratio of 10 or more of a longer dimension oriented along the dimension in the thickness of said first layer (30) and said second layer (31).

7. The substrate (3) according to any one of claims 1 to 6, wherein said plurality of vias (32) form a periodic matrix.

8. The substrate (3) according to claim 7, wherein said vias (32) are separated in pairs by a constant pitch along at least one direction of the main extension plane of said first layer and said second layer, said pitch being between 50 μm and 300 μm, preferably between 100 μm and 200 μm.

9. ​ The substrate (3) according to any one of claims 1 to 8, wherein at least one via (32) is completely surrounded by a groove (35) extending from the second layer (31) to a portion of the first layer (30) over at least a portion of the longitudinal dimension of the via (32).

10. The substrate (3) according to claim 9, wherein the groove (35) extends from the second layer (31) to the first layer (30) over a longitudinal dimension that is less than or equal to the longitudinal dimension of the via (32).

11. The substrate (3) according to any one of claims 1 to 10, further comprising a marker (34) configured to enable alignment of the substrate (3).

12. A method for manufacturing the substrate (3) according to any one of claims 1 to 11, comprising: providing a support substrate (1) comprising at least one first layer (10) based on a semiconducting material, the support substrate (1) having an exposed surface (1a); etching a plurality of vias (32) such that each via (32) extends from the exposed surface (1a) over a portion of the first layer (10), each via being defined by a side wall (320) and a bottom wall (321), and each via (32) having at least one transverse dimension of 30 μm or less; providing a donor substrate (2) comprising a surface layer (20, 21) having an exposed surface (2a); assembling the support substrate (1) and the donor substrate (2) by their exposed surfaces (1a, 2a) such that, by covering the vias (32), each via is defined by the side wall (320), the bottom wall (321), and an upper wall (322) opposite the bottom wall (321); and a method.

13. Following the step of etching the plurality of vias (32), preferably prior to the assembly of the support substrate (1) and the donor substrate (2), the method includes, for each via (32), forming a dielectric material at least on the bottom wall (321) and the side wall (320), according to the method of claim 12.

14. The step of forming a dielectric material on at least the bottom wall (321) and the side wall (320) of the plurality of vias (32) comprises At least thermal oxidation for oxidizing the semiconductive material of the first layer (10) in the bottom wall (321) and the side wall (320), and / or Deposition of the dielectric material on at least the bottom wall (321) and the side wall (320) The method according to claim 13, comprising

15. The surface layer (20, 21) of the donor sub-substrate is a layer based on a material selected from a dielectric material, such as an oxide, a semiconductive material, or a piezoelectric material, preferably a layer made of such a material. The method according to any one of claims 12 to 14

16. The support sub-substrate (1) further comprises a surface layer (11) based on a dielectric material, such as an oxide, on the first layer (10), preferably a surface layer made of the dielectric material. The surface layer has the exposed surface (1a), and / or The surface layer (21) of the donor sub-substrate is a layer based on a dielectric material, such as an oxide, on a layer (20) based on a material selected from a semiconductive material or a piezoelectric material, preferably a layer made of such a dielectric material. The method according to any one of claims 12 to 15

17. The step of etching the plurality of vias (32) is configured to form a periodic matrix. The method according to any one of claims 12 to 16

18. The method further comprises etching a groove (35) that completely surrounds at least one via (32) over at least a portion of the longitudinal dimension of the via (32) before the step of assembling the support sub-substrate (1) and the donor sub-substrate (2). The groove (35) extends from the surface layer (11) to the first layer (10). The method according to any one of claims 12 to 17

19. A method for manufacturing a microelectronic device (4), comprising Providing a substrate (3) according to any one of claims 1 to 11, or a substrate (3) manufactured by the method according to any one of claims 12 to 18, wherein the substrate (3) has a front exposed surface (3a) and a rear exposed surface (3b). A step Forming at least one layer portion (40) of the device (4) on the front exposed surface (3a) of the substrate (3) by deposition of the portion, and / or etching the front exposed surface (3a) of the substrate (3) configured to form the portion; In at least one via, etching by the rear exposed surface (3b) of the substrate (3), wherein, to form a cavity (43), the wall of the upper wall (322) and the bottom wall (321) of the at least one via is etched to open into the via (32), and then the etching is continued until reaching the at least one layer portion (40) of the device (4); Depositing a conductive or semiconductive member (45) to fill the cavity (43); A method comprising.

20. Before the step of etching by the rear exposed surface (3b) of the substrate (3), selecting at least one via (32') to be etched from among the plurality of vias (32), wherein only some of the plurality of vias (32) are selected as the via (32') to be etched, the step comprising; The step of selecting at least one via to be etched; Applying a mask (42) having an opening (420) positioned vertically aligned with the at least one via (32') to be etched on the rear exposed surface (3b) of the substrate (3); Etching the first layer (30) to reach the wall of the at least one via (32') to be etched; The method according to claim 19, comprising.

21. The step of selecting at least one via (32') to be etched comprises the step of applying the mask (42), and then the step of etching the first layer (30) through the opening (420) of the mask (42), the method according to claim 20.

22. The step of selecting at least one via (32') to be etched comprises the step of etching the first layer (30) to reach the wall of the at least one via (32') to be etched, and then the step of applying the mask (42), the method according to claim 20.

23. The step of depositing the conductive or semiconductive member (45) is configured to further cover at least a portion of the rear exposed surface (3b) of the substrate (3) with a conductive or semiconductive layer (46), the method according to any one of claims 19 to 22.

24. The step of mounting a support (41) on the front exposed surface (3a) of the substrate (3) between the step of forming the at least one layer portion (40) of the device (4) and the step of etching by the rear exposed surface (3b) of the substrate (3); The step of removing the support (41) after the step of depositing the conductive or semiconductive member (45) so as to fill the cavity (43). The method according to any one of claims 19 to 23, comprising:

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