System and method for adaptive power multiplexing using a first type of power multiplexer and a second type of power multiplexer

Abstract

A system-on-chip (SOC) includes a power distribution network (PDN) having two different types of power multiplexers. The first type of power multiplexer includes low-resistance switching logic, and the second type includes high-resistance switching logic and digital logic for providing an enable signal to the first type of power multiplexer. A given first type of power multiplexer may have a number of second type of power multiplexers within a loop, the loop including a communication path for the enable signal that feeds back the enable signal to the enable input of the first type of power multiplexer.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims priority and the benefit thereof to U.S. Patent Application No. 17 / 662,460, filed May 9, 2022. Its disclosure is incorporated herein by reference as if fully set forth below and for all applicable purposes.

[0002]

[0002] This application generally relates to power multiplexing, and more specifically, to using a first type of power multiplexer and a second type of power multiplexer to provide adaptive power multiplexing.

Background Art

[0003]

[0003] Conventional computing devices (e.g., smartphones, tablet computers, etc.) may include a system on chip (SOC) having a processor and other arithmetic circuits. The SOC can receive its power from a battery, so conventional designs can balance SOC performance and power usage to provide a desirable experience for the user while requiring as little battery charging as possible.

[0004]

[0004] Power multiplexing is a technique that can be used to save power in some cases. One way that some systems can use power multiplexing to save power is to enable power collapse in some parts of a processing core (using a first power multiplexer and a first power domain), while supplying power to other parts of the processing core (using a second power multiplexer and a second power domain). Another way that some conventional systems can use power multiplexing is to switch from a first power source to a second power source to supply power to a central processing unit (CPU) memory and adjust the second power source to overdrive the CPU memory. This technique can save power by enabling the system-on-a-chip (SOC) to selectively increase the voltage in some components while not increasing the voltage in other components.

Summary of the Invention

[0005]

[0005] Various implementations provide circuits and techniques for more efficiently using routing space and chip area in a power distribution network (PDN). Some implementations may use a first type of power multiplexer (e.g., having high resistance switches) and a second type of power multiplexer (e.g., having low resistance switches) to distribute power multiplexing functionality within a semiconductor chip. For example, the first type of power multiplexer may provide an enable signal to the second type of power multiplexer, and the second type of power multiplexer may be distributed across the chip in a daisy chain or other arrangement. Both the first type of power multiplexer and the second type of power multiplexer can be implemented to save routing space within the chip, thereby providing a PDN that has less impact on routing than other implementations and more efficiently uses semiconductor area.

[0006]

[0006] According to one implementation form, a system-on-chip (SOC) includes a first type of first power multiplexer coupled to a first power supply and a second power supply, the first power multiplexer including first switching logic disposed between the first power supply, the second power supply, and a load, a second type of second power multiplexer coupled to the first power supply and the second power supply, the second power multiplexer including second switching logic between the first power supply, the second power supply, and the load, the second switching logic including an enable input coupled to the first power multiplexer.

[0007]

[0007] According to one implementation form, a method includes transmitting an enable signal from a first type of first power multiplexer to a second type of second power multiplexer, switching a first load from the first power supply to the second power supply by the first power multiplexer and the second power multiplexer, the second power multiplexer switching the first load in response to the enable signal, and receiving the enable signal in the first power multiplexer.

[0008]

[0008] According to one implementation form, the semiconductor chip is a first power multiplexer of a first type and a second power multiplexer of the first type, and the first power multiplexer and the second power multiplexer are arranged in a daisy chain with a controller. The daisy chain passes a control signal from the controller to the first power multiplexer, then to the second power multiplexer, and feeds back the control signal to the controller. The semiconductor chip includes the first power multiplexer and the second power multiplexer, and a third power multiplexer and a fourth power multiplexer of a second type arranged in a first loop from the first power multiplexer. The first loop passes a first enable signal from the first power multiplexer to the third power multiplexer and the fourth power multiplexer, and then returns it to the first power multiplexer. The semiconductor chip also includes a fifth power multiplexer and a sixth power multiplexer of the second type arranged in a second loop within the second power multiplexer. The second loop passes a second enable signal from the second power multiplexer to the fifth power multiplexer and the sixth power multiplexer, and then returns it to the second power multiplexer.

[0009]

[0009] According to yet another implementation form, there is a power distribution network (PDN) on the semiconductor chip. The PDN includes a first means for multiplexing between a first power supply and a second power supply, and a second means for multiplexing between the first power supply and the second power supply. The second means is configured to receive an enable signal from the first means, and the enable signal causes the second means to select between the first power supply, the second power supply, and a power collapse. The first means includes a power multiplexer of a first type, the second means includes a power multiplexer of a second type different from the first type, and further, the second means includes a plurality of power multiplexers of the second type arranged in a loop for feeding back the enable signal to the first means.

Brief Description of the Drawings

[0010]

Figure 1

[0010] Schematic diagram showing an exemplary power multiplexer according to one implementation form.

Figure 2

[0011] Diagram of an exemplary multiplexing circuit configuration including two different types of switching logics according to one implementation form.

Figure 3

[0012] Shows the exemplary switching logic of a power multiplexer according to one implementation form.

Figure 4

[0013] Diagram of an exemplary switching voltage generator according to one implementation form.

Figure 5

[0014] Diagram of an exemplary power multiplexing circuit according to one implementation form.

Figure 6

[0015] Diagram of an exemplary power multiplexing circuit according to one implementation form.

Figure 7

[0016] Diagram of an exemplary power distribution network (PDN) using a number of types of power multiplexers according to one implementation form.

Figure 8

[0017] Diagram showing an exemplary PDN according to one implementation form.

Figure 9

Figure 10

Figure 11

[0018] Diagram showing an exemplary application example of a PDN applied to a memory device according to one implementation form.

Figure 12

[0019] Diagram of an exemplary method adapted according to one implementation form.

Figure 13

[0020] Diagram of an exemplary chip having power multiplexing according to the principles described herein according to one implementation form.

MODE FOR CARRYING OUT THE INVENTION

[0011]

[0021] Some power multiplexing architectures can include a number of power multiplexing components, such as high-resistance switches, low-resistance switches, and enable logic, in a single power multiplexing circuit. However, those power multiplexing circuits may use an undesirable amount of routing space within a system-on-chip (SOC) or processing unit. There is a need in the art for more efficient use of routing space in a power distribution network (PDN).

[0012]

[0022] Various implementations provided herein include systems and methods for providing power multiplexing using a first type of power multiplexer and a second type of power multiplexer. For example, the first type of power multiplexer may include digital logic and first switching logic disposed between a first power supply, a second power supply, and a load. The second type of power multiplexer may be coupled to the first power supply and the second power supply and may include second switching logic disposed between the first power supply, the second power supply, and the load. The second switching logic may include an enable input coupled to the digital logic of the first type of power multiplexer. Thus, in some examples, the first type of power multiplexer may provide a control signal for the second type of power multiplexer.

[0013]

[0023] Continuing with the example, the first switching logic can be implemented to have a higher resistance than that of the second switching logic. In one example, the first switching logic may be referred to as a "minority switch" and the second switching logic may be referred to as a "resting switch", but these terms are used for convenience rather than to define the switching logic. In one implementation, the first switching logic can be turned on to create a conductive path having a high resistance during a first period of a voltage switching operation, and the second switching logic can be turned on to create another conductive path having a low resistance while the first switching logic is turned off during a second time period of the voltage switching operation. Thus, when the voltage is switched from one voltage source to another, there can be a time period during which the high resistance is applied with the help of the minority switch to avoid inrush or protrusion of current.

[0014]

[0024] As described above, the first type of power multiplexer can provide an enable signal to the second type of power multiplexer. For example, the second type of power multiplexer may be arranged in series with other similar power multiplexers with respect to the enable signal, whereby the enable signal generated from the first type of power multiplexer is transmitted on a conductive path passing through the second type of power multiplexer and returned to the enable input in the first type of power multiplexer. In fact, some implementations may include a number of first type of power multiplexers arranged in a daisy chain (e.g., sometimes referred to as a "main chain"), and each of the first type of power multiplexers may have a second type of power multiplexer arranged in its respective chain (e.g., sometimes referred to as a "secondary chain").

[0015]

[0025] Each of the power multiplexers can service a load. For example, a block of memory cells can be serviced by a number of secondary chains. Each power multiplexer within the secondary chain can switch between a first power source, a second power source, and a power breakdown.

[0016]

[0026] Continuing with this example, the power domain of the chip may include a main chain and one or more secondary chains. The chip may include a number of power domains, and the second power domain may include a second main chain having one or more secondary chains of its own.

[0017]

[0027] In one example, the transistors of the minority switches and the standby switches may be controlled using a switching voltage that is generated to be above the highest voltage of two different power supplies. The purpose of the switching voltage may be to have a gate-source voltage that is 0 or greater during the off period of the transistor to ensure that the transistor is turned off. The voltage generator may be implemented in any suitable part of the power multiplexer architecture. For example, the voltage generator may be implemented within a first type of power multiplexer, a second type of power multiplexer, or may be a stand-alone structure. Any suitable method can be used to supply a voltage from the switching voltage generator to the gates of the transistors of the first switching logic and the second switching logic.

[0018]

[0028] The placement of the switching voltage generator may affect the overall architecture of the power distribution network (PDN). For example, in an example where a second type of power multiplexer is implemented with the switching voltage generator, it may result in a larger structure for the individual second type of power multiplexers, but may reduce the amount of switching voltage routing. On the other hand, other implementations may include the switching voltage generator in some but not all of the second type of power multiplexers, or may use a stand-alone switching voltage generator. Such implementations may reduce the size of the second type of power multiplexers (at least those without the switching voltage generator) in exchange for an increase in switching voltage routing.

[0019]

[0029] Various implementations may include advantages over other systems. One advantage may include increased space savings. For example, each of the second type of power multiplexers may include a number of transistors in parallel to provide a desired resistance, and the lower resistance may correspond to more parallel transistors. As a result, the second type of power multiplexer (idle switch) may use on-chip routing resources across multiple metal layers. When paired with the first type of power multiplexer (few switch), the resulting structure may use an undesirably large number of metal layers within the chip structure.

[0020]

[0030] Various implementations of the present disclosure move the idle switches within their own multiplexing structure and out of the structure including the few switches. As a result, even if the number of transistors is the same, fewer routing resources and fewer metal layers can be used. In other words, by moving the idle switches away from the few switches, routing overcrowding can be reduced, and the number of metal layers used for routing can be made fewer. In one example, implementations of the present disclosure may use a total of six metal layers, while a structure having both few switches and idle switches may use nine or more metal layers. Of course, the scope of implementation is not limited to any number of metal layers, and this comparison is provided for ease of explanation. Further, reducing routing overcrowding may allow other components to be moved closer to the power multiplexers within the chip design, thereby allowing for more efficient use of the semiconductor area.

[0021]

[0031] Figure 1 is a conceptual diagram of an example of an adaptive power multiplexing circuit configuration according to one implementation form. Figure 1 shows a simplified block for illustrating a power multiplexer 110 and an enable logic circuit configuration block 124. The enable logic circuit configuration block 124 includes a forward path that can communicate with power management software, such as within an operating system kernel executed on a processor core of an SOC. The forward path may include a signal from the power management software that instructs the enable logic circuit configuration block 124 to select one or the other of the power supplies Vdd1 and Vdd2. A switching signal "sel" is provided from the enable logic circuit configuration block 124 to the multiplexer 110, and an assert or deassert selects one or the other of the power supplies Vdd1 and Vdd2. Although not further described herein, the enable logic circuit configuration block 124 may have additional control signal outputs to other components (not shown) and may receive control signal inputs on a feedback path from those or other components (not shown). Further, the enable logic circuit configuration block 124 may also provide control signal feedback to the power management software.

[0022]

[0032] The output (Vdd_apm) of the power multiplexer 110 is supplied to a load (not shown), such as a memory block, a processing block, or other components on the chip. The power multiplexer 110 is a 2:1 multiplexer that makes a selection between two power supplies Vdd1 and Vdd2 and drives the load output with the voltage Vdd_apm. The circuit of Figure 1 is adaptive in that it is configured to select a specific power rail in response to an external reference, such as through the control signal input of the forward path and the control signal output of the feedback path. The switching signal (sel) in this example is at a voltage level (Vdd_aon) greater than the larger of Vdd1 and Vdd2. The switching voltage level Vdd_aon ensures that the transistors in the multiplexer 110 turn off when Vdd_aon is applied to their control inputs (e.g., base).

[0023]

[0033] The power management logic within the chip can select Vdd1 or Vdd2 at a given time according to the operating mode. As described above, an exemplary operating system kernel may include power management software that can control power usage within the chip. For example, the power management software may decide to put one or more central processing unit (CPU) cores into turbo mode and raise the voltage in one or more memory blocks to support the CPU turbo mode. Similarly, the power management software may decide to put one or more CPU cores into a low operating mode consistent with power saving during normal operation. In such a case, the power management software may lower the voltage in one or more memory blocks. Further, in this example, either raising or lowering the operating voltage in the memory block may include controlling the power multiplexer 110 to select either the higher or lower power supply in accordance with the operating mode.

[0024]

[0034] Figure 2 is a diagram of an exemplary power multiplexing architecture 200 according to one implementation. In this example, there are two power supplies, namely, the CX power supply and the MX power supply, and those power supplies may have different voltage levels (e.g., Vdd1 and Vdd2 in FIG. 1 respectively). The power multiplexing architecture 200 supplies the power output Vdd_apm to the load 230 by selecting the power rail associated with the CX power supply or the power rail associated with the MX power supply. Further, the power multiplexing architecture 200 can be used to cause a power collapse of the load 230, in which case both switches 211 and 212 will be turned off, thereby disconnecting the load 230 from both power rails.

[0025]

[0035] The power multiplexing architecture 200 includes two different switch types. Switch 211 is a first type of switch, and switch 212 is a second type of switch. In one implementation, switch 211 may have a low resistance (e.g., 1 ohm), while switch 212 may have a high resistance (e.g., 50 ohms). Of course, these values are exemplary, and the scope of implementation is not limited to these resistance values.

[0026]

[0036] Continuing with this example, switch 212 can be used during a first time period of the voltage switching operation to prevent inrush or surge current from the load 230. For example, when transitioning from a decayed power level to a CX power level, from a decayed power level to an MX power level, from an MX power level to a CX power level, or vice versa, switch 212 can be turned on (e.g., closed) while switch 211 can be turned off (e.g., open). Then, current flows through the high resistance switch 212 between the selected power rail and the load. After a certain (e.g., microsecond) time has elapsed, both switches 212 can be turned off, but the corresponding switch 211 can be turned on, thereby providing current through the low resistance switch during the duration of the steady state operation.

[0027]

[0037] For example, assume an example where the power multiplexing architecture 200 switches from a power decay to the voltage level associated with power supply CX. During the power decay, both switches 211 and 212 are turned off. In the first part of the voltage switching operation, the architecture 200 turns on switch 212a, which allows current to flow between the power rail of power supply CX and the load 230 at the high resistance associated with switch 212a. After a certain time has elapsed, the architecture 200 turns on switch 211a and turns off switch 212a, thereby allowing current to flow through the low resistance associated with switch 211a.

[0028]

[0038] Although each of switches 211 and 212 is shown as a single switch, various implementation forms may implement each of those switches as a number of switches. For example, the low-resistance switch 211 may be designed to include a number of individual transistors in parallel to achieve low resistance. In addition, the transistor size may be selected to achieve a desired resistance. The high-resistance switch 212 may also be selected according to the number and size to achieve a desired resistance.

[0029]

[0039] The power multiplexing architecture 200 provides the same functionality as described above with respect to the implementation form of FIG. 1, but additionally uses two different types of switches 211 and 212 to prevent inrush and protrusion during the switching operation. The two different types of switches 211 and 212 may be called a rest switch (211) and a minority switch (212) in some examples. Various implementation forms described herein may separate the minority switch and the rest switch into a first type of power multiplexer and a second type of power multiplexer as will be described in more detail below with respect to FIG. 5. Further, the switch 212 does not depend on the switch 211. Rather, the power multiplexer control will be described in more detail with respect to FIGS. 3 and 7.

[0030]

[0040] FIG. 3 is a diagram of an exemplary rest switch 300 according to one implementation form. For example, a p-type metal oxide semiconductor (PMOS) transistor 301 may correspond to the switch 211b in FIG. 2, and the PMOS transistor 302 may correspond to the switch 211a.

[0031]

[0041] The standby switch 300 makes a selection between two power supplies Vdd_mx and Vdd_cx. In one example, Vdd_mx represents the power supply that is used as default for the memory block, and Vdd_cx represents the variable power supply used by the processor. Continuing with this example, during the turbo operation mode, Vdd_cx can be increased and supplied to the memory block by the power multiplexer using the standby switch 300. During the non-turbo operation mode, the power multiplexer can select the Vdd_mx power supply for the memory block using the standby switch 300.

[0032]

[0042] The implementation form of FIG. 3 includes two enable signals En_1 and En_2, and two P-type metal oxide semiconductor (PMOS) transistors 301 and 302. The PMOS transistors 301 and 302 turn off when the gate-source voltage is 0 or higher, and turn on when the gate-source voltage is negative. Therefore, when En_1 is high and En_2 is low, the transistor 301 turns on, and the power multiplexer selects Vdd_mx to output as Vdd_apm. On the other hand, when En_1 is low and En_2 is high, the transistor 302 turns on, and the power multiplexer selects Vdd_cx.

[0033]

[0043] The inverter buffers 311, 312 and 313, 314 indicate drivers for the PMOS transistors 301, 302. For example, the inverter buffers 311, 312 are powered by Vdd_aon, so that when the output of the inverter buffer 312 is a high voltage (digital 1), Vdd_aon is applied to the gate of the transistor 301. Similarly, the inverter buffers 313, 314 are powered by Vdd_aon in the same way, so that when the output of the inverter buffer 314 is digital 1, Vdd_aon is applied to the gate of the transistor 302.

[0034]

[0044] Furthermore, the enable signals En_1 and En_2 are utilized such that only one of them is on at a given time, thereby preventing the scenario where Vdd_mx and Vdd_cx are short-circuited. Nevertheless, both En_1 and En_2 may be low, thereby neither power supply being selected.

[0035]

[0045] When transistor 301 is on and transistor 302 is off, the voltage Vdd_cx is applied to the gate of transistor 302. Vdd_aon is a switching voltage and is selected to be the higher of Vdd_mx and Vdd_cx, thereby ensuring that the gate-source voltage is 0 or higher even if the voltage level of Vdd_cx changes. Similarly, when transistor 301 is turned off, Vdd_aon is applied to its gate, thereby ensuring that the gate-source voltage is 0 or higher during its off state.

[0036]

[0046] Vdd_aon can be provided by one or more voltage generators that are separate from or can be included in a power multiplexer including one or more standby switches. Also, the enable signal can represent a specific implementation form of the switching signal (sel) in FIG. 1 and can be supplied by an enable logic circuit configuration block. Exemplary techniques for supplying Vdd_aon are described in more detail below with respect to FIG. 4.

[0037]

[0047] FIG. 4 is a diagram of an exemplary voltage generator 400 for the switching voltage Vdd_aon according to one implementation. As described above, the switching voltage Vdd_aon can be applied to transistors within standby switches such as transistors 301 and 302 in FIG. 3.

[0038]

[0048] The control signals Sel_mx and Sel_cx may be supplied by a controller such as the controller 701 in FIG. 7, which will be described in more detail below. Only one of the control signals Sel_mx and Sel_cx will be high (digital 1) at any given time, and the control signals Sel_mx and Sel_cx cause the voltage generator 400 to select either the voltage (Vdd_mx) associated with the MX power supply or the voltage (Vdd_cx) associated with the CX power supply as the switching voltage Vdd_aon.

[0039]

[0049] Although not shown in FIG. 4, the control signals Sel_mx and Sel_cx may be generated by a comparator that receives both Vdd_mx and Vdd_cx and outputs the control signals Sel_mx and Sel_cx based on a comparison of the voltage levels associated with Vdd_mx and Vdd_cx. For example, if Vdd_mx is higher than Vdd_cx, the comparator may output Sel_mx as a high voltage and Sel_cx as a low voltage. The reverse may also be true, so if Vdd_cx is higher, Sel_mx may be output as a low voltage and Sel_cx may be output as a high voltage.

[0040]

[0050] In the first example, the control signal Sel_mx is high and the control signal Sel_cx is low. As a result, a high voltage is applied to the gates of the PMOS transistor P3 and the N-type metal oxide semiconductor (NMOS) transistor N1. Similarly, a low voltage (digital 0) is applied to the gates of the transistors P4 and N2. The transistors P3 and N2 turn off, and the transistors N1 and P4 turn on, which applies a low voltage to the gates of the transistors P2 and P6 and a high voltage to the gates of the transistors P1 and P5. As a result, the transistors P2 and P6 turn on, and the transistors P1 and P5 turn off. Therefore, the voltage Vdd_aon becomes Vdd_mx.

[0041]

[0051] In the second example, Vdd_cx is selected. The control signal Sel_mx is low, and the control signal Sel_cx is high. As a result, a low voltage is applied to the gates of PMOS transistor P3 and NMOS transistor N1. A high voltage (digital 1) is applied to the gates of transistors P4 and N2. Transistors P3 and N2 turn on, and transistors N1 and P4 turn off, which applies a high voltage to the gates of transistors P2 and P6 and a low voltage to the gates of transistors P1 and P5. As a result, transistors P2 and P6 turn off, and transistors P1 and P5 turn on. Therefore, the voltage Vdd_aon becomes Vdd_cx.

[0042]

[0052] FIG. 5 is a diagram of exemplary power multiplexers 510, 520, and 530 according to some implementations. Specifically, FIG. 5 is provided to illustrate a contrast between an exemplary power multiplexer 510 that includes both a minority switch and a standby switch and an implementation that separates the minority switch into a first type of power multiplexer and the standby switch into a second type of power multiplexer.

[0043]

[0053] First, looking at the power multiplexer 510, it includes a minority switch 511 and a standby switch 512. As described above, in some implementations, combining the minority switch 511 and the standby switch 512 in a single power multiplexer unit such as a tile can lead to overcrowding of routing. Examples of the minority switch 511 and the standby switch 512 are provided in FIGS. 2 and 3 above. The power multiplexer 510 also includes an AON generator 515 that may conform to a circuit structure similar or identical to that described above with respect to FIG. 4. The comparator 513 may be used to provide a selection signal to the AON generator. For example, as described above with respect to FIG. 4, the switching voltage generator 400 receives the enable signals Sel_mx and Sel_cx, and in some implementations, the comparator 513 may provide the same or similar signals to the AON generator 515. The digital block 514 may include digital logic that provides other enable signals to the minority switch 511 and the standby switch 512 to cause the switches 511, 512 to select either the MX or CX power supply (or cause the load to power down). Examples of such enable signals include the 2-bit signal provided from the main tile 520 to the micro APM tile 530 in FIG. 7 (described in more detail below).

[0044]

[0054] In contrast, various implementations use two different types of power multiplexers, shown here as power multiplexer 520 and power multiplexer 530. Looking at power multiplexer 520, it may also be referred to herein as the first type of power multiplexer or as the main tile (Figure 7). Power multiplexer 520 includes a minority switch 521 that may be the same or similar to minority switch 511. In some implementations, the size of minority switch 521 may be increased to the maximum size that still allows the circuit to achieve the desired resistance. Comparator 522 may be the same or similar to comparator 513 and may apply a select signal to AON generator 515. Digital block 523 may be the same or similar to digital block 514 and may generate an enable signal that selects one or the other (or neither) of the power supplies for minority switch 521 and the sleep switch of micro APM tile 530.

[0045]

[0055] The second type of power multiplexer is shown as micro APM (micro adaptive power multiplexer) tile 530, which includes a sleep switch such as one or more of the sleep switches shown in Figure 3. In this example, the sleep switch of micro APM 530 is driven by Vdd_aon from AON generator 515 and is controlled by an enable signal from digital logic block 523. As described above, advantages of implementations that use the first and second types of power multiplexers include reducing routing overcrowding compared to the design of power multiplexer 510 and being able to use the semiconductor area efficiently.

[0046]

[0056] In some examples, there are an integer (xM) number of micro APM tiles 530 that receive an enable signal from a single power multiplexer 520. The number xM may be selected such that the combined resistance of the set of a large number of micro APM tiles 530 is greater than or equal to the combined resistance of the xN instances of power multiplexer 510.

[0047]

[0057] FIG. 6 is a diagram of different arrangements that can be used for the micro APM power tile 530 of FIG. 5 according to one implementation. Arrangement 650 provides a switching voltage generator 515 within a power multiplexer, along with a sleep switch 611 that can be the same as or similar to the sleep switch of FIG. 3. Also, arrangement 650 includes a driver 612 that can be the same as or similar to that implemented by the inverter buffers 311 - 314 of FIG. 3. Arrangement 650 is constructed such that the larger dimension is the vertical dimension. In contrast, arrangement 652 is similar to arrangement 650, but instead is implemented within a horizontal channel where the larger dimension is the horizontal dimension.

[0048]

[0058] Now, looking at arrangement 654, it is similar to arrangement 650 but does not include the switching voltage generator 515. As a result, arrangement 654 is smaller than arrangement 650. Arrangement 656 is similar to arrangement 654, but is implemented such that its larger dimension is the horizontal dimension instead of the vertical dimension.

[0049]

[0059] The implementation of FIG. 6 shows the concept that a second type of power multiplexer, e.g., the micro APM tile 530 of FIG. 5, may or may not include the switching voltage generator 515. If the switching voltage generator 515 is not included in the micro APM tile, it may be included elsewhere in the chip, but there is a trade - off in terms of switching voltage routing between different micro APM tiles. This concept is further explained with respect to FIGS. 8 - 11.

[0050]

[0060] FIG. 7 is a diagram of an exemplary power multiplexing architecture 700 according to one implementation. The power multiplexing architecture 700 includes a main tile 520, a micro APM tile 530, and a controller 701. The main tile 520 includes a few switches as switching logic as described above with respect to FIG. 5. Specifically, the main tile 520 of FIG. 7 can be implemented in the same or similar manner as the first type of power multiplexer 520 of FIG. 5.

[0051]

[0061] The micro APM tile 530 can be the same as or similar to the second type of power multiplexer 530 shown in FIGS. 5 and 6. The controller 701 may include a processing unit that uses a control signal 704 to control the main tile 520 in order to select a power rail or to power down a load (not shown). For example, the main tile 520 may decode the control signal 704 to generate a control signal 703. The main tiles 520 are arranged in a daisy chain with each other and with the controller 701. In one implementation, the controller 701 controls the main tile 520a to select the power rail MX. The main tile 520a then controls the micro APM tiles 530a - d to select the power rail MX. For example, the main tile 520a may use the control signal 703 corresponding to the enable signals En_1 and En_2 of FIG. 3 to control the micro APM tiles 530a - d. The micro APM tiles 530a - d are also arranged in a loop such that the micro APM tile 530a first receives the control signal 703, the control signal 703 is passed to the micro APM tiles 530b - d, and then returned to the main tile 520a.

[0052]

[0062] When the main tile 520a receives the control signal 703 from the micro APM tile 530D, the main tile 530a passes the control signal 704 to the main tile 520b, and the main tile 520b performs the same or similar power multiplexing as the main tile 520a. For example, the main tile 520b also has the micro APM tiles 530e - h in the loop, causes the micro APM tiles 530e - h to perform power multiplexing, and when the main tile 520b receives the control signal 703 from the micro APM tile 530h, the main tile 520b may transmit the control signal 704 to the main tile 520c. Of course, the scope of the implementation is not limited to the specific number of main tiles 520 or micro APM tiles 530 shown in FIG. 7. Rather, the architecture 700 can be scaled to be appropriate for a given application.

[0053]

[0063] The micro APM tiles 530a - d are arranged in a loop, thereby enabling either the main tile 520a or the controller 701 to check for faults. The same can be said for the loop containing the micro APM tiles 530e - h. Due to the daisy - chain arrangement of the main tiles 520a - 520c, the controller 701 can check for faults in the main tile 520 in a similar manner. Further, in the example of FIG. 7, there are fewer main tiles 520 than micro APM tiles 530, whereby a larger current can flow through the minority switches in the main tile 520 than is assumed for the standby switches in the micro APM tile 530. Therefore, the size of the minority switches in the main tile 520 can be made appropriate for the assumed current.

[0054]

[0064] In the example of FIG. 7, the micro APM tiles 530a - d include a switching voltage generator such as the switching voltage generator 515 of FIGS. 5 and 6. Accordingly, the controller 701 may include a comparator that passes a control signal 702 to each of the micro APM tiles 530a - d. The control signal 702 may correspond to Sel_mx and Sel_cx of FIG. 4. In some implementations, the main tiles 520a and 520b may also include a switching voltage generator and may also receive the control signal 702 similarly.

[0055]

[0065] Although not shown in FIG. 7, each of the main tiles 520 and each of the micro APM tiles 530 may be coupled to a load, as schematically shown above in FIG. 2. For example, each of the micro APM tiles 530a - d supplies power to different loads such as different memory blocks in a memory unit or different processing circuits, and the main tile 520a supplies power to each of those different loads associated with each of the micro APM tiles 530a - d. As described above, the main tile 520 includes minority switches for high resistance, and the micro APM tile 530 includes standby switches for low resistance.

[0056]

[0066] Architecture 700 provides a PDN for a given power domain within the chip. Thus, each of the main tile 520 and the micro APM tile 530 is assumed to select the same voltage (e.g., either MX or CX) or power collapse at a given time. In other words, the PDN shown by architecture 700 does not mix and match voltage levels. To the extent that the chip may have other power domains operating independently, the chip may implement one or more other PDNs having the same or a similar structure as that shown in FIG. 7. An example of an exemplary chip 1300 including power domains 0 to 3 is shown in FIG. 13. Each of the different power domains includes a PDN according to architecture 700. The exemplary chip 1300 may include a central processing unit (CPU), a graphics processing unit (GPU), memory, a modem, etc. within a system-on-chip (SOC). However, since the power multiplexing described herein may be applied to any chip having memory and / or processing, the scope of the implementation form is not limited to SOCs.

[0057]

[0067] FIGS. 8-10 show different arrangements of the PDN according to various implementation forms. For example, the basic building blocks of the main tile and the micro APM can be mixed and matched to implement an adaptive power multiplexing system having different trade-offs such as voltage drop, semiconductor area, routing congestion, etc. As described above, since the sleep switch of the micro APM is separated from the few switches of the main tile, the pitch of different tiles can be increased or decreased as appropriate.

[0058]

[0068] For example, the selection of tile pitch can take into account various factors such as the drop of the Vdd_aon rail during multiplexer switching. The drop of the Vdd_aon rail can be a function of factors such as minority switch strength, load leakage, and parasitic capacitance on the Vdd_aon rail. In some implementations, stronger minority switches can lead to lower drops, load leakage can lead to higher drops, and longer Vdd_aon rails can lead to increased parasitic capacitance. In the case of the Vdd_aon rail, the length can be affected by the placement of the switching voltage generator within the PDN. In scenarios where each micro APM includes a switching voltage generator, the Vdd_aon (switching voltage) routing can be minimized. In contrast, implementations that include a stand-alone switching voltage generator or have the switching voltage generator disposed in only a few micro APMs may exhibit increased switching voltage routing with a longer length of the Vdd_aon rail.

[0059]

[0069] However, engineering trade-offs can be applied to each of these situations. For example, a switching voltage generator within each micro APM results in a larger micro APM while minimizing the drop of the Vdd_aon rail, but moving the Vdd_aon generator to only a few micro APMs or to a stand-alone circuit can enable a simpler micro APM at the cost of increased voltage routing.

[0060]

[0070] First, referring to FIG. 8, FIG. 8 shows an exemplary PDN 800 according to one implementation. The micro APM tile is exemplified by micro APM tile 811. The micro APM tile 811 is included within loop 810, and other loops 820, 830, and 840 are implemented the same as or similar to loop 810. Loop 810 includes a main tile 814 that can be the same as or similar to the main tile 520 of FIGS. 5 and 7. The main tile 814 can communicate with the micro APM via a communication path 812 that carries an enable signal such as control signal 703 of FIG. 7.

[0061]

[0071] As shown in FIG. 7, the main tiles 814-817 can be arranged in a daisy chain loop. The communication path 813 carries control signals such as the control signal 704 in FIG. 7.

[0062]

[0072] It should be noted in FIG. 8 that each of the micro APM tiles (e.g., micro APM tile 811) includes a sleep switch as switching logic and a switching voltage generator. In other words, each of the micro APM tiles generates its own switching voltage (Vdd_aon), thereby reducing or eliminating any need to route the switching voltage between the micro APM tiles. Thus, the implementation of FIG. 8 reduces switching voltage routing in exchange for larger and more complex micro APM tiles.

[0063]

[0073] FIG. 9 is a diagram of an exemplary PDN 900 according to one implementation. Since the communication paths 812 and 813 are the same, the main tiles 814-817 are arranged in the same daisy chain, and the loops 910, 920, 930, 940 have the same shape as the loops 810, 820, 830, 840, the PDN 900 is similar to the PDN 800.

[0064]

[0074] The difference between PDN900 and PDN800 is that PDN900 only includes two micro APM tiles with an integrated switching voltage generator for each loop. Taking loop 910 as an example, it includes micro APM tiles 811 and 912 with an integrated switching voltage generator. The remaining micro APM tiles (exemplified by micro APM tile 911) within loop 910 include a standby switch but do not include an integrated switching voltage generator. In other words, micro APM tile 911 can be the same or similar to items 654 and 656 in FIG. 6, and micro APM tiles 811 and 912 can be the same or similar to items 650 and 652 in FIG. 6. As a result, PDN900 uses switching voltage routing to supply switching voltage to those micro APM tiles that do not have an integrated switching voltage generator among the micro APM tiles. Switching voltage routing uses horizontal routing as exemplified by power rail 925 and vertical routing as exemplified by power rail 926.

[0065]

[0075] Micro APM tiles such as micro APM tile 911 are smaller and less complex than micro APM tiles 811 and 912 because they do not include an integrated switching voltage generator. Smaller micro APM tiles such as micro APM tile 911 can enable a finer-grained arrangement for switching logic, thereby allowing such micro APM tiles to be arranged closer to each other and shortening communication path 812. However, the overhead of switching voltage distribution is higher than that in PDN800, and the switching voltage distribution unit is generally assumed to become more complex as the ratio of micro APM tile 911 to micro APM tile 811 increases.

[0066]

[0076] Figure 10 is a diagram of an exemplary PDN1000 according to one implementation. In PDN1000, since no micro APM tile includes integrated switching voltage generation, PDN1000 is different from PDN800 and PDN900. Rather, each of loops 1010, 1020, 1030, 1040 is made using smaller micro APM tiles such as micro APM tile 911. Switching voltage generation is provided by stand-alone switching voltage generation units 1011, 1012 within loop 1010. The other loops 1020, 1030, 1040 are configured similarly to loop 1010.

[0067]

[0077] The use of stand-alone switching voltage generation units 1011, 1012 involves a more complex voltage routing structure than that found in either PDN800 or PDN900. A switching voltage distribution section as exemplified by horizontal power rails 1025, 1026, 1027 and vertical power rails 1031 - 1036 that serve each of loops 1010, 1020, 1030, 1040 (in the case of loop 1020). PDN1000 represents a further trade-off between using smaller micro APM tiles 911 that allow for a finer placement of standby switches and a more complex switching voltage routing.

[0068]

[0078] Of course, the examples in FIGS. 8 - 10 are merely examples. The number of micro APM tiles within a loop, the number of loops, the number of main tiles, and the number of switching voltage rails can be adjusted to be appropriate for a given application. In other words, the specific structure of the implementations in FIGS. 8 - 10 can be appropriately modified to supply a desired voltage to a given number of loads within the application.

[0069]

[0079] FIG. 11 is a diagram of an exemplary PDN 1100 applied to a memory device 1110 according to one implementation. The memory device 1110 can be any suitable memory device, such as a group like a static random-access memory (SRAM) memory block. The power multiplexing functionality is disposed in columns 1120 and 1130. The power multiplexing functionality is provided by main tiles 1113 - 1119, and the micro APM tiles are exemplified by a micro APM tile 112 having an integrated switching voltage generator and a micro APM tile 1111 not having an integrated switching voltage generator. The micro APM tiles can be arranged in a loop as shown in FIGS. 8 - 10. For example, an exemplary loop is shown as items 1140, 1150, 1160, 1170, 1180, 1190, 1191, and 1192.

[0070]

[0080] FIG. 11 is provided to illustrate that the power multiplexing hardware can be physically arranged on the chip in any suitable manner. Specifically, in FIG. 11, the power multiplexing hardware is disposed within columns 1120, 1130 on opposite sides of the memory device 1110. Although not shown in FIG. 11, the main tiles 1113 - 1119 may be in a daisy chain arrangement as shown in FIGS. 7 - 10, and the micro APM tiles may be arranged in loops 1140, 1150, 1160, 1170, 1180, 1190, 1191, and 1192 as described above with respect to FIGS. 7 - 10.

[0071]

[0081] Further, each of loops 1140, 1150, 1160, 1170, 1180, 1190, 1191, and 1192 can service individual memory blocks within memory device 1110 in any suitable manner. For example, each of loops 1140, 1150, 1160, 1170, 1180, 1190, 1191, and 1192 can service the physically closest of the memory blocks that reach from each side towards the center such that each of the blocks within memory device 110 is serviced by at least one power multiplexing loop.

[0072]

[0082] Of course, the scope of the implementation form is not limited to the physical arrangement shown in FIG. 11. Rather, in other implementation forms, the micro APM tiles may be dispersed around the chip as needed.

[0073]

[0083] The implementation forms described above with respect to FIGS. 5 to 11 can provide advantages over other designs that use only a single type of power multiplexer that combines both a minority switch and a standby switch. As described above, a design that combines a minority switch and a standby switch in a single physical power multiplexing structure may, at least in part, impose a routing cost on the many transistors that make up the switching logic (minority switch and standby switch). Specifically, the routing cost may include using an undesired number of metal layers within the chip. The metal routing within the chip may be of a nature such that as the vertical use of the metal layers by the components increases, the horizontal use of the routing space may further increase. Thus, not only can the routing become more complex, but in addition, the routing may use an undesired amount of silicon area.

[0074]

[0084] In contrast, the various implementations described herein may use at least two types of power multiplexers. A first type of power multiplexer (e.g., main tile 520) may include high-resistance switching logic (e.g., few switches), and a second type of power multiplexer (e.g., micro APM tile 530) may include low-resistance switching logic (e.g., standby switches). The first type of power multiplexer is physically separated from the second type of power multiplexer, and the implementation may include a communication path for providing an enable signal from the first type of power multiplexer, through a loop of the second type of power multiplexer, and back to the first type of power multiplexer. The physical separation of the two different types of power multiplexers can reduce the number of metal layers used for routing, and thus can reduce the silicon area used overall for the same power multiplexing functionality. The reduced routing complexity and the use of less semiconductor area can potentially lead to lower manufacturing costs.

[0075]

[0085] A flowchart of an exemplary method 1200 for multiplexing among multiple power supplies is shown in FIG. 12. In one example, method 1200 is performed by the circuitry shown in FIGS. 1-11. The circuitry may operate under the control of a power management unit that may include hardware and / or software functionality in a processor (e.g., a CPU) of a computing device included within a SOC (not shown) or other structure. For example, the controller 701 of FIG. 7 may represent a stand-alone controller in another processing device such as a CPU or other processor, or hardware and / or software functionality. In some examples, the power management unit includes a processing circuit configuration that executes computer-readable instructions to select one power supply or another as the operating voltage for one or more memory blocks.

[0076]

[0086] In Action 1210, the system sends an enable signal from a first power multiplexer of a first type to a second power multiplexer of a second type. An example where main tile 520a sends control signal 703 to micro APM tiles 530a - d is shown in FIG. 7. In this example, control signal 703 may include enable signals such as En_1 and En_2 in FIG. 3.

[0077]

[0087] In Action 1220, the system switches a first load from a first power source to a second power source by the first power multiplexer and by the second power multiplexer. Looking at the example in FIG. 7, main tile 520a switches the load from the first power source to the second power source (e.g., from CX to MX, or vice versa), and causes micro APM tiles 530 to switch their respective loads from the first power source to the second power source. The first power multiplexer can be switched from the first power source to the second power source in response to a signal from the controller, and the second power multiplexer can be switched from the first power source to the second power source by an enable signal. Each of the individual micro APM tiles 530a - d services its respective load, while main tile 520a services each of these different loads and switches the power for each of these different loads.

[0078]

[0088] Furthermore, each of the first power multiplexer and the second power multiplexer may receive a switching voltage that is equal to or higher than the highest voltage level of the first power source and the second power source. A switching voltage generator 400 is shown, and an example of generating Vdd_aon is described with respect to FIG. 4.

[0079]

[0089] In Action 1230, the first power multiplexer receives an enable signal. For example, in the implementation of FIG. 7, the micro APM tile 530 is within the loop, and the control signal 703 is fed back to the main tile 520a. In some examples, by feeding back the control signal 703 to the main tile 520a, the main tile 520a can confirm the operability of the micro APM tile 530 within the loop.

[0080]

[0090] In Action 1240, the first power multiplexer can send a control signal to a third power multiplexer, and the third power multiplexer is of the first type. An example is shown in FIG. 7 where after the main tile 520a receives the control signal 703 from the micro APM tile 530b, it can send the control signal 704 to the main tile 520b. The main tile 520b may also have a loop of micro APM tiles 530, and after that loop passes and returns the control signal 704 to the main tile 520b, the same control signal 703 can be further sent to an additional main tile 520c. This action can be executed sequentially for each main tile 520 within the daisy chain until the control signal 704 is fed back to the controller 701. As a result, each of the main tiles 520 and the loops of their respective micro APM tiles 530 can switch their respective loads from the first power source to the second power source.

[0081]

[0091] The scope of the implementation is not limited to the actions shown in FIG. 12. Rather, other implementations may add, omit, rearrange, or modify one or more actions. In another example, instead of switching from the first power source to the second power source, the main tiles 520 and the micro APM tiles 530 may switch from the second power source to the first power source, or they may completely power down their loads. Further, some implementations may include repeatedly performing Actions 1210 - 1240 many times during normal operation when the processor on the chip transitions from one power mode to another.

[0082]

[0092] Various implementation forms are further described with respect to the following clauses. Clause 1. A first type of first power multiplexer coupled to a first power supply and a second power supply, the first power multiplexer including first switching logic disposed between the first power supply, the second power supply, and a load, the first power multiplexer; A second type of second power multiplexer coupled to the first power supply and the second power supply, the second power multiplexer being second switching logic between the first power supply, the second power supply, and a load, the second switching logic including an enable input coupled to the first power multiplexer, the second power multiplexer including the second switching logic; A system-on-chip (SOC). Clause 2. The SOC according to Clause 1, wherein the first switching logic includes a first plurality of P-type metal oxide semiconductor (PMOS) transistors, the second switching logic includes a second plurality of PMOS transistors, and further, the first plurality of PMOS transistors are smaller in size than the second plurality of PMOS transistors. Clause 3. The SOC according to Clause 1, wherein the first switching logic includes a first plurality of P-type metal oxide semiconductor (PMOS) transistors, the second switching logic includes a second plurality of PMOS transistors, and further, the first plurality of PMOS transistors have a combined resistance smaller than the combined resistance of the second plurality of PMOS transistors. Clause 4. A second type of third power multiplexer coupled to the first power supply and the second power supply, the third power multiplexer being third switching logic between the first power supply, the second power supply, and another load, the third switching logic including an additional enable input coupled to the first power multiplexer, further comprising the third power multiplexer including the third switching logic; The second power multiplexer and the third power multiplexer are coupled in a loop with the first power multiplexer; The SOC according to any one of Clauses 1 to 3. Clause 5. The SOC according to Clause 4, wherein the loop comprises a first path from the first power multiplexer to the enable input of the second switching logic, a second path from the enable input of the second switching logic to an additional enable input, and a third path from the additional enable input to the first power multiplexer. Clause 6. The SOC according to Clause 4, wherein the second power multiplexer includes a first voltage generator configured to provide a switching voltage to the second switching logic, and further wherein the third power multiplexer includes a second voltage generator configured to provide a switching voltage to the third switching logic. Clause 7. The SOC according to Clause 4, wherein the second power multiplexer includes a first voltage generator configured to provide a switching voltage to the second switching logic and to the third switching logic. Clause 8. The SOC according to Clause 4, further comprising a first voltage generator physically separated from the first power multiplexer and from the second power multiplexer, the first voltage generator being configured to provide a switching voltage to the second switching logic and to the third switching logic. Clause 9. A fourth power multiplexer of a second type coupled to a first power source and a second power source, the fourth power multiplexer including a fourth switching logic between the first power source and the second power source and another load, the fourth switching logic including an additional enable input coupled to the first power multiplexer. Further comprising a control circuit coupled to a plurality of voltage generators associated with each of the first power multiplexer, the second power multiplexer, and the fourth power multiplexer. The SOC according to Clause 1. Clause 10. The SOC according to Clause 9, wherein the control circuit includes a comparator coupled to the first power source and to the second power source, and the output of the comparator is coupled to the plurality of voltage generators. Clause 11. A fifth power multiplexer of a second type coupled to a first power source and a second power source, the fifth power multiplexer being a fifth switching logic between the first power source, the second power source, and another load, the fifth switching logic including an additional enable input coupled to the first power multiplexer, the fifth power multiplexer including the fifth switching logic further comprising a plurality of memory bit cells arranged in a plurality of rows and a plurality of columns The first power multiplexer, the second power multiplexer, and the fifth power multiplexer are arranged in a column parallel to a first column among the plurality of columns The second power multiplexer includes a first voltage generator configured to provide a switching voltage to the fifth switching logic in the second switching logic The SOC according to clause 1 Clause 12 Transmitting an enable signal from a first power multiplexer of a first type to a second power multiplexer of a second type Switching a first load from a first power source to a second power source by the first power multiplexer and the second power multiplexer, the second power multiplexer switching the first load in response to the enable signal Receiving an enable signal in the first power multiplexer, including Method Clause 13. The second power multiplexer is disposed in a loop with a third power multiplexer of the first type and a fourth power multiplexer of the first type, the fourth power multiplexer being coupled to the first power multiplexer The enable signal is received in the first power multiplexer from the fourth power multiplexer through a communication path The first power multiplexer and the third power multiplexer switch a second load from the first power source to the second power source The method according to clause 12 Clause 14. The method according to clause 13, wherein the first power multiplexer and the fourth power multiplexer switch the third load from the first power source to the second power source. Clause 15. After receiving an enable signal in the first power multiplexer, further comprising transmitting, from the first power multiplexer to a fifth power multiplexer of the first type, a control signal instructing the fifth power multiplexer to switch the fourth load from the first power source to the second power source. The method according to clause 12. Clause 16. The method according to clause 15, wherein the first power multiplexer and the fifth power multiplexer are arranged in a daisy chain with a controller that provides a control signal. Clause 17. A power distribution network (PDN) on a semiconductor chip, the PDN comprising: a first means for multiplexing between a first power source and a second power source; a second means for multiplexing between the first power source and the second power source, the second means being configured to receive an enable signal from the first means, the enable signal causing the second means to select between the first power source, the second power source, and a power collapse; and wherein the first means comprises a first type of power multiplexer, the second means comprises a second type of power multiplexer different from the first type of power multiplexer, and further, the second means comprises a plurality of second type of power multiplexers arranged in a loop to feedback the enable signal to the first means. Clause 18. A daisy chain of first type of power multiplexers including the first means, the daisy chain further comprising a daisy chain configured to pass a control signal between the daisy chains of power multiplexers. The PDN according to clause 17. Clause 19. The PDN according to either clause 17 or 18, wherein the first type of power multiplexer includes a first switching logic having a lower resistance than a second switching logic of the second type of power multiplexer. Clause 20. The PDN according to any of clauses 17 or 18, wherein each of the second type of power multiplexers includes respective means for generating a switching voltage. Clause 21. The PDN according to any of clauses 17 or 18, wherein some but not all of the second type of power multiplexers include respective means for generating a switching voltage, and the PDN further comprises means for distributing the switching voltage among the second type of power multiplexers. Clause 22. The PDN according to any of clauses 17 or 18, further comprising means for generating a switching voltage, wherein the means for generating the switching voltage is physically separated from each of the first means and the second means, and the PDN further comprises means for distributing the switching voltage among the second type of power multiplexers. Clause 23. The PDN according to any of clauses 17 or 18, wherein the PDN is physically arranged along opposite sides of a memory device. Clause 24. A first power multiplexer of the first type and a second power multiplexer of the first type, wherein the first power multiplexer and the second power multiplexer are arranged in a daisy chain with a controller, and the daisy chain passes a control signal from the controller to the first power multiplexer and then to the second power multiplexer and feeds back the control signal to the controller, and the first power multiplexer and the second power multiplexer; A third power multiplexer of the second type and a fourth power multiplexer of the second type arranged within a first loop from the first power multiplexer, wherein the first loop passes a first enable signal from the first power multiplexer to the third power multiplexer and the fourth power multiplexer and then back to the first power multiplexer, and the third power multiplexer and the fourth power multiplexer; A fifth power multiplexer and a sixth power multiplexer of a second type disposed within a second loop from a second power multiplexer, wherein the second loop passes a second enable signal from the second power multiplexer to the fifth power multiplexer and the sixth power multiplexer and then back to the second power multiplexer, and the fifth power multiplexer and the sixth power multiplexer. Semiconductor chip. Clause 25. The semiconductor chip according to clause 24, wherein the first type includes first switching logic, the second type includes second switching logic, and the first switching logic has a higher resistance than the resistance of the second switching logic. Clause 26. The semiconductor chip according to clause 24, wherein each of the third power multiplexer and the fourth power multiplexer includes an integrated switching voltage generation circuit configuration. Clause 27. The semiconductor chip according to clause 24, wherein the third power multiplexer includes an integrated switching voltage generation circuit configuration that is not included in the fourth power multiplexer, and the semiconductor chip further includes a voltage distribution unit configured to provide a switching voltage from the third power multiplexer to the fourth power multiplexer. Clause 28. The semiconductor chip according to clause 24, further comprising a switching voltage generation circuit configuration physically separated from the third power multiplexer and the fourth power multiplexer, and further comprising a voltage distribution unit configured to provide a switching voltage to the third power multiplexer and the fourth power multiplexer. Here, as will be understood by those skilled in the art and depending on the specific application at hand, many modifications, substitutions, and variations can be made in and to the materials, devices, configurations, and methods of use of the present disclosure without departing from the spirit and scope of the present disclosure. In light of this, since the specific embodiments described and illustrated herein are only by way of some examples thereof, the scope of the present disclosure should not be limited to the scope of such specific implementations, but rather should be fully equivalent to the scope of the claims appended hereinafter and their functional equivalents.

Claims

1. A first type of first power multiplexer coupled to a first power supply and a second power supply, the first power multiplexer including first switching logic disposed between the first power supply, the second power supply, and a load, the first power multiplexer; A second type of second power multiplexer coupled to the first power supply and the second power supply, the second power multiplexer including second switching logic between the first power supply and the second power supply and the load, the second switching logic including an enable input coupled to the first power multiplexer, a second power multiplexer including the second switching logic; A system-on-chip (SOC).

2. The SOC according to claim 1, wherein the first switching logic includes a first plurality of P-type metal oxide semiconductor (PMOS) transistors, the second switching logic includes a second plurality of PMOS transistors, and further, the first plurality of PMOS transistors are smaller in size than the second plurality of PMOS transistors.

3. The SOC according to claim 1, wherein the first switching logic includes a first plurality of P-type metal oxide semiconductor (PMOS) transistors, the second switching logic includes a second plurality of PMOS transistors, and further, the first plurality of PMOS transistors have a collective resistance smaller than the collective resistance of the second plurality of PMOS transistors.

4. A third type of third power multiplexer coupled to the first power supply and the second power supply, the third power multiplexer including third switching logic between the first power supply and the second power supply and another load, the third switching logic including an additional enable input coupled to the first power multiplexer, further comprising a third power multiplexer including the third switching logic; The second power multiplexer and the third power multiplexer are coupled in a loop with the first power multiplexer; The SOC according to claim 1.

5. The loop includes a first path from the first power multiplexer to the enable input of the second switching logic, a second path from the enable input of the second switching logic to the additional enable input, and a third path from the additional enable input to the first power multiplexer. The SOC according to claim 4.

6. The second power multiplexer includes a first voltage generator configured to provide a switching voltage to the second switching logic. Further, the third power multiplexer includes a second voltage generator configured to provide the switching voltage to the third switching logic. The SOC according to claim 4.

7. The second power multiplexer includes a first voltage generator configured to provide a switching voltage to the second switching logic and the third switching logic. The SOC according to claim 4.

8. The SOC further includes a first voltage generator physically separated from the first power multiplexer and the second power multiplexer. The first voltage generator is configured to provide a switching voltage to the second switching logic and the third switching logic. The SOC according to claim 4.

9. A fourth power multiplexer of the second type coupled to the first power supply and the second power supply. The fourth power multiplexer includes a fourth switching logic between the first power supply and the second power supply and another load. The fourth switching logic includes an additional enable input coupled to the first power multiplexer. A fourth power multiplexer including the fourth switching logic. The SOC further includes a control circuit coupled to a plurality of voltage generators associated with each of the first power multiplexer, the second power multiplexer, and the fourth power multiplexer. The SOC according to clause 1.

10. The control circuit includes a comparator coupled to the first power supply and the second power supply. The output of the comparator is coupled to the plurality of voltage generators. The SOC according to claim 9.

11. A fifth power multiplexer of the second type coupled to the first power source and the second power source, wherein the fifth power multiplexer is a fifth switching logic between the first power source, the second power source, and another load, and the fifth switching logic includes an additional enable input coupled to the first power multiplexer, a fifth power multiplexer including fifth switching logic; Further comprising a plurality of memory bit cells arranged in a plurality of rows and a plurality of columns; The first power multiplexer, the second power multiplexer, and the fifth power multiplexer are arranged in a column parallel to a first column among the plurality of columns; The second power multiplexer includes a first voltage generator configured to provide a switching voltage to the fifth switching logic in the second switching logic; The SOC according to claim 1.

12. Transmitting an enable signal from a first power multiplexer of the first type to a second power multiplexer of the second type; Switching a first load from a first power source to a second power source by the first power multiplexer and the second power multiplexer, wherein the second power multiplexer switches the first load in response to the enable signal; Receiving the enable signal in the first power multiplexer; Method.

13. The second power multiplexer is disposed in a loop with a third power multiplexer of the first type and a fourth power multiplexer of the first type, and the fourth power multiplexer is coupled to the first power multiplexer; The enable signal is received in the first power multiplexer through a communication path from the fourth power multiplexer; The first power multiplexer and the third power multiplexer switch a second load from the first power source to the second power source; The method according to claim 12.

14. The method according to claim 13, wherein the first power multiplexer and the fourth power multiplexer switch a third load from the first power source to the second power source.

15. After receiving the enable signal in the first power multiplexer, a control signal is transmitted from the first power multiplexer to the fifth power multiplexer of the first type, the control signal instructing the fifth power multiplexer to switch a fourth load from the first power supply to the second power supply. The method according to claim 12.

16. The method according to claim 15, wherein the first power multiplexer and the fifth power multiplexer are arranged in a daisy chain with a controller providing the control signal.

17. A power distribution network (PDN) on a semiconductor chip, the PDN comprising: a first means for multiplexing between a first power supply and a second power supply; a second means for multiplexing between the first power supply and the second power supply, the second means being configured to receive an enable signal from the first means, the enable signal causing the second means to select between the first power supply, the second power supply, and a power collapse; the first means comprising a first type of power multiplexer, the second means comprising a second type of power multiplexer different from the first type of power multiplexer, and further, the second means comprising a plurality of the second type of power multiplexer arranged in a loop for feeding back the enable signal to the first means.

18. A daisy chain of the first type of power multiplexer including the first means, the daisy chain further comprising a daisy chain configured to pass a control signal between the daisy chains of the power multiplexers. The PDN according to clause 17.

19. The PDN according to claim 17, wherein the first type of power multiplexer includes a first switching logic having a lower resistance than a second switching logic of the second type of power multiplexer.

20. The PDN according to claim 17, wherein each of the second type of power multiplexer includes respective means for generating a switching voltage.

21. Some, but not all, of the second type of the power multiplexer includes respective means for generating a switching voltage, and the PDN further includes means for distributing the switching voltage among the second type of the power multiplexer. The PDN according to claim 17.

22. The PDN further includes means for generating a switching voltage, the means for generating the switching voltage is physically separated from each of the first means and the second means, and the PDN further includes means for distributing the switching voltage among the second type of the power multiplexer. The PDN according to claim 17.

23. The PDN according to claim 17, wherein the PDN is physically disposed along opposite sides of a memory device.

24. A first power multiplexer of a first type and a second power multiplexer of the first type, wherein the first power multiplexer and the second power multiplexer are arranged in a daisy chain with a controller, and the daisy chain passes a control signal from the controller to the first power multiplexer, then to the second power multiplexer, and feeds back the control signal to the controller. The first power multiplexer and the second power multiplexer, A third power multiplexer and a fourth power multiplexer of a second type disposed within a first loop from the first power multiplexer, wherein the first loop passes a first enable signal from the first power multiplexer to the third power multiplexer and the fourth power multiplexer, and then back to the first power multiplexer. The third power multiplexer and the fourth power multiplexer, A fifth power multiplexer and a sixth power multiplexer of the second type disposed within a second loop from the second power multiplexer, wherein the second loop passes a second enable signal from the second power multiplexer to the fifth power multiplexer and the sixth power multiplexer, and then back to the second power multiplexer. The fifth power multiplexer and the sixth power multiplexer, comprising A semiconductor chip.

25. The semiconductor chip according to claim 24, wherein the first type includes a first switching logic, the second type includes a second switching logic, and the first switching logic has a higher resistance than the resistance of the second switching logic.

26. The semiconductor chip according to claim 24, wherein each of the third power multiplexer and the fourth power multiplexer includes an integrated switching voltage generation circuit configuration.

27. The semiconductor chip according to claim 24, wherein the third power multiplexer includes an integrated switching voltage generation circuit configuration that is not included in the fourth power multiplexer, and the semiconductor chip further includes a voltage distribution unit configured to provide a switching voltage from the third power multiplexer to the fourth power multiplexer.

28. The semiconductor chip according to claim 24, further comprising a switching voltage generation circuit configuration physically separated from the third power multiplexer and the fourth power multiplexer, and the semiconductor chip further comprising a voltage distribution unit configured to provide a switching voltage to the third power multiplexer and the fourth power multiplexer.

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