Cascode normally-off switch using a driver and self-bias

Abstract

The electronic component includes a semiconductor device package. The semiconductor device package includes a conductive structure package base, a first terminal configured to be connected to an inductive load, and a second terminal configured to be connected to a common node or a circuit ground. The package further includes an enhancement-mode transistor and a depletion-mode III-N transistor in a cascode configuration. The enhancement-mode transistor is monolithically integrated with an IC controller and a gate driver on a common silicon substrate, the anode of the rectifier diode is connected to the drain of the enhancement-mode transistor, the cathode of the rectifier diode is connected to the voltage input terminal of the IC controller, and the reservoir capacitor has a first terminal connected to the cathode of the rectifier diode and a second terminal connected to the conductive structure package base.

Description

Technical Field

[0001] The disclosed technology relates to semiconductor electronics and circuits designed for power conversion and related systems.

Background Art

[0002] Power converters are generally used to convert one DC voltage level to another or to convert an AC voltage to a DC voltage. The desire to improve power conversion efficiency has been increasing with the growing demand and requirements for electronic systems such as mobile devices, computers, power supplies, and electric vehicles. Consumer electronics are typically manufactured without an internal power source and are instead powered by a small power supply directly built into an AC plug. These power supplies can draw some power (e.g., from the wall) even when they are not supplying power to a load (e.g., a phone, etc.). Switching power converters use active elements (e.g., bipolar junction transistors) that repeatedly draw energy even when the system is in an "offline" or idle state. Considering how many of these types of power converters are in use and also the fact that they rarely have their plug unplugged or are disconnected from the input power, this energy consumption can be high. Typical topologies used in switching power converters are forward, flyback, boost, and buck converters.

[0003] A switching power converter typically requires a low-voltage control circuit, such as an integrated circuit (e.g., an IC controller), that can turn on and off a primary power device, such as a power MOSFET, in response to the required output voltage and current of the power converter. FIG. 1 shows a prior art switching power supply. As seen in FIG. 1, the power stage of the switching power supply 100 includes several main elements: a power switch 10 (such as a silicon MOSFET), an IC controller 11 that generates signals (e.g., at a pulse-width modulation pin) to turn the power switch "on" and "off", and a gate drive circuit 12 (e.g., an amplifier) to apply the signals to the power switch 10. The power supply 100 can include a current sense (CS) connector 13 with one end connected to the source of the power switch 10 and the other end connected to the CS pin of the IC controller 11. The current sense connector can have a resistive element 14 connected between the current sense node connection at the power switch source and a common node or ground rail. The power switch 10 is connected in series with an inductive element 15, such as an inductor or transformer winding. The inductive element is connected to a positive input voltage 16, which is, for example, a wall outlet or mains power (e.g., 120V or 240V or higher). A second inductive component 19 is magnetically coupled to the first inductive component 15 and is used to generate a switching power supply to the output terminals 18.

[0004] An offline power converter, such as when the power supply 100 is in an idle state, has challenges in startup (or going online) due to the mismatch between the high-voltage input power 16 (e.g., from the wall) and the low-voltage power requirements of the IC controller 11. Conventional power converters (e.g., the prior art of FIG. 1) use an arrangement of components shown in the dashed region 110 for V CCGenerate an input voltage (e.g., 12V to 35V) to supply power to or activate the IC controller 11. This array of components can include a high-voltage bipolar junction (BJT) transistor 20, a resistor 21, a diode 22 (which can be a Zener diode), a capacitor 23, a resistor 24, and a Zener diode 25. The power supply 100 includes an auxiliary winding 17 in addition to the primary winding of the inductive component 15. The auxiliary winding 17 from the inductive component can generate energy to supply power to the IC controller during normal operation, and the input voltage V of the IC controller 11 CC The requirements are provided by the auxiliary winding 17 and can be adjusted by a resistor 26, a diode 27 (which can be a Zener diode), and a capacitor 28. The main drawback of using the startup circuit shown in the dashed area 110 for the power supply 100 is the use of the active component BJT transistor 20. When the power supply 100 is used for high-voltage applications, such as applications requiring 350V or more, especially when the power supply is in an idle state, a significant amount of power can be consumed by the BJT switch 20. As a result, an alternative design for the startup power converter is desired to improve converter efficiency and reduce costs.

Summary of the Invention

[0005] This specification describes a system-in-package (SIP) configuration in which a low-voltage enhancement-mode device and a high-voltage depletion-mode III-N device are used to start a power converter. The low-voltage enhancement-mode device, the high-voltage depletion-mode III-N device, the controller IC, the gate driver, and the startup components can be integrated into a single electronic component module. The term device is generally used for any transistor, switch, or diode when there is no need to distinguish them.

[0006] In a first aspect, an electronic component is described. The electronic component includes a semiconductor device package. The semiconductor device package includes a conductive structure package base, a first terminal configured to be connected to an inductive load, and a second terminal configured to be connected to a common node or a circuit ground. The package further includes an enhancement mode transistor and a depletion mode transistor. The depletion mode III-N transistor has a drain electrode, a source electrode, and a gate electrode. The enhancement mode transistor has a drain electrode, a source electrode, and a gate electrode. The drain electrode of the depletion mode III-N transistor is electrically connected to the first terminal, the source electrode of the depletion mode III-N transistor is electrically connected to the drain electrode of the enhancement mode transistor, the gate electrode of the depletion mode III-N transistor is electrically connected to the conductive structure package base, and the source electrode of the enhancement mode transistor is electrically connected to the conductive structure package base. The enhancement mode transistor is monolithically integrated with an IC controller and a gate driver on a common silicon substrate, the anode of the rectifying diode is connected to the drain of the enhancement mode transistor, the cathode of the rectifying diode is connected to the voltage input terminal of the IC controller, and the reservoir capacitor has a first terminal connected to the cathode of the rectifying diode and a second terminal connected to the conductive structure package base.

[0007] In a second aspect, an electronic circuit is described. The electronic circuit includes a first winding of an inductive component coupled to a high voltage node, and a second winding of the inductive component is coupled to the drain of a high voltage depletion mode transistor. The drain of a low voltage enhancement mode transistor is electrically connected to the source of the depletion mode transistor, the gate of the depletion mode transistor is electrically connected to the source of the enhancement mode transistor, and the source of the enhancement mode transistor is connected to circuit ground. The circuit further includes an IC controller having at least four pins, a first pin being a voltage input pin, a second pin providing a pulse width modulation output signal, a third pin being a current sense pin electrically connected to the source of the enhancement mode transistor, and a fourth pin being electrically connected to circuit ground. The gate drive includes an input connected to the second pin and an output connected to the gate of the enhancement mode transistor, the anode of a diode being electrically connected to the drain of the enhancement mode transistor, the cathode of the diode being electrically connected to an IC controller input pin, a first terminal of a capacitor being electrically connected to the cathode of the diode, a second terminal of the capacitor being electrically connected to circuit ground, and the enhancement mode transistor, the IC controller, the gate driver, the diode, and the capacitor being monolithically integrated in a discrete semiconductor IC device.

[0008] In a third aspect, an electronic package is described. The electronic package includes a conductive structural package base, a first terminal, a second terminal, a first electronic component, and a second electronic component. The first electronic component includes a monolithic integrated circuit formed on a common silicon substrate. The monolithic integrated circuit includes an IC controller, a gate driver, a low-voltage enhancement-mode silicon MOSFET, and an IC controller startup circuit. The second electronic component includes a high-voltage depletion-mode GaN transistor having a gate-source threshold voltage, and the source electrode of the depletion-mode GaN transistor is electrically connected to the drain electrode of the enhancement-mode silicon MOSFET transistor. The first terminal is electrically connected to the drain electrode of the depletion-mode GaN transistor, and the second terminal is electrically connected to the conductive structural package base. The gate electrode of the depletion-mode GaN transistor and the source electrode of the enhancement-mode silicon MOSFET transistor are electrically connected to the conductive package base, and the VCC node of the IC controller is coupled to the drain electrode of the enhancement-mode silicon MOSFET within the monolithic integrated circuit.

[0009] The electronic circuits and / or transistors described herein can include one or more of the following features. A rectifier diode and a reservoir capacitor can form an IC startup circuit, and the IC startup circuit can be monolithically integrated with an enhancement-mode transistor on a common substrate. The depletion-mode III-N transistor can be a high-voltage GaN HEMT having a breakdown voltage exceeding 600V and a gate-source threshold voltage of -15V or less. The enhancement-mode transistor can be a low-voltage silicon MOSFET device having a breakdown voltage greater than the absolute value of the threshold voltage of the depletion-mode transistor. The source electrode and the drain electrode of the depletion-mode III-N transistor are on a first surface of a III-N material structure on a conductive substrate, and the gate electrode is a material structure on a second surface of III-M opposite the first surface.

[0010] The IC controller can include a ground terminal connected to a conductive structure package base, a current sense terminal electrically connected to the source electrode of an enhancement mode transistor, and a gate drive terminal connected to the gate electrode of the enhancement mode transistor. When the first terminal of the package is biased at a voltage exceeding 300V, the second terminal of the package is connected to the circuit ground, the electronic component is in an off state, the drain of the enhancement mode transistor maintains a positive voltage between +15V and +25V with respect to the source electrode of the enhancement mode transistor, and the startup voltage is provided from the drain of the enhancement mode transistor to the IC controller. The rectifying diode does not necessarily have to be a Zener diode.

[0011] The threshold of the GaN HEMT device can be less than -12V. The drain-source voltage of the enhancement mode transistor can be greater than +10V when the electronic circuit is idle or offline. The startup voltage can be provided from the drain-source voltage of the enhancement mode transistor to the voltage input pin of the IC controller when the circuit is idle or offline. The discrete semiconductor IC device and the GaN HEMT device can be assembled into a single electronic component package. The single electronic component package can include a conductive structure package base, and the substrates of the discrete semiconductor IC device and the GaN HEMT device can be physically attached to the conductive structure package base. The IC controller startup circuit can include a diode and a capacitor coupled between the VCC node and the drain electrode of the enhancement mode silicon MOSFET. The drain-source voltage of the enhancement mode silicon MOSFET can be biased to +12V or more when the depletion mode GaN transistor is biased below the gate-source threshold voltage.

[0012] As used herein, a "hybrid enhancement mode electronic device or component", or simply a "hybrid device or component", is an electronic device or component formed from a depletion mode transistor and an enhancement mode transistor, where the depletion mode transistor is capable of a higher operating voltage and / or breakdown voltage compared to the enhancement mode transistor, and the hybrid device or component is configured to operate similarly to a single enhancement mode transistor having a breakdown voltage and / or operating voltage approximately the same height as the depletion mode transistor. That is, a hybrid enhancement mode device or component includes at least three nodes having the following characteristics. When a first node (source node) and a second node (gate node) are held at the same voltage, the hybrid enhancement mode device or component can block a positive high voltage (i.e., a voltage greater than the maximum voltage that an enhancement mode transistor can block) applied to a third node (drain node) with respect to the source node. When the gate node is held at a sufficiently positive voltage (i.e., greater than the threshold voltage of the enhancement mode transistor) with respect to the source node and a sufficiently positive voltage is applied to the drain node with respect to the source node, current flows from the source node to the drain node or from the drain node to the source node. If the enhancement mode transistor is a low voltage device and the depletion mode transistor is a high voltage device, the hybrid component can operate similarly to a single high voltage enhancement mode transistor. The depletion mode transistor can have a breakdown voltage and / or maximum operating voltage that is at least 2 times, at least 3 times, at least 5 times, at least 10 times, or at least 20 times that of the enhancement mode transistor.

[0013] As used herein, the terms group III nitride or group III N materials, layers, devices, etc. refer to the stoichiometric formula B w Alx In y Ga z refers to a material or device composed of a compound semiconductor material based on N, where w + x + y + z is approximately 1, 0 ≦ w ≦ 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and 0 ≦ z ≦ 1. The III-N material, layer, or device can be formed or prepared by either growing directly on a suitable substrate (e.g., by metalorganic chemical vapor deposition), or growing on a suitable substrate, peeling from the original substrate, and bonding to another substrate.

[0014] As used herein, two or more contacts or other items, such as conductive channels or components, are said to be "electrically connected" when they are connected by a material that is sufficiently conductive to ensure that the potential at each of the contacts or other items is the same, e.g., always substantially the same under any bias conditions.

[0015] As used herein, "drain electrode", "source electrode", and "gate electrode" refer to a part of the source, drain, or gate of a device used to be electrically connected to an external structure or device. For example, the drain of a device can be electrically connected to another device by forming a wire bond on the drain electrode.

[0016] As used herein, "voltage blocking" means the ability of a transistor, device, or component to prevent a large current, such as a current exceeding 0.001 times the operating current during normal conduction, from flowing through the transistor, device, or component when a voltage is applied between the transistor, device, or component. In other words, when a transistor, device, or component is blocking the voltage applied to it, the total current passing through the transistor, device, or component does not exceed 0.001 times the operating current during normal conduction. A device with an off-current greater than this value exhibits high losses and low efficiency and is typically not suitable for many applications, especially power switching applications.

[0017] As used herein, a "high voltage device", e.g., a high voltage switching transistor, HEMT, bidirectional switch, or four quadrant switch (FQS), is an electronic device optimized for high voltage applications. That is, when the device is off, it is capable of blocking a high voltage, such as about 300V or more, about 600V or more, or about 1200V or more, and when the device is on, it has a sufficiently low on-resistance (R ON ) such that, for example, it has a sufficiently low conduction loss when a substantial current passes through the device. A high voltage device is capable of blocking at least a voltage equal to the high voltage source or maximum voltage within the circuit in which it is used. A high voltage device is capable of blocking 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltages required by the application. In other words, a high voltage device can block all voltages between 0V and at least V max where V max is the highest voltage that can be supplied by the circuit or power supply, and V max is, for example, 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltages required by the application. In the case of a bidirectional switch or a four quadrant switch, the blocked voltage is of a polarity less than a certain polarity when the switch is off (±300V or ±600V, ±1200V, etc., of ±V max ) and the current can be in either direction when the switch is on.

[0018] As used herein, an “III-N device” is a device having a conductive channel formed within an III-N material. The III-N device can be designed to operate as a transistor or switch in which the state of the device is controlled by a gate terminal, or as a two-terminal device that blocks current in one direction and conducts in the other direction without a gate terminal. The III-N device can be a high-voltage device suitable for high-voltage applications. In such a high-voltage device, when the device is biased off (e.g., when the voltage on the gate relative to the source is less than the device threshold voltage), the device can support at least all source-drain voltages below the high voltage for the application in which the device is used, such as 100V, 300V, 600V, 1200V, 1700V, 2500V, or more. When the high-voltage device is biased (e.g., when the voltage on the gate relative to the source or related power supply terminal is greater than the device threshold voltage), the device can conduct substantial current at a low on-voltage (i.e., a low voltage between the source and drain terminals or between opposite power supply terminals). The maximum allowable on-voltage is the maximum on-state voltage that can be maintained for the application in which the device is used.

[0019] As used herein, the terms “above,” “below,” “between,” and “on” refer to the relative position of one layer with respect to another layer. Thus, for example, one layer disposed above or below another layer may or may not be in direct contact with the other layer and may have one or more intervening layers. Further, one layer disposed between two layers may or may not be in direct contact with the two layers and may have one or more intervening layers. In contrast, a first layer “on” a second layer is in contact with that second layer. Additionally, the relative position of one layer with respect to another layer is provided assuming that operations are performed with respect to the substrate without considering the absolute orientation of the substrate.

[0020] In typical power switching applications where a high-voltage switching transistor is used, the transistor is mainly in one of two states. In a first state, generally referred to as the "on state", the voltage of the gate electrode with respect to the source electrode is higher than the transistor threshold voltage, and a substantial current flows through the transistor. In this state, the voltage difference between the source and the drain is typically low, usually below a few volts, for example, about 0.1 to 5 volts. In a second state, generally referred to as the "off state", the voltage of the gate electrode with respect to the source electrode is lower than the transistor threshold voltage, and except for the off-state leakage current, a substantial current does not flow through the transistor. In this second state, the voltage between the source and the drain can be in any range from about 0V to the value of the circuit high-voltage source, and in some cases, it can be 100V, 300V, 600V, 1200V, 1700V, or higher, but it can be less than the breakdown voltage of the transistor. In some applications, the inductive element in the circuit raises the voltage between the source and the drain even higher than the circuit high-voltage source. Further, there is a short time immediately after the gate is switched on or off while the transistor is in the transition mode between the two aforementioned states. When the transistor is in the off state, it is said to "block the voltage". As used herein, "block the voltage" means the ability of a transistor, device, or component to prevent a large current, such as a current exceeding 0.001 times the average operating current during normal on-state conduction, from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, when a transistor, device, or component is blocking the voltage applied to it, the total current passing through the transistor, device, or component does not exceed 0.001 times the average operating current during normal on-state conduction.

[0021] Details of one or more disclosed implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Additional features and variants may also be included in the implementations. Other features, aspects, and advantages will become apparent from the description, drawings, and claims.

Brief Description of the Drawings

[0022]

Figure 1

[0023]

Figure 2

[0024]

Figure 3

[0025]

Figure 4

[0026]

Figure 5

[0027]

Figure 6A

Figure 6B

[0028]

Figure 7

[0029] Like reference symbols in the various drawings indicate like elements.

Modes for Carrying Out the Invention

[0030] This specification describes a system-in-package (SIP) configuration for starting a switched power converter using a low-voltage enhancement-mode transistor and a high-voltage depletion-mode III-N transistor. The low-voltage enhancement-mode transistor, high-voltage depletion-mode III-N transistor, controller IC, gate driver, and startup components can be integrated into a single electronic component package or module. Further, the low-voltage device, controller element, and startup components can be formed by being monolithically integrated with a common IC substrate. The SIP can have a reduced number of components and integrated efficiency compared to conventional power conversion solutions, thereby enabling lower manufacturing costs and improving system performance.

[0031] Typical power semiconductor devices, such as the power MOSFET 10 of FIG. 1, are manufactured using silicon (Si) semiconductor materials. More recently, wide bandgap materials, such as III-N materials, have been considered for power devices due to their excellent properties. III-nitride or III-N semiconductor devices, such as gallium nitride (GaN / AlGaN) HEMT devices, are now emerging as attractive candidates for carrying large currents, supporting high voltages, and providing very low on-resistance with fast switching times.

[0032] Most conventional III-N HEMTs and related transistor devices are normally on (i.e., have a negative threshold voltage), which means conducting current at zero gate-source voltage (V GS ). These devices with a negative threshold voltage are known as depletion-mode (D-mode) devices. In power electronics, to prevent accidental turn-on of a device (i.e., a device with a positive threshold voltage) that can lead to damage to the device or other circuit components, the device GSIt is preferable to have a normally-off device that is in the off state. A normally-off device is generally called an enhancement mode (E-mode) device.

[0033] The reliable manufacturing and operation of high-voltage E-mode III-N transistors have proven to be very difficult so far. One alternative to a single high-voltage E-mode III-N transistor is to combine a high-voltage D-mode III-N transistor with a low-voltage silicon E-mode FET in a cascode configuration. As shown in FIG. 2, the cascode configuration 200 includes a high-voltage D-mode III-N device 32 and a low-voltage E-mode device 30 to form a hybrid III-N device 210. The source of the D-mode device 32 is electrically connected to the drain of the E-mode device 30 at node 33. The gate of the D-mode device 32 is electrically connected to the source of the E-mode device 30 by a connector 31. The gate of the E-mode device 30 can function as the gate electrode 34 of the hybrid device 210 and can be controlled by a standard gate drive value such as 1.6V to 20V. The device configured in the cascode configuration 200 as shown in FIG. 2 can operate in the same way as a single high-voltage E-mode transistor. The drain of the D-mode device functions as the drain electrode 35 of the hybrid device 210, and the source of the E-mode device 30 functions as the source electrode of the hybrid III-N device 210, and in many cases, the same or similar output characteristics as a single high-voltage normally-off transistor are achieved.

[0034] FIG. 3 shows a schematic diagram of a switching power supply 300, and the hybrid III-N device 210 of FIG. 2 is implemented in place of the power MOSFET 10 shown in FIG. 1. The hybrid III-N device 210 includes a high-voltage depletion mode (D-mode) III-N device 32 such as a GaN HEMT transistor. The III-N device 32 can have a breakdown voltage exceeding 600V and can support a drain-source current (I DS ) exceeding 15A.

[0035] The depletion mode III-N device is a normally-on device, i.e., the device turns "on" when the gate-source voltage is biased at zero volts, and the device turns "off" when the gate-source voltage of the III-N device is biased at a negative voltage less than the threshold voltage of the device. For example, the III-N device 32 can have a substantially negative threshold voltage of -15V, and the device can be biased "off" by biasing the gate-source voltage at -20V or less (hereinafter means that the absolute value of the negative is larger). In some embodiments, the III-N device has a negative threshold voltage of -12V to -30V. The required threshold voltage of the III-N device 32 is important for the startup voltage requirement of the power supply 300, which will be described more clearly herein. The hybrid III-N device 210 includes a low-voltage enhancement mode (E-mode) device 30 such as a silicon MOSFET transistor. The enhancement mode device 30 can have a threshold voltage of 1.6V to 6V. The breakdown voltage of the enhancement mode device 30 can be made larger than the absolute value of the threshold voltage of the depletion mode III-N device 32. The depletion mode III-N device 32 and the enhancement mode device 30 can be packaged in a single hybrid electronic component package.

[0036] The source of the III-N device 32 is electrically connected to the drain of the E-mode device 30 at node 33. The gate of the III-N device 32 is electrically connected to the source of the E-mode device 30 by a connector wire 31. The switching power supply 300 includes an inductive component 15 having a plurality of windings (such as a transformer) each having a pair of terminals. The first terminal of the first winding of the inductive component 15 can be coupled to the input power supply 16, and the second terminal of the first winding is electrically connected to the drain of the III-N device 32. The second inductive component 19 is magnetically coupled to the first inductive component 15 and is used to generate a switching power supply to the output terminal 18.

[0037] The gate of the low voltage enhancement mode device can act as the gate of the hybrid III-N device 210. The integrated circuit (IC) controller 11 and the gate driver 12 can be used to send a pulse width modulation (PWM) signal to control the gate drive pattern to meet the output requirements of the power supply 300. The IC controller 11 can include at least four input / output pins or terminals. The first pin can be a voltage input pin or VCC, the second pin can provide the PWM signal to the gate driver 12, the third pin can connect the current sense (CS) loop 13 to the source of the enhancement mode device 30, and the fourth pin can be connected to the circuit ground or common node. Optionally, the current sense loop 13 can require a sense resistor 14 configured between the current sense loop 13 and the common node or circuit ground.

[0038] A switching power converter such as power supply 300 typically requires a low voltage control circuit such as IC controller 11, which can turn the primary power device (i.e., hybrid device 210) on and off in response to the required output voltage and output current of the power converter. The cascode configuration of hybrid device 210 can easily provide the low voltage startup requirements of IC controller 11 when the power supply is in an "offline" or idle state. For example, IC controller 11 can require a VCC of +10 to +35 volts to start. When hybrid device 210 is in the "off" state, the high voltage D-mode III-N device blocks the input voltage (e.g., from the wall), and the drain-source voltage of E-mode device 30 settles near the absolute value of the threshold voltage of D-mode III-N device 32. Since the gate of D-mode device 32 is coupled (i.e., electrically connected) to the source of E-mode device 30, the gate voltage of D-mode device 32 is essentially fixed at 0V or near it. This means that when D-mode device 32 has a negative gate-source threshold voltage of -15V, the voltage node 33 between the source of D-mode device 32 and the drain of E-mode device 30 is held at approximately +15V (with respect to the source of E-mode device 30), while the hybrid III-N device is biased in the "off" state. For example, the drain-source voltage of E-mode device 30 can be maintained within + / -5 volts or + / -2 volts of the absolute value of the threshold voltage of D-mode III-N device 32 when the D-mode III-N device is in the "off" state and blocking the high voltage input power supply. The voltage maintained at voltage node 33 (i.e., the gate-source voltage of E-mode device 30) can sufficiently supply the voltage required to "start up" IC controller 11 when the power supply is in an "offline" or idle state and the hybrid device 210 is blocking the high voltage input power supply.

[0039] The simplified necessary startup circuit of the power supply 300 is shown in the dashed region 310. The anode of the rectifier diode 36 can be electrically connected to the voltage node 33 between the source of the D-mode device 32 and the drain of the E-mode device 30. The cathode of the diode 36 can be connected to the first terminal of the reservoir capacitor 37 and the VCC input terminal of the IC controller 11. The second terminal of the reservoir capacitor 37 can be connected to a common node or circuit ground. The rectifier diode 36 can be a standard p-n diode in the circuit 300 as compared to the Zener diode required in the circuit 100. Since the Zener diode dissipates power in the reverse conduction mode and has lower energy efficiency compared to a standard p-n diode, the circuit efficiency can be further improved thereby. Here, the voltage held between the D-mode device and the E-mode device of the cascode configuration hybrid device in the "off" state is used to power the startup requirements of the IC controller 11. The value of the reservoir capacitor 37 can be selected according to the power consumption requirements of the IC controller 11. For example, the input voltage 16 can be greater than 600V, and the III-N device 32 can "block" a voltage greater than the input voltage. When the hybrid device 210 is "blocking" the input voltage, the voltage at the source of the III-N device 33 is, for example, about +15V, which can thereby be used to power the startup of the IC controller 11.

[0040] Compared with the startup circuit shown in the dashed-line area 110 of FIG. 1, the complexity of the power supply 300 is significantly reduced compared to the power supply 100 of FIG. 1 where the startup voltage is derived from the input voltage 16. Further, by eliminating the BJT transistor 20 (or JFET or N-channel startup MOSFET) of FIG. 1 used to start a conventional switching power supply, power loss can be reduced and efficiency can be increased. The number of active and passive components of the startup circuit 110 of FIG. 1 is at least 9 components compared to the startup circuit 310 shown in FIG. 3, which can be reduced to just 2 components (a diode and a capacitor). The power supply 300 does not require the auxiliary winding 17 of the inductive component 15 shown in FIG. 1 to supply power to the IC controller 11, which can contribute to a substantial increase in the size and weight of the power conversion.

[0041] FIG. 4 shows a schematic diagram of a switching power supply 400. The power supply 400 is similar to the power supply 300 of FIG. 3 except that it includes a monolithic IC 410. The monolithic IC 410 includes an enhancement-mode FET device 30, an IC controller 11, and a gate driver 12, and is monolithically integrated and formed on a common device substrate (e.g., a silicon substrate). Optionally, the monolithic IC 410 can also include a current sensing resistor 14 integrated on the common substrate. A feature of the power supply 400 is that it can be assembled into a single electronic component package 420. The component package 420 can include a conductive structural package base (not shown) configured to be the circuit ground. The depletion-mode III-N transistor 32, the monolithic IC 410, the rectifier diode 36, and the reservoir capacitor 37 can be attached to the structural package base. The second terminal of the capacitor 37 can be electrically connected to the package base.

[0042] FIG. 5 shows a schematic diagram of a switching power supply 500. The power supply 500 is similar to the power supply 400 of FIG. 4, except that it includes a monolithic IC 510. The monolithic IC 510 is similar to the monolithic IC 410, but further includes a necessary startup circuit (shown by region 310) monolithically integrated on the same common substrate (e.g., a silicon substrate) as the IC controller 11, the gate driver 12, and the E-mode device 30. For clarity, the monolithic IC 510 includes two separate physical parts, i.e., separate and non-overlapping regions on the common substrate. The first part includes the low-voltage enhancement-mode transistor 30, and the second part 512 includes the startup circuit 310, the IC controller 11, and the gate driver 12. The startup circuit 310 can include at least the diode 28 and the capacitor 25 shown in the dashed region 310 of FIG. 3. The anode of the diode 28 is electrically connected to the drain of the enhancement-mode device 30 and is internally integrated with the metal routing layer.

[0043] Furthermore, the monolithic IC 510 and the depletion mode III-N device 32 can be assembled into a single electronic component package 520 to form a simplified system-in-package (SIP) configuration. The SIP package 520 includes the simultaneous implementation of a high-voltage III-N device 32, a low-voltage MOSFET 30, a gate driver 12, an IC controller 11, and a startup circuit in one package. When the package 520 is co-packaged with the monolithic IC device 510, the number of components in the SIP package 520 is reduced to include only two individual electronic semiconductor components, where the first individual component is the high-voltage III-N device 32 and the second individual component is the monolithic IC 510. The SIP package 520 can include at least two terminals, where the first terminal is an input terminal 52 configured to be connected to an inductive component (such as the inductive component 15 in FIG. 4), and the second terminal is a common mode terminal 54 configured to be connected to a circuit ground or a common node. The package 520 can include a conductive structure package substrate, and the first and second individual components are physically attached to the structure package substrate.

[0044] FIG. 6A shows a cross-sectional view of a depletion mode III-N device 600 that can be used as the III-N device 32 shown in FIG. 3. The III-N device 600 includes a substrate 60 that can be formed from silicon, sapphire, silicon carbide, GaN, or another suitable material. A III-N material structure 61 is formed above the substrate 60. The III-N material structure 61 can include a III-N buffer layer 62 (e.g., AlN / AlGaN / GaN), a III-N channel layer 63 (e.g., GaN), and a III-N barrier layer 64 (e.g., AlGaN). The III-N barrier layer 64 has a higher bandgap than the III-N channel layer 63.

[0045] Due to the compositional difference between the barrier layer 64 and the channel layer 63, a two-dimensional electron gas channel 69 (2DEG channel) is induced in the region of the channel layer 63 near the interface of the barrier layer 63. The 2DEG channel 69 can continuously extend between the source electrode 65 and the drain electrode 66. On the other hand, the gate electrode 67A is biased at zero volts. As a result, the III-N device 600 is characterized as a depletion-mode device.

[0046] An insulating layer 68 (e.g., a SiN passivation layer or a gate dielectric layer) is formed above the upper surface of the III-N material structure 61 and between the gate electrode 67A and the upper surface of the III-N material structure 61. The thickness of the insulating layer 68 between the gate electrode 67A and the upper surface of the III-N material structure 61 can be used to adjust the threshold voltage of the device. A thicker insulating layer at that position drives the threshold voltage more negatively. The III-N device 600 is a lateral device characterized in that the source electrode 65 and the drain electrode 66 are formed on the same side of the III-N material structure. As seen in FIG. 6A, each of the drain electrode 66, the source electrode 65, and the gate electrode 67A extends over the insulating layer 68 and includes portions of the electrodes that enable external electrical connection to each electrode, for example, using wire bonds.

[0047] Figure 6B is a cross-sectional view of a depletion mode III-N device 610 similar to the device 600 of Figure 6A. However, the III-N device 610 has a gate connection substrate that enables the gate electrode to be formed on the side of the III-N material structure opposite to the source and drain electrodes. As seen in Figure 6B, the gate 67B includes a metal portion 67' that extends outside the device active region 602 (i.e., the active region is between the source and the drain), and extends, for example, by an ion implantation process, into an inactive region 603 that is electrically insulated from the 2DEG channel 69. The via hole 605 is formed on the surface of the substrate 606 through the III-N material structure. The substrate 606 can be a conductive substrate silicon substrate such as a p+ or n+ doped substrate. The metal portion 67' of the gate 67B is formed in the via hole 605 within the inactive region 603 and contacts the conductive substrate 606. To form the gate electrode 607, a metal layer is formed on the back side of the substrate.

[0048] When using an insulating substrate such as a sapphire substrate, the via hole 605 can extend throughout the thickness of the substrate (not shown), and the metal portion 67' can be formed within the via hole 605 and electrically connected to a metal layer formed on the back surface of the substrate. The source electrode 65 and the drain electrode 66 are formed on the first side of the III-N material structure 61, and the gate electrode 607 is formed on the second side opposite to the first side. When the III-N device 610 is implemented as the depletion mode III-N device 32 of Figure 3, the packaging complexity is reduced by eliminating the need for gate connection wire bonds.

[0049] FIG. 7 is a plan view of an electronic component 700 such as an electronic module or package that includes a plurality of semiconductor devices therein. The electronic component 700 includes an electronic component package 710 that is similar to the system-in-package (SIP) 520 described above in FIG. 5, and includes a conductive structure package base 720. The electronic component 700 includes only two individual semiconductor devices. The first discrete semiconductor device is a high-voltage depletion-mode device. In the electronic component 700, the III-N device 610 of FIG. 6B is used to form the high-voltage depletion-mode transistor 32 shown in FIG. 5, and the second discrete semiconductor device is a low-voltage enhancement-mode device monolithically integrated with an IC controller and a data driver. In the component 700, the monolithic IC 510 shown in FIG. 5 can be used as the second discrete semiconductor device.

[0050] The monolithic IC 510 shown in FIG. 7 can have a first portion that includes a low-voltage enhancement-mode transistor 30, and a second portion 512 that includes components required for startup, an IC controller, and a gate driver. The component 700 includes at least a first terminal 52 (which can be configured to be connected to an inductive component) that extends from the package 520 and is electrically connected to the drain electrode 66 of the III-N device 610. The conductive structure package base 710 can be configured to be connected to a common mode or circuit ground. A second terminal 54 (which can be configured to be connected to a common mode or system ground) extends from the package 520 and is electrically connected to the package base 520.

[0051] The substrate of the depression mode III-N device 610 is directly mounted on and electrically connected to the package substrate 520 such that the gate electrode 607 of the device 610 is electrically connected to the package substrate 520. The enhancement mode device 30 may be a lateral MOSFET device such as an LDMOS type device, in which case both the source electrode and the drain electrode are formed on the same side (i.e., the upper side) of the device. In this case, the source electrode 65 of the III-N device 610 can be electrically connected to the drain electrode 71 of the enhancement mode device 30, for example, using a wire bond. In another embodiment, an LDMOS type device can be used, and the source electrode is formed on the bottom side (not shown) of the device on the opposite side of the drain electrode, such that the source can be directly electrically connected to and physically mounted on the package conductive structure substrate. The source electrode 71 of the device 30 can be connected to the conductive package base 520 using a wire bond. The monolithic IC 510 includes a second portion 512, and the portion 512 includes integrated circuits used to form a startup circuit, an IC controller, and a gate driver. The startup circuit can be powered and electrically connected by the drain electrode 71 via an internal metal routing connection. The PWM of the IC controller and the gate driver can be connected to the gate electrode of the enhancement mode device 30 via an internal metal wiring connection.

[0052] When implemented using a system-in-package solution such as the integrated electronic component 700 shown in FIG. 7, or the circuit diagrams shown in FIGS. 4, 5, and 6A - 6B, the efficiency of the switching power supply and the manufacturing assembly requirements can be significantly improved. The total number of components is reduced, as is the cost. The "offline" efficiency of the system is improved by eliminating the active components used in the startup power supply.

[0053] Some embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the technology and devices described herein. Accordingly, other embodiments are within the scope of the appended claims.

Claims

1. An electronic component, comprising: a semiconductor device package, the semiconductor device package including: a conductive structure package base, a first terminal configured to be connected to an inductive load, and a second terminal configured to be connected to a common node or a circuit ground; a depletion-mode III-N transistor having a drain, a source, and a gate; an enhancement-mode transistor having a drain, a source, and a gate; an IC controller; a gate driver; wherein: the drain of the depletion-mode III-N transistor is electrically connected to the first terminal; the source of the depletion-mode III-N transistor is electrically connected to the drain of the enhancement-mode transistor; the gate of the depletion-mode III-N transistor is electrically connected to the conductive structure package base; the source of the enhancement-mode transistor is electrically connected to the conductive structure package base; and the enhancement-mode transistor is monolithically integrated with the IC controller and the gate driver on a common silicon substrate; the electronic component further includes: a rectifier diode having an anode connected to the drain of the enhancement-mode transistor and a cathode connected to a voltage input terminal of the IC controller; a reservoir capacitor having a positive side connected to the cathode of the rectifier diode and a negative side connected to the conductive structure package base; wherein the electronic component includes: the electronic component.

2. The rectifier diode and the reservoir capacitor form an IC startup circuit, and the IC startup circuit is monolithically integrated with the enhancement-mode transistor on the common silicon substrate. The electronic component according to claim 1.

3. The depletion-mode III-N transistor is a high-voltage GaN HEMT having a breakdown voltage greater than 600V and a gate-source threshold voltage of -15V or less. The electronic component according to claim 1.

4. The enhancement-mode transistor is a low-voltage silicon MOSFET device having a breakdown voltage greater than the absolute value of the threshold voltage of the depletion-mode transistor. The electronic component according to claim 3.

5. The source electrode and the drain electrode of the depression mode transistor are on a first surface of the III-N material structure above the conductive substrate, and the gate electrode is on a second surface of the III-N material structure opposite to the first surface. The electronic component according to claim 1.

6. The gate electrode is electrically connected to the conductive structure package base through the conductive substrate of the depression mode III-N transistor. The electronic component according to claim 5.

7. The IC controller further includes a ground terminal connected to the conductive structure package base, a current sense terminal electrically connected to the source electrode of the enhancement mode transistor, and a gate drive terminal connected to the gate electrode of the enhancement mode transistor. The electronic component according to claim 4.

8. When the first terminal of the package is biased at a voltage greater than 300V, the second terminal of the package is connected to the circuit ground, and the electronic component is in the off state, the drain of the enhancement mode transistor maintains a positive voltage between +15V and +25V with respect to the source electrode of the enhancement mode transistor, and a startup voltage is supplied from the drain of the enhancement mode transistor to the IC controller. The electronic component according to claim 7.

9. The rectifying diode is not a Zener diode. The electronic module according to claim 7.

10. An electronic circuit, A high voltage depression mode transistor having a gate, a source, a drain, and a threshold voltage; A low voltage enhancement mode transistor having a gate, a source, and a drain, wherein the drain of the low voltage enhancement mode transistor is electrically connected to the source of the depression mode transistor, the gate of the depression mode transistor is electrically connected to the source of the enhancement mode transistor, and the source of the enhancement mode transistor is configured to be connected to the circuit ground. A low voltage enhancement mode transistor; An inductive component having a first winding configured to be electrically connected to a high voltage source and a second winding electrically connected to the drain of the high voltage depletion mode transistor; An IC controller having at least four pins, wherein a first pin is a voltage input pin, a second pin provides a pulse width modulation output signal, a third pin is a current sense pin electrically connected to the source of the enhancement mode transistor, and a fourth pin is configured to be electrically connected to the circuit ground; A gate driver having an input connected to the second pin and an output connected to the gate of the enhancement mode transistor; A diode having an anode electrically connected to the drain of the enhancement mode transistor and a cathode electrically connected to the voltage input pin of the IC controller; A capacitor having a positive side electrically connected to the cathode of the diode and a negative side configured to be electrically connected to the circuit ground, wherein the enhancement mode transistor, the IC controller, the gate driver, the diode, and the capacitor are monolithically integrated in a discrete semiconductor IC device; An electronic component comprising.

11. The discrete semiconductor IC device is a silicon-based device, and the depletion mode transistor is a GaN HEMT device. The electronic circuit according to claim 10.

12. The threshold voltage of the GaN HEMT device is -12V or less. The electronic circuit according to claim 11.

13. The high voltage depletion mode transistor is configured such that when the high voltage depletion mode transistor is in the off state and blocks the high voltage source, the drain-source voltage of the enhancement mode transistor is maintained within 2V of the absolute value of the threshold voltage of the high voltage depletion mode transistor. The electronic circuit according to claim 12.

14. A connection is provided between the voltage input pin of the IC controller and the drain of the enhancement mode transistor, and when the high voltage depletion mode transistor is in an off state and blocks the high voltage source, a voltage necessary to activate the IC controller is supplied from the connection. The electronic circuit according to claim 13.

15. The discrete semiconductor IC device and the GaN HEMT device are assembled in a single electronic component package. The electronic circuit according to claim 14.

16. The single electronic component package includes a conductive structure package base, and the substrates of the discrete semiconductor IC device and the GaN HEMT device are directly mounted on and physically attached to the conductive structure package base. The electronic circuit according to claim 15.

17. An electronic package, comprising: A conductive structure package base; A first terminal and a second terminal; A first electronic component including a monolithic integrated circuit formed on a common silicon substrate, the monolithic integrated circuit including an IC controller, a gate driver, a low voltage enhancement mode silicon MOSFET, and an IC controller startup circuit; A second electronic component including a high voltage depletion mode GaN transistor having a gate-source threshold voltage; Comprising: The source electrode of the depletion mode GaN transistor is electrically connected to the drain electrode of the enhancement mode silicon MOSFET transistor, the first terminal is electrically connected to the drain electrode of the depletion mode GaN transistor, the second terminal is electrically connected to the conductive package base, the gate electrode of the depletion mode GaN transistor and the source electrode of the enhancement mode silicon MOSFET transistor are electrically connected to the conductive package base, and the VCC node of the IC controller is connected to the drain of the enhancement mode silicon MOSFET within the monolithic integrated circuit. Electronic package.

18. An electronic package according to claim 17, wherein the IC controller startup circuit includes a diode and a capacitor coupled between the VCC node and the drain electrode of the enhancement-mode silicon MOSFET.

19. The electronic package according to claim 18, wherein the gate-source threshold voltage of the depletion-mode GaN transistor is less than -12V.

20. The electronic package according to claim 19, wherein the drain-source voltage of the enhancement-mode silicon MOSFET is biased to +12V or more when the depletion-mode GaN transistor is biased below the gate-source threshold voltage of the GaN transistor.

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