Asynchronous Clock FSM-Based Clock Switching

Abstract

Aspects of the present disclosure provide an apparatus. In one example, the apparatus (20) includes a clock switching circuit (22) coupled to an oscillator (273) and one or more circuit units (230 / 240 / 250 / 260). The clock switching circuit receives a set of frequency signals (282 / 283 / 284) from the oscillator and provides an uplink primary clock signal (281) and an enable signal (285 / 286) determined in synchronization with the uplink primary clock signal to the one or more circuit units, receives a clock frequency request from the one or more circuit units or a clock management circuit, provides the uplink primary clock signal based on a first signal of the set of frequency signals, and determines whether to continue providing the uplink primary clock signal according to the clock frequency request based on the first signal or a second signal of the set of frequency signals.

Description

Technical Field

[0001] A system-on-chip (SoC) or microcontroller unit (MCU) that includes a combination of a processor, memory, and other hardware components is an embedded system with dedicated functions. The embedded system can be part of a computer or electronic device, such as a chip or an electronic circuit board. The embedded system can include multiple circuit units that can contain various intellectual properties (IP). The circuit units are also referred to as IPs in this specification. For example, designers of systems of application-specific integrated circuits (ASICs) and field-programmable gate array (FPGA) logic integrate IPs as building blocks of the embedded system. The IP includes multiple circuit elements that include a clock generator that provides a clock signal for synchronizing signals and operations within and between the IPs of the embedded system.

Summary of the Invention

[0002] In some examples, an apparatus includes a clock switching circuit coupled to an oscillator and one or more circuit units. The clock switching circuit receives a set of frequency signals from the oscillator and provides an uplink primary clock signal and an enable signal determined in synchronization with the uplink primary clock signal to the one or more circuit units, receives a clock frequency request from the one or more circuit units or a clock management circuit, provides the uplink primary clock signal based on a first signal of the set of frequency signals, and determines whether to continue providing the uplink primary clock signal based on the first signal or a second signal of the set of frequency signals according to the clock frequency request.

[0003] In some examples, a method includes a clock management circuit receiving, from a circuit unit, a clock frequency request for a clock signal having a first frequency. The method also includes the clock management circuit determining, based on a first clock frequency signal from a set of clock frequency signals, an uplink primary clock signal to provide, based on the clock frequency request, where the first clock frequency signal has the first frequency. The method also includes the clock management circuit receiving, from a second circuit unit, a second clock frequency request for a second clock signal having a second frequency. The method also includes the clock management circuit determining, based on the second clock frequency request, to continue providing the uplink primary clock signal based on the first clock frequency signal in response to the second frequency being less than the first frequency. The method also includes the clock management circuit determining, based on the second clock frequency request, to provide the uplink primary clock signal based on the second clock frequency signal from the set of clock frequency signals in response to the second frequency being greater than the first frequency, where the second clock frequency signal has the second frequency. The method also includes providing the uplink primary clock signal and an enable signal to the circuit unit and the second circuit unit, where the enable signal is provided in synchronization with the uplink primary clock signal.

[0004] In some examples, the apparatus includes a clock switching circuit and a finite state machine (FSM). The FSM is configured to provide a first control signal to the clock switching circuit for a state transition that determines switching the uplink primary clock signal from a first clock frequency signal to a second clock frequency signal or a third clock frequency signal, the first clock frequency signal having a faster clock frequency than the second clock frequency signal, and the third clock frequency signal having a slower clock frequency than the second clock frequency signal. The FSM is also configured to provide a second control signal to the clock switching circuit to provide a second clock frequency enable signal and a third clock frequency enable signal together with the uplink primary clock signal, the second clock frequency enable signal and the third clock frequency enable signal being generated in synchronization with the uplink primary clock signal.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0015] Embedded systems such as SoCs and MCUs may include IPs that operate at different clock frequencies. The clock frequencies can be provided as clock signals to the IPs by different clock generators, also referred to as oscillators in this specification. By providing different clock frequencies from different oscillators, the power consumption in the SoC is reduced, for example, to meet certain power constraints. Also, the same IP can perform operations at different clock frequencies. However, problems can occur when exchanging signals across clock boundaries. For example, IPs operating at different clock frequencies generated by different oscillators cannot interact synchronously. In a clock switching method based on combinational logic for changing the clock frequency for a certain IP, glitches can occur in the clock signal due to timing errors in switching according to the cycles between different clock frequencies. Also, in a more complex clock switching method including a synchronizer, latency can occur due to the IP waiting for a certain period of time before switching the clock frequency, such as when switching from a low clock frequency to a high clock frequency or vice versa.

[0016] This description provides an example of a method for switching the clock frequency for a clock signal provided to an IP in order to avoid signal timing glitches and reduce latency. These methods include circuits, systems, and methods for performing clock switching between two or more clock frequencies from one or more respective oscillators. Accordingly, one or more IPs within the system are provided with the same output clock signal and one or more clock enable signals for use in generating and synchronizing internal clocks based on the received clock signal. For example, the IP may be enabled to generate an internal clock in accordance with one of the output clock signal and the clock enable signal via an implementation of an integrated clock gate (ICG). The clock frequency of the output clock signal is determined by a finite state machine (FSM) coupled to a multiplexer for selecting a clock frequency from the available clock frequencies provided by the oscillator. To reduce the presence of glitches in the output clock signal provided to the IP, the clock frequency of the output clock signal provided to the IP based on the control of the FSM may be switched by the IP to the clock frequency required by the IP based on the clock enable signal provided based on the control of the FSM, rather than the clock frequency required by the IP, and may be received in synchronization with the output clock signal.

[0017] FIG. 1 is a block diagram of a processing system 10 configured according to software, hardware, or both to perform clock switching according to various examples described herein. The processing system 10 includes hardware components that may be coupled to or be part of a chip or embedded system such as a SoC or MCU within a device, including IP operating at different clock frequencies. The processing system 10 may also execute a computer program or instructions for performing clock switching. For example, the processing system 10 includes a SoC or MCU (SoC / MCU) 20 having a clock switching circuit 22 that performs clock switching according to various examples described herein. As shown in FIG. 1, the processing system 10 also includes one or more processors 101 and one or more memories 102. The one or more processors 101 are coupled to the SoC / MCU 20 or include the SoC / MCU 20. In some examples, the processing system 10 may also include one or more transceivers 103 for establishing connections. These components may be connected via a bus 105 or in any other suitable manner. In FIG. 1, an example where components are connected via the bus 105 is shown.

[0018] The processor 101 is configured to read and execute computer-readable instructions. For example, the processor 101 is configured to call and execute instructions within a program stored in the memory 102, including instructions 106. In some examples, the instructions 106, when executed, implement an FSM. In response to the processor 101 providing data, the processor 101 drives or controls the transceiver 103 to perform data transmission. The processor 101 also drives and controls the transceiver 103 to perform reception in response to the processor 101 receiving data. Thus, the processor 101 may be considered a control center for performing data transmission and reception, and the transceiver 103 is an executor for performing transmission and reception operations.

[0019] In some examples, memory 102 is coupled to processor 101 via bus 105 or input / output interface 107. In other examples, memory 102 is integrated with processor 101. Memory 102 is configured to store various software programs and / or multiple groups of instructions including instructions 106. Memory 102 may include one or more storage devices. For example, memory 102 may include high-speed random access memory and / or may include non-volatile memory such as one or more disk storage devices, flash memory, or another non-volatile solid-state storage device. Memory 102 may store an operating system such as a real-time operating system (RTOS), ANDROID, IOS, WINDOWS, or LINUX. Memory 102 may also include a network communication program. The network communication program is useful for communicating with one or more attached devices, one or more user devices, or one or more network devices. Memory 102 may also store a user interface program. The user interface program displays the content of an application via a graphical interface and receives data or operations performed by a user on the application via input controls such as a menu, a dialog box, or a physical input device (not shown). Memory 102 is configured to store instructions 106 for implementing various methods and processes provided according to the various examples described herein.

[0020] Transceiver 103 includes a transmitter and a receiver. Transceiver 103 is configured to transmit signals provided by processor 101. Transceiver 103 is also configured to receive signals from other devices or equipment. Processing system 10 may also include a wired network interface or a local area network (LAN) interface to support wired communication. Processing system 10 may also include communication components for transmitting and receiving wireless communication signals.

[0021] The processing system 10 may also include an input / output interface 107 for enabling communication between the processing system 10 and one or more input / output devices (not shown). Examples of input / output devices include voice input / output devices, keystroke input devices, displays, and the like. The input / output devices are configured to effect an interaction between the processing system 10 and a user or an external environment. The input / output devices communicate with the processor 101 via the user interface.

[0022] FIG. 2 is a block diagram of a SoC / MCU 20 comprising a clock switching circuit 22 according to various examples. The SoC / MCU 20 is configured to operate using a clock signal that may have one of various different clock frequencies that can change during operation. For example, the SoC / MCU 20 may be coupled to or be part of a processing system 10 such as a computer or an electronic device. The SoC / MCU 20 includes a central processing unit (CPU) 210 that may be one of the IPs of the SoC / MCU 20. The CPU 210 is coupled to the SoC / MCU 20 and is configured to control the operation of other IPs of the SoC / MCU 20 (e.g., via signaling). The SoC / MCU 20 may also include a power management circuit 220 for providing and regulating power to the IPs and other components of the SoC / MCU 20. The IPs of the SoC / MCU 20 include a timer 230, an analog-to-digital converter (ADC) 240, a digital-to-analog converter (DAC) 250, and one or more peripheral interfaces 260. Examples of the peripheral interfaces 260 include a serial peripheral interface (SPI), a universal asynchronous receiver transmitter (UART), and an inter-integrated circuit (I2C). At least some of the IPs and other components of the SoC / MCU 20 may be coupled to each other. For example, the timer 230 is coupled to the ADC 240, the DAC 250, and one or more peripheral interfaces 260 and may exchange signals with the ADC 240, the DAC 250, and one or more peripheral interfaces 260. The ADC 240 and the DAC 250 are also coupled to one or more peripheral interfaces 260 and may exchange signals with one or more peripheral interfaces 260.

[0023] The SoC / MCU 20 also includes a clock management circuit 270, which provides a clock signal having a frequency selected from a set of available clock frequencies to the IPs of the SoC / MCU 20. For example, the clock management circuit 270 provides an uplink primary clock signal (ULPCLK) 281 to one or more IPs, including at least one of the timer 230, the ADC 240, the DAC 250, and one or more peripheral interfaces 260. The ULPCLK 281 may have a selectable frequency, and the clock management circuit 270 includes a clock switching circuit 22 that switches the clock frequency of the ULPCLK 281 according to requests from the IPs. The clock switching circuit 22 includes a clock frequency selection circuit 271 that selects the clock frequency of the ULPCLK 281 from a plurality of clock frequencies provided by respective oscillators 273. The clock management circuit 270 also includes an FSM 272 coupled to the clock switching circuit 22. The FSM 272 provides a control signal to the clock frequency selection circuit 271 to switch the clock frequency of the ULPCLK 281 to the IPs. The connections for providing the ULPCLK 281 from the clock management circuit 270 to each of the timer 230, the ADC 240, the DAC 250, and one or more peripheral interfaces 260 are indicated by respective arrows in FIG. 2. Requests from the IPs, including the timer 230, the ADC 240, the DAC 250, and one or more peripheral interfaces 260, may be provided to the clock management circuit 270 via the same connection or other connections (not shown).

[0024] In at least some examples, the clock signal provided to the IP by the clock management circuit 270 has a frequency other than the frequency required by each IP that receives the clock signal. For example, a first IP may request a clock signal at a first frequency, and a second IP may request a clock signal at a second frequency that is less than the first frequency. The clock management circuit 270 may provide the clock signal to both the first and second IPs having the first frequency. The clock management circuit 270 may also provide a clock enable signal to the first and second IPs. Based on the clock signal and the clock enable signal, the second IP may derive or otherwise generate an internal clock signal at the second frequency. In some implementations, the second IP generates the internal clock signal via an ICG that gates the clock signal according to the clock enable signal to provide the internal clock signal. Thus, both the first IP and the second IP may receive the same clock signal, but may derive the internal clock signal at their respective required frequencies. This promotes interoperability between the first IP and the second IP and reduces at least some of the problems that may arise, for example, from the first IP and the second IP including components operating at different clock frequencies, such as being received asynchronously from different clock sources. For example, since both the first IP and the second IP receive the same clock signal from the clock management circuit 270 (e.g., ULPCLK), problems in signaling across the boundary between the first IP and the second IP are reduced and the interoperability between the first IP and the second IP may be increased.

[0025] In one example, as shown in FIG. 2, ULPCLK281 is switched between clock signals having three different clock frequencies. The clock signals include a high clock frequency signal (SYSCLK) 282 having a high clock frequency, a medium clock frequency signal (MFCLK) 283 having a medium clock frequency, and a low clock frequency signal (LFCLK) 284 having a low clock frequency. In some examples, SYSCLK282 has a clock frequency equal to about 20 megahertz (MHz), MFCLK283 has a clock frequency equal to about 2 MHz, and LFCLK284 has a clock frequency equal to about 32 kilohertz (kHz). In other examples, a clock divider (not shown) may be useful instead of an oscillator to provide the clock frequency signals. For example, a clock divider may be useful to divide SYSCLK282 to provide MFCLK283 and LFCLK284, but may increase the power consumption associated with providing MFCLK283 and LFCLK284 in comparison to providing MFCLK283 and LFCLK284 via dedicated oscillators.

[0026] The frequency signal is provided according to the frequency and power requirements of the processing system 10. When the clock frequency selection circuit 271 receives a request from the IP, it selects from the input signals SYSCLK282, MFCLK283, and LFCLK284 to be used as a basis for ULPCLK281. For example, the clock frequency of ULPCLK281 can be switched multiple times by the clock frequency selection circuit 271 in the order of multiple clock frequency requests from the IP. When requests for different frequencies are received, the FSM272 arbitrates between the different frequencies and selects one to be used as the basis for ULPCLK281. For example, in response to requests from multiple IPs for clock signals at different frequencies, the clock frequency selection circuit 271 selects, via the FSM272, the highest frequency request from the IP and provides one of SYSCLK282, MFCLK283, or LFCLK284 as ULPCLK281 such that ULPCLK281 has a frequency that satisfies the highest frequency request. The remaining portions of the multiple IPs that request clock signals at frequencies lower than the frequency of ULPCLK281 can derive internal clock signals based on ULPCLK281 and the MFCLK enable signal (MFTICK) 285 or the LFCLK signal (LFTICK) 286.

[0027] The clock switching circuit 22 provides MFTICK285 and LFTICK286 together with ULPCLK281 from the clock frequency selection circuit 271 to indicate to the IP the time to switch the internal clock frequency of the IP to the clock frequency of ULPCLK281. The connections for providing ULPCLK281, MFTICK285, and LFTICK286 from the clock switching circuit 22 to each of the timer 230, ADC240, DAC250, and one or more peripheral interfaces 260 (e.g., collectively "IP" or individually "IP") are indicated by respective arrows in FIG. 2.

[0028] The clock switching circuit 22 performs clock switching to reduce signal timing glitches and latency in the IP. For example, in response to receiving a clock frequency requirement from the IP for the maximum clock frequency, the clock switching circuit 22 may first select SYSCLK282 in the clock frequency selection circuit 271 and provide it as ULPCLK281. The clock switching circuit 22 may then receive a request from the IP for another frequency and, in response, switch to providing ULPCLK281 based on MFCLK283 or LFCLK284. In some examples, the clock switching circuit 22 may receive requests for both the maximum clock frequency (e.g., SYSCLK282) and one of MFCLK283 or LFCLK284. In response, the clock switching circuit 22 may provide ULPCLK281 based on SYSCLK282, and the IP that requests the clock frequency of MFCLK283 or LFCLK284 may internally derive and generate its clock frequency based on ULPCLK281 (e.g., at the frequency of SYSCLK282) and MFTICK285 or LFTICK286. For example, the receiving IP may gate ULPCLK281 according to MFTICK285 or LFTICK286 to generate an internal MF clock signal or an internal LF clock signal, respectively. In some examples, the gating is performed by an ICG included in the receiving IP.

[0029] The clock switching circuit 22 also synchronizes MFTICK285 and LFTICK286 with the clock cycle of ULPCLK281 during each clock switching. A clock cycle is the repeated time period during which a signal transitions between an asserted high value and a low value, and is determined by the clock frequency of the signal. For example, when the clock frequency signal is high, the clock cycle (e.g., period) is short. The clock switching circuit 22 synchronizes MFTICK285 and LFTICK286 with the clock cycle of ULPCLK281 by detecting and aligning the rising edges of the clock cycles of ULPCLK281, MFTICK285, and LFTICK286 within time, as will be described in subsequent examples. In response to receiving a ULPCLK281 at a frequency other than the frequency requested by the IP, the IP is configured to generate an internal clock signal at the requested frequency according to the received ULPCLK281 and the synchronized MFTICK285 or LFTICK286. Synchronizing the clock cycles of MFTICK285 and LFTICK286 with ULPCLK281 reduces signal timing glitches in the IP during clock switching. By first providing SYSCLK282 as ULPCLK281, the clock cycles of MFTICK285 and LFTICK286 can be synchronized quickly in comparison to switching ULPCLK281 to MFCLK283 or LFCLK284, thus reducing the latency in clock switching in the IP.

[0030] FIG. 3 is a diagram of a signal 300 for clock switching according to various examples. The signal 300 can be exchanged within the SoC / MCU 20 and performs clock switching for IP by a clock switching circuit 22 controlled by the FSM 272 or the like. The signal 300 includes a SYSCLK 282 having a first clock cycle 302 corresponding to a first clock frequency (e.g., about 20 MHz), an LFCLK 284 having a second clock cycle 304 corresponding to a second clock frequency (e.g., about 32 kHz), and an MFCLK 283 having a third clock cycle 306 corresponding to a third clock frequency (e.g., about 2 MHz). The SYSCLK 282, LFCLK 284, and MFCLK 283 are provided to the clock switching circuit 22 by their respective oscillators 273. Also shown in FIG. 3 are ULPCLK_MF and ULPCLK_LF. ULPCLK_MF has an average frequency approximately equal to the frequency of MFCLK 283 and represents an internally generated clock that can be generated by an ICG as described herein based on the received ULPCLK 281 and MFTICK 285. ULPCLK_LF has an average frequency approximately equal to the frequency of LFCLK 284 and represents an internally generated clock that can be generated by an ICG as described herein based on the received ULPCLK 281 and LFTICK 286. As shown in FIG. 3, the signal 300 is not shown to scale and is not shown using the exact frequency ratios between the various signals of the signal 300 in order to depict the principles of the present disclosure in waveform.

[0031] Signal 300 includes a first request signal (LFCLK request) 308 that requests LFCLK284, a second request signal (SYSCLK request) 310 that requests SYSCLK282, and a third request signal (MFCLK request) 312 that requests MFCLK283. The LFCLK request 308, SYSCLK request 310, and MFCLK request 312 are provided to the clock management circuit 270 by the same IP or different IPs at different times and may request clock signals at their respective clock frequencies. In this regard, multiple instances of the LFCLK request 308, SYSCLK request 310, and MFCLK request 312 may be received in an example with multiple independent IPs. Signal 300 also includes ULPCLK281, LFTICK286, and MFTICK285 as described above. The clock frequency selection circuit 271 selects one of SYSCLK282, LFCLK284, or MFCLK283 to be used as ULPCLK281 according to a control signal provided by the FSM272. The FSM272 provides a control signal according to the state transition of the FSM272 that determines clock switching and controls the selection by the clock frequency selection circuit 271 of ULPCLK281.

[0032] For example, as shown in FIG. 3, SYSCLK282, LFCLK284, and MFCLK283 are provided to the clock frequency selection circuit 271 by their respective oscillators 273. The LFCLK request 308 can be set and maintained at a pre-asserted high value in response to a request from the IP or the clock management circuit 270. Accordingly, ULPCLK281 is pre-set to the clock frequency of LFCLK284 having the second clock cycle 304. In response to a new request for MFCLK283 or SYSCLK282 by any IP or clock management circuit 270, the clock switching circuit 22 switches ULPCLK281 to SYSCLK282 having the first clock cycle 302. The requests for MFCLK283 or SYSCLK282 are indicated by setting the MFCLK request 312 or the SYSCLK request 310 to a pre-asserted high value, respectively. After switching ULPCLK281 to SYSCLK282, the clock switching circuit 22 synchronizes LFTICK286 and MFTICK285 to ULPCLK281 according to the clock frequency of SYSCLK282. Synchronization of signals includes aligning the rising edges at different clock cycles of signals that are temporally different. Although not specifically shown in FIG. 3, the widths of the clock cycles of LFTICK286 and MFTICK285 can match the widths of the clock cycles of LFCLK284 and MFCLK283, respectively. If the received new request is for SYSCLK282, no further action is taken. If the received new request is for IMFCLK283, first, after switching ULPCLK281 from LFCLK284 to SYSCLK282, the MFCLK request 312 is set or maintained at a pre-asserted high value, and the SYSCLK request 310 is set to a pre-asserted low value. In this case, ULPCLK281 is then switched from SYSCLK282 to MFCLK283. MFTICK285 is also set to a pre-asserted high value. If ULPCLK281 is pre-set to MFCLK283 and a request for SYSCLK282 is received, a similar process can be implemented.

[0033] In another example not shown in FIG. 3, if ULPCLK281 is pre-set to MFCLK283 and a new request for LFCLK284 or SYSCLK282 is received by either the IP or any of the clock management circuits 270, the clock switching circuit 22 switches ULPCLK281 to SYSCLK282. The request for LFCLK284 or SYSCLK282 is indicated by setting the LFCLK request 308 or SYSCLK request 310, respectively, to the asserted high value. After switching ULPCLK281 to SYSCLK282, the clock switching circuit 22 synchronizes LFTICK286 and MFTICK285 to ULPCLK281 according to the clock frequency of SYSCLK282. If the received new request is for SYSCLK282, no further action is taken. If the received new request is for LFCLK284, first ULPCLK281 is switched from MFCLK283 to SYSCLK282, then the LFCLK request 308 is set or maintained at the asserted high value, and the SYSCLK request 310 is set to the asserted low value. In this case, ULPCLK281 is then switched from SYSCLK282 to LFCLK284. LFTICK286 is also set to the asserted high value, and MFTICK285 is set to the asserted low value. In one example, two IPs may request MFCLK283 and LFCLK284 individually. In this case, the requested highest clock frequency is provided together with a clock frequency enable signal set for the requested lowest clock frequency. Thus, the MFCLK request 312 is maintained at the asserted high value, ULPCLK281 is set and maintained to MFCLK283, and cannot be switched to LFCLK284. LFTICK286 is also provided in synchronization with MFCLK283.

[0034] By switching ULPCLK281 from LFCLK284 to SYSCLK282 and then to MFCLK283, or from MFCLK283 to SYSCLK282 and then to LFCLK284, it is possible to synchronize the clock cycle of MFTICK285 faster with the clock cycle of ULPCLK281 compared to directly switching ULPCLK281 from LFCLK284 to MFCLK283. By synchronizing MFTICK285 and LFTICK286 to ULPCLK281 according to the clock frequency of SYSCLK282, signal timing glitches in the IP are avoided when performing clock switching. Switching ULPCLK281 to SYSCLK282 results in a shorter setup time compared to switching to MFCLK283, reducing the latency in clock switching in the IP. For example, when SYSCLK282 is equal to about 20 MHz, the setup time of SYSCLK282 can be less than about 1 microsecond (μs). When MFCLK283 is equal to about 2 MHz, the setup time of MFCLK283 can be equal to about 10 μs. When LFCLK284 is equal to about 32 kHz, the setup time of LFCLK284 can be equal to about 1 millisecond (ms). Faster synchronization in the clock switching circuit 22 also reduces the latency in the IP when performing clock switching. For example, when ULPCLK281 is directly switched from LFCLK284 to MFCLK283, synchronizing the clock cycle of MFTICK285 to the clock cycle of ULPCLK281 may take a longer time because the clock cycle of LFCLK284 is longer compared to SYSCLK282. For example, the clock switching time from LFCLK284 at about 32 kHz to MFCLK283 at about 2 MHz or SYSCLK282 at about 20 MHz can be less than about 2 μs. The state transition of the FSM272 for controlling the clock frequency selection circuit 271 in the clock switching circuit 22 can be less than about 10 - 20 clock cycles of the signal 300, including the synchronization delay.

[0035] FIG. 4 is a diagram of a clock frequency selection circuit 271 according to various examples. The clock frequency selection circuit 271 is configured to selectively provide ULPCLK281 based on SYSCLK282, LFCLK284, or MFCLK283 according to the state transition of the FSM272. The clock frequency selection circuit 271 may include a delay element 410 coupled to a first multiplexer 420 coupled to an AND gate 430, and an ICG440 coupled to a second multiplexer 450 also coupled to the AND gate 430. In some examples, the components of the clock frequency selection circuit 271 may be part of the clock switching circuit 22.

[0036] Although the FSM272 is not shown in FIG. 4, the clock frequency selection circuit may operate at least partially under the control of the FSM272. For example, the FSM272 may be configured by software, hardware, or both in the clock management circuit 270 to provide control signals to the clock frequency selection circuit 271. The control signals determine the state transitions for selecting ULPCLK281 in the clock frequency selection circuit 271. The control signals include a medium clock frequency slow indication signal (slowismfclk) 471 provided to the first multiplexer 420, a clock frequency signal low value signal (frcclklow) 472 provided to the AND gate 430 and the ICG440, and an uplink primary clock frequency slow indication signal (ulpclkisslow) 473 provided to the second multiplexer 450. The values of the control signals provided by the FSM272 provide the state transitions for determining clock switching in the clock frequency selection circuit 271.

[0037] To reduce signal timing glitches in clock switching, the FSM 272 may control the timing of individual control signals for each element of the clock frequency selection circuit 271 to provide a time delay of at least one clock cycle of SYSCLK282 in the control signals. For example, when the clock frequency of SYSCLK282 is about 20 MHz, the control signals slowismfclk, frcclklow, and ulpclkisslow may be separated by a time delay of about 50 nanoseconds (ns).

[0038] The FSM 272 provides slowismfclK471 to the first multiplexer 420, such that the first multiplexer 420 provides the slow clock frequency signal (slowclk) 481 as either MFCLK 283, or a delayed representation of LFCLK (delayed LFCLK) 482 provided by the delay element 410. For example, slowismfclK471 is set to an asserted high value such that the first multiplexer 420 provides slowclK481 as MFCLK 283, or is set to an asserted low value such that the first multiplexer 420 provides the delayed LFCLK 482 as slowclK481. The delayed LFCLK 482 is provided by a delay element 410 which can be any suitable circuit element that produces a controllable or programmable delay, delaying LFCLK 284 by one or more clock cycles of SYSCLK 282. For example, if the clock frequency of SYSCLK 282 is about 20 MHz, LFCLK 284 can be delayed by about 140 ns. The FSM 272 provides frcclklow472 to the AND gate 430 and provides slowclk_frc474 based on slowclK481 and frcclklow472. In some examples, frcclklow472 is provided to the inverted input of the AND gate 430, or an inverter (not shown) is placed in series between the FSM 272 and the AND gate 430 to invert the value of frcclklow472 after the output by the FSM 272 and before it is received by the AND gate 430. The AND gate 430 provides slowclk_frc474 as an asserted value in response to slowclK481 having an asserted value and frcclklow472 having a de-asserted value. Similarly, the AND gate 430 provides slowclk_frc474 having a de-asserted value in response to slowclK481 having a de-asserted value or frcclklow472 having an asserted value.FSM272 also provides frcclklow472 to ICG440, thereby causing ICG440 to gate SYSCLK282 according to frcclklow472 and providing SYSCLK282 as the system clock frequency signal low value indication signal (sysclkfrclow) 483 to the second multiplexer 450. In some examples, frcclklow472 is provided to the inverted gate input of ICG440, or an inverter (not shown) is arranged in series between FSM272 and ICG440 to invert the value of frcclklow472 after the output by FSM272 and before the reception by ICG440. Accordingly, ICG440 provides SYSCLK282 as sysclkfrclow483 in response to frcclklow472 having an asserted low value. FSM272 provides ulpclkisslow473 to the second multiplexer 450, whereby the second multiplexer 450 provides ULPCLK281 as one of slowclk_frc474 or sysclkfrclow483. For example, in response to ulpclkisslow473 having an asserted high value, ULPCLK281 is set to the value of slowclk_frc474. Similarly, in response to ulpclkisslow473 having a de-asserted value, ULPCLK281 is set to the value of sysclkfrclow483.

[0039] In one example, FSM272 controls oscillator 273 as illustrated and described with reference to FIG. 2, thereby providing SYSCLK282, switching ULPCLK281 from SYSCLK282 to MFCLK283 or LFCLK284, turning off LFTICK286 and MFTICK285 after synchronizing them to ULPCLK281, thereby saving power within SoC / MCU20. FSM272 also controls oscillator 273 to turn on in response to receiving a clock switching request, such as switching ULPCLK281 from LFCLK284 to MFCLK283 or from MFCLK283 to LFCLK284.

[0040] FIG. 5 is a diagram of a clock switching circuit 500 according to various examples. The clock switching circuit 500 can be part of the clock switching circuit 22 and is configured to provide MFTICK285 in synchronization with the clock cycle of ULPCLK281 according to the clock frequency of SYSCLK282. The clock switching circuit 500 can include a rising edge detection circuit 501 coupled to the FSM272. The rising edge detection circuit 501 includes a first delay element 502, a second delay element 504 coupled to the first delay element 502, and an AND gate 505 coupled to the second delay element 504. Two first delay elements 502 are shown in FIG. 5, but in various examples, any suitable non-zero number of first delay elements 502 can be included in the rising edge detection circuit 501. In some examples, the first delay element 502 and the second delay element 504 can be flip-flops or latches. The clock switching circuit 500 can also include a counter 507 coupled to the FSM272, an AND gate 508 coupled to the FSM272 and the counter 507, and an OR gate 509 coupled to the AND gate 508 and the FSM272.

[0041] The rising edge detection circuit 501 is configured to detect the rising edge of MFCLK283 and, in response thereto, provide a MFCLK rising edge indication signal (MFEDGE) 513. In at least some examples, MFEDGE 513 may be useful for providing MFTICK285 in synchronization with SYSCLK282. The first delay element 502 and the second delay element 504 of the rising edge detection circuit 501 provide MFCLK283 synchronized with SYSCLK282 based on the detection of the rising edge of MFCLK283. The AND gate 505 provides MFEDGE 513 to the FSM272 based on MFCLK283 provided by the first delay element 502 and the inverted representation of MFCLK283 provided by the second delay element 504. The FSM272 provides MFEDGE 513 and SYSCLK282 to the counter 507 as data and clock inputs, respectively. The counter 507 is configured to provide MFTICK_RAW to the AND gate 508. In some examples, the counter 507 is programmable to provide the programmed number of clock cycles of SYSCLK282 to MFTICK_RAW after the detection time of the rising edge in MFEDGE 513. Thereby, MFTICK_RAW is synchronized with SYSCLK282. The number of clock cycles of the counter 507 may be proportional to the ratio of the clock frequency of SYSCLK282 to the clock frequency of MFCLK283. For example, if the clock frequency of SYSCLK282 is equal to about 20 MHz and the clock frequency of MFCLK283 is equal to about 2 MHz, the number of clock cycles may be equal to about 10.

[0042] The FSM 272 provides an MFCLK selection signal (MF_SEL) 514 and a SYSCLK selection signal (SYS_SEL) 515, which may be useful for providing MFTICK 285. The MF_SEL 514 is provided to the AND gate 508. In some examples, the MF_SEL 514 is provided to the inverted input of the AND gate 508, or an inverter (not shown) is arranged in series between the FSM 272 and the AND gate 508 to invert the value of the MF_SEL 514 after the output by the FSM 272 and before the reception by the AND gate 508. The output of the SYS_SEL 515 and the AND gate 508 is provided to the OR gate 509. In some examples, the SYS_SEL 515 is provided to the inverted input of the OR gate 509, or an inverter (not shown) is arranged in series between the FSM 272 and the OR gate 509 to invert the value of the SYS_SEL 515 after the output by the FSM 272 and before the reception by the OR gate 509. The OR gate 509 provides MFTICK 285 based on performing an OR logical operation between the SYS_SEL 515 (or the inverted representation of the SYS_SEL 515) and the output of the AND gate 508.

[0043] FIG. 6 is a diagram of signals 600 for clock switching according to various examples. The signals 600 include signals that can be switched in the clock switching circuit 500 to perform clock switching for the IP. In at least some examples, the signals shown in FIG. 6 include signals useful for providing MFTICK 285. The signals 600 include SYSCLK 282, MFCLK 283, MFEDGE 513, the MFTICK counter signal (MFTICKCNT) 601 of the counter 507, MFTICK 285, and ULPCLK 281 (where the switch from MFCLK 283 to SYSCLK 282 is shown in FIG. 6). The signals 600 also include ULPCLK_MF as described above. In the description of the signals 600, components in various preceding figures of this description, such as components that may provide or receive the described signals, may be referenced.

[0044] As described above, after detecting the asserted high value 603 of MFCLK283, the rising edge detection circuit 501 provides MFEDGE513. The rising edge detection circuit 501 can also be aligned to start MFEDGE513 at the same time as the SYSCLK falling edge 604. The rising edge detection circuit 501 provides MFEDGE513 to the FSM272, and the FSM272 provides MFEDGE513 to the counter 507. In response to detecting the asserted high value 605 of MFEDGE513, the counter 507 starts a countdown set to a programmed time period. For example, the countdown time period can be approximately equal to 9 clock cycles of SYSCLK282. The 9 clock cycles of the countdown time period are each based on the ratio of 20 MHz to 2 MHz of SYSCLK282 and MFCLK283, taking into account approximately 2 clock cycles for additional clock switching delay in the clock switching circuit 500. Generally, the countdown can be programmed to start at an X - Y value, where X is the integer representation of the frequency ratio between SYSCLK282 and MFCLK283, and Y is the estimated number of clock cycles for synchronization in the clock switching circuit 500. In response to the value of MFTICKCNT601 being asserted (e.g., "1"), MFTICK285 is asserted. Due to the assertion of MFTICK285, the ICG of the received IP provides ULPCLK_MF according to ULPCLK281 and MFTICK285 shown in FIG. 6 respectively. In response to the value of MFTICKCNT601 approaching 0, MFTICK285 is de - asserted. Based on ULPCLK281 and MFTICK285, MFCLK_TICK602 can be provided. For example, the received IP can clock ULPCLK281 via an ICG or the like according to MFTICK285 as described above, and provide MFCLK_TICK602 having an average frequency approximately equal to that of MFCLK283.

[0045] FIG. 7 is a diagram of a clock switching circuit 700 according to various examples. The clock switching circuit 700 can be part of the clock switching circuit 22 and is configured to provide LFTICK286 in synchronization with the clock cycle of ULPCLK281 according to the clock frequency of SYSCLK282. Since the clock frequency of LFCLK284 (e.g., about 32 kHz) can be substantially slower than the clock frequency of SYSCLK282 (e.g., about 20 MHz), in the clock switching circuit 700, when ULPCLK281 switches to SYSCLK282, LFTICK286 can be provided in synchronization with ULPCLK281 without a countdown time period of the clock cycle of SYSCLK282. The clock switching circuit 700 can avoid signal timing glitches that may be caused by signal transitions of ULPCLK281 and LFTICK286 based on LFCLK284 by delaying LFTICK286 or forcing it to a low or high value asserted based on edge detection of LFCLK284.

[0046] In some examples, the clock switching circuit 700 includes a delay element 702, a delay element 704, an AND gate 706, an AND gate 708, an OR gate 709, an AND gate 720, and a multiplexer 714, which are coupled as shown in FIG. 7, respectively. The clock switching circuit 700 also includes a delay element 722, a delay element 724, a delay element 726, a delay element 728, and an inverter 730, which are coupled as shown in FIG. 7, respectively. Two delay elements 722 and two delay elements 726 are shown in FIG. 7, but in various examples, any suitable number can be selected for the delay elements 722 and 726, provided that they are the same number for both the delay element 722 and the delay element 726.

[0047] The delay elements 702 and 704 with the AND gate 706 are configured to detect the rising edge of the delayed LFCLK482 and provide an LFCLK rising edge indication signal (lfclkrise) 710. The delay element 702 provides the LFCLK asserted high indication signal (lfclkishigh) 711 to the AND gate 706, and the delay element 704 provides the inverted and delayed LFCLK asserted high indication signal (~lfclkishigh_dly) 712 to the AND gate 706. Based on lfclkishigh 711 and ~lfclkishigh_dly 712, the AND gate 703 provides lfclkrise 710. The first delay element 702 and the second delay element 704 provide lfclkishigh 711 and ~lfclkishigh_dly 712 based on LFCLK284 and ULPCLK281.

[0048] The AND gate 706 provides a lfclkrise 710 with an asserted high value when both lfclkishigh 711 and ~lfclkishigh_dly 712 have asserted high values. The AND gate 708 provides a lfclkrise 710 based on the output LFCLK rising edge indication signal (lfclkout) 715 and the LFTICK asserted low value indication signal (frclkticklow) 713, and the signal 713 can be provided by the FSM 272. In some examples, frclkticklow 713 is provided to the inverted input of the AND gate 708, or an inverter (not shown) is arranged in series between the FSM 272 and the AND gate 708 to invert the value of frclkticklow 713 after the output by the FSM 272 and before the reception by the AND gate 708. Thus, when lfclkrise 710 has an asserted high value and frclkticklow 713 has an asserted low value, the AND gate 708 provides a lfclkout 715 with an asserted high value. The OR gate 709 provides a first low clock frequency enable signal (ticklf_ulp) 717 synchronized with the clock cycles of lfclkout 715 based on ULPCLK 281 and the LFTICK asserted high value indication signal (frclktickhigh) 716, and the signal 716 can be provided by the FSM 272. When either lfclkout 715 or frclktickhigh 716 has an asserted high value, the OR gate 705 provides a ticklf_ulp 717 with an asserted high value. The multiplexer 714 provides LFTICK 286 based on the ticklf_ulp 717 and the second low clock frequency enable signal (ticklf_sys) 718 synchronized with the clock cycles of SYSCLK 282. The uplink primary clock frequency low speed indication signal (ulpclkisslow) 719 is provided to the multiplexer 714 by the FSM 272 or the like, causing the multiplexer 714 to select either ticklf_ulp 717 or ticklf_sys 718 to provide LFTICK 286.For example, multiplexer 714 provides LFTICK286 as having the value of ticklf_ulp717 in response to ulpclkisslow719 having an asserted high value.

[0049] As described above with respect to FIG. 5, the AND gate 720 provides ticklf_sys718 based on performing an AND logic operation among a signal indicating that MFTICK_RAW and ~lfclk_vec are equal to 2’b00, a signal indicating that ~lfclk_vec is equal to 2’b10, and a signal indicating that ~lfclkvecdly_reg is equal to 2’b10. In some examples, the signal indicating that ~lfclk_vec is equal to 2’b00 is determined according to the logic operation of NOT{(NOT lfclk_vec[1])AND(NOT lfclk_vec[0])}. The logic operation can be performed by any suitable software or hardware implementation (not shown). In some examples, the signal indicating that ~lfclk_vec is equal to 2’b10 is determined according to the logic operation of NOT{lfclk_vec[1]AND(NOT lfclk_vec[0])}. The logic operation can be performed by any suitable software or hardware implementation (not shown). In some examples, the signal indicating that ~lfclkvecdly_reg is equal to 2’b10 is determined according to the logic operation of NOT{lfclkvecdly_reg[1]AND(NOT lfclkvecdly_reg[0])}. The logic operation can be performed by any suitable software or hardware implementation (not shown). In some examples, the delay element 722 provides lfclk_vec[1] based on the inverted representation of SYSCLK282, such as provided by the inverter 730, clocked and delayed by the delayed LFCLK482. The delay element 724 provides lfclkvecdly_reg[1] based on lfclk_vec[1] and the clock according to SYSCLK282. The delay element 726 provides lfclk_vec[0] based on the delayed LFCLK482 (e.g., such as provided by the delay element 410 in FIG. 4, etc.) clocked by the inverted representation of SYSCLK282 and further delayed. The delay element 728 provides lfclkvecdly_reg[0] based on lfclk_vec[0] and clocks according to SYSCLK282.

[0050] Figure 8 is a diagram showing a signal relationship 800 between signal transitions and glitches according to various examples. When switching ULPCLK281 from LFCLK284 to SYSCLK282, the signal transition may include the rising edge of LFCLK284, thereby causing a timing glitch in the IP. For example, a glitch 805 may occur in the IP in response to both ULPCLK281 and LFTICK286 being received with an asserted high value. As shown in Figure 8, before switching ULPCLK281 to SYSCLK282, ULPCLK281 may transition to an asserted high value with LFCLK284. The rising edge of ULPCLK281 may occur before providing a synchronized LFCLK (synchronized LFCLK) 808 that synchronizes LFCLK284 to SYSCLK282. For example, the synchronized LFCLK808 may transition to an asserted high value after one or more clock cycles from LFCLK284 to SYSCLK282. Since ULPCLK281 is transitioned using LFCLK284 instead of the synchronized LFCLK808, LFTICK286 may be forced to an asserted low value by FSM272 after ULPCLK281 transitions to an asserted high value. Thereby, the IP may receive ULPCLK281 and LFTICK286 simultaneously at the asserted high value, thereby causing a glitch 805.

[0051] To avoid glitches, FSM272 is configured to provide LFTICK286 in a manner that does not cause a glitch 805 in the IP. The timing of providing LFTICK286 is based on predicting the rising edge of LFCLK284. FSM272 may be configured to provide LFTICK286 according to four cases of the signal relationship 800 based on the signal values of LFCLK284 and the delayed LFCLK482. The delayed LFCLK482 may be delayed by more than about 2 clock cycles of SYSCLK282, such as a delay of about 140 μs by the delay element 410, and may predict the transition time of the synchronized LFCLK808.

[0052] Among the four cases monitored by the FSM272 and the logic of the clock switching circuit 700 (e.g., AND gate 720), the first case 810 is included when both the LFCLK284 and the delayed LFCLK482 are detected at the asserted low values 811 and 812, respectively. In this case, no current transition is predicted at the synchronized LFCLK808, and the LFTICK286 is provided to the IP from the clock frequency selection circuit 271 together with the ULPCLK281 without causing glitches. The second case 820 is when the asserted low value 821 of the LFCLK284 is detected together with the asserted high value 822 of the delayed LFCLK482. In this case, there is no current rising edge that causes glitches at the LFCLK284, and the LFTICK286 can also be provided to the IP from the clock frequency selection circuit 271 together with the ULPCLK281.

[0053] In the third case 830, when the rising edge or the asserted high value 831 of the LFCLK284 is detected together with the asserted low value 832 of the delayed LFCLK482, a future transition or rising edge for the synchronized LFCLK808 is expected. In this case, when the LFTICK286 is provided to the IP together with the ULPCLK281, glitches 805 may occur. To avoid glitches, the FSM272 does not provide the LFTICK286 to the IP at this point. For example, the FSM272 is configured to delay the provision of the LFTICK286 to the IP for at least one or two clock cycles of the SYSCLK282. The delay in providing the LFTICK286 can avoid receiving both the ULPCLK281 and the LFTICK286 at the asserted high value simultaneously at the IP. In other examples, when the third case 830 occurs, the FSM272 forcibly transitions the LFTICK286 to the asserted low value before the ULPCLK281 transitions to the asserted high value, thereby avoiding the occurrence of glitches 805 at the IP.

[0054] The fourth case is when both LFCLK284 and the delayed LFCLK482 are detected at their respective asserted high values 841 and 842. This indicates that the rising edge of the synchronized LFCLK808 has occurred previously and no current condition for glitch is detected in the IP. In this case, LFTICK286 can also be provided from the clock frequency selection circuit 271 together with ULPCLK281 to the IP without causing a glitch. Table 1 illustrates four cases for configuring the FSM272 to provide LFTICK286 in a manner that does not cause a glitch in the clock signal in the IP. The FSM272 can determine to provide LFTICK286 at the output of the multiplexer 714 within the clock switching circuit 700. TIFF2025518597000002.tif3087

[0055] FIG. 9 is a flowchart of a method 900 for clock switching according to various examples. Method 900 may be implemented by a clock switching circuit 22 to switch the clock frequency of ULPCLK281 and synchronize MFTICK285 and LFTICK286 with the clock cycles of ULPCLK281 according to the clock frequency requirements from the IP. In step 910, the clock frequency requirements are received from the IP by the clock management circuit 270. For example, the clock frequency requirements are received from any of the IPs of the SoC / MCU 20 and request the clock frequency of any of SYSCLK282, MFCLK283, or LFCLK284. In step 920, the clock management circuit 270 determines to switch ULPCLK281 from LFCLK284 to MFCLK283 or from MFCLK283 to LFCLK284 based on the clock frequency requirements. In step 930, ULPCLK281 is switched to SYSCLK282, which is the fastest clock frequency supported by the SoC / MCU 20. For example, ULPCLK281 is switched from LFCLK284 to SYSCLK282 by the clock switching circuit 400 regardless of the requested clock frequency. In step 940, MFTICK285 and LFTICK286 are synchronized with the clock cycles of SYSCLK282. The synchronization is performed by aligning the rising edges of MFTICK285 and LFTICK286 according to the timing of the clock cycles or rising edges of SYSCLK282. For example, MFTICK285 is synchronized with the clock cycles of SYSCLK282 by the clock switching circuit 500, and LFTICK286 is synchronized with the clock cycles of SYSCLK282 by the clock switching circuit 700. In step 950, according to the clock frequency requirements from the IP, ULPCLK281 is switched from SYSCLK282 to MFCLK283 or LFCLK284. In step 960, the synchronized MFTICK285 and LFTICK286 are provided to the IP together with ULPCLK281.

[0056] FIG. 10 is a state diagram 1000 suitable for implementation by a state machine according to various examples. In some examples, the state machine is the FSM 272. The state machine can operate and transition between states at least partially according to the signals and relationships shown in the state diagram 1000. Based on these transitions, the state machine can control a clock selection circuit such as the clock frequency selection circuit 271 to provide a clock signal to other circuits. For example, the state machine can receive requests from various IPs for clock signals having the frequency of SYSCLK282, LFCLK284, or MFCLK283, as described herein. As shown in FIG. 10, a request from an IP to receive a clock signal having the frequency of SYSCLK282 is represented as sysclkreq_sync, and a request from an IP to receive a clock signal having the frequency of MFCLK283 is shown as mfclkreq_sync. A tilde (~) in front of a variable name means a logical NOT function. Thus, a "~" in front of a variable name indicates that the variable has a deasserted value, such as a logical zero value.

[0057] As shown in FIG. 10, each state of the state diagram 1000 corresponds to a control signal provided based on the state machine. In FIG. 10, the control signal is shown as an 8-bit control signal indexed in the right-to-left direction from bit 0 to bit 7. However, in various implementations, the control signal can include a greater number of bits, at least some of which correspond to functionality not described herein. The state machine can provide at least some bits of the control signal to various components of the clock selection circuit, whereby the clock selection circuit provides a clock signal to the IP. The bits of the control signal uniquely correspond to the various control signals described herein, as shown in Table 2 below. TIFF2025518597000003.tif3331

[0058] In state 1002, the state machine controls the clock selection circuit to provide a clock signal such as ULPCLK281 having a frequency approximately equal to the frequency of SYSCLK282. State 1002 can be the reset state of the state machine. Therefore, the state machine starts operating in state 1002 and proceeds to other states of the state machine via state transitions. In response to each of sysclkreq_sync and mfclkreq_sync being received with a de-asserted value (e.g., ~sysclkreq_sync and ~mfclkreq_sync), the state machine transitions to state 1004.

[0059] In state 1004, the state machine implements a delay. For example, state 1004 can be a standby state where the state machine allows clock selection circuit time for setting or implementing other actions or functions outside the scope of the present disclosure. Although shown as a single state, in some examples, state 1004 can be implemented as a plurality of in-progress states instead. In response to ~sysclkreq_sync and ~mfclkreq_sync, and slowfall, the state machine transitions to state 1012. As used herein, slowfall indicates a falling edge detection at slowclK481. In response to sysclkreq_sync or mfclkreq_sync, the state machine transitions to state 1032 and, after a programmed wait time, transitions to state 1002.

[0060] In state 1012, the state machine asserts frcclklow and transitions to state 1014. In state 1014, the state machine maintains the asserted value of frcclklow, asserts ulpclkisslow, asserts frclftickhigh, and transitions to state 1016. In state 1016, the state machine maintains the asserted values of ulpclkisslow and frclftickhigh and de-asserts frcclklow. In response to mfclkfall, the state machine transitions to state 1018. As used herein, mfclkfall indicates a falling edge detection at MFCLK283.

[0061] In state 1018, the state machine controls the clock selection circuit to provide a clock signal having a frequency approximately equal to the frequency of LFCLK284. Also, the state machine maintains the asserted values of ulpclkisslow and frclftickhigh, and asserts frcmfticklow. In some examples, the state machine remains in state 1018 until the reception of sysclkreq_sync or mfclkreq_sync. In response to sysclkreq_sync or mfclkreq_sync, the state machine transitions to state 1022.

[0062] In state 1022, the state machine implements a delay. For example, state 1022 can be a waiting state that allows the state machine the clock selection circuit time to set up or perform other actions or functions outside the scope of the present disclosure. In response to lfclk_vec having the binary value 2’b10 (e.g., the decimal value 2), the state machine transitions to state 1024. In response to lfclk_vec not having the binary value 2’b10 (e.g., not the decimal value 2), the state machine transitions to state 1026.

[0063] In state 1024, the state machine implements a delay. For example, state 1024 can be a waiting state that allows the state machine the clock selection circuit time to set up or perform other actions or functions outside the scope of the present disclosure. In response to lfclk_vec having the binary value 2’b11 (e.g., the decimal value 3), the state machine transitions to state 1026.

[0064] In state 1026, the state machine maintains the asserted values of frcmfticklow and ulpclkisslow, de-asserts frclftickhigh, asserts frclfticklow, asserts frcclklow, and transitions to state 1028.

[0065] In state 1028, the state machine maintains the asserted values of frcmfticklow, frclfticklow, and frcclklow, de-asserts ulpclkisslow, asserts slowismfclk, and transitions to state 1030.

[0066] In state 1030, the state machine maintains the asserted values of frcmfticklow and slowismfclk, de-asserts frclfticklow, and de-asserts frcclklow. In response to the reception of mfgood_sync, the state machine transitions to state 1002. As used herein, mfgood_sync indicates that the oscillator of oscillator 273 that provides MFCLK283 is operating in the normal state.

[0067] When returning to state 1002, the state machine maintains slowismfclk in the asserted state and de-asserts frcmfticklow. In response to ~sysclkreq_sync and mfclkreq_sync, the state machine transitions to state 1040.

[0068] In state 1040, the state machine maintains the asserted value of slowismfclk and implements a delay. For example, state 1040 can be a standby state where the state machine allows clock selection circuit time for setting or implementing other actions or functions outside the scope of the present disclosure. In response to ~sysclkreq_sync and ~mfclkreq_sync, or sysclkreq_sync and mfclkreq_sync, the state machine transitions to state 1002. In response to ~sysclkreq_sync and mfclkreq_sync and lfclk_vec having a binary value of 2’b01 (e.g., a decimal value of 1), the state machine transitions to state 1042.

[0069] In state 1042, the state machine maintains the asserted value of slowismfclk and implements a delay. For example, state 1042 can be a wait state where the state machine allows clock selection circuit time to set or perform other actions or functions outside the scope of the present disclosure. In response to mfclkrise, the state machine transitions to state 1044. As used herein, mfclkrise indicates rising edge detection at MFCLK283.

[0070] In state 1044, the state machine maintains the asserted value of slowismfclk, asserts frclfticklow, asserts frcmftickhigh, asserts frcclklow, and transitions to state 1046. In state 1046, the state machine maintains the asserted values of slowismfclk, frclfticklow, frcmftickhigh, and frcclklow, and asserts ulpclkisslow. In response to mfclkfall, the state machine transitions to state 1048.

[0071] In state 1048, the state machine controls the clock selection circuit to provide a clock signal having a frequency approximately equal to the frequency of MFCLK283. Also, the state machine maintains the asserted values of slowismfclk, frclfticklow, and ulpclkisslow, and de-asserts frclfticklow and frcclklow. In some examples, the state machine remains in state 1048 until the receipt of sysclkreq_sync or ~mfclkreq_sync. In response to sysclkreq_sync or ~mfclkreq_sync, the state machine transitions to state 1052.

[0072] In state 1052, the state machine implements a delay. For example, state 1052 can be a standby state where the state machine allows clock selection circuit time for setting or implementing other actions or functions outside the scope of the present disclosure. In response to mfclkfall, lfclk_vec not having a binary value of 2’b10 (e.g., a decimal value of 2), and lfclkdly_reg not having a value of 2’b10 (e.g., a decimal value of 2), the state machine transitions to state 1054.

[0073] In state 1054, the state machine implements a delay. For example, state 1054 can be a standby state where the state machine allows clock selection circuit time for setting or implementing other actions or functions outside the scope of the present disclosure. In response to lfclk_vec having a binary value of 2’b10 (e.g., a decimal value of 2), or lfclkdly_reg having a value of 2’b10 (e.g., a decimal value of 2), the state machine transitions to state 1056.

[0074] In state 1056, the state machine implements a delay. For example, state 1056 can be a standby state where the state machine allows clock selection circuit time for setting or implementing other actions or functions outside the scope of the present disclosure. In response to mfclkrise, the state machine transitions to state 1058.

[0075] In state 1058, the state machine implements a delay. For example, state 1058 can be a standby state where the state machine allows clock selection circuit time for setting or implementing other actions or functions outside the scope of the present disclosure. In response to mfclkrise, the state machine transitions to state 1060.

[0076] When returning to state 1054, in response to mfclkrise, lfclk_vec not having a binary value of 2’b10 (e.g., a decimal value of 2), and lfclkdly_reg not having a value of 2’b10 (e.g., a decimal value of 2), the state machine transitions to state 1060.

[0077] In state 1060, the state machine implements a delay. For example, state 1060 can be a waiting state where the state machine allows clock selection circuit time for setting or implementing other actions or functions outside the scope of this disclosure. In response to MFTICKCNT601 maintained and provided by counter 507 having a binary value of 4’b0100 (e.g., decimal value of 8), the state machine transitions to state 1062.

[0078] In state 1062, the state machine maintains frcmtickhigh, slowismfclk, and ulpclkisslow as having asserted values, asserts frclfticklow, asserts frcclklow, and transitions to state 1064. In state 1064, the state machine maintains frcmfticklow, slowismfclk, and frcclklow as having asserted values, de-asserts ulpclkisslow, and transitions to state 1066. In state 1066, the state machine maintains frmcmftickhigh and slowismfclk as having asserted values, de-asserts frclfticklow and frcclklow, and transitions to state 1002.

[0079] To provide the control signals shown in FIG. 10 and described herein, a state machine operating according to the above-described states and transitions provides a clock signal to a requesting device such as an IP described herein. The clock signal provided by the clock selection circuit under the control of the state machine can be a frequency among the highest frequencies required by the IP. The clock selection circuit can further provide enable signals such as MFTICK285 and LFTICK286 to the requesting IP. The requesting IP can receive the clock signal provided under the control of the state machine and, by clocking the clock signal according to the enable signal (e.g., via an ICG or the like already described herein), the IP can derive a lower frequency clock signal. However, since these lower frequency clock signals are derived by each requesting IP from the same clock signal provided under the control of the state machine, at least some of the problems associated with exchanging signals across clock boundaries are reduced.

[0080] The term "coupled" is used throughout this specification. This term can encompass connections, communications, or signal paths that enable a functional relationship consistent with the description herein. For example, if device A provides a signal for controlling device B to perform a certain action, in a first example, device A is coupled to device B, or in a second example, if intervening component C does not substantially change the functional relationship between device A and device B, device A is coupled to device B via intervening component C such that device B is controlled by device A via a control signal generated by device A.

[0081] A device “configured” to perform a task or function can be configured by the manufacturer at the time of manufacture to perform that function (e.g., programmed and / or wired), or can be configured (or reconfigured) by the user after manufacture to perform such functions and / or other additional or alternative functions. Such configuration can be via the device's firmware and / or software programming, or via the configuration and / or layout of hardware components, the interconnection of the device, or a combination thereof.

[0082] A circuit or device described as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more circuit elements (flip-flops, latches, gates, multiplexers, counters, etc.) and / or one or more sources (voltage and / or current sources, etc.) may instead include the circuit elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and be adapted to be coupled to at least some of the circuit elements and / or sources such that, at any point in time during or after manufacture, e.g., by an end user and / or a third party, the described structure may be formed.

[0083] Although certain components are described as being of a particular process technology, these components may be interchangeable with those of other process technologies. The circuits described herein are reconfigurable to include the replaced components in order to provide a function that is at least partially similar to the functionality that was available prior to the component replacement.

[0084] Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means + / - 10 percent of the stated value. Within the scope of the claims, modifications are possible in the described examples, and other implementations are possible.

Claims

1. It is a device, A clock switching circuit coupled to an oscillator and one or more circuit units, A set of frequency signals is received from the oscillator. An uplink primary clock signal and an enable signal, which is determined in synchronization with the uplink primary clock signal, are provided to one or more circuit units. Receiving a clock frequency request from one or more of the aforementioned circuit units or clock management circuits, The uplink primary clock signal is provided based on a first signal from the set of frequency signals. In accordance with the clock frequency request, it is determined whether to continue providing the uplink primary clock signal based on the first signal or the second signal from the set of frequency signals. A device including the clock switching circuit configured as described above.

2. The apparatus according to claim 1, An apparatus further comprising a finite state machine (FSM) coupled to the clock switching circuit, the FSM being configured to provide a control signal for controlling the clock switching circuit for providing the uplink primary clock signal.

3. The apparatus according to claim 2, The apparatus includes a clock frequency selection circuit configured to select the uplink primary clock signal from a set of frequency signals in accordance with the control signal.

4. The apparatus according to claim 3, The set of frequency signals includes a low clock frequency signal, a medium clock frequency signal, and a high clock frequency signal. The aforementioned clock frequency selection circuit A delay element having a delay element input configured to receive the low clock frequency signal and a delay element output configured to provide the delayed low clock frequency signal, A first multiplexer having a first input configured to receive the medium clock frequency signal, a second input coupled to the delay element output, and an output configured to provide a low clock frequency signal as one of the medium clock frequency signal or the delayed low clock frequency signal according to a medium clock frequency low speed indicator signal included in the control signal, An AND gate having a first input coupled to the output of the first multiplexer, a second input configured to receive the reciprocal of a low-value indicator of a clock frequency signal included in the control signal, and an output configured to provide an uplink primary clock multiplexer signal, An integrated clock gate (ICG) having a data input configured to receive the high clock frequency signal, a control input configured to receive the clock frequency signal low value indicator signal, and an output configured to provide the system clock frequency signal low value indicator signal, A second multiplexer having a first input coupled to the output of the AND gate, a second input coupled to the output of the ICG, and an output configured to provide the uplink primary clock signal based on the uplink primary clock multiplexer signal, the system clock frequency signal low value indicator signal, and the uplink primary clock frequency low speed indicator signal included in the control signal, A device including a device.

5. The apparatus according to claim 3, The apparatus further comprises a clock switching circuit configured to provide a second enable signal in a manner synchronized with the clock cycle of the high clock frequency signal, based on a medium clock frequency selection signal and a high clock frequency selection signal included in the control signal.

6. The apparatus according to claim 5, The clock switching circuit further includes an edge detection circuit coupled to the FSM, which is configured to detect the rising edge of the medium clock frequency signal, The second enable signal is provided by the clock switching circuit based on the detected rising edge of the medium clock frequency signal. The rising edge detection circuit, A delay element having an output configured to provide a medium clock frequency signal that synchronizes with the high clock frequency signal based on the detection of the rising edge, An AND gate coupled to the delay element, having a first output configured to provide the FSM with a rising edge indicator signal for a medium clock frequency signal, and a second output configured to provide the high clock frequency signal from the delay element, wherein the rising edge indicator signal for the medium clock frequency signal is transmitted based on the detection of the rising edge of the medium clock frequency signal, A device including a device.

7. The apparatus according to claim 6, The aforementioned clock switching circuit A digital counter coupled to the FSM, the digital counter having an output configured to provide a second enable raw signal with the number of clock cycles of the high clock frequency signal after receiving the rising edge indicator signal of the medium clock frequency signal, A second AND gate having a first input coupled to the FSM and configured to receive the reciprocal of the medium clock frequency selection signal included in the control signal, a second input coupled to the output of the digital counter, and an output, An OR gate having a first input coupled to the FSM and configured to receive a high clock frequency signal selection signal from among the control signals, a second input coupled to the output of the second AND gate, and an output configured to provide the medium clock frequency selection signal, A device that further includes the following.

8. The apparatus according to claim 7, A device in which the number of clock cycles of the high-clock-frequency signal is proportional to the ratio of the first clock frequency of the high-clock-frequency signal to the second clock frequency of the medium-clock-frequency signal.

9. The apparatus according to claim 1, The set of frequency signals includes a low clock frequency signal, a medium clock frequency signal, and a high clock frequency signal. The aforementioned clock switching circuit A delay element having a first output configured to provide a low-clock frequency signal high-value indicator signal, and a second output configured to provide a delayed low-clock frequency signal high-value indicator signal, A first AND gate coupled to the delay element, having an output configured to provide a low clock frequency rising edge indicator signal based on the low clock frequency signal high value indicator signal and the delayed low clock frequency signal high value indicator signal, A second AND gate coupled to the first AND gate, the second AND gate having an output configured to provide an output low clock frequency signal rising edge indicator signal based on the reciprocal of the low clock frequency signal low value indicator signal, An OR gate configured to be coupled to the second AND gate to receive a third enable signal high value indicator signal, and having an output configured to provide a low clock frequency synchronized with the uplink primary clock signal, A multiplexer coupled to the OR gate, having an output configured to provide the low clock frequency enable signal based on the low clock frequency synchronized with the clock cycle of the uplink primary clock signal, the low clock frequency synchronized with the clock cycle of the high clock frequency signal, and the uplink primary clock signal low value indicator signal, A device that further includes the following.

10. It is a method, The clock management circuit receives a clock frequency request from the first circuit unit for a clock signal having a first frequency, The clock management circuit determines, based on the clock frequency request, to provide an uplink primary clock signal based on a first clock frequency signal from a set of clock frequency signals, wherein the determination is made that the first clock frequency signal has the first frequency. The clock management circuit receives a second clock frequency request from a second circuit unit for a second clock signal having a second frequency, In response to the second frequency being smaller than the first frequency, the clock management circuit determines, based on the second clock frequency request, to continue providing the uplink primary clock signal based on the first clock frequency signal. In response to the fact that the second frequency is greater than the first frequency, the clock management circuit determines, based on the second clock frequency request, to provide the uplink primary clock signal based on the second clock frequency signal from the set of clock frequency signals, wherein the determination is made that the second clock frequency signal has the second frequency. The uplink primary clock signal and the enable signal are provided to the first circuit unit and the second circuit unit, wherein the enable signal is provided in synchronization with the uplink primary clock signal. Methods that include...

11. The method according to claim 10, In response to the second frequency being greater than the first frequency, the first circuit unit generates a first internal clock signal having the first frequency based on the uplink primary clock signal and the enable signal. In response to the fact that the second frequency is smaller than the first frequency, the second circuit unit generates a second internal clock signal having the second frequency based on the uplink primary clock signal and the enable signal, Methods that further include the above.

12. The method according to claim 10, The clock management circuit receives a third clock frequency request from a third circuit unit for a third clock signal having a third frequency, In response to the third frequency being smaller than the first frequency and the second clock frequency, the clock management circuit determines to continue providing the uplink primary clock signal based on the higher frequency among the first clock frequency signal and the second clock frequency signal. In response to the third frequency being greater than the first and second frequencies, the clock management circuit determines, based on the third clock frequency request, to provide the uplink primary clock signal from the set of clock frequency signals based on the third clock frequency signal, wherein the determination is made that the third clock frequency signal has the third frequency. The uplink primary clock signal, the enable signal, and the second enable signal are provided to the circuit unit, the second circuit unit, and the second circuit unit, wherein the enable signal and the second enable signal are provided in synchronization with the uplink primary clock signal. Methods that further include the above.

13. The method according to claim 12, The first frequency is greater than the second frequency and the third frequency. The method described above is The second circuit unit generates a second internal clock signal having the second frequency based on the uplink primary clock signal and the enable signal, The third circuit unit generates a third internal clock signal having the third frequency based on the uplink primary clock signal and the second enable signal, Methods that further include the above.

14. The method according to claim 12, The third frequency is greater than the first frequency and the second frequency. The method described above is The first circuit unit generates a first internal clock signal having the first frequency based on the uplink primary clock signal and the enable signal, The second circuit unit generates a second internal clock signal having the second frequency based on the uplink primary clock signal and the second enable signal, Methods that further include the above.

15. The method according to claim 10, Providing each frequency signal of the set of clock frequency signals via each oscillator, wherein the set of clock frequency signals includes a third clock frequency signal having a third frequency greater than the first frequency and the second frequency, In response to the third frequency being greater than the first frequency required by the first circuit unit and the second frequency required by the second circuit unit, the oscillator of the oscillator providing the third clock frequency signal is disabled. Methods that further include the above.

16. The method according to claim 10, A method further comprising disabling an oscillator that provides the first clock frequency signal in response to providing the uplink primary clock signal based on the second clock frequency signal.

17. It is a device, Clock switching circuit and A finite state machine (FSM), A first control signal for a state transition is provided to the clock switching circuit to determine whether to switch the uplink primary clock signal from a first clock frequency signal to a second clock frequency signal or a third clock frequency signal. A second control signal is provided to the clock switching circuit in order to provide a second clock frequency enable signal and a third clock frequency enable signal, which are generated in synchronization with the uplink primary clock signal, together with the uplink primary clock signal. The FSM is configured as follows: Includes, An apparatus in which the first clock frequency signal has a faster clock frequency than the second clock frequency signal, and the third clock frequency signal has a slower clock frequency than the second clock frequency signal.

18. The apparatus according to claim 17, The aforementioned FSM, A second clock frequency low-speed indicator signal is provided to the clock switching circuit, causing it to provide a delayed third clock frequency signal or a low clock frequency signal from the second clock frequency signal. The clock switching circuit is provided with a clock frequency signal low value indicator signal that causes the clock switching circuit to provide a system clock frequency signal low value indicator signal based on the high clock frequency signal, and the uplink primary clock multiplexer signal is determined using the low clock frequency signal. The clock switching circuit is provided with an uplink primary clock frequency low-speed indicator signal that causes it to provide an output clock frequency signal based on the uplink primary clock multiplexer signal and the system clock frequency signal low-speed indicator signal. The clock switching circuit is provided with the uplink primary clock multiplexer signal, which causes the clock switching circuit to provide the uplink primary clock signal based on the output clock frequency signal and the high clock frequency signal. A device further configured in this way.

19. The apparatus according to claim 17, The apparatus further configured such that the FSM provides the clock switching circuit with an uplink primary clock frequency low-speed indicator signal, causing the clock switching circuit to provide the third clock frequency enable signal as one of a first third clock frequency enable signal synchronized with the clock cycle of the uplink primary clock signal and a second third clock frequency enable signal synchronized with the clock cycle of the high clock frequency signal.

20. The apparatus according to claim 17, The aforementioned FSM, A second clock frequency selection signal is provided to the clock switching circuit to cause it to select the second clock frequency signal. A high clock frequency selection signal is provided to the clock switching circuit to cause it to select the second clock frequency signal. A device further configured in this way.

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