Semiconductor device and method for manufacturing a semiconductor device

Abstract

The semiconductor device (100) includes a semiconductor body (1) having an upper surface (10), a main electrode (2) on the upper surface, and a gate electrode (3). The semiconductor body includes a drift layer (11) of a first conductivity type, a first base region (12) of a second conductivity type, a second base region (13) of the first conductivity type, a first contact region (14) of the first conductivity type, and a second contact region (15) of the second conductivity type. The second base region has a higher doping concentration than the drift layer. The first contact region is adjacent to the first base region and the upper surface. The second contact region is adjacent to the second base region and the upper surface. The main electrode is in electrical contact with the first and second contact regions. In a first lateral direction, at least a part of the gate electrode is disposed between the first contact region and the second contact region.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices.

Background Art

[0002] There is a need for improved semiconductor devices, for example, semiconductor devices that enable efficient removal of charge carriers such as holes from the semiconductor body during turn-off transients without sacrificing on-state losses. Further, there is a need for improved methods for manufacturing such semiconductor devices.

Summary of the Invention

Means for Solving the Problems

[0003] Embodiments of the present disclosure relate to improved semiconductor devices and improved methods for manufacturing semiconductor devices.

[0004] First, a semiconductor device is identified. According to one embodiment, a semiconductor device includes a semiconductor body having an upper surface, a main electrode on the upper surface, and a gate electrode. The semiconductor body includes a drift layer of a first conductivity type. The semiconductor body further includes a first base region of a second conductivity type vertically disposed between the drift layer and the upper surface. Further, the semiconductor body includes a second base region of a first conductivity type vertically disposed between the drift layer and the upper surface. The second base region has a higher doping concentration than the drift layer and is adjacent to the drift layer. Further, the semiconductor body includes a first contact region of a first conductivity type. The first contact region is adjacent to the first base region and the upper surface. Further, the semiconductor body includes a second contact region of a second conductivity type. The second contact region is adjacent to the second base region and the upper surface. The main electrode is in electrical contact with the first contact region and the second contact region. In a first lateral direction, at least a portion of the gate electrode is disposed between the first contact region and the second contact region, and between the first base region and the second base region.

[0005] Bipolar semiconductor devices such as IGBTs are devices in which both electrons and holes are involved in the conduction process. When both electrons and holes are injected, a high-density plasma is formed in the drift layer, reducing the resistance of this layer and, as a result, decreasing the losses during the on-state. However, during the off-state, the accumulated plasma needs to be rapidly removed to minimize switching losses. Therefore, there is a trade-off between the on-state voltage drop (Vce-sat) and the turn-off switching loss (Eoff) of such devices.

[0006] In the present invention, a complementary transistor for the controlled extraction of a second type of charge carrier, such as holes, is introduced by the second base region and the second contact region. The complementary transistor provides an additional extraction path for the second type of charge carrier that remains active only during the turn-off period of the main transistor having the first base region and the first contact region. Accordingly, the switching losses of the semiconductor device are reduced without impairing its on-state. The functionality of the semiconductor device is not limited, for example, by the trench pitch. Further, since no additional gate connection is required, the Miller capacitance Cgc is not adversely affected. This concept is applicable, for example, to MOS-based bipolar devices such as IGBTs, reverse-conducting (RC)-IGBTs, bi-directional IGBTs (BIGTs), MOS-controlled diodes, etc., and can be converted to both trench and planar architectures.

[0007] The semiconductor body may be based on Si or SiC or GaN or any other semiconductor material. The lateral direction is defined herein as the direction parallel to the upper surface of the semiconductor body. The vertical direction is defined herein as the direction perpendicular to the upper surface.

[0008] The main electrode may be formed of metal. The gate electrode may include or consist of a highly doped metal or polysilicon. The gate electrode is insulated from the semiconductor body, in particular, by an electrical isolation material such as SiO2 or any other dielectric material or a combination of two or more dielectric materials. Accordingly, the semiconductor device may be an insulated gate device. In particular, the gate electrode and the main electrode are electrically insulated from each other and can be set to different potentials for operation.

[0009] The drift layer may extend across the entire lateral extent of the semiconductor body. The drift layer is of a first conductivity type. The first conductivity type can be either electron conduction or hole conduction. The second conductivity type is different from the first conductivity type, i.e., either hole conduction or electron conduction. A region or layer that is electron conducting is n-doped, and a region or layer that is hole conducting is p-doped. For example, the doping concentration in the drift layer is at least 10 8 cm -3 and at most 10 15 cm -3 is.

[0010] The first base region is disposed vertically between the drift layer and the upper surface, i.e., in the vertical direction between the drift layer and the upper surface. For example, the doping concentration in the first base region is at least 10 15 cm -3 and / or at most 10 18 cm -3 is. The first base region may be adjacent to the drift layer and / or the upper surface, i.e., may be in direct contact with the drift layer and / or may form part of the upper surface.

[0011] The second base region is of the same conductivity type as the drift layer but has a higher doping concentration than the drift layer. For example, the doping concentration in the second base region is at least 10 times or at least 100 times higher than that in the drift layer. For example, the doping concentration in the second base region is at least 10 15 cm -3 and / or at most 10 18 cm -3 is.

[0012] The second base region is adjacent to the drift layer, i.e., in direct contact with the drift layer. In particular, there is no region of the second conductivity type disposed vertically between the drift layer and the second base region. Furthermore, the second base region may be adjacent to the upper surface, i.e., may form part of it.

[0013] Here, when comparing the doping concentrations of layers or regions, the average doping concentration or the maximum doping concentration of these layers or regions is compared. When defining the upper and lower limits of the doping concentration in a layer or region, it means that the maximum doping concentration in each layer / region does not exceed the upper limit, and the minimum doping concentration in each layer / region does not fall below the lower limit.

[0014] The first contact region is adjacent to the first base region and the upper surface, that is, it is in direct contact with the first base region and forms part of the upper surface. For example, the first contact region is vertically arranged between the first base region and the upper surface and is adjacent to the first base region in the vertical direction. Additionally or alternatively, the first contact region may be adjacent to the first base region in the first lateral direction.

[0015] The first contact region may be at least partially embedded in the first base region. In particular, the first contact region may be at least partially surrounded laterally by the first base region. The doping concentration in the first contact region is, for example, higher than the doping concentration in the first base region, for example, at least 10 times or at least 100 times higher. For example, the doping concentration in the first contact region is at least 10 17 cm -3 or at least 10 18 cm -3 or at least 10 19 cm -3 is.

[0016] The second contact region is adjacent to the second base region and the upper surface, that is, it is in direct contact with the second base region and forms part of the upper surface. For example, the second contact region is vertically arranged between the second base region and the upper surface and is adjacent to the second base region in the vertical direction. Additionally or alternatively, the second contact region may be adjacent to the second base region in the first lateral direction.

[0017] The second contact region may be at least partially embedded in the second base region. In particular, the second contact region may be at least partially surrounded laterally by the second base region. The doping concentration in the second contact region is, for example, higher than the doping concentration in the second base region, for example, at least 10 times or at least 100 times higher. For example, the doping concentration in the second contact region is at least 10 17 cm -3 or at least 10 18 cm -3 or at least 10 19 cm -3 .

[0018] The contact region is also known as the source region. The thicknesses of the first and second base regions, measured in the vertical direction, may be at least 1 μm and / or at most 8 μm. The thicknesses of the first and second contact regions may each be at least 50 nm and / or at most 1 μm in each case. The lateral extent in the first lateral direction of the first and second contact regions may each be at least 50 nm and / or at most 5 μm in each case. The lateral extent in the first lateral direction of the first and second base regions may each be at least 500 nm and / or at most 5 μm in each case.

[0019] The main electrode is in electrical contact with, i.e., directly electrically contacts, the first and second contact regions. For example, the main electrode is adjacent to the first and second contact regions on the upper surface. For example, the main electrode is not in direct electrical contact with the second base region. An ohmic contact may be formed between the main electrode and the contact region.

[0020] In a first lateral direction, at least a part of the gate electrode, for example, most of the gate electrode or the entire gate electrode, is laterally disposed between a first contact region and a second contact region, and between a first base region and a second base region. For example, in the first lateral direction, only one gate electrode is disposed between the first contact region and the second contact region, and between the first base region and the second base region. As an example, the distance between the first contact region and the second contact region measured in the first lateral direction is at most twice or at most 1.5 times the lateral extent of the gate electrode in the first lateral direction. For example, the distance in the first lateral direction between the first contact region and the second contact region is at most 10 μm.

[0021] According to a further embodiment, the semiconductor device is configured such that, by setting the potential of the gate electrode, a zone of the first base region is inverted by the gate electrode, i.e., the conductivity type is inverted within this zone, and thus, a current flow of charge carriers of a first type between the drift layer passing through this zone and the first contact region is enabled. The inversion zone faces the gate electrode, i.e., it is the zone of the first base region closest to the gate electrode.

[0022] Alternatively, a zone of the second base region is inverted by the gate electrode, and thus, a current flow of charge carriers of a second type between the drift layer passing through this zone and the second contact region is enabled. Here too, the inversion zone faces the gate electrode, i.e., it is the zone of the second base region closest to the gate electrode.

[0023] Thus, the drift layer, the first base region, and the first contact region form part of a first transistor (main transistor), and the drift layer, the second base region, and the second contact region form part of a second transistor (complementary transistor).

[0024] When the first conductivity type is electron conduction, the charge carriers of the first type are electrons. Accordingly, the second conductivity type is hole conduction, and the charge carriers of the second type are holes.

[0025] For example, in the first case, when the zone of the first base region is inverted, a flow of charge carriers of the first type from the main electrode through the first contact region, the inverted zone of the first base region, and into the drift layer becomes possible. For example, in the second case, when the zone of the second base region is inverted, a flow of charge carriers of the second type from the drift layer through the inverted zone of the second base region and the second contact region and into the main electrode becomes possible.

[0026] According to a further embodiment, the semiconductor device is a planar device, i.e., has a planar architecture, and the gate electrode is disposed on the upper surface. For example, in a first lateral direction, the gate electrode is at least partially aligned with the first contact region and the second contact region and / or the first base region and the second base region. Thereby, the gate electrode is isolated from the contact regions by an electrical isolation layer. For example, in a top view onto the upper surface, the gate electrode at least partially overlaps the first and second contact regions, as well as the first and second base regions.

[0027] According to a further embodiment, the semiconductor device is a trench device, i.e., a trench architecture, and the gate electrode is disposed within an active trench. The active trench extends vertically into the semiconductor body from the upper surface. For example, the first and second contact regions and / or the first and second base regions are at least partially aligned with the gate electrode in the vertical direction. That is, in a side view along a first lateral direction, the active trench and the gate electrode therein partially or completely overlap with the first contact region and the second contact region and / or the first base region and the second base region. For example, the active trench extends deeper into the semiconductor body than the first contact region and the second contact region and / or than the first base region and the second base region. For example, the active trench and the gate electrode extend vertically within the semiconductor body by at least 2 μm or at least 4 μm and / or at most 10 μm.

[0028] According to a further embodiment, the semiconductor device comprises a dummy trench disposed adjacent to and spaced apart from the active trench in a first lateral direction.

[0029] In this specification, a trench having a gate electrode therein is referred to as an "active trench". In this specification, a trench having no gate electrode therein is referred to as a "dummy trench". For example, the second base region and the second contact region are disposed between the active trench and the dummy trench in a first lateral direction. The second base region may be adjacent to the active trench and the dummy trench in a first lateral direction.

[0030] According to a further embodiment, the dummy trench is filled with a conductive material such as highly doped polysilicon. The conductive material is electrically isolated from the semiconductor body by, for example, an isolation material. For example, the conductive material within the dummy trench is electrically connected to the main electrode.

[0031] Regardless of whether the trenches in the semiconductor device are active trenches or dummy trenches, they may all have the same dimensions within the limits of manufacturing tolerances. Alternatively, the dummy trenches may be deeper or shallower than the active trenches.

[0032] For example, exactly one active trench is disposed between the first contact region and the second contact region, and between the first base region and the second base region. The first and second contact regions may be adjacent to the active trench on different sides with respect to the first lateral direction. Similarly, the first and second base regions may be adjacent to the active trench on different sides with respect to the first lateral direction.

[0033] According to a further embodiment, an enhancement region of a first conductivity type is disposed vertically between the first base region and the drift layer. For example, the enhancement region extends laterally across the entire lateral extent of the first base region. Thus, the enhancement layer is disposed between the drift layer and the first base region across the entire lateral extent of the first base region. The enhancement region may be adjacent to the first base region and / or the drift layer. In this specification, this enhancement region is also referred to as the "first enhancement region".

[0034] According to a further embodiment, the enhancement region has a doping concentration higher than that of the drift layer. For example, the doping concentration in the first enhancement region is at least 10 times or at least 100 times higher than the doping concentration in the drift layer. For example, the doping concentration in the enhancement region is at least 10 15 cm -3 and / or at most 10 19 cm -3 . The thickness of the enhancement region, measured in the vertical direction, is, for example, at least 1 μm and / or at most 3 μm.

[0035] The enhancement region is a blocking region for a second type of charge carrier, which is, for example, holes. Therefore, it may also be referred to as a "hole blocking region" or a "hole blocking layer", respectively.

[0036] According to a further embodiment, the semiconductor device comprises a third base region of a second conductivity type. The third base region is arranged adjacent to the second base region in a first lateral direction such that the second base region is arranged between the first base region and the third base region in the first lateral direction. The second and third base regions may be spaced apart from each other in the first lateral direction by a trench, for example, exactly one trench. This trench may be an active trench or a dummy trench.

[0037] The third base region is also arranged vertically between the top surface and the drift layer. It may be adjacent to the top surface and / or the drift layer. The doping concentration in the third base region may be the same as or different from the doping concentration in the first base region. The thickness of the third base region, measured in the vertical direction, is, for example, at least 1 μm greater than the thickness of the first base region, for example.

[0038] According to a further embodiment, the third base region extends from the top surface into the semiconductor body. For example, the third base region extends deeper into the semiconductor body than an active trench or a trench. For example, the third base region extends at least 1 μm deeper into the semiconductor body than a trench. The third base region is, for example, a so-called p-well.

[0039] According to a further embodiment, the thickness of the insulating material between the first contact region and / or the first base region and the gate electrode is greater than the thickness of the insulating material between the second contact region and / or the second base region and the gate electrode. For example, the thickness between the first contact region / first base region and the gate electrode is at least 1.5 times or at least 2 times the thickness between the second contact region / second base region and the gate electrode.

[0040] According to a further embodiment, the main electrode is not in direct electrical contact with the second base region. This means that charge carriers cannot flow directly from the main electrode to the second base region or vice versa. Rather, charge carrier exchange must always occur via the second contact region.

[0041] According to a further embodiment, the semiconductor device comprises a further gate electrode. The further gate electrode is laterally spaced from the gate electrode in a first lateral direction. For example, the further gate electrode is at the same potential as the gate electrode. In other words, the gate electrode and the further gate electrode may be short-circuited.

[0042] Also, the further gate electrode may be disposed within an active trench that extends from the top surface into the semiconductor body.

[0043] According to a further embodiment, the second base region is disposed between the gate electrode and the further gate electrode in a first lateral direction. For example, no further gate electrode is disposed between the gate electrode and the further gate electrode in the first lateral direction. The second base region may be adjacent to two active trenches that include the gate electrode and the further gate electrode in the first lateral direction.

[0044] According to a further embodiment, the semiconductor device is configured such that, by setting the potential of the further gate electrode, a zone of the second base region is inverted by the further gate electrode, the zone being located on a side of the second base region opposite to the side of the second base region where a zone of the second base region is inverted by the gate electrode. Thus, the further gate electrode provides a current path to this opposite side. Here, "opposite" refers to the first lateral direction. In other words, the gate electrode and the further gate electrode are disposed on opposite sides and, for example, invert zones of the second base region that are laterally spaced in the first lateral direction.

[0045] In other words, the gate electrode and the further gate electrode establish two channels for the transport of charge carriers, for example a hole channel.

[0046] According to a further embodiment, the first and / or second contact regions are elongated regions that are oblique with respect to the first lateral direction, for example perpendicular to the first lateral direction and extending in a second lateral direction. This means that the lateral extent of the first and / or second contact regions is greater in the second lateral direction than in the first lateral direction in each case. For example, the lateral extent in the second lateral direction is at least twice or at least five times greater than in the first lateral direction in each case. The first and second contact regions may be adjacent to the upper surface over the entire lateral extent in the first and / or second lateral direction.

[0047] Similarly, the first and second base regions may be elongated and extend in the second lateral direction. Also, the trench may be elongated and extend in the second lateral direction.

[0048] According to a further embodiment, the semiconductor device comprises several first contact regions that are adjacent to the upper surface and the first base region and are in electrical contact with the main electrode. These first contact regions are separated and spaced apart from each other in the second lateral direction. For example, each first contact region has a lateral extent in the second lateral direction of at least 500 nm or at least 1 μm. The distance between two adjacent first contact regions in the second lateral direction may be at least 500 nm or at least 1 μm in each case. All features disclosed so far for one first contact region are also disclosed for all other first contact regions, in particular with regard to the doping concentration and the conductivity type.

[0049] According to a further embodiment, the semiconductor device comprises several second contact regions that are adjacent to the upper surface and the second base region and are in electrical contact with the main electrode. These second contact regions are separated and spaced apart from each other in a second lateral direction. For example, each second contact region has a lateral extent in the second lateral direction of at least 500 nm or at least 1 μm. The distance between any two adjacent second contact regions in the second lateral direction may in each case be at least 500 nm or at least 1 μm. All features disclosed so far for one second contact region are also disclosed for all other second contact regions, in particular with regard to the doping concentration and the conductivity type.

[0050] According to a further embodiment, the semiconductor device is a power semiconductor device. For example, the semiconductor device is configured to process a current of at least 1 A and / or a voltage of at least 100 V. The semiconductor device is, for example, a so-called vertical semiconductor device.

[0051] According to a further embodiment, the semiconductor device is a vertical device, i.e., has a vertical architecture. In that case, the cathode and the anode are arranged on both sides of the semiconductor body.

[0052] According to a further embodiment, the semiconductor device is a bipolar semiconductor device in which both electrons and holes contribute to the current during operation.

[0053] According to a further embodiment, the semiconductor device is an insulated gate bipolar transistor, abbreviated as IGBT, or a MOS controlled diode. The semiconductor device is, for example, a reverse conducting (RC)-IGBT or a bidirectional IGBT (BIGT).

[0054] According to a further embodiment, the semiconductor device comprises a further main electrode that is attached to the back surface of the semiconductor body opposite the upper surface. The semiconductor body may comprise a contact layer (anode layer) and / or a buffer layer between the drift layer and the further main electrode.

[0055] Next, a method for manufacturing a semiconductor device is specified. This method is particularly suitable for manufacturing a semiconductor device according to any one of the embodiments described herein. Accordingly, all features disclosed for the semiconductor device are also disclosed for the method, and vice versa.

[0056] According to an embodiment of a method for manufacturing a semiconductor device, the method includes providing a semiconductor body having an upper surface and a drift layer of a first conductivity type. In a further step, a first base region, a second base region, a first contact region and a second contact region are manufactured. The first base region is of a second conductivity type and is manufactured such that the first base region is positioned vertically between the drift layer and the upper surface. The second base region is of the first conductivity type and is manufactured such that the second base region is positioned vertically between the drift layer and the upper surface, and the second base region has a higher doping concentration than the drift layer and is adjacent to the drift layer. The first contact region is of the first conductivity type and is manufactured such that the first contact region is adjacent to the first base region and the upper surface. The second contact region is of the second conductivity type and is manufactured such that the second contact region is adjacent to the second base region and the upper surface. In a further step, a main electrode is attached to the upper surface and electrical contacts are established between the main electrode and the first contact region and between the main electrode and the second contact region. In a further step, the gate electrode is finally formed such that at least a part of the gate electrode is positioned in a first lateral direction between the first contact region and the second contact region and between the first base region and the second base region.

[0057] Before forming the first and second base regions and the first and second contact regions, the drift layer may reach the upper surface, for example form the upper surface. Manufacturing the base region and / or the contact region may include, for example, implanting dopants through the upper surface. For example, a mask is used to define the areas into which dopants are implanted for different regions.

[0058] Hereinafter, with reference to the drawings, a semiconductor device and a method for manufacturing a semiconductor will be described in more detail based on exemplary embodiments. The accompanying drawings are included to provide a further understanding. In the drawings, elements having the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the drawings are exemplary representations and are not necessarily drawn to scale. As long as the elements or components correspond to each other with respect to their functions in different drawings, the description of each of the following drawings will not be repeated. For clarity, elements may not be denoted by corresponding reference numerals in all the drawings.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0060] FIG. 1 shows a cross - section of a section of a first exemplary embodiment of a semiconductor device 100. The semiconductor device 100 includes a semiconductor body 1 made of, for example, Si or SiC or GaN. A main electrode 2 is attached to the upper surface 10 of the semiconductor body 1. The main electrode 2 is, for example, a metal electrode.

[0061] The semiconductor body 1 includes a drift layer 11 of a first conductivity type. Hereinafter, it is assumed that the first conductivity type is electron conduction, and the corresponding doping is n - doping. Thus, the drift layer 11 is n - doped. However, the described embodiments also function when the first conductivity type is hole conduction.

[0062] The first base region 12 and the second base region 13 are each vertically positioned between the drift layer 11 and the upper surface 10. As used herein, "vertically" means the vertical direction V which is perpendicular to the upper surface 10. The first base region 12 and the second base region 13 are arranged adjacent to each other in a first lateral direction L1 which is a direction parallel to the upper surface 10. The first base region 12 has a second conductivity type different from the first conductivity type, that is, in this case, it is p - doped. The second base region 13 has the first conductivity type, that is, it is n - doped. Both base regions 12, 13 are adjacent to the drift layer 11 and the upper surface 10.

[0063] The first contact region 14 is embedded in the first base region 12. The first contact region 14 is of the first conductivity type, i.e., n-doped, and is adjacent to the first base region 12 and the top surface 10. On the top surface 10, the first contact region 14 is in direct mechanical and electrical contact with the main electrode 2. Also, the first base region 12 is in direct mechanical and electrical contact with the main electrode 2 on the top surface 10.

[0064] The second contact region 15 is embedded in the second base region 13. The second contact region 15 is of the second conductivity type, i.e., p-doped, and is adjacent to the second base region 13 and the top surface 10. On the top surface 10, the second contact region 15 is in direct mechanical and electrical contact with the main electrode 2. However, since the main electrode 2 is not in direct mechanical or electrical contact with the second base region 13, the exchange of charge carriers between the main electrode 2 and the second base region 13 must always be carried out via the second contact region 15.

[0065] Horizontally between the base regions 12, 13 and the contact regions 14, 15, the active trench 4 extends from the top surface 10 into the semiconductor body 1 and opens into the drift layer 11. The depth of the active trench 4 measured in the vertical direction V is greater than the thicknesses of the base regions 12, 13 and the contact regions 14, 15 also measured in the vertical direction V. Inside the active trench 4, the gate electrode 3 is disposed. The gate electrode 3 is made of, for example, highly doped polysilicon. The gate electrode 3 is electrically isolated from the semiconductor body 1, particularly from the base regions 12, 13 and the contact regions 14, 15, by an electrically insulating material 5 made of, for example, SiO2. The semiconductor device 100 in FIG. 1 is a so-called trench device.

[0066] The doping concentration of the drift layer 11 is, for example, 10 8 cm -3 or more and 10 15 cm -3 or less. The doping concentration of each of the base regions 12, 13 is, for example, 10 15 cm -3 ~1018 cm -3 is within the range. The doping concentrations in the contact regions 14 and 15 are, in each case, for example, 10 18 cm -3 ~10 21 cm -3 is within the range.

[0067] In the on-state of the semiconductor device 100, the gate electrode 3 may have a positive potential with respect to the semiconductor body 1. Thereby, an inversion zone is formed on the side facing the active trench 4 of the first base region 12, and the inversion zone extends along the active trench 4 from the first contact region 14 to the drift layer 11. Thereby, electrons are injected from the main electrode 2 into the contact region 14 and can move from there through the inversion zone to the drift layer 11.

[0068] In the off-state of the semiconductor device 100, the gate electrode 3 may have a negative potential with respect to the semiconductor body 1. The potentials of the main electrode 2 and a further main electrode may be the same as in the on-state. Thereby, an inversion zone is formed on the side facing the active trench 4 of the second base region 13, and the inversion zone extends along the active trench 4 from the second contact region 15 to the drift layer 11. Thereby, holes come out of the drift layer 11 through the inversion zone, move along the inversion zone, and then can enter the main electrode 2 through the second contact region 15.

[0069] In particular, when the semiconductor device 100 is a bipolar device such as an IGBT, very efficient hole discharge becomes possible in this way, and as a result, the turn-off loss is reduced.

[0070] Here, the transistor realized by the first base region 12 and the first contact region 14 is referred to as the "main transistor", and the transistor realized by the second base region 13 and the second contact region 15 is referred to as the "complementary transistor". In the exemplary embodiments described in this specification, the main transistor is an NMOS transistor, and the complementary transistor is a PMOS transistor.

[0071] The exemplary embodiment of FIG. 2 shows a so-called planar device that does not use trenches as shown in FIG. 1. Instead, the gate electrode 3 is disposed on the upper surface 10 and is electrically isolated from the semiconductor body 1 by the electrical isolation material 5. In a plan view on the upper surface 10, the gate electrode 3 partially covers, i.e., overlaps, the first 14 and second 15 contact regions. The inversion zone and the associated current path in FIG. 1 are mainly directed in the vertical direction V, while the inversion zone and the associated current path in FIG. 2 are mainly directed in the first lateral direction L1.

[0072] The exemplary embodiment of FIG. 3 shows a semiconductor device 100 that is an insulated gate bipolar transistor, abbreviated as IGBT. On the back surface opposite to the upper surface 10 of the semiconductor body 1, a further main electrode 6, which is made of metal, for example, is attached. The semiconductor body 1 includes a further layer 20 of the second conductivity type, i.e., p-doped, which forms the back surface and is in direct electrical and mechanical contact with the further main electrode 6. The doping concentration of the further layer 20 is higher than that of the drift layer 11, for example. A layer 19 of the first conductivity type is attached between the drift layer 11 and the layer 20. The layer 19 is adjacent to the layer 20 and the drift layer 11. The doping concentration in the layer 19 is higher than that of the drift layer 11, for example. The layer 19 is a so-called buffer layer.

[0073] In FIG. 3, the first base region 12 is adjacent to the active trenches 4 on both sides with respect to the first lateral direction L1. Both active trenches 4 are connected to the gate electrode 3. On both sides of the first base region 12, second base regions 13 are also arranged with respect to the first lateral direction L1, and these are each separated from the first base region 12 by one of the active trenches 4.

[0074] Each of the second base regions 13 is between and adjacent to two trenches 4, 40. In either case, only the trench closer to the first base region 12 becomes the active trench 4. Each of the other trenches 40 is a dummy trench. The dummy trench 40 is filled with a conductive material that is electrically connected to, for example, the main electrode 2 and thus has the same potential as the main electrode 2. The dummy trench 40 helps to reduce the capacitance between the gate electrode 3 and a further main electrode 6, which is also called the mirror capacitance or gate-collector capacitance Cgc.

[0075] FIG. 3 and the other figures may show only a part of the semiconductor device. The structures shown in these figures with the base regions 12, 13 and the contact regions 14, 15 may be repeated several times in the first lateral direction L1.

[0076] In the exemplary embodiment of FIG. 4, the semiconductor body 1 is of the second conductivity type, i.e., p-doped, and comprises a third base region 18 that is adjacent to the dummy trench 40 on the side facing outward from the second base region 13. The doping concentration in the third base region 18 may be in the same or a different range as that in the first base region 12. The third base region 18 forms a p-well that reaches deeper into the semiconductor body 1 than the trenches 4, 40. The third base region 18 can provide improved breakdown voltage.

[0077] FIG. 5 shows a detailed view of the exemplary embodiment of FIG. 4, showing only half of the first base region 12, the adjacent second base region 13, and the third base region 18. FIG. 5 shows the doping profile by using different hatchings. The higher the dot density of the hatching, the higher the doping concentration.

[0078] FIG. 6 shows a reference semiconductor device 200, for example, a reference IGBT. In contrast to the IGBT of FIG. 5, the second base region 13 and the second contact region 15 are ignored. Rather, in the lateral direction between the dummy trench 40 and the active trench 4, the semiconductor body 1 adjacent to the upper surface 10 is also made of a semiconductor material of the second conductivity type having, for example, the same doping concentration as the first base region 12. The main electrode 2 is in electrical and mechanical contact (dummy contact) with the semiconductor body 1 in the region between the two trenches 4, 40.

[0079] Figures 7 and 8 show a simulation of the output characteristics Ic vs. Vce (curve 100) of the IGBT according to FIG. 5, compared with the output characteristics (curve 200) of a reference IGBT without a second base region and a second contact region, according to FIG. 6. FIG. 7 shows the range from 0 to 2V, and FIG. 8 shows the range from 0 to 25V. The IGBT according to FIG. 5 shows an improvement of about 130 mV in Vce-sat compared with the reference IGBT according to FIG. 6. In the reference IGBT, the plasma concentration in the drift region (drift layer 11) decreases due to the extraction of holes injected between the on-state dummy trench 40 and the active trench 4, resulting in an increase in on-loss. In the IGBT of FIG. 5, this hole extraction between the on-state dummy trench 40 and the active trench 4 is significantly suppressed (by about 50%, also see FIG. 9). This is the result of arranging a second base region and a second contact region (PMOS transistor) between the active trench 4 and the dummy trench 40. This PMOS transistor is off during the IGBT on-state (Vge > Vth), thereby substantially eliminating the hole extraction path in the region between the active trench 4 and the dummy trench 40. This explains the excellent Vce-sat of the IGBT, which is very close to the Vce-sat of the IGBT without electrical contact of the semiconductor body to the main electrode in the lateral upper surface area (i.e., without dummy contact) between the dummy trench 40 and the active trench 4.

[0080] In short, the electrical contact to the main electrode 2 in the region between the active trench 4 and the dummy trench 40 is effectively invisible during the IGBT on-state, as desired to maintain the plasma concentration.

[0081] FIG. 9 shows the simulated hole current streamlines during the on-state operation of the IGBT according to FIG. 5, and FIG. 10 shows the simulated hole current streamlines of the reference IGBT according to FIG. 6. The density of the contour lines is proportional to the hole current. In FIGS. 9 and 10, Vce is selected to be 3V, and it can be seen that in the IGBT according to FIGS. 5 and 9, the flow of the hole current between the active trench 4 and the dummy trench 40 is significantly suppressed.

[0082] FIG. 11 shows the simulated hole current in the second contact region versus the voltage Vce during the on-state operation of the IGBT (curve 100) and the reference IGBT (curve 200) according to FIG. 5. It can be seen that in the IGBT according to FIG. 5, a reduction of about 50% in the hole current can be achieved in the on-state.

[0083] FIG. 12 shows the simulation of Ic versus Vce for Vge = -15V. It can be seen that the blocking capabilities of the IGBT (curve 100) according to FIG. 5 and the reference IGBT (curve 200) according to FIG. 6 are approximately the same.

[0084] FIG. 13 shows the simulation of the turn-off switching characteristics of the IGBT (curve 100_i) according to FIG. 5 and the reference IGBT (curve 200_i) according to FIG. 6. Curves 100_1, 200_1 show Vce versus time T, curves 100_2, 200_2 show Vge versus time T, and curves 100_3, 200_3 show Ic versus time T. The turn-off switching loss Eoff of the IGBT according to FIG. 5 is very close to the turn-off switching loss Eoff of the reference IGBT according to FIG. 6. Also, note that the Eoff of the IGBT according to FIG. 5 is lower than the Eoff of the reference IGBT that has no electrical contact with the main electrode in the region between the trenches (see the following table). This means that the PMOS transistor that prevents holes from going out in the on-state is currently active in the IGBT off-state and is effective in extracting holes from the IGBT device, thereby reducing its switching loss. In other words, the contact to the main electrode in the region between the dummy trench and the active trench, which was effectively invisible during the IGBT on-state, becomes visible during the IGBT off-state as desired to improve both the on-state and the switching loss simultaneously.

[0085] Figure 14 shows the simulation of the turn-on switching characteristics using the same naming rule as in Figure 13. The IGBT according to Figure 5 exhibits a lower turn-on loss Eon due to the lower gate-emitter capacitance Cge compared to the reference IGBT in Figure 6. However, the total loss E total , that is, E rec +E on (where E rec is the diode reverse recovery loss) remains the same (see the table below).

[0086] Figure 15 shows the simulated technology curves (E off versus V ce-sat ) at 25 °C of the IGBT according to Figure 5 (curve 100) compared to the reference IGBT according to Figure 6 (curve 200). The IGBT according to Figure 5 has an excellent technology curve compared to the reference IGBT. For the same V ce-sat , the IGBT according to Figure 5 shows an Eoff that is 18% lower compared to the reference IGBT. On the other hand, for the same E off , the V ce-sat of the IGBT according to Figure 5 is 5% lower compared to that of the reference IGBT.

[0087] The following table shows a summary of the simulation results of the IGBT according to Figure 5 (row 100), which is compared to the reference IGBT according to Figure 6 (row 200), but there is no electrical contact of the main electrode to the semiconductor body within the region between the active trench 4 and the dummy trench 40 (row 300), that is, there is no dummy contact.

[0088]

Table 1

[0089] FIG. 16 shows a further exemplary embodiment of a semiconductor device 100 similar to that of FIG. 3. However, in contrast to the exemplary embodiment of FIG. 3, a first enhancement region 16 is disposed between the drift layer 11 and the first base region 12. The first enhancement region 16 is of the first conductivity type, i.e., n-doped, and has a doping concentration higher than that of the drift layer 11, for example, at least 10 times higher. The enhancement region 16 improves the on-state loss or Vce-sat by reducing hole leakage.

[0090] FIG. 17 shows an example of an IGBT similar to that of FIG. 16, but with a second enhancement region 17 of the second conductivity type, i.e., p-doped, disposed vertically between the second base region 13 and the drift layer 11. These enhancement regions 17 reduce electron leakage through the electrical contact to the second contact region 15 of the main electrode 2 and improve hole collection during turn-off.

[0091] FIG. 18 shows an exemplary embodiment similar to that of FIG. 4, but further comprising a first enhancement region 16 between the first base region 12 and the drift layer 11.

[0092] The exemplary embodiment of FIG. 19 is similar to that of FIG. 18. However, in the active trench 4, the electrical isolation layer 5 is thicker between the gate electrode 3 and the first contact region 14 than between the second contact region 15 and the gate electrode 3. This design can reduce the Vth of the PMOS transistor to turn on earlier during the IGBT off-state in order to further reduce switching losses. Consequently, the doping concentration of the second base region 13 can be further increased to reduce hole leakage due to diffusion in the IGBT on-state.

[0093] In the exemplary embodiment of FIG. 20, the first contact region 14 extends across the entire lateral extent of the first base region 12 in the first lateral direction L1. In other words, the first contact region 14 extends in the first lateral direction L1 from one active trench 4 to the next active trench 4. Thereby, the hole path from the drift layer 11 through the first base region 12 to the main electrode 2 can be completely suppressed.

[0094] In the exemplary embodiment of FIG. 21, the second contact region 15 has the same lateral extent in the first lateral direction L1 as the second base region 13. In other words, the second contact region 15 extends in the first lateral direction L1 from each active trench 4 to the next dummy trench 40.

[0095] The exemplary embodiment of FIG. 22 is the same as that of FIG. 21. However, here, the trenches on both sides of the second base region 13 are active trenches 4. In this embodiment, the PMOS transistors are formed in both active trenches 4 adjacent to each second base region 13.

[0096] The exemplary embodiment of FIG. 23 shows an exemplary embodiment similar to that of FIG. 22, but has additional dummy trenches 40 sandwiching four active trenches 4 in the first lateral direction L1. A further second base region 13 is formed between the dummy trench 40 and the active trench 4. By adding the dummy trench 40, the mirror capacitance Cgc can be further reduced.

[0097] In the exemplary embodiment of FIG. 24, in contrast to FIG. 23, the second contact region 15 is formed in a further second base region 13. The main electrode 2 may also be in electrical contact with these second contact regions 15.

[0098] In the exemplary embodiment of FIG. 25, the second base region 13 is formed only between the active trench 4 and the dummy trench 40. On the other side of the dummy trench 40, a third base region 18 of the second conductivity type is formed. The dummy trench 40 and the active trench 4 extend deeper into the semiconductor body 1 than the base regions 12, 13, 18.

[0099] In the exemplary embodiment of FIG. 26, a planar IGBT 100 similar to that of FIG. 2 is shown. Here too, an enhancement region 16 of the first conductivity type is disposed between the first base region 12 and the drift layer 11.

[0100] FIG. 31 shows an exemplary embodiment of a planar IGBT 100 having a non-uniform thickness of the electrical isolation layer 5 for reducing the gate capacitance.

[0101] FIG. 27 shows an exemplary embodiment of the semiconductor device 100 in a plan view of the top surface 10. As can be seen here, the base regions 12, 13 and the contact regions 14, 15 are elongated, and in each case, the main extension direction is parallel to a second lateral direction L2 perpendicular to the first lateral direction L1.

[0102] In the exemplary embodiment of FIG. 28, a plurality of first contact regions 14 are embedded in the same first base region 12. These first contact regions 14 are arranged successively and spaced apart from each other in the second lateral direction L2.

[0103] In FIG. 29, a plurality of second contact regions 15 are embedded in the second base region 13. The second contact regions 15 are arranged successively and spaced apart from each other in the second lateral direction L2. Different from what is shown in FIG. 29, the first contact regions 14 do not have to be located exactly on the opposite side of the second contact regions 15 and may be arranged in an alternating configuration.

[0104] In contrast to what is shown in the exemplary embodiments, the thickness (depth) of the first base region 12 and the second base region 13 can be different from each other. Also, the intervals between the trenches 4, 40 can be different from each other.

[0105] FIG. 30 shows a flowchart of an exemplary embodiment of a method for manufacturing a semiconductor device.

[0106] In step S1, a semiconductor body having an upper surface and a drift layer of a first conductivity type is provided. In further steps S2, S3, S4 and S5, a first base region, a second base region, a first contact region and a second contact region are manufactured. The first base region is of a second conductivity type and is manufactured so that the first base region is positioned vertically between the drift layer and the upper surface. The second base region is of a first conductivity type and is manufactured so that the second base region is positioned vertically between the drift layer and the upper surface, and the second base region has a higher doping concentration than the drift layer and is adjacent to the drift layer. The first contact region is of a first conductivity type and is manufactured so that the first contact region is adjacent to the first base region and the upper surface. The second contact region is of a second conductivity type and is manufactured so that the second contact region is adjacent to the second base region and the upper surface. In a further step S6, a main electrode is attached to the upper surface and electrical contacts are established between the main electrode and the first contact region and between the main electrode and the second contact region. In a further step S7, the gate electrode is finally formed so that the gate electrode is positioned in a first lateral direction between the first contact region and the second contact region and between the first base region and the second base region.

[0107] The embodiments shown in the above-described drawings represent exemplary embodiments of an improved semiconductor device and an improved method for manufacturing a semiconductor device, and thus they do not constitute a complete list of all embodiments by the improved semiconductor device and the improved method. The actual semiconductor device and method can be different from the shown embodiments, for example with regard to the arrangement and elements.

Description of Symbols

[0108] Reference Symbol 1 Semiconductor Body 2 Main Electrode 3 Gate Electrode 4 Active Trench 5 Electrical Isolation Material 6 Further Main Electrode 10 Upper Surface 11 Drift Layer 12 First Base Region 13 Second Base Region 14 First Contact Region 15 Second Contact Region 16 First Enhancement Region 17 Second Enhancement Region 18 Third Base Region 19 Layer 20 Layer 40 Dummy Trench 100 Semiconductor Device 200 Reference Semiconductor Device Si Method Step L1 First Lateral Direction L2 Second Lateral Direction V Vertical Direction 100_i Label of Curve 200_i Label of Curve

Claims

1. A semiconductor body (1) having an upper surface (10), A main electrode (2) on the upper surface (10), And a gate electrode (3), A semiconductor device (100) comprising: The semiconductor body (1) includes: A drift layer (11) of a first conductivity type, A first base region (12) of a second conductivity type vertically disposed between the drift layer (11) and the upper surface (10), A second base region (13) of the first conductivity type vertically disposed between the drift layer (11) and the upper surface (10), having a doping concentration higher than that of the drift layer (11) and adjacent to the drift layer (11), A first contact region (14) of the first conductivity type, adjacent to the first base region (12) and the upper surface (10), A second contact region (15) of the second conductivity type, adjacent to the second base region (13) and the upper surface (10), And is provided with, The main electrode (2) is in electrical contact with the first contact region (14) and the second contact region (15), In a first lateral direction (L1), at least a part of the gate electrode (3) is disposed between the first contact region (14) and the second contact region (15), and between the first base region (12) and the second base region (13). A semiconductor device (100).

2. By setting the potential of the gate electrode (3) of the semiconductor device (100), A zone of the first base region (12) is inverted by the gate electrode (3), and a current flow of first-type charge carriers between the drift layer (11) and the first contact region (14) through this zone becomes possible, Alternatively, the zone of the second base region (13) is inverted by the gate electrode (3), enabling the flow of a current of charge carriers of the second type between the drift layer (11) and the second contact region (14) passing through this zone. The semiconductor device according to claim 1, configured as such.

3. The semiconductor device (100) is a planar device, and the gate electrode (3) is disposed on the upper surface (10). The semiconductor device (100) according to claim 1 or 2.

4. The semiconductor device (100) is a trench device, and the gate electrode (3) is disposed within an active trench (4) extending in a vertical direction (V) from the upper surface (10) into the semiconductor body (1). The semiconductor device (100) according to claim 1 or 2.

5. Further comprising at least one dummy trench (40) disposed adjacent to and spaced apart from the active trench (4) in the first lateral direction (L1). The dummy trench (40) is filled with a conductive material electrically connected to the main electrode (2). The semiconductor device (100) according to claim 4.

6. The enhancement region (16) of the first conductivity type is disposed vertically between the first base region (12) and the drift layer (11). The enhancement region (16) has a doping concentration higher than that of the drift layer (11). The semiconductor device (100) according to any one of the preceding claims.

7. The third base region (18) of the second conductivity type is disposed adjacent to the second base region (13) in the first lateral direction (L1) such that the second base region (13) is disposed between the first (12) and the third (18) base regions in the first lateral direction (L1). The semiconductor device (100) according to any one of the preceding claims.

8. The semiconductor device (100) according to claim 7, which incorporates claim 4, wherein the third base region (18) extends deeper into the semiconductor body (1) from the upper surface (10) than the active trench (4) within the semiconductor body (1).

9. The semiconductor device (100) according to any one of the preceding claims, wherein the thickness of the insulating material (5) between the first contact region (14) and / or the first base region (12) and the gate electrode (3) is greater than the thickness of the insulating material (5) between the second contact region (15) and / or the second base region (13) and the gate electrode (3).

10. The semiconductor device (100) according to any one of the preceding claims, wherein the main electrode (2) is not in direct electrical contact with the second base region (13).

11. Further comprising an additional gate electrode (3) spaced apart from the gate electrode (3) in the first lateral direction (L1), wherein the second base region (13) is disposed between the gate electrode (3) and the additional gate electrode (3) in the first lateral direction (L1), The semiconductor device (100) according to claim 2, or any one of claims 3 to 10 incorporating claim 2, wherein the semiconductor device (100) is configured such that by setting the potential of the additional gate electrode (3), a zone of the second base region (13) is inverted by the additional gate electrode (3), the zone being located on a side of the second base region (13) opposite to the side of the second base region (13) where the zone of the second base region (13) is inverted by the gate electrode (3), and thereby providing a current path to this opposite side.

12. The semiconductor device (100) according to any one of the preceding claims, wherein the first (14) and / or second (15) contact regions are elongated regions extending in a second lateral direction (L2) that is oblique with respect to the first lateral direction (L1).

13. Comprising several first contact regions (14) adjacent to the upper surface (10) and the first base region (12) and in electrical contact with the main electrode (2), the first contact regions (14) being separated and spaced apart from each other in a second lateral direction (L2) that is oblique with respect to the first lateral direction (L1), and / or Comprising several second contact regions (15) adjacent to the upper surface (10) and the second base region (13) and in electrical contact with the main electrode (2), the second contact regions (15) being separated and spaced apart from each other in a second lateral direction (L2) that is oblique with respect to the first lateral direction (L1), the semiconductor device (100) according to any one of the preceding claims.

14. The semiconductor device (100) according to any one of the preceding claims, wherein the semiconductor device (100) is an IGBT.

15. A method for manufacturing a semiconductor device (100), comprising: Providing a semiconductor body (1) having an upper surface (10) and a drift layer (11) of a first conductivity type; A first base region (12) of a second conductivity type, the first base region (12) being vertically positioned between the drift layer (11) and the upper surface (10); A second base region (13) of the first conductivity type, the second base region (13) being vertically positioned between the drift layer (11) and the upper surface (10), the second base region (13) having a higher doping concentration than the drift layer (11) and being adjacent to the drift layer (11); A first contact region (14) of the first conductivity type, wherein the first contact region (14) is adjacent to the first base region (12) and the upper surface (10), the first contact region (14); A second contact region (15) of the second conductivity type, wherein the second contact region (15) is adjacent to the second base region (13) and the upper surface (10), the second contact region (15); To manufacture; Attach a main electrode (2) to the upper surface (10) and establish electrical contact between the main electrode (2) and the first contact region (14), and between the main electrode (2) and the second contact region (15); To form a gate electrode (3), and finally, form at least a part of the gate electrode (3) to be located between the first contact region (14) and the second contact region (15) and between the first base region (12) and the second base region (13) in a first lateral direction (L1); A method comprising.

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