Method for manufacturing a power semiconductor having an electrode and housed in a package, package of a power semiconductor
The method of growing high-aspect-ratio nanowires on power semiconductor electrodes and integrating them into a package addresses the issue of thermomechanical stress, enhancing the assembly's flexibility and durability while maintaining efficient electrical and thermal performance.
Patent Information
- Application Number
- JP2025520199
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-09-27
- Filing Date
- 2023-04-18
- Publication Date
- 2025-06-26
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Conventional power semiconductor assemblies are prone to damage from thermomechanical stress due to mismatched thermal expansion coefficients and temperature gradients, leading to interconnect failure.
A method for manufacturing power semiconductors with high-aspect-ratio nanowires grown on electrodes using electrodeposition within a template, which are then integrated into a package with a cured prepreg and conductive layers to form a single conductor unit.
The nanowire structure enhances the assembly's flexibility and durability, effectively absorbing mechanical displacement due to thermal effects without causing damage, while maintaining efficient current and heat transmission.
Smart Images
Figure 2025519978000001_ABST
Abstract
Description
Technical Field
[0001] The present invention generally relates to a method and system for manufacturing an assembly of power semiconductors housed in a package.
Background Art
[0002] Conventionally, power semiconductors are electrically connected to external components via wire bonding and soldering, and are in thermal contact with a conductive substrate for heat transport. To enable wiring of wire bonds to a power semiconductor, for example, a plurality of layers including an aluminum metallization layer, a solder layer, and a passivation layer are required.
[0003] When the assembly is subjected to thermomechanical stress due to thermal expansion coefficient mismatch and temperature gradient, damage may occur in the interconnects, ultimately leading to failure of the power semiconductor.
[0004] As an alternative to wire bonding, embedding a power semiconductor in a printed circuit board (PCB) can be mentioned. The connections are made with microvias by laser drilling. Although the parasitic inductance of the connections is improved, the flexibility of the microvias subjected to thermal and mechanical stress is not optimal.
[0005] To overcome the aforementioned problems, soft interconnects composed of micro / nano copper wires have been proposed. The nanowires have a high aspect ratio, and their height is several times larger than the diameter. This shape provides flexibility to deform under mechanical stress. The nanowires form a nanowire forest with a relatively high density to efficiently transmit current and heat.
[0006] Mechanical displacement due to thermal effects between the power semiconductor and the printed circuit board is absorbed by the deformation of the nanowires without causing damage. The method for manufacturing copper nanowires may be performed by electrodeposition using a porous membrane, which functions as a template and dissolves after the realization of the nanowires.
Summary of the Invention
Problems to be Solved by the Invention
[0007] An object of the present invention is to provide a method for manufacturing a highly reliable and easily mountable power semiconductor housed in a package, an assembly thereof, and a package including a power semiconductor that is highly resistant to stress.
Means for Solving the Problems
[0008] Therefore, the present invention is a method for manufacturing a power semiconductor having electrodes and housed in a package, the method comprising: placing a masking film over the entire upper and lower surfaces of the power semiconductor and forming an opening over the electrodes; placing a conductive layer over the masked upper and lower surfaces of the power semiconductor; placing a template over the electrodes and nanowires of the power semiconductor; electrodepositing a conductive material to form nanowires over the electrodes of the power semiconductor, wherein the formation of the nanowires is performed within the template; removing the masking film and the material thereon; inserting the power semiconductor into a cavity of a prepreg panel; curing the prepreg panel; dissolving the template; placing prepreg over the upper and lower surfaces of the cured prepreg panel and over a portion of the power semiconductor between two electrode metallizations; depositing a conductive layer on the surface of the placed prepreg; curing the placed prepreg; after curing the prepreg, placing a conductive layer on the upper and lower surfaces of a panel including at least one power semiconductor; Etching a part of a conductive layer on a cured prepreg on a part of a power semiconductor between two electrode metallizations; relates to a method including this.
[0009] Therefore, it is possible to grow nanowires with a high aspect ratio on each electrode of the power semiconductor. The size of the nanowires is determined by the size of the holes in the film. The elasticity of the nanowires is higher than that of microvias filled with copper.
[0010] Furthermore, the nanowires are protected by the film during handling and transfer steps. The dissolution of the film is performed just before the completion of the nanowires.
[0011] According to a specific feature, each template covers a part of the conductive layer on the electrode and a part of the conductive layer on the masking film, respectively.
[0012] The present invention also relates to a package of a power semiconductor, a conductive layer on each electrode of the power semiconductor, nanowires on a part of the conductive layer on the electrode, a cured prepreg on both sides of the power semiconductor and on a part of the masking film separating the two electrodes, a conductive layer on the nanowires, wherein the conductive layer on each electrode of the power semiconductor, the nanowires, and the conductive layer on the nanowires form a single conductor unit; relates to a package including this.
[0013] Therefore, the obtained structure is suitable for conducting current and heat while withstanding mechanical deformation.
[0014] According to a specific feature, the height of the nanowires is 30 to 100 times the width of the nanowires.
[0015] As a result, even if the coefficient of thermal expansion (CTE) of the laminated structure is different, a flexible bond between the die and the package is achieved.
[0016] According to a specific feature, the conductive layer on each electrode of the power semiconductor functions as a thermal interface material that dissipates heat from the power semiconductor.
[0017] Therefore, the junction temperature of the power device is controlled.
[0018] According to a specific feature, the nanowire is made of a material with electrical conductivity and thermal conductivity such as copper, nickel, aluminum, silver, gold, or carbon, or an alloy of these materials.
[0019] In this way, an electrical connection is made between the die and the power package.
[0020] According to a specific feature, the nanowire covers 50% - 90% of the surface of the electrode.
Brief Description of the Drawings
[0021]
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Embodiments for Carrying Out the Invention
[0022] The features of the present invention will become more apparent by reading the following description of the exemplary embodiments. This description is created with respect to the accompanying drawings.
[0023] FIG. 1 represents an example of an algorithm for manufacturing an assembly of power semiconductors housed in a package.
[0024] This algorithm is executed, for example, by a processor 120 of a system 12 for manufacturing an assembly of power semiconductors housed in a package, which is disclosed with reference to FIG. 12.
[0025] In step S100, the processor 120 issues an instruction to deposit a masking film on the entire upper and lower surfaces of the power semiconductor. For example, a masking mask is placed on the upper and lower surfaces of a wafer including the power semiconductor. In the same step, the processor 120 issues an instruction to form an opening on the surface of the upper electrode and / or the bottom electrode.
[0026] In step S101, the processor 120 issues an instruction to sequentially deposit a seed layer, a diffusion barrier layer, and a conductive layer on the upper and lower surfaces of the masked wafer. To maintain reasonable compatibility with standard PCB processes, the conductive layer is generally made of copper. The purpose of the conductive layer is to function as a pre-distribution layer for the next processing step and is peeled off before singulation.
[0027] Referring to FIG. 2, an example is shown.
[0028] FIG. 2 represents an example in which different layers are deposited on a power semiconductor.
[0029] The power semiconductor 200 has at least three electrodes shown as 250a, 250b, and 250c.
[0030] The remaining portions of the masking film are shown as 220a, 220b, 220c, 220d, and 220e.
[0031] The conductive layers are shown as 240a, 240b, and 240c.
[0032] The electrodes 250a and 250b are separated by a part 220b of the masking film.
[0033] For simplicity, the seed layer and the diffusion barrier are not shown in FIG. 2.
[0034] FIG. 3 represents an enlarged view of a part of a power semiconductor on which different layers are deposited.
[0035] In an enlarged view of the part of the power semiconductor shown as 300 in FIG. 1, the power semiconductor 200 on which the seed layer 320 and the diffusion barrier layer 310 are deposited is shown.
[0036] In step S102, the processor 120 issues an instruction to place a template on the electrode metallization of the power semiconductor. The template 400a covers a part of the conductive layer 240a on the electrode 250a and a part of the conductive layer on the masking films 220a and 220b. For example, the template 400a overlaps the masking films 220a and 220b by 200 micrometers.
[0037] Template 400b covers a part of the conductive layer 240a on the electrode 250b and a part of the conductive layer on the masking films 220b and 220c. For example, template 400b overlaps the masking films 220b and 220c by only 200 micrometers.
[0038] Template 400c covers a part of the conductive layer 240b on the electrode 250c and a part of the conductive layer on the masking films 220d and 220e. For example, template 400c overlaps the masking films 220d and 220e by only 200 micrometers.
[0039] FIG. 4 shows an example of the placement of the template.
[0040] FIG. 4 represents an example of depositing a template on a power semiconductor to implement nanowires.
[0041] The templates are shown as 400a, 400b, and 400c. For example, the template is an AAO matrix clamped to the upper surfaces of the power semiconductor electrodes 250a, 250b, and 250c across the entire wafer surface. By pressing the template onto the wafer, good contact is ensured at the interface between the film and copper, preparing for nanowire deposition. The surface of the template is generally larger than the surface of the power semiconductor electrode. A sufficient margin is added to relax the constraints regarding the placement accuracy.
[0042] In step S103, the processor 120 issues an instruction to perform electrodeposition to form nanowires.
[0043] The redistribution copper layers 240a and 240b are connected to one potential and function as cathodes in the reaction. A copper electrode (anode) is placed near the wafer to be plated. Both electrodes, i.e., the wafer and the anode, are immersed in an electrolytic bath. The growth of the nanowires stops before reaching the upper surface of the template. Since the nanowires and the template are delicate, the clamping pressure can be released.
[0044] The height of the nanowire is 30 to 100 times the width of the nanowire.
[0045] The nanowire is made of a material having electrical conductivity and thermal conductivity such as copper, nickel, aluminum, silver, gold, or carbon, or an alloy of these materials.
[0046] Referring to FIG. 5, an example is shown.
[0047] FIG. 5 shows an example of a nanowire on a power semiconductor.
[0048] In FIG. 5, nanowires 500a, 500b, and 500c are shown.
[0049] The photoresist films 220a to 220e and the material on the photoresist films 220a to 220e are removed by a lift-off method, and a power semiconductor having a copper pad and a template in which the nanowire is laminated on the upper surface of each electrode of the power semiconductor are exposed. The singulation of the power semiconductor is performed using a laser or a blade. The template functions as a protective case for the nanowire during die handling.
[0050] The nanowire covers 50% to 90% of the electrode surface.
[0051] In step S104, one or more dies are forcibly inserted into a prepreg panel having a dedicated cavity for each. The thickness of the uncured dielectric is about the same as the thickness of the power semiconductor. Optionally, a small amount of adhesive or a frame can be added to prevent the power semiconductor from coming out of the cavity. The first lamination step is performed with a pressure plate made of a non-adhesive material with an opening on the power semiconductor. During this first lamination, the prepreg flows into the gap between the die and the cavity, and mechanically mounts the power semiconductor on the panel of the printed circuit board. The PCB panel will now be used as a holding material for the power semiconductor in all subsequent processes.
[0052] FIG. 6 shows an example in which a power semiconductor is inserted between prepregs 600a and 600b.
[0053] In step S105, the processor 120 issues an instruction to cure the prepreg.
[0054] FIG. 7 shows examples of the cured prepregs 700a and 700b.
[0055] In step S106, the processor 120 issues an instruction to dissolve the templates 400a, 400b, and 400c.
[0056] At this stage, the template dissolves, and the nanowire array shown in FIG. 8 is exposed.
[0057] A cavity 800 is shown between the electrodes.
[0058] In step S107, the processor 120 issues an instruction to deposit prepreg on the upper and lower surfaces of the cured prepregs 600a and 600b and in the cavity 800.
[0059] The prepreg layers are shown as 910a, 910b, 910c, 910d, and 910e and are disposed on the cured prepregs 700a and 700b and in the cavity 800.
[0060] The processor 120 issues an instruction to deposit a conductive layer on the surface of the disposed prepreg.
[0061] Referring to FIG. 9, an example is shown.
[0062] The copper layers 900a, 900b, 900c, 900d, and 900e each have one or more openings on the upper surface of the electrodes. The area of the opening is slightly smaller than the area of the nanowire. The copper layers 900a, 900b, 900c, 900d, and 900e overlap with the outer edge of the nanowire array and form an elongated strip for electrical contact after lamination. The width of this strip is directly determined by the accuracy when placing the foil on the panel including at least one power semiconductor. In practice, an accuracy of 50 micrometers to 100 micrometers is expected.
[0063] Figure 10 discloses a panel including at least one power semiconductor after curing of the prepregs 910a, 910b, 910c, 910d, and 910e in step S108. The cured prepreg 100a is a combination of the cured prepreg 700a and the prepregs 910a and 910e. The cured prepreg 100b is the cured prepreg 910b, and the prepreg 100c is a combination of the cured prepreg 700b and the prepregs 910a and 910e.
[0064] In step S109, after curing of the prepreg, the processor 120 issues an instruction to electrodeposit the copper layers 110a and 110b on both sides of the panel including at least one power semiconductor. The electrodeposition at this point is an overplating process, where copper bridges connect the tips of the nanowires to form a continuous layer of copper combined with the initial copper layer.
[0065] A part of the copper layer on the cured prepreg 100b is etched.
[0066] Figure 11 shows the copper layers 110a, 110b, and 110c.
[0067] The obtained two - layer PCB is continuously manufactured using standard PCB manufacturing steps and results in a power module.
[0068] This method enables the production of a package for a power semiconductor that includes the following. · A conductive layer on each electrode of the power semiconductor, · Nanowires on a part of the conductive layer on the electrode, · A cured prepreg between both sides of the power semiconductor and two electrodes, · A conductive layer on the nanowires, where the conductive layer on each electrode of the power semiconductor, the nanowires, and the conductive layer on the nanowires form a single conductor unit.
[0069] The conductive layer on each electrode of the power semiconductor functions as a thermal interface material that dissipates heat from the power semiconductor.
[0070] Figure 12 shows an example of a device for manufacturing an assembly of a power semiconductor housed in a package.
[0071] Device 12 has an architecture based on, for example, components connected by bus 121 and a processor 120 controlled by a program as disclosed in Figure 1.
[0072] Bus 121 links processor 120 to read-only memory ROM 122, random-access memory RAM 123, and input / output I / O IF interface 125. The input / output I / O IF interface 125 enables device 12 to control various processes of the manufacturing process.
[0073] Memory 123 includes registers for the purpose of storing variables and program instructions related to an algorithm as disclosed in Figure 1. Read-only memory, or in some cases flash memory 122, includes program instructions related to an algorithm as disclosed in Figure 1. This program is loaded into random-access memory 123 when power is applied to device 12. Alternatively, this program can also be executed directly from ROM memory 122.
[0074] The process performed by device 12 can also be implemented in software by executing a set of instructions or programs by a programmable computing machine such as a PC (personal computer), DSP (digital signal processor), or microcontroller, or can be implemented in hardware by a machine or dedicated components such as an FPGA (field programmable gate array) or ASIC (application specific integrated circuit).
[0075] In other words, device 12 includes a circuit unit that causes device 12 to execute a program related to the algorithm as disclosed in FIG. 1, or a device including the circuit unit.
Claims
1. A method for manufacturing a power semiconductor having electrodes and housed in a package, the method comprising: placing a masking film over the entire upper and lower surfaces of the power semiconductor and forming an opening over the electrodes; placing a conductive layer on the masked upper and lower surfaces of the power semiconductor; placing a template over the electrodes and the nanowires of the power semiconductor; electrodepositing a conductive material to form nanowires over the electrodes of the power semiconductor, wherein the formation of the nanowires is performed within the template; removing the masking film and the material thereon; inserting the power semiconductor into a cavity of a prepreg panel; curing the prepreg panel; dissolving the template; placing prepreg over the upper and lower surfaces of the cured prepreg panel and over a portion of the power semiconductor between two electrode metallizations; depositing a conductive layer on the surface of the placed prepreg; curing the placed prepreg; after curing the prepreg, placing a conductive layer on the upper and lower surfaces of the panel comprising at least one power semiconductor; etching a portion of the conductive layer over the cured prepreg over a portion of the power semiconductor between two electrode metallizations; A method comprising the above steps.
2. The method according to claim 1, wherein each template covers a portion of the conductive layer over the electrodes and a portion of the conductive layer over the masking film.
3. A package for a power semiconductor, comprising: a conductive layer over each electrode of the power semiconductor; nanowires over a portion of the conductive layer over the electrodes; cured prepreg on both sides of the power semiconductor and over a portion of a masking film separating two electrodes; a conductive layer over the nanowires, wherein the conductive layer over each electrode of the power semiconductor, the nanowires, and the conductive layer over the nanowires form a single conductor unit; A package comprising the above components.
4. The package according to claim 3, characterized in that the height of the nanowire is 30 to 100 times the width of the nanowire.
5. The package according to claim 3 or 4, characterized in that the conductive layer on each electrode of the power semiconductor functions as a thermal interface material for dissipating heat from the power semiconductor.
6. The package according to any one of claims 3 to 5, characterized in that the nanowire is made of a material having conductivity and thermal conductivity, such as copper, nickel, aluminum, silver, gold, carbon, or an alloy of these materials.
7. The package according to any one of claims 3 to 6, characterized in that the nanowire covers 50% to 90% of the surface of the electrode.