High luminous flux LED with a low operating voltage that utilizes two P-N junctions connected in parallel and has one tunnel junction

Abstract

An LED having first and second p-n junctions sequentially deposited on the same wafer is provided. The first and second junctions have n-layers and p-layers in reverse deposition order. One light-emitting active region is embedded between the n-layer and the p-layer of the first junction, and another light-emitting active region is embedded between the n-layer and the p-layer of the second junction. Contacts are processed so that a forward current can pass through both junctions in parallel using a single voltage source. For a given forward current, the LED operates at a lower voltage with a higher luminous flux and efficiency.

Description

Technical Field

[0001] Government license rights This invention was made with government support under Award Number DE-EE009163 awarded by the Department of Energy (DOE). The United States government has certain rights in this invention.

[0002] Embodiments of the present disclosure generally relate to an array of light emitting diode (LED) devices and methods of manufacturing the same. More specifically, embodiments are directed to light emitting diode devices having first and second p-n junctions sequentially deposited on the same wafer, the first and second junctions having n-layers and p-layers in reverse deposition order. One light emitting active region is embedded between the n-layer and the p-layer of the first junction, and another light emitting active region is embedded between the n-layer and the p-layer of the second junction.

Background Art

[0003] A light emitting diode (LED) is a semiconductor light source that emits visible light when an electric current flows through it. An LED combines a P-type semiconductor with an N-type semiconductor. LEDs generally use group III compound semiconductors. Group III compound semiconductors provide stable operation at higher temperatures than devices using other semiconductors. Group III compounds are typically formed on a substrate made of sapphire or silicon carbide (SiC).

[0004] Generally, indium gallium nitride (InGaN)-based light-emitting diodes (LEDs), and particularly green LEDs, suffer from a problem known as "efficiency droop." Droop refers to the non-thermal decrease in the external quantum efficiency (EQE) of an LED as the current density increases. Droop is caused by an increase in the non-radiative Auger recombination rate as the carrier density increases. The optimization of multiple quantum well designs to minimize Auger recombination (droop) has been the subject of extensive research over the years. In particular, for green LEDs, it has been found that the design changes necessary to improve droop unfortunately also increase the forward voltage. The interaction between droop and forward voltage makes it very difficult to further improve the lumens per watt and power conversion efficiency (PCE) of green LEDs operated at high current densities.

[0005] Reducing the current density is a known straightforward method to reduce the forward voltage and increase the EQE and PCE. Increasing the total emitter area is a way to lower the current density while maintaining a certain light output, but that approach increases the system cost and is not viable for applications that require a small light source size. Tunnel junction cascade LEDs are a device design proposed to obtain high flux from a small source size at a lower current density. In a cascade LED, two or more p-n junctions of the same polarity, each surrounding a light-emitting active region, are stacked, and current passes through each of them in series. Since light is emitted from both junctions, the same light output can be obtained at a reduced current density and higher efficiency.

[0006] However, the drawback of cascade LEDs is their high operating voltage (inevitable for multiple junctions connected in series). Even with the efficiency improvement by reducing the current density, cascade LEDs require 10 A / cm 2 to match the flux of conventional LEDs at 40 A / cm 2It is necessary to operate above. The forward voltage of the cascade LED will exceed 6V, and such a high voltage limits the range of possible applications. For example, a 6V cascade LED cannot be used to upgrade an existing lighting system designed with a 3.5V driver.

[0007] Therefore, an improved LED device is needed.

Summary of the Invention

[0008] Embodiments of the present disclosure are directed to an LED device and a method of manufacturing an LED device. In one or more embodiments, a light emitting diode (LED) device is a first light emitting stack on a second light emitting stack, the first light emitting stack having a first n-type layer on a first tunnel junction, the first tunnel junction on a first p-type layer, and the first p-type layer on a first light emitting active region, the second light emitting stack having a second n-type layer in contact with the first light emitting active region and on a second light emitting active region, and the second p-type layer on the second light emitting active region, the first light emitting stack on the second light emitting stack, and a metal contact on the second light emitting stack and extending to the first light emitting stack.

[0009] Further embodiments of the present disclosure are directed to a method of manufacturing an LED device. In one or more embodiments, a method of manufacturing a light emitting diode (LED) die includes epitaxially growing a first light emitting stack and a second light emitting stack on an epitaxial wafer, the first light emitting stack having a first n-type layer on a first tunnel junction, the first tunnel junction on a first p-type layer, and the first p-type layer on a first light emitting active region, the second light emitting stack having a second n-type layer in contact with the first light emitting active region and on a second light emitting active region, and the second p-type layer on the second light emitting active region, and forming at least one metal contact on the second light emitting stack.

[0010] A further embodiment of the present disclosure is directed to a method of manufacturing a thin film flip chip (TFFC) die. In one or more embodiments, a method of manufacturing a thin film flip chip (TFFC) die includes forming two p-n junctions in sequence on an epitaxial wafer to form an epitaxial stack, the epitaxial stack having at least one n-type layer and at least one p-type layer, a light-emitting active region being embedded between the at least one n-type layer and the at least one p-type layer, dry etching the epitaxial stack to form two vias of different depths, conformally depositing a dielectric layer in the two vias, removing a portion of the dielectric layer to form a contact opening, depositing one or more of an anode layer and a cathode layer in the contact opening, depositing a bonding metal layer on one or more of the anode layer or the cathode layer, singulating the thin film flip chip (TFFC) die, and bonding the thin film flip chip (TFFC) die to a submount.

Brief Description of the Drawings

[0011] To enable a more detailed understanding of the above-described features of the present disclosure, a more specific description of the present disclosure, briefly summarized above, is provided with reference to the embodiments, some of which are shown in the accompanying drawings. It should be noted, however, that the accompanying drawings show only typical embodiments of this disclosure and are therefore not to be considered as limiting its scope, as the present disclosure may admit to other equally effective embodiments. The embodiments described herein are shown by way of example and not limitation in the figures of the accompanying drawings, in which like elements are referred to by like reference numerals.

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[0012] For ease of understanding, the same reference numerals are used, where possible, to designate the same elements common to these figures. These figures are not drawn to scale. For example, the height and width of the mesa are not drawn to scale.

DETAILED DESCRIPTION OF THE INVENTION

[0013] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or process steps described in the following description. The present disclosure can have other embodiments and can be implemented or executed in various ways.

[0014] As used herein, the term "substrate" according to one or more embodiments refers to an intermediate or final structure having a surface or surface portion on which a process acts. Further, references to a substrate in some embodiments also refer to only a portion of the substrate, unless the context clearly indicates otherwise. Also, references to deposition on a substrate according to some embodiments include deposition on a bare substrate or on a substrate on which one or more layers, films, features or materials have been deposited or formed thereon.

[0015] In one or more embodiments, "substrate" means any substrate or the surface of a material formed on a substrate on which film processing is performed during a manufacturing process. In exemplary embodiments, the substrate surface on which processing is performed can be, depending on the application, materials such as silicon, silicon oxide, silicon-on-insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, etc., and any other suitable materials such as metals, metal nitrides, group III nitrides (e.g., GaN, AlN, InN, and other alloys), metal alloys, and other conductive materials. The substrate includes, without limitation, light emitting diode (LED) devices. The substrate in some embodiments is subjected to a pretreatment process for polishing, etching, reducing, oxidizing, hydroxylation, annealing, UV curing, electron beam curing, and / or baking the substrate surface. In addition to direct film processing on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps can also be performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include the underlying layer as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0016] The terms "wafer" and "substrate" are used interchangeably herein. Thus, as used herein, a wafer functions as a substrate for the formation of the LED devices described herein.

[0017] The following, with reference to the accompanying drawings, examples of a plurality of different optical illumination systems and / or light-emitting diode (“LED”) implementations will be more fully described. These examples are not mutually exclusive, and features found in one example can be combined with features found in one or more other examples to achieve further implementations. Accordingly, it is understood that the examples shown in the accompanying drawings are provided for illustrative purposes only and are not intended to limit the present disclosure in any way. Throughout, like elements are referred to by like reference numerals.

[0018] Among the most efficient light sources currently available are semiconductor light-emitting devices, or light-output emitting devices such as those that emit light output in, for example, ultraviolet (UV) or infrared (IR) ranges. These devices can include light-emitting diodes, resonant-cavity light-emitting diodes, vertical-cavity surface-emitting lasers, edge-emitting lasers, or the like (hereinafter referred to as “LEDs”). LEDs can be attractive candidates for many different applications, for example, due to their small size and lower power requirements. For example, they can be used as light sources (e.g., flash light and camera flash) for portable battery-powered devices such as cameras and mobile phones. They can also be used, for example, for automotive lighting, head-up display (HUD) lighting, horticultural lighting, street lighting, video torches, general lighting (e.g., lighting of homes, stores, offices, and studios, theater / stage lighting, and architectural lighting), augmented reality (AR) lighting, virtual reality (VR) lighting, as backlights for displays, and also for IR spectroscopy. A single LED will provide light that is not brighter than an incandescent light source, and thus, for applications where brighter light is desired or required, multi-junction devices or arrays of LEDs (e.g., monolithic LED arrays, micro-LED arrays, etc.) can be used.

[0019] The present disclosure generally relates to the manufacture of green light sources for use in high-power general lighting systems.

[0020] The embodiments described herein describe an LED device and a method of forming an LED device. In particular, the present disclosure describes an LED device having first and second p-n junctions deposited in sequence on the same wafer, where the first and second junctions have n-layers and p-layers in opposite deposition orders, and a method of manufacturing the LED device. One light-emitting active region is embedded between the n-layer and the p-layer of the first junction, and another light-emitting active region is embedded between the n-layer and the p-layer of the second junction. In one or more embodiments, both active regions emit the same color, and efficiency advantages are expected primarily for cyan or longer-wavelength light. Contacts are processed such that a forward current can pass through both junctions in parallel using a single voltage source. For a given forward current, the disclosed LED operates at a lower voltage with a higher luminous flux and efficiency than a standard LED having a similar light-emitting active region.

[0021] As used herein, the term "p-n junction" refers to the boundary between two semiconductor layers of opposite conductivity types, a p-type and an n-type. The "p" side contains an excess of holes, and the "n" side contains an excess of electrons. The excess holes and electrons can be obtained, respectively, by intentional doping with acceptor or donor impurities, and / or may result from the presence of natural crystal defects. The boundary is not necessarily abrupt, flat, or smooth. The boundary can include a gradient of impurity concentration and / or a layer of intrinsic (neutral) conductivity type between the p-type and n-type layers. The boundary may be characterized by a protrusion of the p-type semiconductor into the n-type semiconductor or vice versa.

[0022] One or more embodiments require p-side down nitride epitaxy in which a p-type layer is grown in front of the quantum well, which is the reverse of the normal case where an n-type layer is grown in front of the quantum well. There has been a widely supported perception that high-efficiency p-side down LEDs are not achievable due to unintentional acceptor dopant incorporation into the quantum well. However, in one or more embodiments, unintentional acceptor dopant incorporation into the quantum well is advantageously reduced using special growth conditions for manufacturing high-efficiency p-side down LEDs. At current lighting-related current densities, the EQE deficit between p-side down LEDs and conventional LEDs is not large and can be further reduced.

[0023] In one or more embodiments, there are two general configurations of epitaxy used to fabricate the desired dual active region LED. The examples described herein relate to a thin film flip chip (TFFC) die architecture, but the same epitaxy design can be processed into other die architectures using similar manufacturing methods. Chip scale packages, vertical thin films, and lateral dies are other possible architectures. In the first epitaxy configuration, shown in FIG. 1, all metal contacts can be made to the n-type layer and the contact polarity is the same as that of traditional devices. In the second or alternative epitaxy configuration, shown in FIG. 2, only one tunnel junction needs to be grown, facilitating epitaxy growth.

[0024] Embodiments of the present disclosure are described with reference to figures showing devices and processes for device formation according to one or more embodiments of the present disclosure. The processes shown are merely possible examples of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the exemplary uses.

[0025] One or more embodiments of the present disclosure will be described with reference to the drawings. FIG. 1 shows a schematic cross-sectional view of an epitaxial structure 100 of "Configuration A" according to one or more embodiments. FIG. 2 shows a schematic cross-sectional view of an alternative epitaxial structure 200 of "Configuration B" according to one or more alternative embodiments. A further aspect of the present disclosure relates to a method of manufacturing a thin film flip chip (TFFC) device from an epitaxial structure as shown in FIGS. 3 and 4.

[0026] Referring to FIG. 1, the dual active region LED wafer 100 is manufactured by forming a plurality of group III nitride layers on a substrate 102 to form two p-n junction LEDs including a light emitting active region on the substrate. Those two p-n junctions are connected in parallel. The light emitting active region includes a first light emitting active region 106a and a second light emitting active region 106b. Any order of stacking these different active regions is within the scope of the present disclosure.

[0027] According to a particular specific embodiment, the dual active region LED wafer 100 has a first light emitting stack 105a having a first n-type layer 104a formed on the substrate 102, a first light emitting active region 106a grown on the first n-type layer 104a, a first p-type layer 108a formed on the first light emitting active region 106a, and a first tunnel junction 110a formed on the first p-type layer 108a.

[0028] In one or more embodiments, the first light-emitting active region 106a is a green light-emitting active region. In the illustrated embodiment, a first tunnel junction 110a is present on the first junction, particularly on the first p-type layer 108a. A tunnel junction is a structure that enables electrons to tunnel from the valence band of the p-type layer to the conduction band of the n-type layer in reverse bias. When electrons tunnel, holes are left in the p-type layer, and as a result, carriers are generated in both regions. Thus, in an electronic device such as a diode where only a small leakage current flows in reverse bias, a large current can flow in reverse bias across the tunnel junction. A tunnel junction has a special alignment of the conduction band and valence band in a p / n tunnel junction. This can be achieved by using a very high doping (e.g., p++ / n++ junction). Further, group III nitride materials have an inherent polarization that creates an electric field at the heterointerface between different alloy compositions. In some situations, this polarization field can also be utilized to achieve the band alignment for tunneling.

[0029] Still referring to FIG. 1, the dual active region LED wafer 100 further has a second light-emitting stack 105b on the first light-emitting stack 105a. The second light-emitting stack 105b includes a second n-type layer 104b on the first tunnel junction 110a, a second tunnel junction 110b on the second n-type layer 104b, a second light-emitting active region 106b grown on the second p-type layer 108b, and a third n-type layer 104c on the second light-emitting active region 106b. In one or more embodiments, the second light-emitting active region 106b is also a green light-emitting active region. In the illustrated embodiment, a second tunnel junction 110b is present on the second light-emitting stack 105a, particularly on the second n-type layer 104b.

[0030] In one or more embodiments, a nucleation layer (not shown) and a dislocation density control layer (not shown) are grown on a suitable substrate 102, such as patterned sapphire or unpatterned sapphire. In one or more embodiments, the nucleation layer has a group III nitride material. In certain embodiments, the nucleation layer has gallium nitride (GaN) or aluminum nitride (AlN).

[0031] In one or more embodiments, a first n-type layer 104a is grown on the substrate 102, the nucleation layer, and / or the dislocation density control layer. In one or more embodiments, the first n-type layer 104a is formed on the substrate 102. The substrate 102 can be any substrate known to those skilled in the art configured to be used in the formation of an LED device. In one or more embodiments, the substrate 102 has one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), and spinel. In one or more embodiments, the substrate 102 is a transparent substrate. In certain embodiments, the substrate 102 has sapphire. In one or more embodiments, the substrate 102 is not patterned prior to the formation of the LED. Thus, in some embodiments, the substrate 102 can be considered unpatterned, flat, or substantially flat. In other embodiments, the substrate 102 is a patterned substrate.

[0032] In one or more embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c can have any III-V semiconductor including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also referred to as III-nitride materials. Thus, in some embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c can independently have one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), and indium aluminum nitride (InAlN). In a particular embodiment, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c have gallium nitride (GaN). In one or more embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c are independently doped with an n-type dopant such as silicon (Si) or germanium (Ge). In one or more embodiments, the dopant concentration ranges from 1e17 to 2e19 cm -3 -3. In one or more embodiments, the first n-type layer 104a can have a thickness in the range of 1 μm to 3 μm to ensure a wide process margin for subsequent etching processes used to contact this layer.

[0033] In one or more embodiments, the layer of III-nitride material can be deposited by one or more of sputter deposition, atomic layer deposition (ALD), metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), plasma atomic layer deposition (PEALD), and plasma chemical vapor deposition (PECVD).

[0034] "Sputter deposition" as used herein refers to a physical vapor deposition (PVD) method of thin film deposition by sputtering. In sputter deposition, materials such as group III nitrides are emitted from a target, which is the source, onto a substrate. This technique is based on ion bombardment of the source material, which is the target. The ion bombardment is a purely physical process, namely, it results in vaporization by sputtering of the target material.

[0035] When used in accordance with some embodiments herein, "atomic layer deposition" (ALD) or "cyclic deposition" refers to a vapor phase technique used to deposit a thin film on a substrate surface. The process of ALD involves the substrate surface or a portion of the substrate being exposed alternately to precursor(s), i.e., two or more reactive compounds, to deposit a layer of material on the substrate surface. When the substrate is exposed to the precursor(s) alternately, the precursors are introduced sequentially or simultaneously. The precursors are introduced into the reaction zone of the processing chamber and the substrate or a portion of the substrate is exposed to those precursors separately.

[0036] When used in accordance with some embodiments herein, "chemical vapor growth" refers to a process in which a film of material is deposited from the vapor phase by decomposition of a chemical substance on a substrate surface. In CVD, the substrate surface is exposed to a precursor and / or a co-reactant simultaneously or substantially simultaneously. A particular subset of CVD processes commonly used in LED manufacturing uses organometallic precursor chemicals and is referred to as metalorganic chemical vapor deposition (MOCVD) or metalorganic vapor phase epitaxy (MOVPE). As used herein, "substantially simultaneously" refers to either a parallel flow or a case where there is overlap for most of the exposure of the precursors.

[0037] As used herein according to some embodiments, "plasma enhanced atomic layer deposition (PEALD)" refers to a technique for depositing a thin film on a substrate. For a thermal ALD process, in some examples of the PEALD process, materials can be formed from the same chemical precursors but at a higher deposition rate and lower temperature. In the PEALD process, generally, a reactive gas and a reactive plasma are sequentially introduced into a process chamber having a substrate therein. A first reactive gas is pulsed in the process chamber and adsorbed on the substrate surface. Thereafter, the reactive plasma is pulsed and introduced into the process chamber to react with the first reactive gas to form a deposited material, such as a thin film, on the substrate. Similar to the thermal ALD process, a purge step can be performed between each delivery of reactants.

[0038] As used herein according to one or more embodiments, "plasma enhanced chemical vapor deposition (PECVD)" refers to a technique for depositing a thin film on a substrate. In the PECVD process, a vapor or liquid phase source material, such as a vapor of a group III nitride material in the gas phase or a liquid phase group III nitride material mixed in a carrier gas, is introduced into a PECVD chamber. A plasma initiation gas is also introduced into the chamber. Generation of plasma in the chamber creates excited radicals. The excited radicals chemically bond to the surface of a substrate located in the chamber to form a desired film thereon.

[0039] In one or more embodiments, the μLED array 100 is manufactured by disposing the substrate 102 in a metalorganic vapor phase epitaxy (MOVPE) reactor such that a μLED array layer is epitaxially grown.

[0040] In one or more embodiments, after the growth of the first n-type layer 104a, the first light-emitting active region 106a is grown. The first light-emitting active region 106a may include (one or more) electron blocking layers grown after the quantum wells and a strain control layer grown before the quantum wells, and is composed of multiple quantum wells. The process of growing the strain control layer may generate V-pit defects before the growth of the first quantum well. The number of quantum wells typically used in green LEDs ranges from 4 to 12, the typical barrier thickness ranges from 5 nm to 25 nm, the well thickness ranges from 1 nm to 5 nm, and the indium concentration in the wells ranges from 15% indium to 25% indium. In some embodiments, the active region can be doped with Si or Ge, and in other embodiments, the active region is not doped. After the first light-emitting active region 106a is grown, the first p-type layer 108a is grown on the first light-emitting active region.

[0041] In one or more embodiments, the first p-type layer 108a and the second p-type layer 108b may each independently have any III-V semiconductor including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also referred to as group III nitride materials. Thus, in some embodiments, the first p-type layer 108a and the second p-type layer 108b each independently have one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), and indium aluminum nitride (InAlN). In one or more embodiments, magnesium (Mg) is the acceptor dopant of the first p-type layer 108a. Then, the first tunnel junction 110a is grown, which is 10 19 ~10 21 cm -3It has a highly doped p-GaN layer and an n-GaN layer with doping concentrations within a range and a layer thickness typically less than 50 nm. The first tunnel junction 110a may also utilize a thin InGaN layer or a plurality of graded InGaN layers disposed between the highly doped GaN layers.

[0042] In some embodiments, the first p-type layer 108a and the second p-type layer 108b each independently have a series of doped p-type layers. In one or more embodiments, the first p-type layer 108a and the second p-type layer 108b each independently have a gallium nitride (GaN) layer. The first p-type layer 108a and the second p-type layer 108b can each independently be doped with any suitable p-type dopant known to those skilled in the art. In one or more embodiments, the first p-type layer 108a and the second p-type layer 108b can each independently be doped with magnesium (Mg). In one or more embodiments, the first p-type layer 108a and the second p-type layer 108b each independently have a first magnesium-doped p-type aluminum gallium nitride layer, a magnesium-doped p-type gallium nitride layer, and a second magnesium-doped p-type aluminum gallium nitride layer.

[0043] In one or more embodiments, a second n-type layer 104b is grown. To ensure an even current distribution within the device, it may be advantageous to match the sheet resistance of the first and second n-type layers 104a, 104b, although mismatched implementations are also possible using the differences in the spacing of the first and second sets of contact vias described later. In one or more embodiments, the second n-type layer 104b has a thickness of at least 100 nm so that contacts can later be etched into this layer. An AlGaN layer (not shown) may be embedded within the second n-type layer 104b to facilitate controlled etching to a specific depth.

[0044] After the second n-type layer is grown, a second tunnel junction 110b is grown. The design of the second tunnel junction may be the same as or different from that of the first tunnel junction 110a.

[0045] In one or more embodiments, after the second tunnel junction 110b is grown, a second p-type layer 108b is grown, followed by a second light-emitting active region 106b. The general range of parameter limitations for the second light-emitting active region 106b is the same as that for the first light-emitting active region 106a, although some differences in specific details may be required to obtain similar characteristics for the first and second active regions with opposite polarities. It is desirable to match their characteristics to ensure that the current flowing through the first and second active regions is similar for a given voltage.

[0046] In one or more embodiments, epitaxy is terminated by the growth of a third n-type layer 104c. In the embodiments depicted in FIGS. 3 and 4, the third n-type layer 104c is not a current spreading layer and can thus be grown with a thickness and doping lower than those of the first two n-type layers.

[0047] FIG. 3 shows a schematic cross-sectional view of the first variation 100 of FIG. 1 after being processed into a thin-film flip-chip (TFFC) die design. The die is designed with electrical contacts such that the "middle" n-type layer of this structure is a common cathode (or common anode) for both of the two p-n junctions in the stack. This is a common anode in the first variation A 100 of FIG. 1 and a common cathode in the second variation B 200 of FIG. 2. Examples of possible thin-film flip-chip (TFFC) die designs are shown in FIGS. 3 and 4. In one or more embodiments, a set of additional contact vias that are not required in a standard LED die (or cascaded LEDs) is needed, but the EQE droop and voltage advantages from sharing the current through the two active regions can outweigh the disadvantage of losing some active regions to the additional vias.

[0048] After epitaxial growth, the wafer is processed through the following manufacturing steps, resulting in an LED die that appears in cross-section as shown in FIG. 3. For growth on a patterned sapphire substrate, the final step on the list may be omitted. The main difference between the standard TFFC die design and the design of one or more embodiments herein is the second set of vias required to contact the second n-type layer 104b.

[0049] Referring to FIG. 3, two sets of vias 120a, 120b are dry etched to form the TFFC die design 150. The vias 120a, 120b have different depths D1, D2. In one or more embodiments, D2 can range from 0.1 micron to 1.0 micron, and D1 can range from 0.4 micron to 3 microns.

[0050] In one or more embodiments, the epitaxial stack of FIG. 1 is first subjected to acceptor activation annealing. In some embodiments, it is preferable to perform acceptor activation annealing after dry etching to allow hydrogen to escape from the implanted p-type layer through the via sidewalls.

[0051] In one or more embodiments, a conformal dielectric layer 112 is deposited within vias 120a, 120b. As used herein, the term "dielectric" refers to an electrically insulating material that can be polarized by an applied electric field. In one or more embodiments, the dielectric layer includes, but is not limited to, oxides such as silicon oxide (SiO2), aluminum oxide (Al2O3), nitrides such as silicon nitride (Si3N4), etc. In one or more embodiments, the dielectric layer has a multi-layer of silicon nitride (Si3N4), silicon oxide (SiO2), or silicon dioxide (SiO2) and silicon nitride (Si3N4). In some embodiments, the composition of the dielectric is non-stoichiometric with respect to the ideal molecular formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), oxynitrides (e.g., silicon oxynitride (SiON)), and carbon oxynitrides (e.g., silicon carbon oxynitride (SiNCO)).

[0052] Still referring to FIG. 3, in one or more embodiments, a portion of the dielectric layer 112 is removed by dry etching to form contact openings 122, 124. A cathode metal layer 116 is deposited along the sidewalls of via 120a in the deeper via 120a at contact opening 122. The cathode metal layer 116 can have any suitable material known to those skilled in the art. In one or more embodiments, the cathode metal layer 116 is any highly reflective metal that makes an ohmic contact with the n-type layer. In one or more specific embodiments, the cathode metal layer 116 has an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0053] In one or more embodiments, an anode metal layer 118 is deposited along the sidewall of the via 120b in the shallower contact opening 124 of the via 120b. The anode metal layer 118 can have any suitable material known to those skilled in the art. In one or more embodiments, the anode metal layer 118 is any highly reflective metal that forms an ohmic contact with the n-type layer. In some embodiments, the anode metal layer 118 and the cathode metal layer 116 have the same material, are deposited in the same process, and are patterned using techniques such as lift-off or dry etching. In one or more specific embodiments, the anode metal layer 118 has an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0054] In one or more embodiments, a bonding metal layer 114 is deposited in the contact openings 122, 124. In some embodiments, the bonding metal layer 114 is a thicker metal layer with a composition different from that of the cathode metal layer 116 and the anode metal layer 118 to facilitate bonding to a subsequent submount. In one or more embodiments, the metal of the bonding metal layer 114 can have any suitable material known to those skilled in the art. In one or more embodiments, the bonding metal layer 114 has one or more of titanium (Ti) and gold (Au).

[0055] Referring to FIG. 3, in one or more embodiments, the die is singulated. Then, the die is bonded to the submount 126 using a technique such as gold-gold interconnect bonding. The final steps are laser lift-off and subsequent photoelectrochemical etching for texturing the surface 128.

[0056] FIG. 2 shows a schematic cross-sectional view of an alternative epitaxial configuration 200, "Configuration B", according to one or more alternative embodiments. A further aspect of the present disclosure relates to a method of manufacturing a thin film flip chip (TFFC) device from an epitaxial configuration as shown in FIG. 4.

[0057] Referring to FIG. 2, the dual active region LED 200 is fabricated by forming a plurality of group III nitride layers on a substrate 202 to form two p-n junction LEDs including light-emitting active regions on the substrate. These two p-n junctions are connected in parallel. The light-emitting active regions include a first light-emitting active region 106a and a second light-emitting active region 106b. Any order of stacking these different active regions is within the scope of the present disclosure.

[0058] According to a particular specific embodiment, the dual active region LED 200 has a first light-emitting stack 205a having a first n-type layer 204a formed on the substrate 202, a first tunnel junction 210a formed on the first n-type layer 204a, and a first p-type layer 208a formed on the first tunnel junction 210a, and a first light-emitting active region 206a is grown on the first p-type layer 208a.

[0059] In one or more embodiments, the first light-emitting active region 206a is a green light-emitting active region. In the illustrated embodiment, a first tunnel junction 210a is present on the first junction, particularly on the first n-type layer 204a.

[0060] Still referring to FIG. 2, the dual active region LED 200 further has a second light-emitting stack 205b on the first light-emitting stack 205a. The second light-emitting stack 205b includes a second n-type layer 204b on the first light-emitting active region 206a, a second light-emitting active region 206b on the second n-type layer 204b, and a second p-type layer 208b on the second light-emitting active region 206b. In one or more embodiments, the second light-emitting active region 206b is also a green light-emitting active region.

[0061] In one or more embodiments, a nucleation layer (not shown) and a dislocation density control layer (not shown) are grown on a suitable substrate 202, such as patterned sapphire or unpatterned sapphire. In one or more embodiments, the nucleation layer has a group III nitride material. In a particular embodiment, the nucleation layer has gallium nitride (GaN) or aluminum nitride (AlN).

[0062] In one or more embodiments, the first n-type layer 204a is grown on a substrate 202, a nucleation layer, and / or a dislocation density control layer. In one or more embodiments, the first n-type layer 204a is formed on the substrate 202. The substrate 202 can be any substrate known to those skilled in the art configured to be used in the formation of an LED device. In one or more embodiments, the substrate 202 has one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), and spinel. In one or more embodiments, the substrate 202 is a transparent substrate. In certain embodiments, the substrate 202 has sapphire. In one or more embodiments, the substrate 202 is not patterned prior to the formation of the LED. Thus, in some embodiments, the substrate 202 can be considered unpatterned and flat or substantially flat. In other embodiments, the substrate 202 is a patterned substrate.

[0063] In one or more embodiments, the first n-type layer 204a and the second n-type layer 204b can have any III-V semiconductor including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also referred to as group III nitride materials. Thus, in some embodiments, the first n-type layer 204a and the second n-type layer 204b independently have one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), and indium aluminum nitride (InAlN). In a particular embodiment, the first n-type layer 204a and the second n-type layer 204b have gallium nitride (GaN). In one or more embodiments, the first n-type layer 204a and the second n-type layer 204b are independently doped with an n-type dopant such as, for example, silicon (Si) or germanium (Ge). In one or more embodiments, the dopant concentration is 1e17~2e19cm -3is in the range. In one or more embodiments, the first n-type layer 204a may have a thickness in the range of 1 μm to 3 μm to ensure a wide process margin for subsequent etching processes used to contact this layer.

[0064] In one or more embodiments, the dual active region LED 200 is manufactured by placing the substrate 202 in a metalorganic vapor phase epitaxy (MOVPE) reactor such that the dual active region LED layer is epitaxially grown.

[0065] In one or more embodiments, after the growth of the first n-type layer 204a, the first tunnel junction 210a is grown, followed by the growth of the first p-type layer 208a. In one or more embodiments, the first tunnel junction 210a has a doping concentration in the range of 10 19 ~10 21 cm -3 and has highly doped p-GaN and n-GaN layers with a layer thickness typically less than 50 nm. In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b may independently have any III-V semiconductor including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also referred to as group III nitride materials. Thus, in some embodiments, the first p-type layer 208a and the second p-type layer 208b independently have one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), and indium aluminum nitride (InAlN). In one or more embodiments, magnesium (Mg) is the acceptor dopant of the first p-type layer 208a.

[0066] In some embodiments, the first p-type layer 208a and the second p-type layer 208b each independently have a series of doped p-type layers. In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b each independently have a gallium nitride (GaN) layer. The first p-type layer 208a and the second p-type layer 208b can each independently be doped with any suitable p-type dopant known to those skilled in the art. In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b can each independently be doped with magnesium (Mg). In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b each independently have a first magnesium-doped p-type aluminum gallium nitride layer, a magnesium-doped p-type gallium nitride layer, and a second magnesium-doped p-type aluminum gallium nitride layer.

[0067] Next, the first light-emitting active region 206a is grown. The first light-emitting active region 206a can include a multiple quantum well and (one or more) electron blocking layers grown after the quantum well and a strain control layer grown before the quantum well. The process of growing the strain control layer can generate V-pit defects before the growth of the first quantum well. The number of quantum wells typically used in green LEDs ranges from 4 to 12, the typical barrier thickness ranges from 5 nm to 25 nm, the well thickness ranges from 1 nm to 5 nm, and the indium concentration in the well ranges from 15% indium to 25% indium. In some embodiments, the active region can be doped with Si or Ge, and in other embodiments, the active region is not doped.

[0068] In one or more embodiments, a second n-type layer 204b is grown on the first light-emitting active region 206a. To ensure a uniform current distribution within the device, it may be advantageous to match the sheet resistances of the first and second n-type layers 204a, 204b, although non-matching implementations are also possible using the differences in the spacing of the first and second sets of contact vias described later. In one or more embodiments, the second n-type layer 204b has a thickness of at least 100 nm so that contacts can be etched into this layer later. An AlGaN layer (not shown) may be embedded within the second n-type layer 204b to facilitate controlled etching to a specific depth.

[0069] After the second n-type layer 204b is grown, a second light-emitting active region 206b is grown, followed by the growth of the second p-type layer 208b. The general range of parameter restrictions for the second light-emitting active region 206b is the same as for the first light-emitting active region 206a, although some differences in specific details may be required to obtain similar characteristics for the first and second active regions with opposite polarities. It is desirable to ensure that the currents flowing through the first and second active regions are similar for a given voltage.

[0070] FIG. 4 shows a schematic cross-sectional view of the second variation 200 of FIG. 2 after processing into a thin-film flip-chip (TFFC) die design. After epitaxial growth, the wafer is processed through the following manufacturing steps, resulting in an LED die that appears as the cross-section shown in FIG. 4. In the growth on a patterned sapphire substrate, the final step on the list may be omitted. The main difference between the standard TFFC die design and the design of one or more embodiments here is the second set of vias required to contact the second n-type layer 204b.

[0071] Referring to FIG. 4, two sets of vias 220a, 220b are dry etched to form the TFFC die design 250. The vias 220a, 220b have different depths D1, D2. In one or more embodiments, D2 can range from 0.1 micron to 1.0 micron, and D1 can range from 0.4 micron to 3 microns.

[0072] In one or more embodiments, the epitaxial stack of FIG. 2 is first subjected to acceptor activation annealing. In some embodiments, it is preferred to perform acceptor activation annealing after dry etching to allow hydrogen to escape from the implanted p-type layer through the via sidewalls.

[0073] In one or more embodiments, a conformal dielectric layer 212 is deposited within the vias 220a, 220b. In one or more embodiments, the dielectric layer includes, but is not limited to, oxides such as silicon oxide (SiO2), aluminum oxide (Al2O3), nitrides such as silicon nitride (Si3N4). In one or more embodiments, the dielectric layer has a silicon nitride (Si3N4), silicon oxide (SiO2), or a multi-layer of silicon dioxide (SiO2) and silicon nitride (Si3N4). In some embodiments, the composition of the dielectric is non-stoichiometric with respect to the ideal molecular formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), oxicarbides (e.g., silicon oxicarbide (SiOC)), and oxynitridocarbides (e.g., silicon oxynitridocarbon (SiNCO)).

[0074] Referring still to FIG. 4, in one or more embodiments, a portion of the dielectric layer 212 is removed by dry etching to form contact openings 222, 224. A cathode metal layer 216 is deposited along the sidewalls of the via 220a in the deeper via 220a in the contact opening 224. The cathode metal layer 216 may have any suitable material known to those skilled in the art. In one or more embodiments, the cathode metal layer 216 is any highly reflective metal that makes an ohmic contact with the n-type layer. In one or more specific embodiments, the cathode metal layer 216 has an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0075] In one or more embodiments, an anode metal layer 218 is deposited along the sidewalls of the via 220b in the contact opening 222 in the shallower via 220b. The anode metal layer 218 may have any suitable material known to those skilled in the art. In one or more embodiments, the anode metal layer 218 is any highly reflective metal that makes an ohmic contact with the n-type layer. In some embodiments, the anode metal layer 218 and the cathode metal layer 216 have the same material, are deposited in the same process, and are patterned using techniques such as lift-off or dry etching. In one or more specific embodiments, the anode metal layer 218 has an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0076] In one or more embodiments, a bonding metal layer 214 is deposited in the contact openings 222, 224. In some embodiments, the bonding metal layer 214 is a thicker metal layer with a composition different from that of the cathode metal layer 216 and the anode metal layer 218 to facilitate bonding to a subsequent submount. In one or more embodiments, the metal of the bonding metal layer 214 may have any suitable material known to those skilled in the art. In one or more embodiments, the bonding metal layer 214 has one or more of titanium (Ti) and gold (Au).

[0077] Referring to FIG. 4, in one or more embodiments, the die is singulated. Then, the die is bonded to the submount 226 using a technique such as, for example, gold-gold interconnect bonding. The final steps are laser lift-off and subsequent photoelectrochemical etching to texture the surface 228.

[0078] FIG. 5 shows a schematic cross-sectional view of the epitaxial structure of FIG. 2 after processing into a lateral die 275. In one or more embodiments, the lateral die 275 includes a first dual active region LED having a first n-type layer 204a formed on a substrate 202, a first tunnel junction 210a formed on the first n-type layer 204a, a first p-type layer 208a formed on the first tunnel junction 210a, and a first light-emitting active region 206a grown on the first p-type layer 208a, and a second light-emitting stack 205b on the first light-emitting stack 205a. The second light-emitting stack 205b includes a second n-type layer 204b on the first light-emitting active region 206a, a second light-emitting active region 206b on the second n-type layer 204b, and a second p-type layer 208b on the second light-emitting active region 206b.

[0079] In one or more embodiments, the cathode metal layer 216 extends from the second n-type layer 204b to the second p-type layer 208b. In some embodiments, since the dielectric layer 212 is adjacent to the die and the cathode metal layer 216, the cathode metal layer 216 is not in electrical contact with the second p-type layer. In other embodiments (not shown), the cathode metal layer 216 does not extend completely to the top of the die. Extending the cathode metal layer 216 to the top allows for additional room for including wire bonding pads 232 while maintaining the narrow width of the cathode metal layer 216 on the side of the mesa of the die. The cathode metal layer 216 can have any suitable metal known to those skilled in the art. In one or more specific embodiments, the cathode metal layer 216 has an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0080] In one or more embodiments, the anode contact 218 is formed on the top surface of the second p-type layer 208b and extends to the first n-type layer 204a. The anode contact 218 can have any suitable material known to those skilled in the art. In one or more embodiments, the anode contact has transparent indium tin oxide (ITO).

[0081] In one or more embodiments, a dielectric layer 212 is formed on the die 275 to insulate the die from one or more of the anode contact 218 and the cathode metal layer 216. In one or more embodiments, the dielectric layer 212 includes, but is not limited to, oxides such as silicon oxide (SiO2), aluminum oxide (Al2O3), and nitrides such as silicon nitride (Si3N4). In one or more embodiments, the dielectric layer has silicon nitride (Si3N4), silicon oxide (SiO2), or a multi-layer of silicon dioxide (SiO2) and silicon nitride (Si3N4). In some embodiments, the composition of the dielectric 212 is non-stoichiometric with respect to the ideal molecular formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), oxicarbides (e.g., silicon oxycarbide (SiOC)), and oxynitridocarbides (e.g., silicon oxynitridocarbon (SiNCO)).

[0082] In one or more embodiments, the lateral die 275 is mounted on the submount 226. A wire 230a can connect the positive terminal 232 of the submount 226 to the die 275. A wire 230b can connect the negative terminal 234 of the submount 226 to the die 275.

[0083] FIG. 6 shows a process flow diagram of a method 60 for manufacturing a dual active region LED die according to one or more embodiments. In the method, at process 62, two p-n junctions are sequentially grown epitaxially on the same epitaxial wafer. At process 64, a metal contact is formed on the second p-n junction.

[0084] FIG. 7 shows a process flow diagram of a method 50 for manufacturing a thin film flip chip (TFFC) die design in accordance with one or more embodiments of the present disclosure. Referring to FIG. 7, in one or more embodiments, the method begins at process 52 by forming two p-n junctions in sequence on the same epitaxial wafer to form an epitaxial stack, the epitaxial stack having at least one n-type layer and at least one p-type layer, with a light-emitting active region embedded between the at least one n-type layer and the at least one p-type layer. At process 54, two sets of vias at different depths are dry etched into the epitaxial stack. At process 56, a dielectric layer is conformally deposited within the vias. At process 58, a portion of the dielectric layer is removed to form a contact opening within the vias, the contact opening exposing at least one n-type layer. At process 60, cathode metal and anode metal are deposited within the vias on the dielectric layer. At process 62, a bonding metal layer is deposited. At process 64, die singulation is performed. At process 66, the die is bonded to a submount. At process 68, laser lift-off is performed.

[0085] FIG. 8 shows an example of a general device in accordance with some embodiments. The device 600 can be, for example, a laptop computer (PC), a tablet PC, a smartphone, or a mobile device such as augmented reality (AR) / virtual reality (VR), or an automotive device. Various elements can be provided on the backplane shown above, while other elements can be local or remote. The examples described herein can include logic or some components, modules, or mechanisms, or can operate thereon.

[0086] Modules and components are tangible entities (e.g., hardware) capable of performing specified operations and can be configured or arranged in a particular manner. In one example, a circuit can be arranged as specified as a module (e.g., internally or with respect to an external entity such as another circuit). In one example, all or part of one or more computer systems (e.g., stand-alone, client, or server computer systems), or one or more hardware processors, can be configured by firmware or software (e.g., instructions, an application portion, or an application) as a module that operates to perform the specified operations. In one example, the software can reside on a machine-readable medium. In one example, the software causes the hardware to perform the operations specified for the hardware when executed by the hardware underlying the module.

[0087] Accordingly, the terms “module” (and “component”) are understood to encompass tangible entities that are physically constructed, specially configured (e.g., hardwired), or temporarily (e.g., ephemerally) configured (e.g., programmed) to operate as specified or to perform some or all of any of the operations described herein. Considering an example where a module is temporarily configured, each of the modules need not be instantiated at any given moment. For example, if a module includes a general-purpose hardware processor configured using software, the general-purpose hardware processor can be configured as different modules at different times. The software can, for example, configure the hardware processor as appropriate to configure a particular module at one time and a different module at a different time.

[0088] The electronic device 600 can include a hardware processor (or equivalently a processing circuit) 602 (e.g., a central processing unit (CPU), GPU, hardware processor core, or any combination thereof), and a memory 604 (which may include main memory and static memory), and some or all of them can communicate with each other via an interlink (e.g., a bus) 608. The memory 604 can include any or all of removable storage and non-removable storage, volatile memory or non-volatile memory. The electronic device 600 can further include, for example, a display / light source 610 such as the LED described above, or a video display, an alphanumeric input device 612 (e.g., a keyboard), and a user interface (UI) navigation device 614 (e.g., a mouse). In one example, the display / light source 610, the input device 612, and the UI navigation device 614 may be a touch screen display. The electronic device 600 can additionally include a storage device (e.g., a drive unit) 616, a signal generation device 618 (e.g., a speaker), a network interface device 620, one or more cameras 628, and one or more sensors 630 such as, for example, a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors such as those described herein. The electronic device 600 can further include an output controller, such as, for example, a serial (e.g., universal serial bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection, for communicating with or controlling one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0089] The memory device 616 may include a non-transitory machine-readable medium 622 storing one or more sets of data structures or instructions 624 (e.g., software) that embody or are utilized by any one or more of the techniques or functions described herein. The instructions 624 may also be fully or at least partially present within the memory 604 and / or within the hardware processor 602 during execution thereof by the electronic device 600. Although the machine-readable medium 622 is shown as a single medium, the term “machine-readable medium” may include a single medium or a plurality of media (e.g., a centralized or distributed database, and / or associated caches and servers) configured to store one or more instructions 624.

[0090] The term “machine-readable medium” may include any medium that can store, encode, or carry instructions for execution by the electronic device 600 to cause the electronic device 600 to perform any one or more of the techniques of the present disclosure, or that can store, encode, or carry data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory, as well as optical and magnetic media. Specific examples of machine-readable media may include, for example, non-volatile memory such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices, magnetic disks such as internal hard disks and removable disks, magneto-optical disks, random access memory (RAM), as well as CD-ROM and DVD-ROM disks.

[0091] Command 624 can further be transmitted or received on a communication network using a transmission medium via a network interface device that utilizes any one of several wireless local area network (WLAN) transfer protocols or an SPI or CAN bus. Examples of communication networks can include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a cellular phone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network. Communication on the network can include, for example, one or more different protocols such as the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard family known as Wi-Fi (registered trademark), the IEEE 802.16 standard family known as WiMax (registered trademark), the IEEE 802.16.4 standard family, the long term evolution (LTE) standard family, the universal mobile telecommunications system (UMTS) standard family, a peer-to-peer (P2P) network, a next generation (NG) / sixth generation (6G) standard, and the like. In one example, network interface device 620 can include one or more physical jacks (e.g., Ethernet (registered trademark), coaxial, or telephone jacks) or one or more antennas for connecting to transmission medium 626.

[0092] Note that the term "circuit" as used herein refers to, and includes as part of, an electronic circuit, a logic circuit, a processor (shared, dedicated, or group), and / or a memory (shared, dedicated, or group), an application specific integrated circuit (ASIC), a field programmable device (FPD) (e.g., a field programmable gate array (FPGA), a programmable logic device (PLD), a complex programmable logic device (CPLD), a high-capacity PLD (HCPLD), a structured ASIC, or a programmable system on a chip), a digital signal processor (DSP), etc. configured to provide the recited functionality. In some embodiments, the circuit can provide at least a portion of the recited functionality by executing one or more software or firmware programs. The term "circuit" can also refer to a combination of one or more hardware elements (or a combination of circuits used in an electrical or electronic system) and program code used to execute the functionality of the program code. In these embodiments, the combination of the hardware elements and the program code can be referred to as a particular type of circuit.

[0093] The term "processor circuit" or "processor" as used herein therefore refers to, and includes as part of, a circuit capable of sequentially and automatically performing a sequence of arithmetic or logical operations, or of recording, storing, and / or transferring digital data. The term "processor circuit" or "processor" can refer to one or more application processors, one or more baseband processors, a physical central processing unit (CPU), a single-core or multi-core processor, and / or any other device capable of executing computer-executable instructions, such as program code, software modules, and / or functional processes, or of operating in some other manner.

[0094] Camera 628 can sense light of at least one or more wavelengths emitted by the LED. Camera 628 may include an optical system (e.g., at least one camera lens) capable of collecting reflected light of the illumination reflected from and / or emitted by the illuminated area. The camera lens can direct the reflected light onto a multi-pixel sensor (also referred to as a light sensor) to form an image on the multi-pixel sensor.

[0095] Processor 602 can control and drive the LED via one or more drivers. For example, processor 602 may optionally control one or more LEDs in the LED array independently of one or more other LEDs in the LED array to illuminate the area as specified.

[0096] In addition, sensor 630 may be incorporated into camera 628 and / or light source 610. Sensor 630 can sense visible light and / or infrared light, and in addition to receiving the reflected light from the LED, may further sense ambient light and / or fluctuations / flicker of the ambient light. The sensor may have one or more segments (capable of sensing the same wavelength / wavelength range or different wavelengths / wavelength ranges) similar to the LED array.

[0097] FIG. 9 shows an example of an illumination system according to some embodiments. As described above, some of the elements shown in illumination system 700 may not be present, while other additional elements may be arranged within illumination system 700. Illumination system 700 may include a controller 702 that controls illumination using a pixel array 710 including a plurality of individual pixels 712.

[0098] In some embodiments, some or all of the components described as controller 702 may be disposed on a backplane, such as a complementary metal oxide semiconductor (CMOS) backplane. Controller 702 can be coupled to or include one or more processors 704. The processor 704 can receive image data (in frame units) via an interface, process the image data, and control generator 706a. For example, it can control an analog signal or PWM duty cycle and / or turn-on time for generating an image indicated by the image data in illumination system 700.

[0099] Controller 702 may further include a frame buffer 708. The frame buffer 708 can store one or more images before one or more processors 704 and can also store instructions for execution by one or more processors 704.

[0100] Generator 706a can be controlled by processor 704 and can generate a drive signal according to an instruction. Generator 706a can be connected to a driver 706b for driving pixel array 710 so that pixel 712 provides light of a desired intensity.

[0101] Each pixel 712 may include one or more LEDs 714. The LEDs 714 can be of different colors and can be controlled individually or in groups. As shown, each pixel 712 can include a PWM switch and a current source for each pixel 712 or LED 714. Pixel 712 can be driven by driver 706b. A signal from generator 706a can open and close the switch according to the value of the signal. A signal corresponding to the intensity of light can cause the current source to generate current to generate light of the corresponding intensity in pixel 712.

[0102] Illumination system 700 may further include a power supply 720. In some embodiments, power supply 720 can be a battery that generates power for controller 702.

[0103] Figure 10 shows an example of a hardware configuration for implementing the above-disclosed subject matter according to some embodiments. In particular, the hardware configuration 800 may include an LED die 802 that includes an (one or more) LED array, and a backplane such as, for example, a CMOS backplane 804. The LED die 802 can be coupled to the CMOS backplane 804 by one or more interconnects 810, and the interconnects 810 can provide for signal transmission between the LED die 802 and the CMOS backplane 804. The interconnects 810 can have one or more solder bump joints, one or more copper pillar bump joints, other types of interconnects known in the art, or some combination thereof.

[0104] The LED die 802 may include circuitry for implementing the above-described LED array. In particular, the LED die 802 may include a plurality of LEDs. The LED die 802 can include a shared active layer and a shared substrate for the LED array, whereby the LED array can be a monolithic LED array. Each LED of the LED array can include an individual segmented active layer and / or substrate. In some embodiments, the LED die 802 may further include switches and current sources for driving the LED array as described above. In other embodiments, the switches and current sources may be included in the CMOS backplane 804. The LEDs can be micro-LEDs or LEDs larger than micro-LEDs.

[0105] The CMOS backplane 804 may include circuitry for implementing a control module. The CMOS backplane 804 can utilize the interconnects 810 to provide drive signals and intensity-related signals to the LED array, and cause the LED array to generate light according to the signals and intensity.

[0106] The hardware configuration 800 may further include a printed circuit board (PCB) 806. The PCB 806 may include circuits for implementing the various functions described herein. The PCB 806 may be coupled to the CMOS backplane 804. For example, the PCB 806 may be coupled to the CMOS backplane 804 via one or more wire bonds 812. The PCB 806 and the CMOS backplane 804 may exchange, among other signals, image data, power, and / or feedback via the coupling.

[0107] As shown, the LED and the circuit supporting the LED array can be packaged and can include a submount or printed circuit board for powering and controlling light generation by the LED. The PCB supporting the LED array may include electrical vias, heat sinks, ground planes, electrical traces, and flip chips or other mounting systems. The submount or PCB may be formed of any suitable material, such as ceramic, silicon, aluminum, etc. If the submount material is conductive, an insulating layer may be formed on the substrate material, and a metal electrode pattern may be formed on the insulating layer for contact with the micro-LED array. The submount may act as a mechanical support, provide an electrical interface between the electrodes on the LED array and the power supply, and may also provide a heat sink function.

[0108] Generally, various applications can be supported by an LED array. Such applications can include stand-alone applications for providing general illumination (e.g., inside or outside a room or vehicle) or for providing a specific image. In addition to devices such as lighting fixtures, projectors, mobile devices, etc., the system can be used to provide AR and VR-based applications. Visualization systems such as VR and AR systems are becoming increasingly common across a number of fields such as entertainment, education, healthcare, and business. To provide AR / VR to the user, various types of devices can be used, including headsets, glasses, and projectors. Such AR / VR systems can include components similar to those described above, particularly, a micro LED array, a display or screen (which may include a touch screen element), a micro LED array controller, sensors, and a controller. The AR / VR components may be arranged within a single structure, or one or more of the illustrated components may be mounted separately and connected via wired or wireless communication. Power and user data can be provided to the controller. User data input can include information provided by voice commands, tactile feedback, eye or pupil position identification, or a connected keyboard, mouse, or game controller. The sensors can include cameras, depth sensors, voice sensors, accelerometers, two-axis or three-axis gyroscopes, and other types of motion and / or environment / wearer sensors that provide user input data. Other sensors can include, but are not limited to, barometric pressure, stress sensors, temperature sensors, or any other suitable sensors for local or remote environmental monitoring. In some embodiments, the control input can include detected touches or taps, gesture inputs, or control based on the headset or display position. As another example, based on one or more measurement signals from one or more gyroscopes or position sensors that measure translational or rotational motion, the estimated position of the AR / VR system relative to an initial position can be determined.

[0109] In some embodiments, the controller may control individual micro LEDs or one or more groups of LEDs to display content (AR / VR and / or non-AR / VR) to the user while controlling other LEDs and sensors used in gaze tracking to adjust the displayed content. The content display LEDs are designed to emit light within the visible band (about 400 nm to 780 nm), while the LEDs used for tracking may be designed to emit light within the IR band (about 780 nm to 2,200 nm). In some embodiments, the tracking LEDs and the content LEDs may operate simultaneously. In some embodiments, the content LEDs may be deactivated, and thus, the tracking LEDs may be controlled to emit tracking light during time periods when no content is being displayed to the user. The AR / VR system may incorporate an optical system and / or an AR / VR display as described above, for example, to couple the light emitted by the LED array onto the AR / VR display.

[0110] In some embodiments, the AR / VR controller may use data from sensors, integrate the measurement signals received from the accelerometer over time to estimate a velocity vector, and integrate the velocity vector over time to determine an estimated position of a reference point for the AR / VR system. In other embodiments, the reference point used to describe the position of the AR / VR system may be based on a depth sensor, a camera positioning view, or an optical flow field. Based on changes in the position, orientation, or movement of the AR / VR system, the system controller may send an image or command to the light emitting array controller. Changes or modifications to the image or command may also be made by user data input or automatic data input.

[0111] Generally, in a VR system, a display can present a view of a scene, such as a 3D scene, to a user. The user can move within the scene, for example, by changing the position of the user's head or walking. The VR system can detect the user's movement and change the view of the scene to match the movement. For example, when the user rotates the user's head, the system can present a view of the scene where the viewing direction changes to match the user's gaze. Thus, the VR system can simulate the presence of the user within a 3D scene. Also, the VR system can receive tactile input from, for example, a wearable position sensor and optionally provide tactile feedback to the user.

[0112] On the other hand, in an AR system, the display can incorporate elements from the user's surroundings into the view of the scene. For example, the AR system can add text captions and / or visual elements to the view of the user's surroundings. For example, a retailer can use an AR system to show a user how furniture would look in a room of the user's house by incorporating a visualization of the furniture on a captured image of the user's surroundings. As the user moves around the user's room, the visualization takes the user's movement into account and changes the visualization of the furniture to match the movement. For example, the AR system can position a virtual chair within the room. The user can stand in front of the position of the virtual chair within the room and view the front side of the chair. The user can move to the area behind the position of the virtual chair within the room and view the back side of the chair. Thus, the AR system can add elements to the dynamic view of the user's surroundings.

[0113] Figure 11 shows a block diagram of an example of a system according to some embodiments. System 900 may provide AR / VR functionality using micro LEDs. System 900 may include a wearable housing 912, such as a headset or goggles. The housing 912 can mechanically support and house the elements detailed below. In some examples, one or more of the elements detailed below may be separate from the wearable housing 912 and can be included in one or more additional housings that can be coupled to the wearable housing 912 wirelessly and / or via a wired connection. For example, a separate housing can reduce the weight of the wearable goggles, such as by including a battery, a radio, and other elements. The housing 912 can include one or more batteries 914 that can power any or all of the elements detailed below. The housing 12 can include circuitry that can be electrically coupled to an external power source, such as a wall outlet, to recharge the battery 914. The housing 912 can include one or more radios 916 for wireless communication with a server or network via a suitable protocol, such as WiFi.

[0114] System 900 can include one or more sensors 918, such as, for example, optical sensors, audio sensors, tactile sensors, thermal sensors, gyro sensors, time-of-flight sensors, triangulation-based sensors, and others. In some examples, one or more of the sensors can sense the location, position, and / or orientation of the user. In some examples, one or more of the sensors 918 can generate a sensor signal in response to the sensed location, position, and / or orientation. The sensor signal can include sensor data corresponding to the sensed location, position, and / or orientation. For example, the sensor data can include a surrounding depth map. In some examples, such as for an AR system, one or more of the sensors 918 can capture a real-time video image of the surroundings proximate to the user.

[0115] System 900 can include one or more video generation processors 920. The one or more video generation processors 920 can receive scene data representing a 3D scene from a server and / or a storage medium, such as a set of position coordinates for objects within a scene or a depth map of the scene. This data can be received from the server and / or the storage medium. The one or more video generation processors 920 can receive one or more sensor signals from the one or more sensors 918. In response to the scene data representing the surroundings and at least one sensor signal representing the location and / or orientation of the user relative to the surroundings, the one or more video generation processors 920 can generate at least one video signal corresponding to a view of the scene. In some examples, the one or more video generation processors 920 can generate two video signals, one for each eye of the user, representing views of the scene from the viewpoints of the user's left and right eyes respectively. In some examples, the one or more video generation processors 920 can generate three or more video signals and combine them to provide one video signal for both eyes, two video signals for both eyes, or other combinations.

[0116] System 900 can include one or more light sources 922 that can provide light to a display of the system 900. Suitable light sources 922 can include, for example, the micro LEDs described above. The one or more light sources 922 can include light generating elements having different colors or wavelengths. For example, the light source can include a red light emitting diode that can emit red light, a green light emitting diode that can emit green light, and a blue light emitting diode that can emit blue light. The red, green, and blue lights are combined in specific ratios to generate suitable colors that are visually perceptible within the visible portion of the electromagnetic spectrum.

[0117] System 900 can include one or more modulators 924. The modulator 924 can be implemented in one of at least two configurations. In a first configuration, the modulator 924 can include a circuit that can directly modulate a light source 922. For example, the light source 922 can include an array of light-emitting diodes, and the modulator 924 can directly modulate the power, voltage, and / or current directed to each light-emitting diode in the array to form modulated light. The modulation can be performed in an analog manner and / or a digital manner. In some examples, the light source 922 can include an array of red light-emitting diodes, an array of green light-emitting diodes, and an array of blue light-emitting diodes, and the modulator 924 can directly modulate the red light-emitting diodes, the green light-emitting diodes, and the blue light-emitting diodes to form modulated light for generating a specified image.

[0118] In a second configuration, the modulator 924 can include a modulation panel, such as a liquid crystal panel. The light source 922 can generate uniform illumination or substantially uniform illumination to illuminate the modulation panel. The modulation panel can include pixels. Each pixel can form modulated light by selectively attenuating a respective portion of the modulation panel area in response to an electrical modulation signal. In some examples, the modulator 924 can include a plurality of modulation panels that can modulate different colors of light. For example, the modulator 924 can include a red modulation panel that can attenuate red light from a red light source, such as a red light-emitting diode, a green modulation panel that can attenuate green light from a green light source, such as a green light-emitting diode, and a blue modulation panel that can attenuate blue light from a blue light source, such as a blue light-emitting diode.

[0119] In an example of a second configuration, the modulator 924 can receive uniform white light or nearly uniform white light from a white light source such as a white light emitting diode. The modulation panel can include a wavelength selection filter on each pixel of the modulation panel. The panel pixels can be arranged in groups (e.g., three or four groups, etc.), and each group can form a pixel of a color image. For example, each group can include panel pixels having a red color filter, panel pixels having a green color filter, and panel pixels having a blue color filter. Other suitable configurations can also be used.

[0120] System 900 can include one or more modulation processors 926 that can receive a video signal from, for example, one or more video generation processors 920 and, in response, can generate an electrical modulation signal. In a configuration where the modulator 924 directly modulates the light source 922, the electrical modulation signal can drive the modulator 924. In a configuration where the modulator 924 includes a modulation panel, the electrical modulation signal can drive the modulation panel.

[0121] System 900 can include one or more beam combiners 928 (also known as beam splitters 928) that can combine light beams of different colors to form a single multi - color beam. In a configuration where the light source 922 can include a plurality of light emitting diodes of different colors, system 900 can include one or more wavelength - sensitive (e.g., dichroic) beam combiners 928 that can combine light of different colors to form a single multi - color beam.

[0122] System 900 can direct the modulated light towards the viewer's eyes in at least one of two configurations. In a first configuration, System 900 can function as a projector and can include a suitable projection optical system 930 capable of projecting the modulated light onto one or more screens 932. The screen 932 can be placed at a suitable distance from the user's eyes. System 900 can optionally include one or more lenses 934 capable of placing a virtual image of the screen 932 at a suitable distance from the eyes, such as a near focal distance, for example, 500 mm, 750 mm, or another suitable distance. In some examples, System 900 can include a single screen 932 and can direct the modulated light towards both of the user's eyes. In some examples, System 900 can include two screens 932 and can direct the modulated light from each screen 932 towards each of the user's eyes. In some examples, System 900 can include three or more screens 932. In a second configuration, System 900 can direct the modulated light directly towards one or both eyes of the viewer. For example, the projection optical system 930 can form an image on the retina of the user's eye, or can form an image on each of the retinas of the user's two eyes.

[0123] In some configurations of the AR system, System 900 can include at least a partially transparent display such that the user can see through the display to the user's surroundings. In such a configuration, the AR system can generate modulated light corresponding to an augmentation of the surroundings rather than the surroundings themselves. For example, in the case where a retailer shows a chair, the AR system can direct modulated light corresponding to the chair but not to the rest of the room towards the screen or towards the user's eyes.

[0124] FIG. 12 shows an example of a method for manufacturing a lighting device according to some embodiments. Not all of the processes need to be performed in method 1000, and / or additional processes may exist. The processes may be performed in an order different from that shown in FIG. 12.

[0125] In process 1002, a temporary substrate is attached to an initial structure including a sapphire substrate and an epitaxial layer (including an n-type semiconductor layer, a p-type semiconductor layer, and an active region). If a TCO layer is deposited on the initial structure, the temporary substrate is attached to the TCO layer.

[0126] In process 1004, the sapphire substrate is etched or otherwise removed, and the n-type semiconductor layer is etched so that the remaining epitaxial layer has a thickness significantly smaller than the thickness of the initial structure.

[0127] In process 1006, the epitaxial layer is formed into trapezoidal pixels by etching.

[0128] In process 1008, an oxide layer is deposited on the pixels, and then the oxide layer is etched so as to expose the n-type semiconductor layer at the top of the pixels and the temporary substrate or the TCO layer.

[0129] In process 1010, a metal seed layer and a metal plating are deposited on the oxide layer and the opening, and the metal plating is etched to electrically insulate portions thereof. Another oxide layer is deposited on the metal plating, the opening is etched to expose a part of the metal plating, and a bonding layer is deposited on the opening to provide a bonding pad that contacts the exposed metal plating portion.

[0130] In process 1012, the resulting structure is hybridized by attaching a monolithic structure to the bonding pad.

[0131] In process 1014, the temporary substrate is removed from the hybrid structure.

[0132] In Process 1016, if it does not already exist, a periodic nanostructure is patterned on the TCO layer that can be deposited after removal of the temporary substrate.

[0133] Here, only specific features of the system and method are illustrated and described, but numerous changes and modifications will occur to those skilled in the art. Accordingly, it should be understood that the appended claims are intended to cover all such changes and modifications. The method processes may be performed substantially simultaneously or in a different order.

[0134] Embodiments

[0135] Various embodiments are listed below. It should be understood that the embodiments listed below can be combined with all aspects and other embodiments in accordance with the scope of the present invention.

[0136] Embodiment (a). A light-emitting diode (LED) die, which is a first light-emitting stack on a second light-emitting stack, wherein the first light-emitting stack has a first n-type layer on a first tunnel junction, the first tunnel junction on a first p-type layer, and the first p-type layer on a first light-emitting active region, and the second light-emitting stack has a second n-type layer in contact with the first light-emitting active region and on a second light-emitting active region, and the second light-emitting active region on a second p-type layer, a first light-emitting stack on a second light-emitting stack, and a metal contact on the second light-emitting stack and extending to the first light-emitting stack.

[0137] Embodiment (b). The LED die of embodiment (a), wherein the metal contact has one or more of a cathode layer or an anode layer.

[0138] Embodiment (c). The LED die of embodiments (a) to (b), wherein a single voltage source is used to pass a forward current through the first light-emitting stack and the second light-emitting stack in parallel.

[0139] Embodiment (d). The LED die of Embodiments (a) to (c) further having a submount.

[0140] Embodiment (e). The first n-type layer, the second n-type layer, and the third n-type layer each independently have one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), and indium aluminum nitride (InAlN), etc. The LED die of Embodiments (a) to (d).

[0141] Embodiment (f). The first n-type layer, the second n-type layer, and the third n-type layer have gallium nitride (GaN). The LED die of Embodiments (a) to (e).

[0142] Embodiment (g). The cathode layer and the anode layer each independently have one or more of aluminum (Al) or silver (Ag). The LED die of Embodiments (a) to (f).

[0143] Embodiment (h). The LED die of Embodiments (a) to (g) further having a dielectric layer on the LED die.

[0144] Embodiment (i). The LED die of Embodiments (a) to (h) further having a bonding metal layer.

[0145] Embodiment (j). The bonding metal layer has one or more of titanium (Ti) and gold (Au). The LED die of Embodiments (a) to (i).

[0146] Embodiment (k). One or more of the first light-emitting active region and the second light-emitting active region emit green light. The LED die of Embodiments (a) to (j).

[0147] Embodiment (l). A method of manufacturing a light-emitting diode (LED) die, comprising epitaxially growing a first light-emitting stack and a second light-emitting stack on an epitaxial wafer, wherein the first light-emitting stack has a first n-type layer on a first tunnel junction, the first tunnel junction on a first p-type layer, and the first p-type layer on a first light-emitting active region, and the second light-emitting stack has a second n-type layer in contact with the first light-emitting active region and on a second light-emitting active region, and the second light-emitting active region on a second p-type layer, and forming at least one metal contact on the second light-emitting stack.

[0148] Embodiment (m). The method of embodiment (l), wherein the metal contact has one or more of a cathode layer or an anode layer.

[0149] Embodiment (n). The method of embodiments (l) to (m), wherein a single voltage source is used to pass a forward current through the first light-emitting stack and the second light-emitting stack in parallel.

[0150] Embodiment (o). The method of embodiments (l) to (n), further comprising mounting the LED die on a submount.

[0151] Embodiment (p). The method of embodiments (l) to (o), further comprising forming a dielectric layer on the LED die.

[0152] Embodiment (q). The method of embodiments (l) to (p), further comprising forming a bonding metal layer.

[0153] Embodiment (r). The method of embodiments (l) to (q), wherein one or more of the first light-emitting active region and the second light-emitting active region emit green light.

[0154] Embodiments. A method of manufacturing a thin film flip chip (TFFC) die, comprising forming two p-n junctions in sequence on an epitaxial wafer to form an epitaxial stack, the epitaxial stack having at least one n-type layer and at least one p-type layer, a light-emitting active region being embedded between the at least one n-type layer and the at least one p-type layer, dry etching the epitaxial stack to form two vias with different depths, conformally depositing a dielectric layer in the two vias, removing a part of the dielectric layer to form a contact opening, depositing one or more of an anode layer and a cathode layer in the contact opening, depositing a bonding metal layer on one or more of the anode layer or the cathode layer, singulating the thin film flip chip (TFFC) die, and bonding the thin film flip chip (TFFC) die to a submount.

[0155] Embodiment (t). The epitaxial stack has a first light-emitting stack and a second light-emitting stack, the first light-emitting stack having a first n-type layer on a first tunnel junction, the first tunnel junction on a first p-type layer, and the first p-type layer on a first light-emitting active region, the second light-emitting stack having a second n-type layer in contact with the first light-emitting active region and on a second light-emitting active region, and the second light-emitting active region on a second p-type layer, the method of Embodiment (s).

[0156] The use of the terms "a", "an", and "the" and similar references in the context of describing the materials and methods herein (in particular, in the context of the following claims) should be construed to cover both the singular and the plural unless otherwise indicated herein or clearly contradicted by the context. The recitation of a range of values herein is merely intended to serve as a shorthand way of referring individually to each separate value falling within the range, and each separate value is incorporated herein as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by the context. The use of any and all examples, or illustrative language (e.g., "such as") provided herein is merely intended to better illuminate the materials and methods and is not intended to limit the scope otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0157] Herein, in order to describe various elements, reference may be made throughout this specification to terms such as first, second, third, etc., but those elements should not be limited by these terms. These terms may be used to distinguish one element from another.

[0158] Throughout this specification, references to a layer, region, or substrate as being "on" or extending "onto" another element can mean that it can be directly on or extend directly onto the other element, or intervening elements may also be present. When an element is referred to as being "directly on" or extending "directly onto" another element, intervening elements may be absent. Also, when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element and / or connected or coupled to the other element through one or more intervening elements. When an element is referred to as being "directly connected to" or "directly coupled to" another element, no intervening elements are present between that element and the other element. It is understood that these terms are intended to encompass that element in different orientations in addition to the orientation shown in the figures.

[0159] Relative terms such as, for example, "under", "above", "upper", "lower", "horizontal", or "vertical" may be used herein to describe the relationship of one element, section, or region to another element, section, or region as shown in the figures. It is understood that these terms are intended to encompass the device in different orientations in addition to the orientation shown in the figures.

[0160] Throughout this specification, references to "one embodiment", "a particular embodiment", "one or more embodiments", or "an embodiment" mean that a particular mechanism, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, phrases such as, for example, "in one or more embodiments", "in a particular embodiment", "in one embodiment", or "in an embodiment" appearing in various places in this specification are not necessarily referring to the same embodiment of the present disclosure. In one or more embodiments, the particular mechanisms, structures, materials, or characteristics are combined in any suitable manner.

[0161] The disclosure herein has been described with reference to particular embodiments, but it should be understood that these embodiments merely illustrate the principles and applications of the disclosure. It will be apparent to those skilled in the art that various changes and modifications can be made to the methods and apparatuses of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure is intended to cover changes and modifications within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting diode (LED) die, which is a first light-emitting stack on a second light-emitting stack, wherein the first light-emitting stack has a first n-type layer on a first tunnel junction, the first tunnel junction on a first p-type layer, and the first p-type layer on a first light-emitting active region, the second light-emitting stack has a second n-type layer in contact with the first light-emitting active region and on a second light-emitting active region, and the second light-emitting active region on a second p-type layer, and is the first light-emitting stack on the second light-emitting stack, and a metal contact on the second light-emitting stack and extending to the first light-emitting stack, wherein the LED die has the above components.

2. The LED die according to claim 1, wherein the metal contact has one or more of a cathode layer or an anode layer.

3. The LED die according to claim 1, wherein a single voltage source is used to allow a forward current to pass through the first light-emitting stack and the second light-emitting stack in parallel.

4. The LED die according to claim 1, further comprising a submount.

5. The LED die according to claim 1, wherein the first n-type layer, the second n-type layer, and the third n-type layer independently have one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), and indium aluminum nitride (InAlN).

6. The LED die according to claim 5, wherein the first n-type layer, the second n-type layer, and the third n-type layer have gallium nitride (GaN).

7. The LED die according to claim 2, wherein the cathode layer and the anode layer independently have one or more of aluminum (Al) or silver (Ag).

8. The LED die according to claim 2, further comprising a dielectric layer on the LED die.

9. The LED die according to claim 2, further comprising a bonding metal layer.

10. The LED die according to claim 9, wherein the bonding metal layer has one or more of titanium (Ti) and gold (Au).

11. One or more of the first light-emitting active region and the second light-emitting active region emit green light, the LED die according to claim 1.

12. A method of manufacturing a light-emitting diode (LED) die, comprising: Epitaxially growing a first light-emitting stack and a second light-emitting stack on an epitaxial wafer, the first light-emitting stack having a first n-type layer on a first tunnel junction, the first tunnel junction on a first p-type layer, and the first p-type layer on a first light-emitting active region, the second light-emitting stack having a second n-type layer in contact with the first light-emitting active region and on a second light-emitting active region, and a second p-type layer on the second light-emitting active region; Forming at least one metal contact on the second light-emitting stack; A method having the above.

13. The method according to claim 12, wherein the metal contact has one or more of a cathode layer or an anode layer.

14. Using a single voltage source to pass a forward current through the first light-emitting stack and the second light-emitting stack in parallel, the method according to claim 12.

15. The method according to claim 12, further comprising mounting the LED die on a submount.

16. The method according to claim 13, further comprising forming a dielectric layer on the LED die.

17. The method according to claim 13, further comprising forming a bonding metal layer.

18. One or more of the first light-emitting active region and the second light-emitting active region emit green light, the method according to claim 12.

19. A method of manufacturing a thin film flip chip (TFFC) die, comprising: Sequentially forming two p-n junctions on an epitaxial wafer to form an epitaxial stack, the epitaxial stack having at least one n-type layer and at least one p-type layer, and a light-emitting active region embedded between the at least one n-type layer and the at least one p-type layer; Dry etching the epitaxial stack to form two vias with different depths; Conformally depositing a dielectric layer in the two vias; Removing a part of the dielectric layer to form a contact opening; Depositing one or more of an anode layer and a cathode layer in the contact opening; Depositing a bonding metal layer on one or more of the anode layer or the cathode layer; Scribing the thin film flip chip (TFFC) die, Bonding the thin film flip chip (TFFC) die to a submount, A method comprising the steps of.

20. The method according to claim 19, wherein the epitaxial stack has a first light emitting stack and a second light emitting stack, the first light emitting stack having a first n-type layer on a first tunnel junction, the first tunnel junction on a first p-type layer, and the first p-type layer on a first light emitting active region, and the second light emitting stack having a second n-type layer in contact with the first light emitting active region and on a second light emitting active region, and the second light emitting active region on a second p-type layer.

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