Memory chip, chip stack structure, and memory

Abstract

The present disclosure provides a memory chip, a chip stack structure, and a memory. For the memory chip, n through-hole sets in a first region and n through-hole sets in a second region are symmetric with respect to a first axis, n through-hole sets in a third region and n through-hole sets in a fourth region are symmetric with respect to the first axis, n through-hole sets in the first region and n through-hole sets in the fourth region are symmetric with respect to a second axis. For each through-hole set, a first through-hole and a second through-hole are symmetric with respect to a third axis, a third through-hole and a fourth through-hole are symmetric with respect to the third axis, and the first through-hole and the fourth through-hole are symmetric with respect to a fourth axis.

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims the priority of a Chinese patent application with an application number of 202310680606.3 and an invention title of "Memory Chip, Chip Stack Structure and Memory", which was filed with the Chinese Patent Office on June 8, 2023, and all of its content is incorporated herein by reference.

[0002] This application relates to, but is not limited to, memory chips, chip stack structures and memories.

Background Art

[0003] With the development of integrated circuit technology, the manufacturing process of semiconductor devices has made remarkable progress. However, in recent years, the development of two - dimensional semiconductor technology has faced various problems such as physical limitations, limitations of current development technology, and limitations of memory electron density. In such a situation, in order to solve the difficulties faced by two - dimensional semiconductor devices and reduce the production cost of unit memory cells, a bonding process can be used to stack multiple chips to form a three - dimensional semiconductor device. However, for three - dimensional semiconductor devices, the connection structure between different chips still has problems such as large parasitic capacitance and large parasitic resistance, which affect the signal transmission quality.

Summary of the Invention

[0004] This disclosure provides a memory chip, a chip stack structure and a memory.

[0005] The technical solution of this disclosure is realized as follows.

[0006] In a first aspect, an embodiment of the present disclosure provides a memory chip, the memory chip including 2×2 regions distributed in an array along an active surface of the memory chip, each of the regions being penetrated by n sets of through holes, where n is a natural number, the n sets of through holes in the first region and the n sets of through holes in the second region being symmetric with respect to a first axis, the n sets of through holes in the third region and the n sets of through holes in the fourth region being symmetric with respect to the first axis, the n sets of through holes in the first region and the n sets of through holes in the fourth region being symmetric with respect to a second axis, the first axis and the second axis both being located on the active surface, the first axis and the second axis being perpendicular to each other and intersecting at the center of the active surface, for each set of through holes, each set of through holes including 2×2 through holes distributed in an array, the first through hole and the second through hole being symmetric with respect to a third axis, the third through hole and the fourth through hole being symmetric with respect to the third axis, the first through hole and the fourth through hole being symmetric with respect to a fourth axis, the third axis and the fourth axis both being located on the active surface, the third axis and the fourth axis being perpendicular to each other and intersecting at the center of the set of through holes, the first axis and the third axis of each set of through holes both being parallel to a first side of the memory chip, the second axis and the fourth axis of each set of through holes both being parallel to a second side of the memory chip.

[0007] In some embodiments, the n first through holes in the first region and the n second through holes in the second region are symmetric with respect to the first axis, the n third through holes in the third region and the n fourth through holes in the fourth region are symmetric with respect to the first axis, and the n first through holes in the first region and the n fourth through holes in the fourth region are symmetric with respect to the second axis.

[0008] In some embodiments, the n second through-holes in the first region and the n first through-holes in the second region are symmetric with respect to the first axis, the n fourth through-holes in the third region and the n third through-holes in the fourth region are symmetric with respect to the first axis, and the n second through-holes in the first region and the n third through-holes in the fourth region are symmetric with respect to the second axis.

[0009] In some embodiments, the n third through-holes in the first region and the n fourth through-holes in the second region are symmetric with respect to the first axis, the n first through-holes in the third region and the n second through-holes in the fourth region are symmetric with respect to the first axis, and the n third through-holes in the first region and the n second through-holes in the fourth region are symmetric with respect to the second axis.

[0010] In some embodiments, the n fourth through-holes in the first region and the n third through-holes in the second region are symmetric with respect to the first axis, the n second through-holes in the third region and the n first through-holes in the fourth region are symmetric with respect to the first axis, and the n fourth through-holes in the first region and the n first through-holes in the fourth region are symmetric with respect to the second axis.

[0011] In some embodiments, any one of the through-holes penetrates the memory chip along a direction perpendicular to the active surface, and different through-holes in the same memory chip are electrically insulated from each other.

[0012] In some embodiments, the memory chip further includes 4n first driving circuits, the 4n through-holes are connected to the 4n first driving circuits in a one-to-one correspondence, and only one through-hole in each through-hole group is connected to the first driving circuit.

[0013] In some embodiments, the memory chip further includes a positioning structure, and by being located in a reference region, the positioning structure indicates the location of the reference region, and the reference region is one of the 2×2 regions.

[0014] In a second aspect, an embodiment of the present disclosure provides a chip stacking structure, the chip stacking structure includes at least one stacking unit, and each stacking unit includes a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip sequentially stacked along a third direction, the third direction is perpendicular to the active surface of each memory chip, the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all memory chips described in the first aspect, the first memory chip and the second memory chip are stacked face to face, the second memory chip and the third memory chip are stacked back to back, and the third memory chip and the fourth memory chip are stacked face to face.

[0015] In some embodiments, a first region in the first memory chip, a second region in the second memory chip, a third region in the third memory chip, and a fourth region in the fourth memory chip are aligned along the third direction, a second region in the first memory chip, a first region in the second memory chip, a fourth region in the third memory chip, and a third region in the fourth memory chip are aligned along the third direction, a third region in the first memory chip, a fourth region in the second memory chip, a first region in the third memory chip, and a second region in the fourth memory chip are aligned along the third direction, and a fourth region in the first memory chip, a third region in the second memory chip, a second region in the third memory chip, and a first region in the fourth memory chip are aligned along the third direction.

[0016] In some embodiments, the n first vias in the first region in the first memory chip, the n second vias in the second region in the second memory chip, the n third vias in the third region in the third memory chip, and the n fourth vias in the fourth region in the fourth memory chip are aligned along a third direction, the n second vias in the first region in the first memory chip, the n first vias in the second region in the second memory chip, the n fourth vias in the third region in the third memory chip, and the n third vias in the fourth region in the fourth memory chip are aligned along the third direction, the n third vias in the first region in the first memory chip, the n fourth vias in the second region in the second memory chip, the n first vias in the third region in the third memory chip, and the n second vias in the fourth region in the fourth memory chip are aligned along the third direction, and the n fourth vias in the first region in the first memory chip, the n third vias in the second region in the second memory chip, the n second vias in the third region in the third memory chip, and the n first vias in the fourth region in the fourth memory chip are aligned along the third direction.

[0017] In some embodiments, the n first vias in the second region of the first memory chip, the n second vias in the first region of the second memory chip, the n third vias in the fourth region of the third memory chip, and the n fourth vias in the third region of the fourth memory chip are aligned along a third direction; the n second vias in the second region of the first memory chip, the n first vias in the first region of the second memory chip, the n fourth vias in the fourth region of the third memory chip, and the n third vias in the third region of the fourth memory chip are aligned along the third direction; the n third vias in the second region of the first memory chip, the n fourth vias in the first region of the second memory chip, the n first vias in the fourth region of the third memory chip, and the n second vias in the third region of the fourth memory chip are aligned along the third direction; and the n fourth vias in the second region of the first memory chip, the n third vias in the first region of the second memory chip, the n second vias in the fourth region of the third memory chip, and the n first vias in the third region of the fourth memory chip are aligned along the third direction.

[0018] In some embodiments, the n first vias in the third region in the first memory chip, the n second vias in the fourth region in the second memory chip, the n third vias in the first region in the third memory chip, and the n fourth vias in the second region in the fourth memory chip are aligned along a third direction; the n second vias in the third region in the first memory chip, the n first vias in the fourth region in the second memory chip, the n fourth vias in the first region in the third memory chip, and the n third vias in the second region in the fourth memory chip are aligned along the third direction; the n third vias in the third region in the first memory chip, the n fourth vias in the fourth region in the second memory chip, the n first vias in the first region in the third memory chip, and the n second vias in the second region in the fourth memory chip are aligned along the third direction; and the n fourth vias in the third region in the first memory chip, the n third vias in the fourth region in the second memory chip, the n second vias in the first region in the third memory chip, and the n first vias in the second region in the fourth memory chip are aligned along the third direction.

[0019] In some embodiments, the n first vias in the fourth region of the first memory chip, the n second vias in the third region of the second memory chip, the n third vias in the second region of the third memory chip, and the n fourth vias in the first region of the fourth memory chip are aligned along the third direction. The n second vias in the fourth region of the first memory chip, the n first vias in the third region of the second memory chip, the n fourth vias in the second region of the third memory chip, and the n third vias in the first region of the fourth memory chip are aligned along the third direction. The n third vias in the fourth region of the first memory chip, the n fourth vias in the third region of the second memory chip, the n first vias in the second region of the third memory chip, and the n second vias in the first region of the fourth memory chip are aligned along the third direction. The n fourth vias in the fourth region of the first memory chip, the n third vias in the third region of the second memory chip, the n second vias in the second region of the third memory chip, and the n first vias in the first region of the fourth memory chip are aligned along the third direction.

[0020] In some embodiments, the first region in the first memory chip, the fourth region in the second memory chip, the third region in the third memory chip, and the second region in the fourth memory chip are aligned along the third direction. The second region in the first memory chip, the third region in the second memory chip, the fourth region in the third memory chip, and the first region in the fourth memory chip are aligned along the first direction. The third region in the first memory chip, the second region in the second memory chip, the first region in the third memory chip, and the fourth region in the fourth memory chip are aligned along the third direction. The fourth region in the first memory chip, the first region in the second memory chip, the second region in the third memory chip, and the third region in the fourth memory chip are aligned along the third direction.

[0021] In some embodiments, the n first vias in the first region of the first memory chip, the n fourth vias in the fourth region of the second memory chip, the n third vias in the third region of the third memory chip, and the n second vias in the second region of the fourth memory chip are aligned along a third direction; the n second vias in the first region of the first memory chip, the n third vias in the fourth region of the second memory chip, the n fourth vias in the third region of the third memory chip, and the n first vias in the second region of the fourth memory chip are aligned along the third direction; the n third vias in the first region of the first memory chip, the n second vias in the fourth region of the second memory chip, the n first vias in the third region of the third memory chip, and the n fourth vias in the second region of the fourth memory chip are aligned along the third direction; and the n fourth vias in the first region of the first memory chip, the n first vias in the fourth region of the second memory chip, the n second vias in the third region of the third memory chip, and the n third vias in the second region of the fourth memory chip are aligned along the third direction.

[0022] In some embodiments, the n first vias in the second region in the first memory chip, the n fourth vias in the third region in the second memory chip, the n third vias in the fourth region in the third memory chip, and the n second vias in the first region in the fourth memory chip are aligned along a third direction; the n second vias in the second region in the first memory chip, the n third vias in the third region in the second memory chip, the n fourth vias in the fourth region in the third memory chip, and the n first vias in the first region in the fourth memory chip are aligned along the third direction; the n third vias in the second region in the first memory chip, the n second vias in the third region in the second memory chip, the n first vias in the fourth region in the third memory chip, and the n fourth vias in the first region in the fourth memory chip are aligned along the third direction; and the n fourth vias in the second region in the first memory chip, the n first vias in the third region in the second memory chip, the n second vias in the fourth region in the third memory chip, and the n third vias in the first region in the fourth memory chip are aligned along the third direction.

[0023] In some embodiments, the n first vias in the third region in the first memory chip, the n fourth vias in the second region in the second memory chip, the n third vias in the first region in the third memory chip, and the n second vias in the fourth region in the fourth memory chip are aligned along the third direction. The n second vias in the third region in the first memory chip, the n third vias in the second region in the second memory chip, the n fourth vias in the first region in the third memory chip, and the n first vias in the fourth region in the fourth memory chip are aligned along the third direction. The n third vias in the third region in the first memory chip, the n second vias in the second region in the second memory chip, the n first vias in the first region in the third memory chip, and the n fourth vias in the fourth region in the fourth memory chip are aligned along the third direction. The n fourth vias in the third region in the first memory chip, the n first vias in the second region in the second memory chip, the n second vias in the first region in the third memory chip, and the n third vias in the fourth region in the fourth memory chip are aligned along the third direction.

[0024] In some embodiments, the n first vias in the fourth region of the first memory chip, the n fourth vias in the first region of the second memory chip, the n third vias in the second region of the third memory chip, and the n second vias in the third region of the fourth memory chip are aligned along a third direction; the n second vias in the fourth region of the first memory chip, the n third vias in the first region of the second memory chip, the n fourth vias in the second region of the third memory chip, and the n first vias in the third region of the fourth memory chip are aligned along the third direction; the n third vias in the fourth region of the first memory chip, the n second vias in the first region of the second memory chip, the n first vias in the second region of the third memory chip, and the n fourth vias in the third region of the fourth memory chip are aligned along the third direction; and the n fourth vias in the fourth region of the first memory chip, the n first vias in the first region of the second memory chip, the n second vias in the second region of the third memory chip, and the n third vias in the third region of the fourth memory chip are aligned along the third direction.

[0025] In some embodiments, for two memory chips connected face-to-face, the vias aligned along their third direction are connected by a hybrid bonding structure; for two memory chips connected back-to-back, the vias aligned along their third direction are connected by conductive bumps; alternatively, for two memory chips connected face-to-face or two memory chips connected back-to-back, the vias aligned along their third direction are all connected by a hybrid bonding structure; or, for two memory chips connected face-to-face or two memory chips connected back-to-back, the vias aligned along their third direction are all connected by conductive bumps.

[0026] In some embodiments, each of the memory chips further includes 4n first driving circuits. In each of the memory chips, the 4n first driving circuits are connected in a one-to-one correspondence to the first ends of the 4n first vias, and the first ends of the first vias are located on the active surface of the memory chip.

[0027] In some embodiments, the chip stack structure further includes a logic chip. The first of the stacking units is stacked on the logic chip along a third direction, and the other stacking units are sequentially stacked on the previous stacking unit along the third direction. The logic chip includes 16n fifth vias and 16n second driving circuits. 4n of the fifth vias are in an aligned state in a one-to-one correspondence with 4n of the first vias in the first memory chip along the third direction. 4n of the fifth vias are in an aligned state in a one-to-one correspondence with 4n of the second vias in the first memory chip along the third direction. 4n of the fifth vias are in an aligned state in a one-to-one correspondence with 4n of the third vias in the first memory chip along the third direction. 4n of the fifth vias are in an aligned state in a one-to-one correspondence with 4n of the fourth vias in the first memory chip along the third direction. The 16n second driving circuits are connected in a one-to-one correspondence to the first ends of the 16n fifth vias, and the first ends of the fifth vias are located on the active surface of the logic chip.

[0028] In some embodiments, the chip stack structure further includes 16n electrical paths. When the chip stack structure includes m of the stacking units, one fifth via, m of the first vias, m of the second vias, m of the third vias, and m of the fourth vias that are in an aligned state along a third direction are connected to form one of the electrical paths, where m is a positive integer.

[0029] In a third aspect, an embodiment of the present disclosure provides a memory, and the memory includes the chip stack structure described in the second aspect.

[0030] Embodiments of the present disclosure provide a memory chip, a chip stack structure, and a memory. By reducing the number of settings of the drive circuit and the data selector, not only the parasitic capacitance is reduced, but also the chip stack structure formed by the memory chip realizes a signal rotation transmission effect through a direct connection structure of through holes, and the parasitic resistance is also reduced.

Brief Description of the Drawings

[0031]

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Embodiments for Carrying Out the Invention

[0032] In the following, with reference to the drawings in the embodiments of the present disclosure, the technical solutions in the embodiments of the present disclosure will be further described clearly and completely. Understandably, the specific embodiments described in this specification are only intended to explain the related applications and do not limit the present application. Furthermore, it should be noted that for the sake of convenience of explanation, only the parts related to the related applications are illustrated in the drawings. Unless otherwise specified, all technical terms and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used in the present disclosure are only adopted to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following, the description of "some embodiments" describes a subset of all possible embodiments. Understandably, "some embodiments" can be the same subset or a different subset of all possible embodiments and can be combined with each other without contradiction. Furthermore, it should be noted that the terms such as "first / second / third" in the embodiments of the present disclosure do not limit a specific order but distinguish similar objects. Understandably, since "first / second / third" can be converted to a specific order or the order of front and back when appropriate, the embodiments of the present disclosure described in this specification can be executed in an order other than those illustrated or described in this specification.

[0033] Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Low-voltage and low-power DDR (LPDDR: Low Power DDR).

[0034] Before describing the embodiments of the present disclosure, three directions related to the three-dimensional structure in the plane in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, the Y-axis, and the Z-axis direction (not related to the embodiments of the present disclosure). The semiconductor chip may include an upper surface (active surface) located on the front side and a bottom surface (non-active surface) located on the back side opposite to the front side. On the premise of not considering the flatness of the upper surface and the bottom surface, the direction intersecting (for example, perpendicular) the upper surface and the bottom surface of the semiconductor chip is defined as the third direction. On the active surface of the semiconductor chip, two intersecting directions, that is, the first direction and the second direction are defined, and the direction of the active surface of the semiconductor chip can be determined based on the first direction and the second direction. In the embodiments of the present disclosure, the first direction and the second direction may be perpendicular to each other. In other embodiments, the first direction and the second direction may not be perpendicular.

[0035] In particular, the drawings shown in the present disclosure do not mean actual drawings of specific microelectronic devices or their components, but are merely ideal representations for explaining exemplary embodiments. Therefore, the drawings are not necessarily to scale.

[0036] In the following, each embodiment of the present disclosure will be described in detail with reference to the drawings.

[0037] In one embodiment, a memory chip is provided. The memory chip includes a plurality of through holes (also called silicon through holes, which realize signal transmission between different chips), and all the through holes can be located at any position. In particular, every four through holes can be functionally regarded as a set of through holes, and there is no limitation on the position of each of these four through holes.

[0038] In a specific embodiment, eight of the above-mentioned memory chips and one logic chip are stacked to form a 3D memory device. At the same time, the through holes of each of the eight memory chips are aligned along the third direction, and nine through holes in an aligned state along the third direction are connected to form a single electrical path. Referring to FIG. 1, FIG. 1 is a schematic diagram of signal transmission of a chip stacking structure. As shown in FIG. 1, this chip stacking structure includes memory chips 0 to 7 and a logic chip. In FIG. 1, each memory chip shows only four through holes D0 to D3. These four through holes D0 to D3 belong to the same set of through holes. At this time, the through holes D0 in the eight memory chips and one logic chip are all aligned to form a single electrical path, and the through holes D1 in the eight memory chips and one logic chip are all aligned to form a single electrical path... The same applies to the other through holes.

[0039] At the same time, each memory chip and logic chip is further provided with a plurality of drive circuits (in FIG. 1, only one drive circuit is shown by a dashed frame, and the other drive circuits are not framed). Each through hole is connected to one drive circuit. Each memory chip is further provided with a plurality of data selectors (for example, mux0 to 7 in FIG. 1). Each set of through holes corresponds to one data selector. That is, all the through holes of one set of through holes are connected to the data ports of the data selector via their respective drive circuits. That is, the data selector can select which signal transmitted from which through hole is output inside the memory chip, or to which through hole the signal output from the memory chip is output.

[0040] In the entire memory device, these eight memory chips are divided into four channels (CH0, CH1, CH4, CH5) for management. Memory chip 0 and memory chip 4 belong to channel CH0, memory chip 1 and memory chip 5 belong to channel CH1, memory chip 2 and memory chip 6 belong to channel CH4, and memory chip 3 and memory chip 7 belong to channel CH5. Correspondingly, the input / output signal I / O_CH0 of channel CH0 is transmitted through an electrical path consisting of "via hole D0 in the logic chip, via hole D0 in memory chip 0 - via hole D0 in memory chip 1 - via hole D0 in memory chip 2 - via hole D0 in memory chip 3 - via hole D0 in memory chip 4 - via hole D0 in memory chip 5 - via hole D0 in memory chip 6 - via hole D0 in memory chip 7". However, the selection signals of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 are both SEL_C0. That is, the input / output signal I / O_CH0 can enter memory chip 0 and memory chip 4 via the above electrical path, and the signal output process can be understood similarly.

[0041] As can be seen from the above, the memory chip 0 may obtain signals only from the through-hole D0, the memory chip 1 may obtain signals only from the through-hole D1, ……, that is, each memory chip may obtain signals only from one through-hole within one set of through-holes. It should be noted that different memory chips may need to obtain signals from different through-holes. However, during the manufacturing process, all memory chips need to be designed with exactly the same structure (this can maximize cost and labor reduction), so all through-holes within the memory chips need to design corresponding drive structures and data selectors to achieve structural consistency. Furthermore, when adopting the chip stacking structure shown in FIG. 1, one drive circuit corresponds to each through-hole. In the operation process of this chip stacking structure, it is necessary to operate all drive circuits within all memory chips in the same channel, which results in a large load and large parasitic capacitance, seriously affecting the performance of the chips therein, limiting the transmission efficiency, increasing power consumption, and also limiting the number of chip stacks within the three-dimensional solid device.

[0042] In another embodiment, referring to FIG. 2, FIG. 2 is a signal transmission schematic diagram of another chip stacking structure. Only some through-holes (D0 to D3) are shown in FIG. 2, and the others are omitted. In FIG. 4, the identifiers of the through-holes aligned along the third direction are the same. As shown in FIG. 2, the chip stacking structure similarly includes eight memory chips and one logic chip aligned along the third direction. However, the through-holes within each memory chip are rotationally connected to different through-holes at different positions within another memory chip, realizing an overall spiral upward connection. That is, the input / output signal I / O_CH0 of the channel CH0 is transmitted through "the through-hole D0 within the logic chip, the through-hole D1 within the memory chip 0 - the through-hole D2 within the memory chip 1 - the through-hole D3 within the memory chip 2 - the through-hole D0 within the memory chip 3 - the through-hole D1 within the memory chip 4 - the through-hole D2 within the memory chip 5 - the through-hole D3 within the memory chip 6 - the through-hole D0 within the memory chip 7", and the same applies to other signals.

[0043] In this way, memory chip 0 acquires input / output signal I / O_CH0 through the output end of via hole D0 in the logic chip, memory chip 1 acquires input / output signal I / O_CH1 through the input end of via hole D0 in memory chip 0, memory chip 2 acquires input / output signal I / O_CH4 through the input end of via hole D0 in memory chip 1, and memory chip 3 can output input / output signal I / O_CH5 through the input end of via hole D0 in memory chip 2... For each memory chip, only one via hole in each set of via holes needs to be connected to the drive circuit, and there is no need to provide a data selector. By reducing the number of devices, the parasitic capacitance can be reduced. However, compared with the direct connection structure of via holes in Fig. 1, the process of rotational connection of via holes in Fig. 2 (for example, via hole D0 of memory chip 0 is connected to via hole D1 of memory chip 1) is more complex. Specifically, a horizontal interconnection structure (one of them is indicated by a star mark in Fig. 2) needs to be provided between adjacent via holes in each memory chip in Fig. 2. The signal interconnection structure may be a metal interconnection line, a via hole, etc. In order to achieve the rotational connection of via holes, the input signal must first be transmitted upward from via hole D0 to below via hole D0 of memory chip 1 (without transmitting to via hole D0 of memory chip 1), and then be transmitted horizontally from below via hole D0 of memory chip 1 to via hole D1 of memory chip 1. Therefore, when the input signal is sequentially transmitted from via hole D0 of the logic chip to via hole D0 of memory chip 4, it also needs to pass through the interconnection structure in each memory chip, and the same is true for the output signal. Therefore, inevitably, the parasitic resistance increases and the complexity of the process also increases.

[0044] In particular, in the chip stacking structures of Fig. 1 and Fig. 2, all chips have their active surfaces facing upward. That is, different memory chips are stacked back-to-front, and both the memory chip and the logic chip are stacked back-to-front. That is, the non-active surface of the upper chip contacts the active surface of the lower chip.

[0045] In summary, on the one hand, in the chip stacking structure of FIG. 1, since there are too many drive circuits and data selectors, the load and parasitic capacitance become large. In the chip stacking structure of FIG. 2, the parasitic resistance becomes large due to the rotational structure. On the other hand, there are certain problems in the stacking structures of FIGS. 1 to 2, and they cannot be directly applied to the face-to-face stacking structure. Specifically, one method for further realizing the face-to-face chip stacking structure is to use two sets of masks to create two different types of chips, namely, a chip with the active surface facing upward and a chip with the active surface facing downward. This method has a high process complexity and the cost cannot be controlled. Another method is to create another set of vias and connect both sets of vias to the same drive circuit in the memory chip. However, in this case, the internal wiring of the memory chip becomes complex, not only increasing the process complexity but also increasing the power consumption.

[0046] Therefore, the embodiments of the present disclosure propose a memory chip and a chip stacking structure that not only have small parasitic capacitance and parasitic resistance but also can realize the face-to-face stacking method.

[0047] In still another embodiment of the present disclosure, referring to FIG. 3, FIG. 3 is a schematic diagram showing the configuration of a memory chip 10 according to an embodiment of the present disclosure. The memory chip 10 includes 2×2 regions distributed in an array along the active surface of the memory chip 10. In the following description, the 2×2 regions are respectively referred to as a first region 11, a second region 12, a third region 13, and a fourth region 14. Also, with respect to the active surface of the memory chip 10, a first axis AA' and a second axis BB' exist on the active surface of the memory chip 10. The first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center of the active surface. The first axis AA' is parallel to one side of the memory chip 10, and the second axis BB' is parallel to the other side of the memory chip 10. In particular, FIG. 3 can be regarded as a cross-sectional view along the active surface of the memory chip 10.

[0048] Referring to FIG. 3, each region is penetrated by n sets of through holes 20 (only one set of through holes in each region of FIG. 3 is shown, and the others are omitted), where n is a natural number. The n sets of through holes 20 in the first region 11 and the n sets of through holes 20 in the second region 12 are symmetric with respect to the first axis AA'. The n sets of through holes 20 in the third region 13 and the n sets of through holes 20 in the fourth region 14 are symmetric with respect to the first axis AA'. The n sets of through holes 20 in the first region 11 and the n sets of through holes 20 in the fourth region 14 are symmetric with respect to the second axis BB'. Here, the "n sets of through holes 20 in the first region 11" specifically means "n sets of through holes 20 that penetrate the first region 11 in the memory chip 10", and the same applies to other expressions.

[0049] It should be noted that the number and position of the sets of through holes 20 in each region can be adjusted according to the actual situation. However, the number of sets of through holes in each of the four regions must be the same, and it is necessary to follow the above symmetric distribution rule. FIG. 4 shows three sets of through holes 20 for each region. Of course, the number of sets of through holes 20 can also be 2, 4, 5, 6, 7... etc., and in other cases, it can be understood adaptively.

[0050] In the embodiments of the present disclosure, the number of through holes in each set of through holes 20 is 4. Following the same distribution rule, hereinafter, any one set of through holes 20 will be described as an example.

[0051] Referring to FIG. 3, for each set of through holes 20 (for example, the set of through holes 20 in the first region 11), there are a third axis CC' and a fourth axis DD' in each set of through holes 20. Both the third axis CC' and the fourth axis DD' are located on the active surface. The third axis CC' is parallel to the first axis AA', the fourth axis DD' is parallel to the second axis BB', and the third axis CC' and the fourth axis DD' are perpendicular to each other and intersect at the center of the set of through holes 20.

[0052] For each through-hole group 20, each said through-hole group 20 includes 2×2 through-holes distributed in an array. The first through-hole D0 and the second through-hole D1 are symmetric with respect to the third axis CC'. The third through-hole D2 and the fourth through-hole D3 are symmetric with respect to the third axis CC'. The first through-hole D0 and the fourth through-hole D3 are symmetric with respect to the fourth axis DD'.

[0053] It should be noted that each through-hole group 20 has its own third axis CC' and fourth axis DD'. That is, the first through-hole D0 and the second through-hole D1 of the same through-hole group 20 are symmetric with respect to the third axis CC' of this through-hole group 20. The third through-hole D2 and the fourth through-hole D3 of the same through-hole group 20 are symmetric with respect to the third axis CC' of this through-hole group 20. The first through-hole D0 and the fourth through-hole D3 of the same through-hole group 20 are symmetric with respect to the fourth axis DD' of this through-hole group 20. The second through-hole D1 and the third through-hole D2 of the same through-hole group 20 are symmetric with respect to the fourth axis DD' of this through-hole group 20.

[0054] It should be noted that the through-hole can also be called a Through Silicon Via (TSV). Specifically, it is a vertical interconnection structure that penetrates a silicon wafer / memory chip.

[0055] It should be noted that the above memory chip 10 can be specifically applied to DRAM, SDRAM, DDR, LPDDR... etc.

[0056] It should be noted that any one of the through-holes penetrates the memory chip along a direction perpendicular to the active surface (i.e., the third direction), and different through-holes in the same memory chip 10 are electrically insulated.

[0057] It should be noted that in the embodiments of the present disclosure, there is no restriction on the numbering order of each region and the numbering order of the through-holes in each through-hole group 20.

[0058] In some embodiments, referring to FIG. 3 or FIG. 4, the n first through holes D0 in the first region 11 and the n second through holes D1 in the second region 12 are symmetric with respect to the first axis AA', the n third through holes D2 in the third region 13 and the n fourth through holes D3 in the fourth region 14 are symmetric with respect to the first axis AA', the n first through holes D0 in the first region 11 and the n fourth through holes D3 in the fourth region 14 are symmetric with respect to the second axis BB', and the n second through holes D1 in the second region 12 and the n third through holes D2 in the third region 13 are symmetric with respect to the second axis BB'.

[0059] In some embodiments, referring to FIG. 3 or FIG. 4, the n second through holes D1 in the first region 11 and the n first through holes D0 in the second region 12 are symmetric with respect to the first axis AA', the n fourth through holes D3 in the third region 13 and the n third through holes D2 in the fourth region 14 are symmetric with respect to the first axis AA', the n second through holes D1 in the first region 11 and the n third through holes D2 in the fourth region 14 are symmetric with respect to the second axis BB', and the n first through holes D0 in the second region 12 and the n fourth through holes D3 in the third region 13 are symmetric with respect to the second axis BB'.

[0060] In some embodiments, referring to FIG. 3 or FIG. 4, the n third through holes D2 in the first region 11 and the n fourth through holes D3 in the second region 12 are symmetric with respect to the first axis AA', the n first through holes D0 in the third region 13 and the n second through holes D1 in the fourth region 14 are symmetric with respect to the first axis AA', the n third through holes D2 in the first region 11 and the n second through holes D1 in the fourth region 14 are symmetric with respect to the first axis AA', and the n fourth through holes D3 in the second region 12 and the n first through holes D0 in the third region 13 are symmetric with respect to the second axis BB'.

[0061] In some embodiments, referring to FIG. 3 or FIG. 4, the n fourth through holes D3 in the first region 11 and the n third through holes D2 in the second region 12 are symmetric with respect to the first axis AA', the n second through holes D1 in the third region 13 and the n first through holes D0 in the fourth region 14 are symmetric with respect to the first axis AA', the n fourth through holes D3 in the first region 11 and the n first through holes D0 in the fourth region 14 are symmetric with respect to the second axis BB', and the n third through holes D2 in the second region 12 and the n second through holes D1 in the third region 13 are symmetric with respect to the second axis BB'.

[0062] In some embodiments, referring to FIG. 5, the memory chip 10 further includes 4n first drive circuits 30, and the 4n through holes are connected to the 4n first drive circuits 30 in a one-to-one correspondence, and only one through hole in each through hole group 20 is connected to the first drive circuit 30. That is, for each through hole group 20, only the signal transmitted through one of the through holes therein enters or is output from the inside of the chip.

[0063] In some embodiments, the memory chip 10 further includes a positioning structure (not shown), and by being located in the reference region, the positioning structure indicates the location of the reference region, where the reference region is one of the 2×2 regions (the first region, the second region, the third region, or the fourth region).

[0064] It should be noted that in the chip manufacturing process, it is necessary to manufacture a plurality of chips simultaneously. In order to distinguish different regions in the chip, it is necessary to create a positioning structure in the first region (which may also be the second region, the third region, or the fourth region) of each memory chip. However, in different chips, the same region needs to be selected as the reference region. Thereby, during subsequent assembly, the position of the reference region can be identified by the positioning structure, and at the same time, the positions of other regions can be determined in combination with the orientation of the active surface of the chip.

[0065] In addition, the memory chip 10 may include a plurality of positioning structures. Different positioning structures are located in different regions to indicate the absolute position of the location region. For example, the memory chip 10 may include four positioning structures, with one positioning structure distributed in each of the first region to the fourth region. Since the four positioning structures are different from each other, each region can be better identified. That is, the first region to the fourth region can all be regarded as reference regions.

[0066] In this way, the embodiments of the present disclosure provide a memory chip 10. The through holes in the memory chip 10 have special symmetry and can be directly applied to the front-to-front stacked structure without the need for two sets of masks or two sets of through holes. Also, only one through hole in each through hole group is connected to the driving circuit, eliminating the need to provide a data selector for through hole selection, and reducing the number of devices. Thereby, compared with the memory chip in FIG. 1, the parasitic capacitance is reduced, the circuit board area is saved, the chip manufacturing cost is reduced, and when the subsequent memory chip 10 forms a stacked structure, the parasitic resistance can be reduced compared with the memory chip in FIG. 2 (for specific reasons, refer to the following description).

[0067] In yet another embodiment of the present disclosure, referring to FIG. 6, FIG. 6 shows a chip stacking structure 40 according to an embodiment of the present disclosure. The chip stacking structure 40 includes at least one stacking unit. Each stacking unit includes a first memory chip 41, a second memory chip 42, a third memory chip 43, and a fourth memory chip 44 that are sequentially stacked along a third direction. The third direction is perpendicular to the active surface of each memory chip. The first memory chip 41, the second memory chip 42, the third memory chip 43, and the fourth memory chip 44 are all the aforementioned memory chips 10. The first memory chip 41 and the second memory chip 42 are stacked face to face, that is, the upper surface (i.e., the active surface) of the first memory chip 41 is adjacent to the upper surface of the second memory chip 42. The second memory chip 42 and the third memory chip 43 are stacked back to back, that is, the back surface (i.e., the non-active surface) of the second memory chip 42 is adjacent to the back surface of the third memory chip 43. The third memory chip 43 and the fourth memory chip 44 are stacked face to face, that is, the upper surface of the third memory chip 43 is adjacent to the upper surface of the fourth memory chip 44.

[0068] As one possibility, for two memory chips connected face to face, the through holes aligned along their third direction are connected by a hybrid bonding structure (also called Hyperbonding or bonding pillars). For two memory chips connected back to back, the through holes aligned along their third direction are connected by conductive bumps (also called UBumps or micro bumps).

[0069] As another possibility, for two memory chips connected face-to-face or two memory chips connected back-to-back, the through-holes aligned along the third direction of both are connected by a hybrid bonding structure. That is, the through-holes aligned along the third direction between two memory chips connected face-to-face are connected by a hybrid bonding structure, and the through-holes aligned along the third direction between two memory chips connected back-to-back are also connected by a hybrid bonding structure.

[0070] As yet another possibility, for two memory chips connected face-to-face or two memory chips connected back-to-back, the through-holes aligned along the third direction of both are connected by conductive bumps. That is, the through-holes aligned along the third direction between two memory chips connected face-to-face are connected by conductive bumps, and the through-holes aligned along the third direction between two memory chips connected back-to-back are also connected by conductive bumps.

[0071] It should be noted that compared with conductive bumps, the face-to-face connection using a hybrid bonding structure enhances the adhesion between adjacent memory chips and basically has no gap, so the height of the chip stacking structure can be significantly reduced, which is one of the advantages of face-to-face stacking. Of course, two memory chips connected back-to-back are also connected by a hybrid bonding structure, but their connection performance is weaker than that when connected face-to-face.

[0072] In a specific embodiment, referring to FIG. 7, the first region 11 in the first memory chip 41a, the second region 12 in the second memory chip 42a, the third region 13 in the third memory chip 43a, and the fourth region 14 in the fourth memory chip 44a are aligned along the third direction. The second region 12 in the first memory chip 41a, the first region 11 in the second memory chip 42a, the fourth region 14 in the third memory chip 43a, and the third region 13 in the fourth memory chip 44a are aligned along the third direction. The third region 13 in the first memory chip 41a, the fourth region 14 in the second memory chip 42a, the first region 11 in the third memory chip 43a, and the second region 12 in the fourth memory chip 44a are aligned along the third direction. The fourth region 14 in the first memory chip 41a, the third region 13 in the second memory chip 42a, the second region 12 in the third memory chip 43a, and the first region 11 in the fourth memory chip 44a are aligned along the third direction.

[0073] It should be noted that the memory chip may be divided into an upper bit transmission region and a lower bit transmission region, and the arrows in FIG. 7 are uniformly located in the upper bit transmission region of the memory chip.

[0074] That is, after providing the first memory chip 41a, not only is the second memory chip 42a provided on top of the first memory chip 41a face to face, but also the positions along the third direction of the upper bit transmission region in the second memory chip 42a and the lower bit transmission region in the first memory chip 41a are substantially the same. Then, the third memory chip 43a is provided on top of the second memory chip 42a back to back, and at the same time, the positions along the third direction of the upper bit transmission region in the third memory chip 43a and the upper bit transmission region in the second memory chip 42a are substantially the same, but the positions of the specific devices in these two memory chips do not overlap (specifically, they exhibit a mirror image relationship). Then, the fourth memory chip 44a is provided on top of the third memory chip 43a face to face, and at the same time, the positions along the third direction of the upper bit transmission region in the fourth memory chip 44a and the lower bit transmission region in the third memory chip 43a are substantially the same. Thereby, the first memory chip 41a, the second memory chip 42a, the third memory chip 43a, and the fourth memory chip 44a form a stacked unit.

[0075] Furthermore, it should be noted that the chip stack structure 40 may include a plurality of stacked units. Referring to FIG. 9, after forming the first stacked unit, the fifth memory chip 45a is provided back-to-back on top of the fourth memory chip 44a. The positions of the upper bit transmission regions in the fifth memory chip 45a and the fourth memory chip 44a along the third direction are substantially the same, but the positions of the specific devices in these two memory chips do not overlap (specifically, they exhibit a mirror image relationship). Thereafter, the sixth memory chip 46a is provided face-to-face on top of the fifth memory chip 45a. It is necessary to control the positions of the upper bit transmission region in the sixth memory chip 46a and the lower bit transmission region in the fifth memory chip 45a along the third direction to be substantially the same. Thereafter, the seventh memory chip 47a is provided back-to-back on top of the sixth memory chip 46a. At the same time, the positions of the upper bit transmission regions in the seventh memory chip 47a and the sixth memory chip 46a along the third direction are substantially the same, but the positions of the specific devices in these two memory chips do not overlap (specifically, they exhibit a mirror image relationship). Thereafter, it is provided face-to-face on top of the seventh memory chip 47a. At the same time, by making the positions of the upper bit transmission region in the eighth memory chip 48a and the lower bit transmission region in the seventh memory chip 47a along the third direction substantially the same, the fifth memory chip 45a, the sixth memory chip 46a, the seventh memory chip 47a, and the eighth memory chip 48a form one stacked unit. In other words, the fifth memory chip 45a of the second stacked unit can also be regarded as the first memory chip 41a of the first stacked unit, the sixth memory chip 46a of the second stacked unit can also be regarded as the second memory chip 42a of the first stacked unit, the seventh memory chip 47a of the second stacked unit can also be regarded as the third memory chip 43a of the first stacked unit, and the eighth memory chip 48a of the second stacked unit can also be regarded as the fourth memory chip 44a of the first stacked unit. Referring to FIG. 8, FIG. 8 is a schematic diagram of the active surface tiling of each chip of the stacked unit shown in FIG. 7. In particular, the four through holes penetrating with a dashed line in FIG. 7 are represented as the four through holes surrounded by a dashed line in FIG. 8.

[0076] On the one hand, referring to FIG. 8, each through hole in the first region 11 within the first memory chip 41a has the following positional characteristics.

[0077] (1) The n first through holes D0 in the first region 11 of the first memory chip 41a, the n second through holes D1 in the second region 12 of the second memory chip 42a, the n third through holes D2 in the third region 13 of the third memory chip 43a, and the n fourth through holes D3 in the fourth region 14 of the fourth memory chip 44a are aligned along the third direction.

[0078] (2) The n second through holes D1 in the first region 11 of the first memory chip 41a, the n first through holes D0 in the second region 12 of the second memory chip 42a, the n fourth through holes D3 in the third region 13 of the third memory chip 43a, and the n third through holes D2 in the fourth region 14 of the fourth memory chip 44a are aligned along the third direction.

[0079] (3) The n third through holes D2 in the first region 11 of the first memory chip 41a, the n fourth through holes D3 in the second region 12 of the second memory chip 42a, the n first through holes D0 in the third region 13 of the third memory chip 43a, and the n second through holes D1 in the fourth region 14 of the fourth memory chip 44a are aligned along the third direction.

[0080] (4) The n fourth through holes D3 in the first region 11 of the first memory chip 41a, the n third through holes D2 in the second region 12 of the second memory chip 42a, the n second through holes D1 in the third region 13 of the third memory chip 43a, and the n first through holes D0 in the fourth region 14 of the fourth memory chip 44a are aligned along the third direction.

[0081] In particular, in FIGS. 7 and 8, only one set of through holes in one region is shown as an example. Actually, there are multiple sets of through holes in each region, and the sets of through holes in different regions have the same alignment characteristics. The alignment situation of other through holes is not shown, and it can be understood adaptively with reference to FIGS. 7 and 8 in combination with the textual description.

[0082] On the other hand, each through-hole in the second region 12 of the first memory chip 41a has the following positional characteristics.

[0083] (1) The n first through-holes D0 in the second region 12 of the first memory chip 41a, the n second through-holes D1 in the first region 11 of the second memory chip 42a, the n third through-holes D2 in the fourth region 14 of the third memory chip 43a, and the n fourth through-holes D3 in the third region 13 of the fourth memory chip 44a are aligned along the third direction.

[0084] (2) The n second through-holes D1 in the second region 12 of the first memory chip 41a, the n first through-holes D0 in the first region 11 of the second memory chip 42a, the n fourth through-holes D3 in the fourth region 14 of the third memory chip 43a, and the n third through-holes D2 in the third region 13 of the fourth memory chip 44a are aligned along the third direction.

[0085] (3) The n third through-holes D2 in the second region 12 of the first memory chip 41a, the n fourth through-holes D3 in the first region 11 of the second memory chip 42a, the n first through-holes D0 in the fourth region 14 of the third memory chip 43a, and the n second through-holes D1 in the third region 13 of the fourth memory chip 44a are aligned along the third direction.

[0086] (4) The n fourth through-holes D3 in the second region 12 of the first memory chip 41a, the n third through-holes D2 in the first region 11 of the second memory chip 42a, the n second through-holes D1 in the fourth region 14 of the third memory chip 43a, and the n first through-holes D0 in the third region 13 of the fourth memory chip 44a are aligned along the third direction.

[0087] On the other hand, each through-hole in the third region 13 of the first memory chip 41a has the following positional characteristics.

[0088] (1) The n first through-holes D0 in the third region 13 of the first memory chip 41a, the n second through-holes D1 in the fourth region 14 of the second memory chip 42a, the n third through-holes D2 in the first region 11 of the third memory chip 43a, and the n fourth through-holes D3 in the second region 12 of the fourth memory chip 44a are aligned along the third direction.

[0089] (2) The n second through-holes D1 in the third region 13 of the first memory chip 41a, the n first through-holes D0 in the fourth region 14 of the second memory chip 42a, the n fourth through-holes D3 in the first region 11 of the third memory chip 43a, and the n third through-holes D2 in the second region 12 of the fourth memory chip 44a are aligned along the third direction.

[0090] (3) The n third through-holes D2 in the third region 13 of the first memory chip 41a, the n fourth through-holes D3 in the fourth region 14 of the second memory chip 42a, the n first through-holes D0 in the first region 11 of the third memory chip 43a, and the n second through-holes D1 in the second region 12 of the fourth memory chip 44a are aligned along the third direction.

[0091] (4) The n fourth through-holes D3 in the third region 13 of the first memory chip 41a, the n third through-holes D2 in the fourth region 14 of the second memory chip 42a, the n second through-holes D1 in the first region 11 of the third memory chip 43a, and the n first through-holes D0 in the second region 12 of the fourth memory chip 44a are aligned along the third direction.

[0092] Furthermore, on the other hand, each through-hole in the fourth region 14 of the first memory chip 41a has the following positional characteristics.

[0093] (1) The n first through-holes D0 in the fourth region 14 of the first memory chip 41a, the n second through-holes D1 in the third region 13 of the second memory chip 42a, the n third through-holes D2 in the second region 12 of the third memory chip 43a, and the n fourth through-holes D3 in the first region 11 of the fourth memory chip 44a are aligned along the third direction.

[0094] (2) The n second through-holes D1 in the fourth region 14 of the first memory chip 41a, the n first through-holes D0 in the third region 13 of the second memory chip 42a, the n fourth through-holes D3 in the second region 12 of the third memory chip 43a, and the n third through-holes D2 in the first region 11 of the fourth memory chip 44a are aligned along the third direction.

[0095] (3) The n third through-holes D2 in the fourth region 14 of the first memory chip 41a, the n fourth through-holes D3 in the third region 13 of the second memory chip 42a, the n first through-holes D0 in the second region 12 of the third memory chip 43a, and the n second through-holes D1 in the first region 11 of the fourth memory chip 44a are aligned along the third direction.

[0096] (4) The n fourth through-holes D3 in the fourth region 14 of the first memory chip 41a, the n third through-holes D2 in the third region 13 of the second memory chip 42a, the n second through-holes D1 in the second region 12 of the third memory chip 43a, and the n first through-holes D0 in the first region 11 of the fourth memory chip 44a are aligned along the third direction.

[0097] Thus, FIGS. 7 to 9 show a specific chip stacking method, and FIGS. 10 to 12 show another specific chip stacking method, which will be specifically described below.

[0098] Referring to FIG. 10, the first region 11 in the first memory chip 41b, the fourth region 14 in the second memory chip 42b, the third region 13 in the third memory chip 43b, and the second region 12 in the fourth memory chip 44b are aligned along the third direction, the second region 12 in the first memory chip 41b, the third region 13 in the second memory chip 42b, the fourth region 14 in the third memory chip 43b, and the first region 11 in the fourth memory chip 44b are aligned along the first direction, The third region 13 in the first memory chip 41b, the second region 12 in the second memory chip 42b, the first region 11 in the third memory chip 43b, and the fourth region 14 in the fourth memory chip 44b are aligned along the third direction. The fourth region 14 in the first memory chip 41b, the first region 11 in the second memory chip 42b, the second region 12 in the third memory chip 43b, and the third region 13 in the fourth memory chip 44b are aligned along the third direction.

[0099] Similarly, the arrows in FIG. 10 are uniformly located in the upper bit transmission region of the memory chip.

[0100] That is, the positions along the third direction of the upper bit transmission region in the second memory chip 42b and the upper bit transmission region in the first memory chip 41b are substantially the same, but the positions of the specific devices in these two memory chips do not overlap (specifically, they exhibit a mirror image relationship). The positions along the third direction of the upper bit transmission region in the third memory chip 43b and the lower bit transmission region in the second memory chip 42b are substantially the same. The positions along the third direction of the upper bit transmission region in the fourth memory chip 44b and the upper bit transmission region in the third memory chip 43b are substantially the same, but the positions of the specific devices in these two memory chips do not overlap (specifically, they exhibit a mirror image relationship).

[0101] Similarly, the number of stacked units may also be plural. Referring to FIG. 12, after forming the first stacked unit, the fifth memory chip 45b to the eighth memory chip 48b are continuously stacked, and the positions along the third direction of the upper bit transmission region in the fifth memory chip 45b and the lower bit transmission region in the fourth memory chip 44b are substantially the same, and the positions along the third direction of the upper bit transmission region in the sixth memory chip 46b and the upper bit transmission region in the fifth memory chip 45b are substantially the same. However, the positions of the specific devices in these two memory chips do not overlap (specifically, they exhibit a mirror image relationship). The positions along the third direction of the upper bit transmission region in the seventh memory chip 47b and the lower bit transmission region in the sixth memory chip 46b are substantially the same, and the positions along the third direction of the upper bit transmission region in the eighth memory chip 48b and the upper bit transmission region in the seventh memory chip 47b are substantially the same. However, the positions of the specific devices in these two memory chips do not overlap (specifically, they exhibit a mirror image relationship).

[0102] Referring to FIG. 11, FIG. 11 is a schematic diagram of the active surface tiling of each chip of the stacked unit shown in FIG. 10. In particular, the four through holes penetrated by the broken line in FIG. 10 are represented as the four through holes surrounded by the broken line in FIG. 11.

[0103] On the one hand, referring to FIG. 11, each through hole in the first region 11 in the first memory chip 41b has the following position characteristics.

[0104] (1) The n first through holes D0 in the first region 11 in the first memory chip 41b, the n fourth through holes D3 in the fourth region 14 in the second memory chip 42b, the n third through holes D2 in the third region 13 in the third memory chip 43b, and the n second through holes D1 in the second region 12 in the fourth memory chip 44b are aligned along the third direction. (2) The n first through-holes D1 in the first region 11 of the first memory chip 41b, the n third through-holes D2 in the fourth region 14 of the second memory chip 42b, the n fourth through-holes D3 in the third region 13 of the third memory chip 43b, and the n first through-holes D0 in the second region 12 of the fourth memory chip 44b are aligned along the third direction. (3) The n third through-holes D2 in the first region 11 of the first memory chip 41b, the n first through-holes D1 in the fourth region 14 of the second memory chip 42b, the n first through-holes D0 in the third region 13 of the third memory chip 43b, and the n fourth through-holes D3 in the second region 12 of the fourth memory chip 44b are aligned along the third direction. (4) The n fourth through-holes D3 in the first region 11 of the first memory chip 41b, the n first through-holes D0 in the fourth region 14 of the second memory chip 42b, the n second through-holes D1 in the third region 13 of the third memory chip 43b, and the n third through-holes D2 in the second region 12 of the fourth memory chip 44b are aligned along the third direction.

[0105] In particular, in FIGS. 10 and 11, only one set of through-holes in one region is shown as an example. Actually, there are multiple sets of through-holes in each region, and different regions have similar alignment characteristics for the sets of through-holes. The alignment situations of other through-holes are not shown. With reference to FIGS. 10 and 11 in combination with the textual description, it can be adaptively understood.

[0106] On the other hand, each through-hole in the second region 12 of the first memory chip 41b has the following positional characteristics.

[0107] (1) The n first through-holes D0 in the second region 12 of the first memory chip 41b, the n fourth through-holes D3 in the third region 13 of the second memory chip 42b, the n third through-holes D2 in the fourth region 14 of the third memory chip 43b, and the n second through-holes D1 in the first region 11 of the fourth memory chip 44b are aligned along the third direction. (2) The n second vias D1 in the second region 12 of the first memory chip 41b, the n third vias D2 in the third region 13 of the second memory chip 42b, the n fourth vias D3 in the fourth region 14 of the third memory chip 43b, and the n first vias D0 in the first region 11 of the fourth memory chip 44b are aligned along the third direction. (3) The n third vias D2 in the second region 12 of the first memory chip 41b, the n second vias D1 in the third region 13 of the second memory chip 42b, the n first vias D0 in the fourth region 14 of the third memory chip 43b, and the n fourth vias D3 in the first region 11 of the fourth memory chip 44b are aligned along the third direction. (4) The n fourth vias D3 in the second region 12 of the first memory chip 41b, the n first vias D0 in the third region 13 of the second memory chip 42b, the n second vias D1 in the fourth region 14 of the third memory chip 43b, and the n third vias D2 in the first region 11 of the fourth memory chip 44b are aligned along the third direction.

[0108] On the other hand, each via in the third region 13 of the first memory chip 41b has the following positional characteristics.

[0109] (1) The n first vias D0 in the third region 13 of the first memory chip 41b, the n fourth vias D3 in the second region 12 of the second memory chip 42b, the n third vias D2 in the first region 11 of the third memory chip 43b, and the n second vias D1 in the fourth region 14 of the fourth memory chip 44b are aligned along the third direction. (2) The n second vias D1 in the third region 13 of the first memory chip 41b, the n third vias D2 in the second region 12 of the second memory chip 42b, the n fourth vias D3 in the first region 11 of the third memory chip 43b, and the n first vias D0 in the fourth region 14 of the fourth memory chip 44b are aligned along the third direction. (3) The n third through-holes D2 in the third region 13 of the first memory chip 41b, the n second through-holes D1 in the second region 12 of the second memory chip 42b, the n first through-holes D0 in the first region 11 of the third memory chip 43b, and the n fourth through-holes D3 in the fourth region 14 of the fourth memory chip 44b are aligned along the third direction. (4) The n fourth through-holes D3 in the third region 13 of the first memory chip 41b, the n first through-holes D0 in the second region 12 of the second memory chip 42b, the n second through-holes D1 in the first region 11 of the third memory chip 43b, and the n third through-holes D2 in the fourth region 14 of the fourth memory chip 44b are aligned along the third direction.

[0110] Furthermore, on the other hand, each through-hole in the fourth region 14 of the first memory chip 41b has the following positional characteristics.

[0111] (1) The n first through-holes D0 in the fourth region 14 of the first memory chip 41b, the n fourth through-holes D3 in the first region 11 of the second memory chip 42b, the n third through-holes D2 in the second region 12 of the third memory chip 43b, and the n second through-holes D1 in the third region 13 of the fourth memory chip 44b are aligned along the third direction. (2) The n second through-holes D1 in the fourth region 14 of the first memory chip 41b, the n third through-holes D2 in the first region 11 of the second memory chip 42b, the n fourth through-holes D3 in the second region 12 of the third memory chip 43b, and the n first through-holes D0 in the third region 13 of the fourth memory chip 44b are aligned along the third direction. (3) The n third through-holes D2 in the fourth region 14 of the first memory chip 41b, the n second through-holes D2 in the first region 11 of the second memory chip 42b, the n first through-holes D0 in the second region 12 of the third memory chip 43b, and the n fourth through-holes D3 in the third region 13 of the fourth memory chip 44b are aligned along the third direction. (4) The n fourth through-holes D3 in the fourth region 14 of the first memory chip 41b, the n first through-holes D0 in the first region 11 of the second memory chip 42b, the n second through-holes D1 in the second region 12 of the third memory chip 43b, and the n third through-holes D2 in the third region 13 of the fourth memory chip 44b are aligned along the third direction.

[0112] In this way, the chip stacking structures in FIGS. 10 to 12 also satisfy the usage requirements in the same manner.

[0113] In some embodiments, referring to FIGS. 13 and 14, FIGS. 13 and 14 are signal transmission schematic diagrams of the chip stacking structure 40. In particular, FIG. 13 is shown corresponding to the chip stacking structure shown in FIG. 7, and FIG. 14 is shown corresponding to the chip stacking structure shown in FIG. 10. In particular, in the following description, the first memory chip 41 can refer to the first memory chip 41a or the first memory chip 41b, and the same applies to other memory chips.

[0114] As shown in FIG. 13 or FIG. 14, each memory chip further includes 4n first drive circuits 30 (only one is shown for each memory chip in FIG. 13). In each memory chip, the 4n first drive circuits 30 are connected in a one-to-one correspondence to the first ends of the 4n first through-holes D0, where the first ends are located on the active surface of the memory chip.

[0115] That is, in any of the first memory chip 41, the second memory chip 42, the third memory chip 43, or the fourth memory chip 44, the first drive circuits 30 therein are all connected to the first through-holes D0. That is, the first memory chip 41, the second memory chip 42, the third memory chip 43, or the fourth memory chip 44 all adopt the same structure.

[0116] In some embodiments, referring to FIGS. 9 and 12, the chip stack structure 40 further includes a logic chip 50. The first said stacked unit is stacked on the logic chip 50 along the third direction, and the other said stacked units are sequentially stacked on the previous stacked unit along the third direction. Here, between the first memory chip and the logic chip 50, they are stacked back-to-front, or the first memory chip and the logic chip 50 are stacked back-to-back.

[0117] Referring to FIGS. 13 and 14, the logic chip 50 includes 16n fifth vias 502 and 16n second drive circuits 501.

[0118] For the 16n fifth vias 502, 4n of the fifth vias 502 are in a one-to-one corresponding alignment state with 4n first vias D0 in the first memory chip 41 along the third direction, 4n of the fifth vias 502 are in a one-to-one corresponding alignment state with 4n second vias D1 in the first memory chip 41 along the third direction, 4n of the fifth vias 502 are in a one-to-one corresponding alignment state with 4n third vias D2 in the first memory chip 41 along the third direction, and 4n of the fifth vias 502 are in a one-to-one corresponding alignment state with 4n fourth vias D3 in the first memory chip 41 along the third direction. The 16n second drive circuits 501 are connected to the first ends of the 16n fifth vias 502 in a one-to-one correspondence, and the first ends are located on the active surface of the logic chip 50.

[0119] That is, the logic chip 50 and the aforementioned memory chip 10 have the same installation positions of the vias, but each via in the logic chip 50 is connected to one drive circuit.

[0120] It should be noted that FIGS. 13 and 14 are abstract circuit schematic diagrams. The drive circuit is only provided adjacent to the via to which it is connected, and the connection relationship is not specifically depicted. It can be understood adaptively in combination with the textual description.

[0121] The chip stack structure 40 further includes 16n electrical vias, and one fifth through-hole 502, at least one first through-hole D0, at least one second through-hole D1, at least one third through-hole D2, and at least one fourth through-hole D3 that are aligned along the third direction are connected to form one electrical via.

[0122] It should be noted that when the chip stack structure 40 includes m stacked units, one fifth through-hole 502, m first through-holes D0, m second through-holes D1, m third through-holes D2, and m fourth through-holes D3 that are aligned along the third direction are connected to form one electrical via, and m is a positive integer.

[0123] In this way, referring to FIG. 13 or FIG. 14, the input / output signal I / O_CH0 of channel CH0 is transmitted through "the through-hole 502 in the logic chip, the through-hole D0 in the memory chip 0 - the through-hole D1 in the memory chip 1 - the through-hole D2 in the memory chip 2 - the through-hole D3 in the memory chip 3 - the through-hole D0 in the memory chip 4 - the through-hole D1 in the memory chip 5 - the through-hole D2 in the memory chip 6 - the through-hole D3 in the memory chip 7", and the same applies to other signals. At this time, the first memory chip 41 acquires the input / output signal I / O_CH0 through the input end of its own through-hole D0, the second memory chip 42 acquires the input / output signal I / O_CH1 through the input end of its own through-hole D0, the third memory chip 43 acquires the input / output signal I / O_CH4 through the input end of its own through-hole D0, and the fourth memory chip 44 acquires the input / output signal I / O_CH5 through the input end of its own through-hole D0... In other words, referring to FIG. 13 or FIG. 14, for the chip stack structure 40, from a physical perspective, the through-holes therein are still in a direct connection structure, but from the absolute position of the through-holes on the active surface, the through-holes therein can be regarded as a functional rotation structure. That is, a signal transmission effect as shown in FIG. 2 (i.e., a rotation transmission effect such as through-hole D0 - through-hole D1 - through-hole D2 - through-hole D3...) is realized by the physical direct connection structure. Briefly speaking, compared with the fact that the horizontal interconnection structure is essential in the physical spiral structure of the chip stack structure in FIG. 2, the chip stack structure in FIG. 13 or FIG. 14 is a physical direct connection structure, does not require a horizontal interconnection structure, has a significantly reduced parasitic resistance, and greatly improves the transmission speed and transmission performance.

[0124] In one embodiment, the general manufacturing process of the chip stack structure 40 is as follows.

[0125] In step S801, a wafer is provided.

[0126] In step S802, the wafer is divided into a plurality of chip regions, and the main body structure of the aforementioned memory chip is formed in each chip region.

[0127] In step S803, the wafer is cut to obtain a plurality of memory chips.

[0128] In step S804, 4m memory chips and one logic chip are aligned along the third direction (the alignment rule is as described above), and a conductive bump and / or a hybrid bonding structure are formed between two chips to form one chip stack structure 40.

[0129] In another embodiment, the schematic manufacturing process of the chip stack structure 40 is as follows.

[0130] In step S901, 4m wafers are provided.

[0131] In step S902, each wafer is divided into a plurality of chip regions, and the main body structure of the aforementioned memory chips is formed in each chip region.

[0132] In step S903, the 4m wafers are aligned along the third direction (the alignment rule is as described above), and a conductive bump and / or a hybrid bonding structure are formed between two adjacent wafers.

[0133] It should be noted that for two adjacent wafers, there are multiple pairs of memory chips aligned along the third direction, and for each pair of memory chips aligned along the third direction, a conductive bump and / or a hybrid bonding structure are formed.

[0134] In step S904, the 4m wafers are cut to obtain a plurality of pre-stack structures.

[0135] In step S905, the plurality of pre-stack structures and the plurality of logic chips are assembled in correspondence to form a plurality of chip stack structures 40.

[0136] Furthermore, in another embodiment, the schematic manufacturing process of the chip stack structure 40 is as follows.

[0137] In step S1001, provide 4m + 1 wafers.

[0138] In step S1002, divide each wafer into a plurality of chip regions, form the main body structure of the aforementioned memory chip in each chip region within 4m wafers, and form the main body structure of the aforementioned logic chip in each chip region within one wafer.

[0139] In step S1003, align the 4m + 1 wafers along the third direction (the alignment rule is as described above), and form conductive bumps and / or hybrid bonding structures between two adjacent wafers.

[0140] It should be noted that for two adjacent wafers, there are a plurality of pairs of memory chips aligned along the third direction, and for each pair of memory chips aligned along the third direction, a conductive bump and / or a hybrid bonding structure is formed.

[0141] In step S1004, cut the 4m + 1 wafers to obtain a plurality of chip stack structures 40.

[0142] As can be seen from the above, the memory chip according to the embodiment of the present disclosure not only reduces the parasitic capacitance by reducing the set numbers of the drive circuit and the data selector, but also, the chip stack structure formed by the memory chip realizes the signal rotation transmission effect through the direct connection structure of the through holes, and also reduces the parasitic resistance. As a result of the simulation experiment, the stack structure provided by this embodiment of the present disclosure has a parasitic capacitance reduced by about 7% compared with the structure shown in FIG. 2, and its parasitic resistance is reduced by about 95% compared with the structure shown in FIG. 2. Thereby, more chips can be stacked and the signal transmission quality is improved.

[0143] In yet another embodiment of the present disclosure, referring to FIG. 15, FIG. 15 is a schematic diagram showing the configuration of the memory 70 according to an embodiment of the present disclosure. As shown in FIG. 15, the memory 70 includes at least the aforementioned chip stack structure 40.

[0144] The above are only preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure. It should be noted that in this specification, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such a process, method, article or device. Unless otherwise specifically limited, the elements defined by the expression "including..." do not exclude the presence of other same elements in the process, method, article or device including such elements. The sequence numbers of the above embodiments of the present disclosure are for illustrative purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in some method embodiments provided by the present disclosure can be arbitrarily combined without contradiction to obtain new method embodiments. The features disclosed in some product embodiments provided by the present disclosure can be arbitrarily combined without contradiction to obtain new product embodiments. The features disclosed in some method or device embodiments provided by the present disclosure can be arbitrarily combined without contradiction to obtain new method embodiments or device embodiments. The above content is only a specific embodiment of the present disclosure, and the protection scope of the present disclosure is not limited thereto. Any deformation or substitution that can be easily conceived by those skilled in the art within the technical scope disclosed by the present disclosure should be included within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Industrial Applicability

[0145] Embodiments of the present disclosure provide a memory chip, a chip stack structure, and a memory. By reducing the number of settings of the drive circuit and the data selector, not only the parasitic capacitance is reduced, but also the chip stack structure formed by the memory chip realizes a signal rotation transmission effect through a direct connection structure of vias, and the parasitic resistance is also reduced.

Claims

1. A memory chip (10), wherein the memory chip (10) includes 2×2 regions distributed in an array along the active surface of the memory chip (10), and each of the regions is penetrated by n sets of through holes (20), where n is a natural number, the n sets of through holes (20) in the first region (11) and the n sets of through holes (20) in the second region (12) are symmetric with respect to the first axis (AA'), the n sets of through holes (20) in the third region (13) and the n sets of through holes (20) in the fourth region (14) are symmetric with respect to the first axis (AA'), the n sets of through holes (20) in the first region (11) and the n sets of through holes (20) in the fourth region (14) are symmetric with respect to the second axis (BB'), the first axis (AA') and the second axis (BB') are both located on the active surface, and the first axis (AA') and the second axis (BB') are perpendicular to each other and intersect at the center of the active surface, for each of the sets of through holes (20), each of the sets of through holes (20) includes 2×2 through holes distributed in an array, the first through hole (D0) and the second through hole (D1) are symmetric with respect to the third axis (CC'), the third through hole (D2) and the fourth through hole (D3) are symmetric with respect to the third axis (CC'), the first through hole (D0) and the fourth through hole (D3) are symmetric with respect to the fourth axis (DD'), the third axis (CC') and the fourth axis (DD') are both located on the active surface, and the third axis (CC') and the fourth axis (DD') are perpendicular to each other and intersect at the center of the set of through holes (20), a memory chip (10), wherein the first axis (AA') and the third axis (CC') of each of the sets of through holes (20) are both parallel to the first side of the memory chip (10), and the second axis (BB') and the fourth axis (DD') of each of the sets of through holes (20) are both parallel to the second side of the memory chip (10).

2. The n first through holes (D0) in the first region (11) and the n second through holes (D1) in the second region (12) are symmetric with respect to the first axis (AA'), the n third through holes (D2) in the third region (13) and the n fourth through holes (D3) in the fourth region (14) are symmetric with respect to the first axis (AA'), The n first through-holes (D0) in the first region (11) and the n fourth through-holes (D3) in the fourth region (14) are symmetric with respect to the second axis (BB'). The memory chip (10) according to claim 1.

3. The n second through-holes (D1) in the first region (11) and the n first through-holes (D0) in the second region (12) are symmetric with respect to the first axis (AA'). The n fourth through-holes (D3) in the third region (13) and the n third through-holes (D2) in the fourth region (14) are symmetric with respect to the first axis (AA'). The n second through-holes (D1) in the first region (11) and the n third through-holes (D2) in the fourth region (14) are symmetric with respect to the second axis (BB'). The memory chip (10) according to claim 2.

4. The n third through-holes (D2) in the first region (11) and the n fourth through-holes (D3) in the second region (12) are symmetric with respect to the first axis (AA'). The n first through-holes (D0) in the third region (13) and the n second through-holes (D1) in the fourth region (14) are symmetric with respect to the first axis (AA'). The n third through-holes (D2) in the first region (11) and the n second through-holes (D1) in the fourth region (14) are symmetric with respect to the second axis (BB'). The memory chip (10) according to claim 3.

5. The n fourth through-holes (D3) in the first region (11) and the n third through-holes (D2) in the second region (12) are symmetric with respect to the first axis (AA'). The n second through-holes (D1) in the third region (13) and the n first through-holes (D0) in the fourth region (14) are symmetric with respect to the first axis (AA'). The n fourth through-holes (D3) in the first region (11) and the n first through-holes (D0) in the fourth region (14) are symmetric with respect to the second axis (BB'). The memory chip (10) according to claim 4.

6. Any one of the through-holes penetrates the memory chip (10) along a direction perpendicular to the active surface, and different through-holes in the same memory chip (10) are electrically insulated from each other. The memory chip (10) according to any one of claims 1 to 5.

7. The memory chip (10) further includes 4n first drive circuits (30), the 4n through-holes are connected in a one-to-one correspondence with the 4n first drive circuits (30), and only one through-hole in each through-hole group (20) is connected to the first drive circuit (30), The memory chip (10) according to any one of claims 1 to 6.

8. The memory chip (10) further includes a positioning structure, by being located in a reference region, the positioning structure indicates the location of the reference region, and the reference region is one of the 2×2 regions, The memory chip (10) according to any one of claims 1 to 7.

9. A chip stacking structure (40), the chip stacking structure (40) includes at least one stacking unit, and each stacking unit includes a first memory chip (41, 41a, 41b), a second memory chip (42, 42a, 42b), a third memory chip (43, 43a, 43b), and a fourth memory chip (44, 44a, 44b) sequentially stacked along a third direction. The third direction is perpendicular to the active surface of each memory chip. The first memory chip (41, 41a, 41b), the second memory chip (42, 42a, 42b), the third memory chip (43, 43a, 43b), and the fourth memory chip (44, 44a, 44b) are all memory chips (10) according to any one of claims 1 to 7, the first memory chip (41, 41a, 41b) and the second memory chip (42, 42a, 42b) are stacked face to face, the second memory chip (42, 42a, 42b) and the third memory chip (43, 43a, 43b) are stacked back to back, and the third memory chip (43, 43a, 43b) and the fourth memory chip (44, 44a, 44b) are stacked face to face. A chip stacking structure (40).

10. A first region (11) in the first memory chip (41, 41a, 41b), a second region (12) in the second memory chip (42, 42a, 42b), a third region (13) in the third memory chip (43, 43a, 43b), and a fourth region (14) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction, The second region (12) in the first memory chip (41, 41a, 41b), the first region (11) in the second memory chip (42, 42a, 42b), the fourth region (14) in the third memory chip (43, 43a, 43b), and the third region (13) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The third region (13) in the first memory chip (41, 41a, 41b), the fourth region (14) in the second memory chip (42, 42a, 42b), the first region (11) in the third memory chip (43, 43a, 43b), and the second region (12) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The fourth region (14) in the first memory chip (41, 41a, 41b), the third region (13) in the second memory chip (42, 42a, 42b), the second region (12) in the third memory chip (43, 43a, 43b), and the first region (11) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stack structure (40) according to claim 9.

11. The n first vias (D0) in the first region (11) of the first memory chip (41, 41a, 41b), the n second vias (D1) in the second region (12) of the second memory chip (42, 42a, 42b), the n third vias (D2) in the third region (13) of the third memory chip (43, 43a, 43b), and the n fourth vias (D3) in the fourth region (14) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second vias (D1) in the first region (11) of the first memory chip (41, 41a, 41b), the n first vias (D0) in the second region (12) of the second memory chip (42, 42a, 42b), the n fourth vias (D3) in the third region (13) of the third memory chip (43, 43a, 43b), and the n third vias (D2) in the fourth region (14) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third through-holes (D2) in the first region (11) in the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the second region (12) in the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the third region (13) in the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the fourth region (14) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the first region (11) in the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the second region (12) in the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the third region (13) in the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the fourth region (14) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stacking structure (40) according to claim 10.

12. The n first through-holes (D0) in the second region (12) in the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the first region (11) in the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the fourth region (14) in the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the third region (13) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the second region (12) in the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the first region (11) in the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the fourth region (14) in the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the third region (13) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third vias (D2) in the second region (12) in the first memory chip (41, 41a, 41b), the n fourth vias (D3) in the first region (11) in the second memory chip (42, 42a, 42b), the n first vias (D0) in the fourth region (14) in the third memory chip (43, 43a, 43b), and the n second vias (D1) in the third region (13) in the fourth memory chip (44, 44a, 44b) are aligned along a third direction. The n fourth vias (D3) in the second region (12) in the first memory chip (41, 41a, 41b), the n third vias (D2) in the first region (11) in the second memory chip (42, 42a, 42b), the n second vias (D1) in the fourth region (14) in the third memory chip (43, 43a, 43b), and the n first vias (D0) in the third region (13) in the fourth memory chip (44, 44a, 44b) are aligned along a third direction. The chip stack structure (40) according to claim 11.

13. The n first vias (D0) in the third region (13) in the first memory chip (41, 41a, 41b), the n second vias (D1) in the fourth region (14) in the second memory chip (42, 42a, 42b), the n third vias (D2) in the first region (11) in the third memory chip (43, 43a, 43b), and the n fourth vias (D3) in the second region (12) in the fourth memory chip (44, 44a, 44b) are aligned along a third direction. The n second vias (D1) in the third region (13) in the first memory chip (41, 41a, 41b), the n first vias (D0) in the fourth region (14) in the second memory chip (42, 42a, 42b), the n fourth vias (D3) in the first region (11) in the third memory chip (43, 43a, 43b), and the n third vias (D2) in the second region (12) in the fourth memory chip (44, 44a, 44b) are aligned along a third direction. The n third through-holes (D2) in the third region (13) in the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the fourth region (14) in the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the first region (11) in the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the second region (12) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the third region (13) in the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the fourth region (14) in the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the first region (11) in the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the second region (12) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stack structure (40) according to claim 12.

14. The n first through-holes (D0) in the fourth region (14) in the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the third region (13) in the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the second region (12) in the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the first region (11) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the fourth region (14) in the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the third region (13) in the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the second region (12) in the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the first region (11) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third vias (D2) in the fourth region (14) of the first memory chip (41, 41a, 41b), the n fourth vias (D3) in the third region (13) of the second memory chip (42, 42a, 42b), the n first vias (D0) in the second region (12) of the third memory chip (43, 43a, 43b), and the n second vias (D1) in the first region (11) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth vias (D3) in the fourth region (14) of the first memory chip (41, 41a, 41b), the n third vias (D2) in the third region (13) of the second memory chip (42, 42a, 42b), the n second vias (D1) in the second region (12) of the third memory chip (43, 43a, 43b), and the n first vias (D0) in the first region (11) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stack structure (40) according to claim 13.

15. The first region (11) in the first memory chip (41, 41a, 41b), the fourth region (14) in the second memory chip (42, 42a, 42b), the third region (13) in the third memory chip (43, 43a, 43b), and the second region (12) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The second region (12) in the first memory chip (41, 41a, 41b), the third region (13) in the second memory chip (42, 42a, 42b), the fourth region (14) in the third memory chip (43, 43a, 43b), and the first region (11) in the fourth memory chip (44, 44a, 44b) are aligned along the first direction. The third region (13) in the first memory chip (41, 41a, 41b), the second region (12) in the second memory chip (42, 42a, 42b), the first region (11) in the third memory chip (43, 43a, 43b), and the fourth region (14) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The fourth region (14) in the first memory chip (41, 41a, 41b), the first region (11) in the second memory chip (42, 42a, 42b), the second region (12) in the third memory chip (43, 43a, 43b), and the third region (13) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stack structure (40) according to claim 9.

16. The n first vias (D0) of the first region (11) in the first memory chip (41, 41a, 41b), the n fourth vias (D3) of the fourth region (14) in the second memory chip (42, 42a, 42b), the n third vias (D2) of the third region (13) in the third memory chip (43, 43a, 43b), and the n second vias (D1) of the second region (12) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second vias (D1) of the first region (11) in the first memory chip (41, 41a, 41b), the n third vias (D2) of the fourth region (14) in the second memory chip (42, 42a, 42b), the n fourth vias (D3) of the third region (13) in the third memory chip (43, 43a, 43b), and the n first vias (D0) of the second region (12) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third vias (D2) of the first region (11) in the first memory chip (41, 41a, 41b), the n second vias (D1) of the fourth region (14) in the second memory chip (42, 42a, 42b), the n first vias (D0) of the third region (13) in the third memory chip (43, 43a, 43b), and the n fourth vias (D3) of the second region (12) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the first region (11) in the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the fourth region (14) in the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the third region (13) in the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the second region (12) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stack structure (40) according to claim 15. [

17. ] The n first through-holes (D0) in the second region (12) in the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the third region (13) in the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the fourth region (14) in the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the first region (11) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the second region (12) in the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the third region (13) in the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the fourth region (14) in the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the first region (11) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third through-holes (D2) in the second region (12) in the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the third region (13) in the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the fourth region (14) in the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the first region (11) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the second region (12) of the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the third region (13) of the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the fourth region (14) of the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the first region (11) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stack structure (40) according to claim 16.

18. The n first through-holes (D0) in the third region (13) of the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the second region (12) of the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the first region (11) of the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the fourth region (14) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the third region (13) of the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the second region (12) of the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the first region (11) of the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the fourth region (14) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third through-holes (D2) in the third region (13) of the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the second region (12) of the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the first region (11) of the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the fourth region (14) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the third region (13) of the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the second region (12) of the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the first region (11) of the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the fourth region (14) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stack structure (40) according to claim 17.

19. The n first through-holes (D0) in the fourth region (14) of the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the first region (11) of the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the second region (12) of the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the third region (13) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the fourth region (14) of the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the first region (11) of the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the second region (12) of the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the third region (13) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third through-holes (D2) in the fourth region (14) of the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the first region (11) of the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the second region (12) of the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the third region (13) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth vias (D3) in the fourth region (14) of the first memory chip (41, 41a, 41b), the n first vias (D0) in the first region (11) of the second memory chip (42, 42a, 42b), the n second vias (D1) in the second region (12) of the third memory chip (43, 43a, 43b), and the n third vias (D2) in the third region (13) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stacking structure (40) according to claim 18.

20. For two memory chips connected face to face, the vias aligned along the third direction of both are connected by a hybrid bonding structure. For two memory chips connected back to back, the vias aligned along the third direction of both are connected by conductive bumps, or For two memory chips connected face to face or two memory chips connected back to back, the vias aligned along the third direction of both are all connected by a hybrid bonding structure, or For two memory chips connected face to face or two memory chips connected back to back, the vias aligned along the third direction of both are all connected by conductive bumps. The chip stacking structure (40) according to any one of claims 9 to 19.

21. Each of the memory chips further includes 4n first drive circuits (30). In each of the memory chips, the 4n first drive circuits (30) are connected in a one-to-one correspondence to the first ends of the 4n first vias (D0), and the first ends of the first vias (D0) are located on the active surface of the memory chip. The chip stacking structure (40) according to claim 20.

22. The chip stacking structure (40) further includes a logic chip (50). The first stacking unit is stacked on the logic chip (50) along the third direction, and the other stacking units are sequentially stacked on the previous stacking unit along the third direction. The logic chip (50) includes 16n fifth vias (502) and 16n second drive circuits (501). Four n fifth vias (502) are in one-to-one correspondence and alignment with four n first vias (D0) in the first memory chip (41, 41a, 41b) along the third direction. Four n fifth vias (502) are in one-to-one correspondence and alignment with four n second vias (D1) in the first memory chip (41, 41a, 41b) along the third direction. Four n fifth vias (502) are in one-to-one correspondence and alignment with four n third vias (D2) in the first memory chip (41, 41a, 41b) along the third direction. Four n fifth vias (502) are in one-to-one correspondence and alignment with four n fourth vias (D3) in the first memory chip (41, 41a, 41b) along the third direction. The 16n second drive circuits (501) are connected to the first ends of the 16n fifth vias (502) in one-to-one correspondence. The first ends of the fifth vias (502) are located on the active surface of the logic chip (50). The chip stack structure (40) according to claim 21.

23. The chip stack structure (40) further includes 16n electrical paths. When the chip stack structure (40) includes m of the stacking units, one fifth via (502), m of the first vias (D0), m of the second vias (D1), m of the third vias (D2), and m of the fourth vias (D3) that are in alignment along the third direction are connected to form one of the electrical paths, where m is a positive integer. The chip stack structure (40) according to claim 22.

24. A memory including the chip stack structure (40) according to any one of claims 9 to 23.

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