Self-aligned back-gate contact for backside signal line integration

Abstract

The semiconductor array structure includes a substrate and a plurality of field effect transistors (FETs) arranged in columns on the substrate. Each FET includes a first source / drain region, a second source / drain region, at least one channel connecting the source / drain regions, and a gate adjacent to the at least one channel. A plurality of front signal lines are on the front side of the FETs, a plurality of backside power rails are on the back side of the FETs, and a plurality of backside signal wirings are on the back side. The front signal connection extends from the front signal line to the first source / drain region, the power connection extends from the backside power rail to the second source / drain region, and the backside gate contact connection extends from the backside signal wiring to the gate. The backside gate contact connections each have a bottom surface dimension larger than the gate length.

Description

Technical Field

[0001] The present invention generally relates to the fields of electricity, electronics, and computers, and more particularly to signal lines of integrated circuits (ICs).

[0002] In integrated circuit technology, the power supply network of a chip supplies power and reference voltage to active devices. The power supply network is separated from the signal network. Conventionally, both the power supply network and the signal network are fabricated on the front side of the wafer by back-end-of-line (BEOL) processing. Various proposals have been made to implement power distribution on the back side of the silicon wafer, which may enable, for example, direct power supply, improvement of system performance, improvement of chip area utilization, and reduction of BEOL complexity.

[0003] So far, providing additional networks on the back side of a chip has been limited to power rather than signals.

Summary of the Invention

[0004] The principle of the present invention provides a technique of self-aligned backside gate contacts for backside signal line integration. In one aspect, an exemplary semiconductor structure includes a backside power rail, a backside signal line, a front-side signal line, a first source-drain region, a second source-drain region, at least one channel coupling the first and second source-drain regions, a gate adjacent to the at least one channel, a front-side signal connection from the front-side signal line to the first source-drain region, a power connection from the backside power rail to the second source-drain region, and a backside gate contact from the gate to the backside signal line.

[0005] In a further aspect, an exemplary semiconductor array structure includes a substrate and a plurality of field effect transistors disposed on the substrate, each of which includes a first source / drain region, a second source / drain region, at least one channel coupling the first and second source / drain regions, and a gate having a certain gate length and adjacent to at least one channel, and the plurality of field effect transistors are arranged in a columnar manner, a plurality of front signal lines in front of the plurality of field effect transistors, a plurality of back power rails on the back of the plurality of field effect transistors, and a plurality of back signal wirings on the back of the plurality of field effect transistors. The plurality of front signal connections extend from the plurality of front signal lines to the first source / drain region, the plurality of power connections extend from the back power rails to the second source / drain region, and the plurality of back gate contact connections extend from the back signal wirings to the gate. The back gate contact connections each have a bottom dimension greater than the gate length.

[0006] In another aspect, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium, and the HDL design structure includes elements that, when processed by a computer-aided design system, generate a machine-executable representation of the device / circuit. The HDL design structure includes the semiconductor structure or semiconductor array structure described above.

[0007] In yet another aspect, an exemplary method of forming a semiconductor structure includes defining n-type and p-type active regions in a nanosheet stack on a substrate, forming a trench isolation (STI) region between the active regions, forming a back-gate contact via in the trench isolation (STI) region in a space between the n-type active region and the p-type active region, forming a dummy gate and a gate spacer such that a bottom portion of the back-gate contact via is filled with a dummy gate material of the dummy gate, removing the dummy gate, forming a replacement high-k metal gate such that the back-gate contact via is filled with a high-k metal gate material of a high-k metal gate adjacent to a bottom surface of the gate to obtain a resulting structure, forming back-end-of-line wiring on a front surface of the resulting structure opposite the substrate, and forming a back signal line that connects to the high-k metal gate material within the back-gate contact via.

[0008] In yet another aspect, another exemplary method of forming a semiconductor structure includes defining n-type and p-type active regions in a nanosheet stack on a substrate, forming a trench isolation (STI) region between the active regions, forming a back-gate contact via in the trench isolation (STI) region in a space between the n-type active region and the p-type active region, filling the back-gate contact via with a sacrificial back-gate contact material and recessing the sacrificial back-gate contact material, forming a dummy gate and a gate spacer such that a bottom portion of the back-gate contact via contacts a dummy gate material of the dummy gate and is filled with the sacrificial back-gate contact material, removing the dummy gate, forming a replacement high-k metal gate such that a bottom portion of the back-gate contact via contacts a high-k metal gate material of a high-k metal gate and is filled with the sacrificial back-gate contact material to obtain a resulting structure, forming back-end-of-line wiring on a front surface of the resulting structure opposite the substrate, removing the sacrificial back-gate contact material to form a void, and forming a back signal line that connects to the high-k metal gate material through the void.

[0009] As used herein, to "facilitate" an action includes performing the action, making the action easier, assisting in performing the action, or causing the action to be performed. Thus, by way of example and not limitation, instructions executed by a processor can facilitate an action performed by a semiconductor manufacturing apparatus by sending appropriate data or commands that cause or assist in the performance of the action. Even if an action is facilitated by something other than an actor performing the action, the action is performed by some entity or combination of entities. The techniques disclosed herein are capable of providing very beneficial technical effects. Some embodiments may not have these potential advantages, and these potential advantages are not necessarily required for all embodiments. By way of example and not limitation, one or more embodiments can provide one or more of the following: ·Improvement in the system performance of an integrated circuit ·Improvement in the chip area utilization rate of an integrated circuit ·Reduction in the BEOL complexity of an integrated circuit

[0010] These and other features and advantages will become apparent from the following detailed description of exemplary embodiments to be read in conjunction with the accompanying drawings.

[0011] The following drawings are presented for purposes of illustration only and not limitation, and like reference numerals (if used) indicate corresponding elements throughout several views.

Brief Description of the Drawings

[0012]

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DETAILED DESCRIPTION OF THE INVENTION

[0013] It should be understood that the elements in the figures are illustrated for simplicity and clarity. Common and well - understood elements that may be useful or necessary in a commercially viable embodiment may not be illustrated to make the illustrated embodiments easier to view.

[0014] The principles of the invention described herein are in the context of exemplary embodiments. Further, it will be apparent to those skilled in the art that given the teachings herein, numerous modifications can be made to the illustrated embodiments that are within the scope of the claims. That is, no limitation or inference should be intended or drawn with respect to the embodiments shown and described herein.

[0015] As described above, various proposals have been made to implement power distribution on the backside of a silicon wafer, which may enable, for example, direct power supply, improvement of system performance, improvement of chip area utilization, and reduction of BEOL complexity. Currently proposed technologies supply power to the source / drain (S / D) regions of field - effect transistors (FETs), but do not provide a connection to the gates of the FETs. Advantageously, one or more embodiments add a backside gate connection, for example, to provide a clock signal track. Heretofore, power vias have been provided to connect the S / D epitaxy to the backside power supply network (BSPDN). One or more embodiments provide both power vias for the S / D epitaxy for power connection and power vias for the gates to the backside signal line connection.

[0016] For example, in one or more embodiments, a semiconductor device includes at least one power contact via connecting S / D epitaxy to a backside power rail and a signal line contact via connecting an FET gate to a backside clock signal. In some cases, the signal line contact has a bottom surface dimension larger than the gate and is capped with a gate spacer. In some cases, the signal contact is a T-shaped structure on the bottom surface of the gate. In some cases, the power via contact and the backside power rail are disposed within N2N and P2P spaces. In some cases, the signal line contact and the backside clock signal are disposed within an N2P space. Note that "N2N" refers to the space between adjacent n-type FETs (NFETs), "P2P" refers to the space between adjacent p-type FETs (PFETs), and "N2P" refers to the space between an adjacent NFET and PFET. In one or more embodiments, the signal line contact is filled with a high-k metal gate (HKMG).

[0017] In one or more exemplary embodiments, an exemplary process flow includes defining an active region and forming shallow trench isolation (STI), forming a backside gate contact via in the STI region between N2P spaces, and forming a dummy gate and gate spacers such that the bottom portion of the backside gate contact via is filled with dummy gate material. In the final structure, the bottom portion of the backside gate contact via filled with dummy gate material is ultimately filled with HKMG material as described later, and the resulting region is separated from the FEOL structure by the gate spacers. In one or more exemplary embodiments, the exemplary process flow further includes removing the dummy gate and forming a replacement high-k metal gate (HKMG) such that the backside gate contact via is also filled with HKMG attached to the bottom surface of the gate, flipping the wafer, and forming a backside signal line connected to the backside gate contact via.

[0018] Figure 1 is a high-level layout (top view) of an exemplary semiconductor structure 101 according to one aspect of the present invention. Note the backside power rails (e.g., VSS (e.g., ground voltage) 269, VDD (e.g., positive supply voltage) 271) and signal lines (e.g., clock signal 273). Also note the NFET region 109 and PFET region 111, which are sketched schematically. As described above, the space between NFETs 109 is referred to as the N2N space, the space between PFETs 111 is referred to as the P2P space, and the space between NFET 109 and PFET 111 is referred to as the N2P space. Under the N2N and P2P spaces, note the respective backside power rails (VSS 269, VDD 271) connected to the S / D epitaxy, and under the N2P space, note the backside clock signal 273 connected to the gate 201 (seen in FIG. 2A below).

[0019] Next, consider a first exemplary process flow according to one aspect of the present invention, now referring to FIGS. 2A and 2B. FIG. 2B is a cross-sectional view of the starting wafer structure obtained along the cut line Y in FIG. 2A (along the gate). Elements similar to those in FIG. 1 in FIG. 2A have the same reference characters. FIGS. 2A and 5A (described below) are top views of the completed structure and have reference cut lines. Note the gate 201. The starting wafer structure includes a lower silicon portion 203, an intermediate etch stop portion 205 of (e.g.) buried oxide (BOX) or silicon germanium (SiGe), and an upper silicon portion 207. Outside the upper silicon portion, there is a nanosheet structure including alternating layers of SiGe 209, 211, 213, 215 and silicon nanosheets 217, 219, 221, 223. The SiGe regions 209, 211, 213, 215 (and 205 if made of SiGe) can include, for example, SiGe with a Ge% in the range of 15 to 75%. Those skilled in the art will be generally familiar with the formation of nanosheet transistors.

[0020] FIG. 3 is a cross-sectional view of the structure of FIG. 2B obtained along the cut plane line Y in FIG. 2A after nano-sheet patterning. In particular, a hard mask 225 (e.g., a layer of insulator or a multi-layer thereof) is deposited, gaps are created in the hard mask using lithography, and etching is performed to create trenches 227 corresponding to the gaps in the hard mask (the regions under the remaining hard mask 225 are not etched). Those skilled in the art will be generally familiar with patterning of the hard mask by lithography techniques and etching of the nano-sheet structure.

[0021] FIG. 4 is a cross-section of the structure of FIG. 3 obtained along the cut plane line Y (along the gate) in FIG. 2A after deposition of trench isolation (STI) material 229 (e.g., SiO or other suitable oxides, and if necessary, a suitable liner can be first deposited using known techniques and materials) and removal of the hard mask 225 (the hard mask can be stripped using known techniques and materials). The STI can be deposited, for example, using furnace chemical vapor deposition (FCVD) or other suitable techniques.

[0022] Next, refer to FIGS. 5A and 5B-5C. (B) of FIGS. 5B-5C is a cross-sectional view of the structure obtained along the cut plane line Y1 of FIG. 5A. The alternating layers of SiGe 209, 211, 213, 215 and silicon nanosheets 217, 219, 221, 223 are not numbered in FIGS. 5B-5C(B) to 17(B) to avoid clutter. Elements similar to those in FIGS. 1 and 2A in FIG. 5A have the same reference characters. (C) of FIGS. 5B-5C is a cross-sectional view of the structure obtained along the cut plane line X2 of FIG. 5A. FIGS. 5B-5C show the structure of FIG. 4 after appropriate etching such as back gate contact patterning and reactive ion etching (RIE). Note the organic planarization layer (OPL) 231 and the via 233 formed in the STI 229 under the corresponding opening of the OPL 231. An appropriate type of OPL can be employed. Those skilled in the art will be familiar with the deposition and stripping of the OPL, the patterning of the OPL using lithography techniques, and the formation of the corresponding vias in the STI material. Overall, the cut plane lines X1 and X2 intersect the gate, the cut plane line Y1 is along the gate, and the cut plane line Y2 is parallel to the gate between two adjacent gates.

[0023] Next, refer to FIGS. 6(A), 6(B), 6(C) and 6(D). FIG. 6(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A. FIG. 6(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A. FIG. 6(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A. FIG. 6(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A. FIGS. 6(A)-6(D) show the structure of FIGS. 5B-5C after the formation of the dummy gate 235 and the deposition of the gate hard mask material 237. The dummy gate is shown as a single structure to avoid clutter, but it should be noted that it can include, for example, a thin SiO2 liner with amorphous silicon (a-Si) added in a known manner. For example, after the deposition of the thin liner, the amorphous Si material is deposited, planarization is performed, and the gate hard mask material 237 (which can be a multi-layer insulator, for example) is deposited. Those skilled in the art will be generally familiar with the dummy gate process.

[0024] Next, refer to FIGS. 7(A), 7(B), 7(C) and 7(D). FIG. 7(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A. FIG. 7(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A. FIG. 7(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A. FIG. 7(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A. FIGS. 7(A)-7(D) show the structure of FIGS. 6(A)-6(D) after appropriate etching such as reactive ion etching (RIE) of the dummy gate material after lithographic patterning of the gate hard mask material 237. As a result, as will be apparent from the following description, various voids (not separately numbered) including interlayer insulation (ILD), epitaxially grown source / drain regions, and contacts will be formed later. For example, the hard mask is patterned and the a-Si is etched to form the dummy gate 235. Those skilled in the art will be generally familiar with the techniques of lithographic patterning and etching.

[0025] Next, refer to FIGS. 8(A), 8(B), 8(C), and 8(D). FIG. 8(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A. FIG. 8(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A. FIG. 8(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A. FIG. 8(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A. FIGS. 8(A) to 8(D) show the structures of FIGS. 7(A) to 7(D) after the formation of the gate spacer 241, the recessing of the nanosheet, the formation of the inner spacer 239, and the epitaxial growth of the p-type source / drain region 243 and the n-type source / drain region 245. SiGe 209, 211, 213, 215 are etched back laterally (for example, using a vapor phase HCl process in this embodiment), and the inner spacer 239 is filled in the resulting area. Those skilled in the art will be familiar with the techniques of subsequent epitaxial growth of the p-type and n-type source / drain regions and the deposition of the gate spacer 241. Suitable materials for the gate spacer 241 include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, which can be deposited in a known manner. A non-limiting example of the material of the inner spacer 239 is SiN, and the spacer 239 can be formed in a known manner.

[0026] Next, refer to FIGS. 9(A), 9(B), 9(C), and 9(D). FIG. 9(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A. FIG. 9(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A. FIG. 9(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A. FIG. 9(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A. FIGS. 9(A) to 9(D) show the structures of FIGS. 8(A) to 8(D) after interlayer dielectric (ILD) filling, chemical mechanical polishing (CMP), gate cutting, dummy gate and SiGe removal, and replacement high-k metal gate (HKMG) formation. The ILD 247 (for example, FCVD SiO2, generally, exemplary materials for the ILD layer include SiO x, low-k oxides (dielectric constant < 3.9), SiN, or combinations of these materials (e.g., SiN and SiO2), HKMG material 249, and gate cut 251 are noted. As seen at 253, the back-gate contact (part of material 249) is self-aligned to the middle gate (referring back to the dummy-gate RIE shown in FIGS. 7(A) - 7(D), even if the gate shifts left or right, the back-gate contact is connected to the bottom surface of the gate). To move from the structure of FIGS. 8(A) - 8(D) to the structure of FIGS. 9(A) - 9(D), the dummy-gate 235 and the sacrificial a-Si portions of the sacrificial nanosheets 209, 211, 213, 215 are selectively removed, a conformal high-k metal gate stack is formed, the cavity for the gate cut 251 is patterned and etched, the cavity is filled with an insulating material (e.g., similar to other suitable insulating materials considered herein), and the gate cut 251 is formed. In one or more embodiments, the gate stack is a high-k metal gate (HKMG) stack. HKMG includes a combination of a high-k insulating layer and a metal gate feature. Some non-limiting examples of the high-k insulating layer can include hafnium silicon oxide, zirconium silicon oxide, hafnium oxide, or zirconium oxide. Some non-limiting examples of the metal gate feature can also include work-function-tunable materials such as titanium nitride, titanium aluminum nitride, titanium silicon nitride, tantalum nitride, tantalum aluminum nitride, or tantalum silicon nitride. The components of HKMG can be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or a combination of these two processes in one or more embodiments. The term "high-k" has a clear meaning to those skilled in the art in the context of a high-k metal gate (HKMG) stack and is not just a relative term.

[0027] Next, refer to FIGS. 10(A), 10(B), 10(C) and 10(D). FIG. 10(A) is a cross-sectional view of the structure obtained along the cut plane line X1 of FIG. 5A. FIG. 10(B) is a cross-sectional view of the structure obtained along the cut plane line X2 of FIG. 5A. FIG. 10(C) is a cross-sectional view of the structure obtained along the cut plane line Y1 of FIG. 5A. FIG. 10(D) is a cross-sectional view of the structure obtained along the cut plane line Y2 of FIG. 5A. FIGS. 10(A) to 10(D) show the structures of FIGS. 9(A) to 9(D) after forming the middle-of-line (MOL) contacts, back-end-of-line (BEOL) interconnects, and carrier wafer bonding. Pay attention to the VBPR (via for connection to the back power rail) 255, source / drain contact (CA) 257, VA (via connecting the source / drain contact to the BEOL wiring) 259, VB (via connecting the gate to the BEOL wiring) 261, BEOL wiring 263, and carrier wafer 265. Those skilled in the art will be familiar with conventional MOL and BEOL processes, as well as wafer bonding techniques. Conventionally, BEOL refers to the interconnects, contacts, vias, and insulating layers that wire active devices into a specific circuit configuration. The recently introduced middle-of-line (MOL) interconnects help relieve congestion in local paths. MOL is usually located under the first metal layer, and in FIGS. 10(A) to 10(D), elements 255, 257 can be regarded as MOL, and elements 259, 261, 263 can be regarded as BEOL.

[0028] Next, refer to FIGS. 11(A), 11(B), 11(C) and 11(D). FIG. 11(A) is a cross-sectional view of the structure obtained along the cut plane line X1 of FIG. 5A after inversion. FIG. 11(B) is a cross-sectional view of the structure obtained along the cut plane line X2 of FIG. 5A after inversion. FIG. 11(C) is a cross-sectional view of the structure obtained along the cut plane line Y1 of FIG. 5A after inversion. FIG. 11(D) is a cross-sectional view of the structure obtained along the cut plane line Y2 of FIG. 5A after inversion. FIGS. 11(A) to 11(D) show the structures of FIGS. 10(A) to 10(D) after inversion, i.e., "flipping". Those skilled in the art will be familiar with the fixtures and techniques for flipping semiconductor wafers during fabrication.

[0029] Next, refer to FIGS. 12(A), 12(B), 12(C), and 12(D). FIG. 12(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A after inversion. FIG. 12(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A after inversion. FIG. 12(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A after inversion. FIG. 12(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A after inversion. FIGS. 12(A) to 12(D) show the structures of FIGS. 11(A) to 11(D) after removing the substrate 203 and stopping at the etching stop layer 205. Those skilled in the art will be familiar with suitable etchants for etching silicon and stopping on oxides or SiGe.

[0030] Next, refer to FIGS. 13(A), 13(B), 13(C), and 13(D). FIG. 13(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A after inversion. FIG. 13(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A after inversion. FIG. 13(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A after inversion. FIG. 13(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A after inversion. FIGS. 13(A) to 13(D) show the structures of FIGS. 12(A) to 12(D) after removing the etching stop layer 205 (e.g., using a conventional wet etching process).

[0031] Next, refer to FIGS. 14(A), 14(B), 14(C), and 14(D). FIG. 14(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A after inversion. FIG. 14(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A after inversion. FIG. 14(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A after inversion. FIG. 14(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A after inversion. FIGS. 14(A) to 14(D) show the structures of FIGS. 13(A) to 13(D) after recessing the silicon substrate 207 (e.g., using a conventional dry etching process).

[0032] Next, refer to FIGS. 15(A), 15(B), 15(C), and 15(D). FIG. 15(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A after inversion. FIG. 15(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A after inversion. FIG. 15(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A after inversion. FIG. 15(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A after inversion. FIGS. 15(A) to 15(D) show the structures of FIGS. 14(A) to 14(D) after the deposition of the backside ILD267 (appropriate materials and techniques for ILD247 can also be used for ILD267).

[0033] Next, refer to FIGS. 16(A), 16(B), 16(C), and 16(D). FIG. 16(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A after inversion. FIG. 16(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A after inversion. FIG. 16(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A after inversion. FIG. 16(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A after inversion. FIGS. 16(A) to 16(D) show the structures of FIGS. 15(A) to 15(D) after forming the backside power rails (e.g., VSS269, VDD271) and signal lines (e.g., clock signal 273). The metallization process for various metal lines and vias can be performed by a conventional single damascene process. Suitable materials include copper and other conductive metals. As described elsewhere in this specification, in one or more embodiments, the backside gate contact is self-aligned to the middle gate, and even if the gate is shifted left or right, the backside gate contact is connected to the bottom surface of the gate.

[0034] Next, refer to FIGS. 17(A), 17(B), 17(C), and 17(D). FIG. 17(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A after inversion. FIG. 17(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A after inversion. FIG. 17(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A after inversion. FIG. 17(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A after inversion. FIGS. 17(A) to 17(D) show the structures of FIGS. 16(A) to 16(D) after the formation of the backside interconnecting portion 275 (generally, the backside interconnecting portion can include a power supply network and can also include wiring for signal routing). Given the teachings of this specification, those skilled in the art will be able to form the backside interconnecting portion by adapting conventional techniques.

[0035] Next, consider a second exemplary process flow according to an aspect of the present invention. The first step is the same as the step described with respect to FIGS. 2A to 5B-5C (C). Next, refer to FIGS. 18(A) and 18(B). FIG. 18(A) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A. FIG. 18(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A. FIGS. 18(A) and 18(B) show the structure of FIGS. 5B-5C after filling the trench 233 with a sacrificial backside gate contact such as silicon nitride (SiN) 501 and recessing it. Given the teachings of this specification, those skilled in the art can adapt known techniques for filling with SiN or a similar material and recessing it. In the second exemplary process flow, FIGS. 18(A) to 19(D) are before inversion, and FIGS. 20(A) to 23(D) are after inversion.

[0036] Next, refer to FIGS. 19(A), 19(B), 19(C), and 19(D). FIG. 19(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A. FIG. 19(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A. FIG. 19(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A. FIG. 19(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A. FIGS. 19(A) to 19(D) show the structures of FIGS. 18(A) and 18(B) after the formation of the dummy gate 235, the deposition of the gate hard mask material 237, the reactive ion etching (RIE) of the dummy gate material, the spacer 241, the recessing of the nanosheet, the formation of the inner spacer 239, and the epitaxial growth of the p-type source / drain region 243 and the n-type source / drain region 245 in the same manner as FIGS. 6(A) to 8(D). The dummy gate is shown as a single structure to avoid clutter, but it should be noted that, for example, it can include a structure in which amorphous silicon (a-Si) is added to a thin SiO2 liner in a known manner. For example, a thin liner is deposited, then an amorphous Si material is deposited, planarization is performed, and the gate hard mask material 237 (which can be, for example, a multilayer insulator) is deposited. Those skilled in the art will be generally familiar with the dummy gate process. After the lithographic patterning of the gate hard mask material 237, appropriate etching such as reactive ion etching (RIE) of the dummy gate material forms various gaps (not separately numbered) that will later include the interlayer dielectric (ILD), the epitaxially grown source / drain regions, and the contacts, as will become apparent from the following description. For example, the hard mask is patterned and the a-Si is etched to form the dummy gate 235. Those skilled in the art will be generally familiar with the techniques of lithographic patterning and etching. Those skilled in the art will be generally familiar with the techniques of subsequent epitaxial growth of the p-type and n-type source / drain regions and the deposition of the liner 241.

[0037] The structures shown in FIGS. 19(A) to 19(D) can be subjected to a process similar to the process shown in FIGS. 9(A) to 15(D), including the deposition of the backside ILD 267, in order to obtain the structures shown in FIGS. 20(A) to 20(D). FIG. 20(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A. FIG. 20(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A. FIG. 20(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A. FIG. 20(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A.

[0038] Conventional lithography and etching can be performed on the backside BPR and signal lines as part of the formation of the backside power rails and signal lines. Note the cavity 511 for forming the clock signal line, the cavity 513 for forming the VSS power rail, and the cavity 515 for forming the VDD power rail. FIG. 21(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A. FIG. 21(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A. FIG. 21(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A. FIG. 21(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A. Known lithography and etching techniques can be used to create appropriate cavities in the backside ILD 267.

[0039] FIG. 22(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A. FIG. 22(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A. FIG. 22(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A. FIG. 22(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A. FIGS. 22(A) to 22(D) show the structures of FIGS. 21(A) to 21(D) after selectively removing the sacrificial backside gate contact (e.g., SiN) 501 and removing the HfO2 exposed from the HKMG 249 adjacent to the SiN 501 (e.g., using a conventional dry etching or wet etching process).

[0040] FIG. 23(A) is a cross-sectional view of the structure obtained along the cutting plane line X1 of FIG. 5A. FIG. 23(B) is a cross-sectional view of the structure obtained along the cutting plane line X2 of FIG. 5A. FIG. 23(C) is a cross-sectional view of the structure obtained along the cutting plane line Y1 of FIG. 5A. FIG. 23(D) is a cross-sectional view of the structure obtained along the cutting plane line Y2 of FIG. 5A. FIGS. 23(A) to 23(D) show the structures of FIGS. 22(A) to 22(D) after forming the backside power rails (e.g., VSS269, VDD271) and signal lines (e.g., clock signal 273A). The clock signal line 273A is similar to the clock signal line 273, but extends below the area where SiN501 and the exposed HfO2 have been removed. The various metal lines and metallization processes for vias can be performed by a conventional single damascene process. Suitable materials include copper and other conductive metals. As described elsewhere in this specification, in one or more embodiments, the backside gate contact is self-aligned to the middle gate, and even if the gate is shifted to the left or right, the backside gate contact is connected to the bottom surface of the gate.

[0041] Note that FIGS. 23(A) to 23(D) show steps that can be similarly performed to move from the structures of FIGS. 15(A) to 15(D) to the structures of FIGS. 16(A) to 16(D). For example, as seen in FIGS. 5B-5C, note that various features typically have a larger diameter towards the side of the structure in which they are formed.

[0042] The manufacture of semiconductor devices involves various steps in the device patterning process. For example, the manufacture of semiconductor chips may start from a plurality of device patterns generated by, for example, CAD (Computer-Aided Design), and then subsequent efforts are made to replicate these device patterns onto a substrate. The replication process may include various exposure techniques, and various subtractive material processing procedures (etching) or additive material processing procedures (deposition) or both. For example, in the photolithography process, first a layer of photoresist material is applied onto the substrate, and then this is selectively exposed according to one or more predetermined device patterns. The portion of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beam, X-rays, etc.) may undergo some changes in its solubility in a particular solution. The photoresist can then be developed with a developer, which can remove the unexposed portion (in the case of negative resist) or the exposed portion (in the case of positive resist) of the resist layer, and a pattern of the photoresist, i.e., a photomask, can be formed. The pattern of the photoresist, i.e., the photomask, is then copied or transferred onto the substrate under the pattern of the photoresist.

[0043] There are numerous techniques used by those skilled in the art to remove materials at various stages of creating a semiconductor structure. As used herein, these processes are collectively referred to as "etching". For example, etching techniques include wet etching, dry etching, chemical oxide removal (COR) etching, reactive ion etching (RIE), etc., all of which are known techniques for removing the selected materials when forming a semiconductor structure. Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. SC2 contains a strong acid such as hydrochloric acid and hydrogen peroxide. The techniques and applications of etching are well understood by those skilled in the art, and thus a more detailed description of such processes is not presented herein.

[0044] The overall manufacturing method and the structures formed thereby are novel, although the individual specific processing steps necessary to implement this method may utilize conventional semiconductor manufacturing techniques and conventional semiconductor manufacturing tools. These techniques and tools will be familiar to those of ordinary skill in the relevant art given the teachings of this specification. For example, those of ordinary skill in the art will be proficient in epitaxial growth, self-aligned contact formation, high-k metal gate formation, etc. The term "high-k" has a clear meaning to those of ordinary skill in the art in the context of a high-k metal gate (HKMG) stack and is not merely a relative term. Still further, one or more of the processing steps and tooling used to manufacture semiconductor devices are also described in several readily available publications, such as, for example, the following, all of which are incorporated herein by reference: James D. Plummer et al., "Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition", Prentice Hall, 2001, and P. H. Holloway et al., "Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices", Cambridge University Press, 2008. Although several individual processing steps are described herein, these steps are for illustrative purposes only, and it is emphasized that those of ordinary skill in the art may be familiar with several equally suitable alternative forms that may be applicable.

[0045] It should be understood that the various layers or regions or combinations thereof shown in the accompanying figures may not be drawn to exact scale. Still further, for ease of explanation, one or more semiconductor layers of the type commonly used in such integrated circuit devices may not be explicitly shown in a given figure. This does not imply that the semiconductor layers not explicitly shown are omitted in an actual integrated circuit device.

[0046] FIG. 25 is a schematic diagram of the backside interconnect 275 according to an aspect of the present invention. The interconnect may include a voltage supply rail VDD2404 coupled (at position "A") to the power supply 2402 and VDD271 of FIG. 24, a ground rail VSS2404 coupled (at position "B") to the ground terminal 2404 and VSS269 of FIG. 24, and a clock signal line 2406 coupled (at position "C") to the clock signal 2406 and clock signals 273, 273A of FIG. 24. FIG. 25 is a schematic diagram, and the elements 2402, 2404, 2406 can be at different wiring levels.

[0047] Considering the discussion so far, from a general perspective, the exemplary semiconductor structure will be understood to include a backside power rail (e.g., the power portion 2402 of the backside interconnect 275 having the connections as contemplated), a backside signal line (e.g., the signal portion 2406 of the backside interconnect 275 having the connections as contemplated), a first source / drain region (e.g., the left p-epi 243 in FIG. 17(A) or FIG. 23(A), or the corresponding n-epi in the case of an NFET), and a second source / drain region (e.g., the right p-epi 243 in FIG. 17(A) or FIG. 23(A), or the corresponding n-epi in the case of an NFET). Also included are at least one channel coupling the first and second source / drain regions (e.g., the nanosheet between the first and second S / D regions in FIG. 17(A) or FIG. 23(A)), and a gate adjacent to at least one channel (e.g., the gate surrounding the nanosheet in FIG. 17(A) or FIG. 23(A), and connected to the clock signals 273, 273A in FIG. 17(B) or FIG. 23(B)). The frontside connections 257, 259 are provided to the first source / drain region (in one or more embodiments, the source / drain region wiring 257, 259 to the BEOL wiring 263 includes signal connections rather than power connections). The power connections (e.g., the elements 257, 255, 271 in FIG. 17(D), FIG. 23(D), or the elements 257, 255, 269 in the case of an nFET) are provided from the backside power rail to the second source / drain region. The backside gate contact is provided from the gate to the backside signal line (e.g., the T-shaped portion of the element 273 with the gate in FIG. 17(B), or the element 273A in FIG. 23(B)).

[0048] In some cases, the gate has a certain length and the backside gate contact has a bottom dimension larger than the gate length. For example, refer to the consideration of the following dimensions X and Y.

[0049] In some cases, as seen in FIG. 17(B), the gate is a high-K metal gate and the backside gate contact includes the T-shaped portion of the high-K metal gate.

[0050] In some cases, the backside signal line is a backside clock signal line. In some embodiments, the backside gate contact includes a portion of the backside clock signal line extending towards the gate (e.g., the metal coming down from element 273A in FIG. 23(B)).

[0051] In another aspect, an exemplary semiconductor array structure includes a substrate 207 and a plurality of field effect transistors disposed on the substrate. Each FET includes a first source / drain region (e.g., the left p-epi 243 in FIGS. 17(A) or 23(A), or the corresponding n-epi in the case of an NFET), and a second source / drain region (e.g., the right p-epi 243 in FIGS. 17(A) or 23(A), or the corresponding n-epi in the case of an NFET). Each FET also includes at least one channel coupling the first and second source / drain regions (e.g., the nanosheet between the first and second S / D regions in FIGS. 17(A) or 23(A)), and a gate having a gate length X as seen in FIGS. 17(A) and 23(A) and adjacent to at least one channel (e.g., the gate surrounding the nanosheet in FIGS. 17(A) or 23(A), and connected to the clock signals 273, 273A in FIGS. 17(B) or 23(B)). For example, as seen in the top view of FIG. 5A, the plurality of field effect transistors are arranged in columns.

[0052] The array structure further includes a plurality of front signal lines (for example, a part of the BEOL wiring 263 connected to the VA (via for connecting the source / drain contact to the BEOL wiring) 259 in FIGS. 17(A) and 23(A)) on the front of the plurality of field effect transistors. In one or more embodiments, the source / drain region wirings 257, 259 to the BEOL wiring 263 include signal connections rather than power connections because the power is moved to the back surface / FEOL. Thus, a plurality of back power rails (for example, the power part of the back interconnect 275 according to FIG. 25 coupled to VSS 269 to n-epi and VDD 271 to p-epi in FIGS. 17(D) and 23(D)) on the back of the plurality of field effect transistors are also included. A plurality of back signal wirings (for example, the signal part of the back interconnect 275 connected to the elements 273, 273A in FIGS. 17(B) and 23(B)) are provided on the back of the plurality of field effect transistors. The plurality of front signal connections 257, 259 are provided from the plurality of front signal lines to the first source / drain region. The plurality of power connections (elements 257, 255, 271 in FIGS. 17(D), 23(D), or elements 257, 255, 269 in the case of nFET) are provided from the back power rail to the second source / drain region. The plurality of back gate contact connections (for example, the T-shaped part of the gate and the element 273 in FIG. 17(B), or the element 273A in FIG. 23(B)) are provided from the back signal wiring to the gate, and each of the back gate contact connections has a bottom dimension Y larger than the gate length X as seen in FIGS. 17(B) and 23(B).

[0053] In some cases, the gates of the plurality of field effect transistors include high-K metal gates, and the plurality of back gate contact connections include the T-shaped part of the high-K metal gate as seen in FIG. 17(B). In some cases, the back signal wiring includes a back clock signal wiring. In some cases, the plurality of back gate contact connections include a part of the back clock signal wiring extending towards the gate (for example, the metal coming down from the element 273A in FIG. 23(B)).

[0054] For example, referring to FIG. 5A, in one or more embodiments, the first adjacent pair of the columns of transistors is n-type 109, and the second adjacent pair of the columns of transistors is p-type 111. In some cases, the back-side clock signal wiring 273 (which also applies to 273A) is located between corresponding ones of the n-type columns and the p-type columns. In some instances, the back-side power connection and the back-side power rail are located between pairs of n-type columns (e.g., VSS269) and between pairs of p-type columns (e.g., VDD271).

[0055] In one or more embodiments, the channel includes a nanosheet channel region (e.g., the nanosheet between the first and second S / D regions in FIGS. 17(A) or 23(A)), and the gate includes an all-around gate (e.g., the gate surrounding the nanosheet in FIGS. 17(A) or 23(A), and connected to the clock signals 273, 273A in FIGS. 17(B) or 23(B)).

[0056] Referring to FIG. 24, in one or more embodiments, the array structure further includes a first signal source (e.g., clock signal 2406) coupled to a plurality of back-side signal wirings, a logic signal source 2408 coupled to a plurality of front-side signal lines, and a power source (e.g., power source 2402 coupled to VDD and ground terminal 2404 coupled to VSS) coupled to a plurality of back-side power rails. Element 2400 generally represents an individual device or an array of devices according to any of the disclosed embodiments.

[0057] In another aspect, referring to FIGS. 2A-17(D), an exemplary method of forming a semiconductor structure, as seen in FIG. 3, includes defining n-type and p-type active regions in a nanosheet stack on a substrate 203 and, as seen in FIG. 4, forming a trench isolation (STI) region 229 between the active regions (as shown, in one or more embodiments, while located between the active regions, the STI does not extend to the top of the nanosheet stack). Note that the active regions are referred to as n-type and p-type for convenience. It should be understood that in one or more embodiments, the n-type and p-type source / drain regions will be epitaxially grown later. Referring to FIGS. 5A-5B-5C(C), one or more embodiments further include forming a back-gate contact via 233 in the trench isolation (STI) region 229 in the space between the n-type active region and the p-type active region.

[0058] Referring to FIGS. 6(A)-7(D), the exemplary method further includes forming a dummy gate 235 and, referring to FIGS. 8(A)-8(D), also includes forming a gate spacer 241. As best seen in FIGS. 7(B) and 8(B), the bottom portion 236 of the back-gate contact via (note that in the example it is in the shape of a "T") is filled with the dummy gate material of the dummy gate 235. As described elsewhere, FIGS. 8(A)-8(D) show the structure of FIGS. 7(A)-7(D) after the formation of the gate spacer 241, the recessing of the nanosheets, the formation of the inner spacer 239, and the epitaxial growth of the p-type source / drain region 243 and the n-type source / drain region 245. As best seen in FIG. 8(B), the spacer 241 is in the thin vertical portion of the "T" and extends laterally to the same thickness as the protruding horizontal bar of the "T". In the final structure, the region 236 is filled with an HKMG material as described later, and the resulting region 253 is separated from the FEOL structure by the gate spacer 241.

[0059] Referring to FIGS. 9(A) - 9(D), the method further includes forming a replacement high - k metal gate 249 such that the dummy gate is removed and the back - side gate contact via is filled with the high - k metal gate material 253 of the high - k metal gate adjacent to the bottom surface of the gate (such that the high - k metal gate material 253 replaces the dummy material 236). As considered elsewhere, to move from the structure of FIGS. 8(A) - 8(D) to the structure of FIGS. 9(A) - 9(D), the sacrificial a - Si portions of the dummy gate 235 and the sacrificial nanosheets 209, 211, 213, 215 are selectively removed, a conformal high - k metal gate stack is formed, the cavity for the gate cut 251 is patterned and etched, the cavity is filled with an insulating material, and the gate cut 251 is formed. Thus, FIGS. 9(A) - 9(D) show the resulting structure from these operations.

[0060] Referring to FIGS. 10(A) - 10(D), the method further includes forming back - end - of - line wiring 263 on the front surface of the resulting structure opposite the substrate. In particular, FIGS. 10(A) - 10(D) show the structure of FIGS. 9(A) - 9(D) after forming middle - of - line (MOL) contacts, back - end - of - line (BEOL) interconnects, and carrier - wafer bonding. Note the VBPR (via for connection to the back - side power rail) 255, source / drain contact (CA) 257, VA (via connecting the source / drain contact to the BEOL wiring) 259, VB (via connecting the gate to the BEOL wiring) 261, BEOL wiring 263, and carrier wafer 265.

[0061] Referring to FIGS. 11(A) - 17(D), the method further includes forming a back - side (substrate - side) signal line (e.g., a clock signal 273) that connects to the HKMG material 253 within the back - side gate contact via.

[0062] In some cases, referring to FIGS. 8(A) - 8(D), the method further includes growing p-type 243 and n-type 245 source / drain regions in p-type and n-type active regions, with the nanosheets of the nanosheet stack forming a channel therebetween. This defines a plurality of p-type field effect transistors, each including first and second corresponding ones of the p-type source / drain regions, and a plurality of n-type field effect transistors, each including first and second corresponding ones of the n-type source / drain regions. Further steps, as seen in FIGS. 16(A) - 16(D), include forming a backside power rail that connects the second corresponding ones of the p-type source / drain regions and the second corresponding ones of the n-type source / drain regions. Note each of the backside power elements (VSS 269, VDD 271) connected to the S / D epitaxy.

[0063] In some cases, referring to FIGS. 10(A) - 10(D), a further method step includes forming a front side signal element (e.g., VA 259) that connects the first corresponding ones of the p-type source / drain regions and the first corresponding ones of the n-type source / drain regions.

[0064] In yet another aspect, referring to FIGS. 3 to 5B-5C (C), and further to FIGS. 18(A) to 23(D), another exemplary method of forming a semiconductor structure, as seen in FIG. 3, includes defining n-type and p-type active regions in a nanosheet stack on a substrate 203, and as seen in FIG. 4, forming a trench isolation (STI) region 229 between the active regions (as shown, in one or more embodiments, while located between the active regions, the STI does not extend to the top of the nanosheet stack). Note that the active regions are referred to as n-type and p-type for convenience. It should be understood that in one or more embodiments, the n-type and p-type source / drain regions are epitaxially grown at a later time. Referring to FIGS. 5A to 5B-5C (C), one or more embodiments further include forming a back gate contact via 233 in the trench isolation (STI) region 229 in the space between the n-type active region and the p-type active region.

[0065] Referring to FIGS. 18(A) and 18(B), the method further includes filling the back gate contact via with a sacrificial back gate contact material (e.g., silicon nitride (SiN) 501) and recessing the sacrificial back gate contact material. For example, the sacrificial back gate contact material can be recessed to the same height as the bottom surface of the nanosheet.

[0066] Referring to FIGS. 19(A) to 19(D), the method further includes forming a dummy gate 235 and a gate spacer 241 such that the bottom portion of the back gate contact via contacts the dummy gate material of the dummy gate 235 and is filled with the sacrificial back gate contact material 501. In the example of FIGS. 19(A) to 19(D), the spacer 241 also has a bottom portion adjacent to the sacrificial back gate contact material 501.

[0067] Referring to FIGS. 20(A) - 20(D), the method still further includes forming a replacement high - K metal gate 249 such that the dummy gate is removed and the bottom portion of the back - side gate contact via contacts the high - K metal gate material of the high - K metal gate 249 and is filled with a sacrificial back - side gate contact material 501. As a result, an intermediate result structure similar to that shown in FIGS. 9(A) - 9(D) is obtained.

[0068] Referring again to FIGS. 20(A) - 20(D), the method further includes forming back - end - of - line wiring 263 on the front side of the resulting structure opposite the substrate. In particular, FIGS. 20(A) - 20(D) show the structure of FIGS. 19(A) - 19(D) after forming middle - of - line (MOL) contacts, back - end - of - line (BEOL) interconnects, and carrier wafer bonding. Note VBPR (via for connection to back - side power rail) 255, source / drain contact (CA) 257, VA (via connecting source / drain contact to BEOL wiring) 259, VB (via connecting gate to BEOL wiring) 261, BEOL wiring 263, and carrier wafer 265.

[0069] As best seen in FIG. 22(B), the method further includes removing the sacrificial back - side gate contact material 501. In this example, the adjacent portion of the gate spacer 241 is also removed. The resulting void is denoted as 500.

[0070] Referring to FIGS. 21(A) - 23(D), the method further includes forming a back - side (substrate - side) signal line (e.g., clock signal 273A) that connects to the HKMG material 249 within the back - side gate contact via through the region 500 where the sacrificial back - side gate contact material 501 has been removed, as best seen in FIG. 23(B).

[0071] In some cases, referring to FIGS. 19(A) - 19(D), the method further includes growing p - type 243 and n - type 245 source - drain regions in p - type and n - type active regions, with the nanosheets of the nanosheet stack forming a channel therebetween. Thereby, a plurality of p - type field - effect transistors each including first and second corresponding ones of the p - type source - drain regions and a plurality of n - type field - effect transistors each including first and second corresponding ones of the n - type source - drain regions are defined. Further steps as seen in FIGS. 23(A) - 23(D) include forming a back - side power rail connecting the second corresponding ones of the p - type source - drain regions and the second corresponding ones of the n - type source - drain regions. Note each of the back - side power rails (VSS269, VDD271) connected to the S / D epitaxy. In some cases, referring to FIGS. 20(A) - 20(D), further method steps include forming a front - side signal connection (e.g., VA259) connecting the first corresponding ones of the p - type source - drain regions and the first corresponding ones of the n - type source - drain regions.

[0072] One or more embodiments are implemented in the context of gate - all - around nanosheet technology, as shown in the non - limiting exemplary embodiments. Thus, in one or more embodiments, the NFETs and PFETs include a channel region in the form of a nanosheet channel region, and the NFETs and PFETs include a gate in the form of a gate - all - around. However, those skilled in the art will understand that the techniques disclosed herein can be applied to other types of transistors as well, for example.

[0073] FIG. 26 shows a computer system 12 that can be used to execute a design process, which will be described later with respect to FIG. 27. The computer system 12 can include, for example, one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including the system memory 28 to the processor 16. Element 16 can be connected to the bus using, for example, an appropriate bus interface unit.

[0074] Bus 18 represents one or more of several types of bus structures including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, such architectures can include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0075] The computer system / server 12 typically includes various computer system readable media. Such media can be any available media that is accessible by the computer system / server 12 and includes both volatile and nonvolatile media, removable and non-removable media.

[0076] System memory 28 can include a computer system readable medium in the form of volatile memory, such as random access memory (RAM) 30 or cache memory 32 or both. Computer system / server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 can be provided to read from and write to a non-removable non-volatile magnetic medium (not shown, typically called a “hard drive”). Although not shown, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a “floppy (R) disk”), and an optical disk drive for reading from and writing to a removable non-volatile optical disk such as a CD-ROM, DVD-ROM, or other optical media can be provided. In such examples, each can be connected to bus 18 by one or more data media interfaces. As further depicted and described below, memory 28 can include at least one program product having a set (e.g., at least one) of program modules configured to execute, for example, the design process shown in FIG. 27.

[0077] Programs / utilities 40 has a set (e.g., at least one) of program modules 42 and, by way of example and not limitation, can also be stored in memory 28, such as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or combinations thereof, can include an implementation of a networking environment. Program modules 42 generally execute software-implemented functions or methodologies or both.

[0078] The computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, a pointing device, a display 24, one or more devices that enable a user to interact with the computer system / server 12, or any device (e.g., a network card, a modem, etc.) or combination thereof that enables the computer system / server 12 to communicate with one or more other computing devices. Such communication can be carried out via the input / output (I / O) interface 22. Further, the computer system / server 12 can communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, via the network adapter 20. As depicted, the network adapter 20 communicates with other components of the computer system / server 12 via the bus 18. Although not shown, it should be understood that other hardware components or software components or both may be used with the computer system / server 12. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0079] Referring further to FIG. 26, note the processor 16, the memory 28, and the keyboard, pointing device, etc., which are the input / output interfaces 22 to the display 24 and the external device 14. As used herein, the term "processor" is intended to include any processing device, such as, for example, a CPU (central processing unit) or other form of processing circuit or both, including devices. Further, the term "processor" may refer to two or more individual processors. The term "memory" is intended to include memory associated with a processor or CPU, such as, for example, RAM (random access memory) 30, ROM (read only memory), fixed memory devices (e.g., hard drive 34), removable memory devices (e.g., diskettes), flash memory, etc. In addition, as used herein, the expression "input / output interface" is intended to assume an interface to one or more mechanisms (e.g., a mouse) for inputting data to the processing unit and one or more mechanisms (e.g., a printer) for providing results associated with the processing unit. The processor 16, the memory 28, and the input / output interface 22 can be interconnected, for example, via a bus 18 as part of the data processing unit 12. Suitable interconnections via, for example, the bus 18 can be provided to a network interface 20, such as a network card, for interfacing with a computer network, and to a media interface, such as a diskette or CD-ROM drive, for interfacing with a suitable medium.

[0080] Accordingly, computer software containing instructions or code for performing a desired task can be stored in one or more of the associated memory drives (e.g., ROM, fixed or removable memory), and when ready to be utilized, can be loaded partially or entirely (e.g., into RAM) and implemented by a CPU. Such software may include, but is not limited to, firmware, resident software, microcode, etc.

[0081] A data processing system suitable for storing or executing program code or both includes at least one processor 16 coupled directly or indirectly to a memory element 28 via a system bus 18. Memory elements can include local memory utilized during actual execution of program code, bulk storage, and cache memory 32 that provides temporary storage of at least some program code to reduce the number of times code must be retrieved from bulk storage during execution.

[0082] Input / output or I / O devices (including, but not limited to, keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through an intervening I / O controller.

[0083] A network adapter 20 can also be coupled to the system to enable the data processing system to be coupled to other data processing systems or remote printers or storage devices through an intervening private or public network. Currently available types of network adapters include modems, cable modems, and Ethernet(R) cards, among others. As used herein, including in the claims, "server" includes a physical data processing system (e.g., system 12 as shown in FIG. 26) executing a server program. It should be understood that such a physical server may or may not include a display and a keyboard. Further, FIG. 26 represents, for example, a conventional general-purpose computer that can be used to implement aspects of the design process described below.

[0084] Exemplary design processes used in semiconductor design, manufacturing, or testing, or combinations thereof

[0085] One or more embodiments of hardware according to aspects of the present invention can be implemented using techniques of semiconductor integrated circuit design simulation, testing, layout, or manufacturing, or combinations thereof. In this regard, FIG. 27 shows a block diagram of an exemplary design flow 700 used, for example, in the logical design, simulation, testing, layout, and manufacturing of semiconductor ICs. Design flow 700 includes a process, machine, or mechanism, or combinations thereof, for processing a design structure or device and generating a logically or otherwise functionally equivalent representation of a design structure, or device, or combinations thereof, as disclosed herein. The design structure processed or generated, or both, by design flow 700 may be encoded on a machine-readable storage medium such that when executed or otherwise processed on a data processing system, it includes data or instructions, or both, that generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of a hardware component, circuit, device, or system. The machine includes, but is not limited to, any machine used in the IC design process, such as a machine for designing, manufacturing, or simulating a circuit, component, device, or system. For example, the machine can include: a lithography apparatus, a machine and / or equipment for generating a mask (e.g., an electron beam writer), a computer and / or equipment for simulating a design structure, any device used in a manufacturing process or a test process, or any machine for programming a functionally equivalent representation of a design structure on any medium (e.g., a machine for programming a programmable gate array).

[0086] The design flow 700 may vary depending on the type of representation to be designed. For example, the design flow 700 for building an application specific integrated circuit (ASIC) may be different from the design flow 700 for designing standard components, or the design flow 700 for instantiating the design into a programmable array (e.g., a programmable gate array (PGA) or a field programmable gate array (FPGA) provided by Altera(R) Inc. or Xilinx(R) Inc.).

[0087] FIG. 27 shows a plurality of such design structures, preferably including an input design structure 720 processed by a design process 710. The design structure 720 may be a logic simulation design structure generated and processed by the design process 710 to generate a logically equivalent functional representation of a hardware device. Additionally or alternatively, the design structure 720 may include data or program instructions or both that generate a functional representation of the physical structure of a hardware device when processed by the design process 710. Whether representing functional design features or structural design features or both, the design structure 720 can be generated using electronic computer-aided design (ECAD) as implemented by a core developer / designer. Once encoded on a gate array or storage medium, the design structure 720 is accessed and processed by one or more hardware modules and / or software modules within the design process 710 to simulate or otherwise functionally represent an electronic component, circuit, electronic module or logic module, device, apparatus, or system. Thus, the design structure 720 can include a file or other data structure that includes human-readable or machine-readable or both source code, compiled structure, and computer-executable code structure that functionally simulates or otherwise represents circuit or other levels of hardware logic design when processed by a design data processing system or simulation data processing system. Such data structures can include hardware description language (HDL) design entities, or lower-level HDL design languages such as Verilog or VHDL, or higher-level design languages such as C or C++, or other data structures that are compliant with, or compatible with, or both, these.

[0088] The design process 710 preferably employs and incorporates hardware modules or software modules or both for synthesizing, transforming, or otherwise processing design / simulation functional equivalents of components, circuits, devices, or logical structures to generate a Netlist 780, which may include a design structure such as the design structure 720. The Netlist 780 may include a compiled or otherwise processed data structure representing a list of wirings, discrete components, logic gates, control circuits, I / O devices, models, etc., that describe connections to other elements and circuits in an integrated circuit design. The Netlist 780 can be synthesized using an iterative process in which the netlist 780 is resynthesized multiple times depending on the design specifications and parameters of the device. Similar to other types of design structures described herein, the netlist 780 can be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic disk drive, an optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or alternatively, the medium may be a system or cache memory, buffer space, or other suitable memory.

[0089] The design process 710 may include hardware and software modules for processing various input data structure types including the Netlist 780. Such data structure types may exist, for example, within the library elements 730 and may include a set of commonly used elements, circuits, and devices, including models, layouts, and symbol representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include the design specification 740, the characteristic data 750, the verification data 760, the design rules 770, and the test data file 785 which may include input test patterns, output test results, and other test information. The design process 710 may further include standard mechanical design processes such as process simulations of operations such as stress analysis, thermal analysis, mechanical event simulations, casting, molding, die press forming, etc. One of ordinary skill in mechanical design can understand the possible range of mechanical design tools and applications used in the design process 710 without departing from the spirit and scope of the present invention. The design process 710 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, placement and routing operations, etc.

[0090] The design process 710 incorporates logic design tools and physical design tools, such as an HDL compiler and a simulation model building tool, and processes the design structure 720, along with some or all of the depicted support data structures and, if applicable, additional machine design or data, to generate a second design structure 790. The design structure 790 exists on a storage medium or a programmable gate array in a data format used for data exchange of mechanical devices and structures (e.g., IGES, DXF, Parasolid XT, JT, DRG, or information stored in any other suitable format for storing or rendering such mechanical design structures). Similar to the design structure 720, preferably, the design structure 790 exists on a data storage medium and, when processed by an ECAD system, generates one or more files, data structures, or other computer-encoded data or instructions that result in a logically or otherwise functionally equivalent form, such as one or more of the IC designs disclosed herein. In one embodiment, the design structure 790 may include a compiled executable HDL simulation model that functionally simulates the devices disclosed herein.

[0091] The design structure 790 can also adopt a data format used for the exchange of integrated circuit layout data or symbol data format (e.g., information stored in GDSII (GDS2), GL1, OASIS, map file, or any other suitable format for storing such design data structures) or both. The design structure 790 can include, for example, symbol data, map files, test data files, design content files, manufacturing data, layout parameters, wiring, metal levels, vias, shapes, data of paths through the manufacturing line, and any other data required by the manufacturer or other designers / developers to create the devices or structures described herein. Thereafter, the design structure 790 can proceed to stage 795, such as proceeding to tape-out, being released for manufacturing, being released to a mask house, being sent to another design house, being sent back to the customer, etc.

[0092] Those skilled in the art will understand that the exemplary structures described above can be distributed in a raw form (i.e., a single wafer having multiple unpackaged chips), as bare dies, in a packaged form, or in a form incorporated as part of an intermediate or final product.

[0093] Integrated circuits according to aspects of the present invention can be employed in essentially any application or electronic system or both. Given the teachings of the present disclosure provided herein, those skilled in the art will be able to consider other implementations and applications of the embodiments disclosed herein.

[0094] The exemplification of the embodiments described in this specification is intended to provide a general understanding of various embodiments and is not intended to function as a complete description of all elements and features of the devices and systems that can utilize the circuits and techniques described herein. Given the teachings of this specification, many other embodiments will be apparent to those skilled in the art. Other embodiments can be utilized and derived therefrom without departing from the scope of the present disclosure, such that structural and logical substitutions and changes can be made. Also, note that in some alternative implementations, some of the steps of the exemplified methods may occur out of the order depicted in the figures. For example, two steps shown consecutively may actually be executed substantially simultaneously, or depending on the functionality involved, certain steps may sometimes be executed in the reverse order. Also, the drawings are merely illustrative and are not drawn to scale. Therefore, this specification and the drawings should be considered in an illustrative rather than a restrictive sense.

[0095] The embodiments in this specification are referred to, individually or collectively, or both, as "embodiments" merely for convenience and are not intended to limit the scope of this application to a single embodiment or inventive concept, even if multiple embodiments are actually shown. Thus, although specific embodiments have been illustrated and described herein, it should be understood that arrangements that achieve the same purpose can be substituted for the specific embodiments shown. That is, the present disclosure is intended to cover any adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those skilled in the art given the teachings of this specification.

[0096] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to be limiting. As used in this specification, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprise", "comprising", or both, when used in this specification, specify the presence of the stated feature, step, operation, element, or component, or combination thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, or groups thereof, or combinations thereof. Terms such as "bottom", "top", "above", "over", "under", "below", etc. are used to indicate the relative position of elements or structures with respect to each other, as opposed to relative height. In this specification, when a layer of a structure is described as "over" another layer, it should be understood that there may or may not be intervening elements or layers between the two specified layers. When a layer is "directly on" another layer, it indicates that the two layers are in direct contact. As used in this specification and the appended claims, the term "about" means within plus or minus 10%.

[0097] Corresponding structures, materials, acts, and equivalents of all means or step-plus-function elements in the following claims are intended to include any structures, materials, or acts for performing a function in combination with other claimed elements as specifically claimed. The description of various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit thereof. The embodiments have been chosen and described in order to best explain the principles and practical applications, and may enable others skilled in the art to appreciate various embodiments with various modifications suitable for the particular use contemplated.

[0098] The Abstract is provided to comply with 35 U.S.C. 1.76(b), which requires an abstract that will allow the reader to quickly grasp the nature of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it will be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, claimed subject matter may reside in less than all features of a single embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

[0099] Given the teachings provided herein, one skilled in the art will be able to contemplate other implementations and applications of the technology and disclosed embodiments. Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the exemplary embodiments are not limited to those precise embodiments, and that various other changes and modifications may be made by those skilled in the art without departing from the scope of the appended claims.

Claims

1. A semiconductor structure comprising: a backside power rail; backside signal lines; frontside signal lines; a first source / drain region; a second source / drain region; at least one channel coupling the first and second source / drain regions; a gate adjacent to the at least one channel; a frontside signal connection from the frontside signal lines to the first source / drain region; a power connection from the backside power rail to the second source / drain region; a backside gate contact from the gate to the backside signal lines and a semiconductor structure.

2. The semiconductor device according to claim 1, wherein the gate has a gate length and the backside gate contact has a bottom surface dimension larger than the gate length.

3. The semiconductor device according to claim 2, wherein the gate comprises a high-k metal gate and the backside gate contact comprises a T-shaped portion of the high-k metal gate.

4. The semiconductor device according to claim 2, wherein the backside signal lines include backside clock signal lines and the backside gate contact includes a portion of the backside clock signal lines extending towards the gate.

5. A semiconductor array structure comprising: a substrate; a plurality of field effect transistors disposed on the substrate, each including a first source / drain region, a second source / drain region, at least one channel coupling the first and second source / drain regions, and a gate having a gate length and adjacent to the at least one channel, the plurality of field effect transistors being arranged in columns; a plurality of frontside signal lines in front of the plurality of field effect transistors; a plurality of backside power rails behind the plurality of field effect transistors; a plurality of backside signal wirings behind the plurality of field effect transistors; a plurality of frontside signal connections from the plurality of frontside signal lines to the first source / drain region; a plurality of power connections from the backside power rails to the second source / drain region; a plurality of backside gate contact connections from the backside signal wirings to the gate, the backside gate contact connections each having a bottom surface dimension larger than the gate length and a semiconductor array structure.

6. The semiconductor array structure according to claim 5, wherein the gates of the plurality of field effect transistors include a high-K metal gate, and the plurality of back gate contact connections include a T-shaped portion of the high-K metal gate.

7. The semiconductor array structure according to claim 5, wherein the back signal wiring includes a back clock signal wiring, and the plurality of back gate contact connections include a part of the back clock signal wiring extending toward the gate.

8. The semiconductor array structure according to claim 7, wherein the first adjacent pair of the columns is n-type, and the second adjacent pair of the columns is p-type.

9. The semiconductor array structure according to claim 8, wherein the back clock signal wiring is located between corresponding ones of the n-type columns and the p-type columns.

10. The semiconductor array structure according to claim 9, wherein the power connection and the back power rail are located between pairs of the n-type columns and between pairs of the p-type columns.

11. The channel includes a nanosheet channel region, The semiconductor array structure according to claim 5, wherein the gate includes a full surround gate.

12. A first signal source coupled to the plurality of back signal wirings, A second signal source coupled to the plurality of front signal lines, The semiconductor array structure according to claim 5, further comprising a power supply coupled to the plurality of back power rails.

13. A method of forming a semiconductor structure, comprising: Defining n-type and p-type active regions in a nanosheet stack on a substrate, and forming a trench isolation (STI) region between the active regions; Forming a back gate contact via in the trench isolation (STI) region in a space between the n-type active region and the p-type active region; Forming the dummy gate and the gate spacer such that a bottom portion of the back gate contact via is filled with a dummy gate material of the dummy gate; Removing the dummy gate and forming a replacement high-K metal gate such that the back gate contact via is filled with a high-K metal gate material of the high-K metal gate adjacent to a bottom surface of the gate, to obtain a resulting structure; Forming back end of line wiring on a front surface of the resulting structure opposite to the substrate; Forming a back signal line connecting to the high-K metal gate material within the back gate contact via A method comprising the steps of.

14. Growing p-type and n-type source / drain regions in the p-type and n-type active regions, with channels formed between nanosheets of the nanosheet stack, and defining a plurality of p-type field-effect transistors each including first and second corresponding ones of the p-type source / drain regions, and a plurality of n-type field-effect transistors each including first and second corresponding ones of the n-type source / drain regions, Forming a backside power rail connected to the second corresponding one of the p-type source / drain regions and the second corresponding one of the n-type source / drain regions The method according to claim 13, further comprising.

15. The method according to claim 14, further comprising forming a front-side signal connection connected to the first corresponding one of the p-type source / drain regions and the first corresponding one of the n-type source / drain regions.

16. A method of forming a semiconductor structure, comprising: Defining n-type and p-type active regions in a nanosheet stack on a substrate, and forming a trench isolation (STI) region between the active regions; Forming a backside gate contact via in the trench isolation (STI) region in a space between the n-type active region and the p-type active region; Filling the backside gate contact via with a sacrificial backside gate contact material and recessing the sacrificial backside gate contact material; Forming the dummy gate and gate spacers such that a bottom portion of the backside gate contact via contacts a dummy gate material of a dummy gate and is filled with the sacrificial backside gate contact material; Removing the dummy gate and forming a replacement high-K metal gate such that the bottom portion of the backside gate contact via contacts a high-K metal gate material of a high-K metal gate and is filled with the sacrificial backside gate contact material to obtain a resulting structure; Forming back-end-of-line wiring on a front surface of the resulting structure opposite the substrate; Removing the sacrificial backside gate contact material to form a void; Forming a backside signal line connected to the high-K metal gate material through the void A method comprising.

17. Growing p-type and n-type source / drain regions in the p-type and n-type active regions, with channels formed between the nanosheets of the nanosheet stack, and defining a plurality of p-type field-effect transistors each including first and second corresponding ones of the p-type source / drain regions, and a plurality of n-type field-effect transistors each including first and second corresponding ones of the n-type source / drain regions, Forming a backside power rail connected to the second corresponding one of the p-type source / drain regions and the second corresponding one of the n-type source / drain regions The method according to claim 16, further comprising.

18. The method according to claim 17, further comprising forming a front-side signal connection connecting the first corresponding one of the p-type source / drain regions and the first corresponding one of the n-type source / drain regions.

19. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure including elements that, when processed by a computer-aided design system, generate a machine-executable representation of a semiconductor array structure, the HDL design structure being A substrate, A plurality of field-effect transistors disposed on the substrate, each including a first source / drain region, a second source / drain region, at least one channel coupling the first and second source / drain regions, and a gate having a certain gate length and adjacent to the at least one channel, the plurality of field-effect transistors being arranged in columns, the plurality of field-effect transistors, A plurality of front-side signal lines in front of the plurality of field-effect transistors, A plurality of backside power rails on the backside of the plurality of field-effect transistors, A plurality of backside signal wirings on the backside of the plurality of field-effect transistors, A plurality of front-side signal connections from the plurality of front-side signal lines to the first source / drain region, A plurality of power connections from the backside power rails to the second source / drain region, A plurality of backside gate contact connections from the backside signal wirings to the gate, the backside gate contact connections each having a bottom surface dimension larger than the gate length, the backside gate contact connections An HDL design structure including.

20. The design structure according to claim 19, wherein the gate of the plurality of field effect transistors includes a high-K metal gate, and the plurality of back gate contact connections include a T-shaped portion of the high-K metal gate.

21. The design structure according to claim 19, wherein the back signal wiring includes a back clock signal wiring, the plurality of back gate contact connections include a part of the back clock signal wiring extending toward the gate, the first adjacent pair of the columns is n-type, and the second adjacent pair of the columns is p-type.

22. The design structure according to claim 21, wherein the back clock signal wiring is located between corresponding ones of the n-type columns and the p-type columns.

23. The design structure according to claim 22, wherein the power connection and the back power rail are located between pairs of the n-type columns and between pairs of the p-type columns.

24. The channel includes a nanosheet channel region, The design structure according to claim 19, wherein the gate includes a perimeter gate.

25. a first signal source coupled to the plurality of back signal wirings, a second signal source coupled to the plurality of front signal lines, and a power supply coupled to the plurality of back power rails The design structure according to claim 19, further comprising.

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