Josephson RF envelope - DC converter

Abstract

A method of using a Josephson junction to convert an envelope of a radio frequency signal into a baseband control pulse includes the step of injecting a bias current into an envelope detection circuit. The bias current is specified based on first and second critical currents of a superconducting device within the envelope detection circuit. The first critical current corresponds to the envelope detection circuit not receiving an RF signal. The second critical current corresponds to the envelope detection circuit receiving a maximum RF signal. The method further includes the step of receiving a modulated radio frequency (RF) signal at the envelope detection circuit to detect an envelope of the received RF signal. The output of the envelope detection circuit is used to drive an output load. The output is generated based on the envelope detected by the envelope detection circuit.

Description

Technical Field

[0001] The present disclosure generally relates to quantum computing systems.

Background Art

[0002] In order to apply magnetic flux to a superconducting quantum interference device (SQUID), it is important to generate a spectrally broad baseband signal (DC - 1GHz). To incorporate a SQUID into a quantum computing (QC) architecture, generally both a radio frequency (RF) digital - to - analog converter (DAC) and a baseband DAC are included to generate both quantum bit control pulses and SQUID magnetic flux pulses. Currently, these signals are generated by digital - to - analog converters (DACs) at room temperature and sent via high - bandwidth cables to a dilution refrigerator (DR), where the signals then undergo dispersion and distortion due to the finite skin depth of the signal carrier and a slight impedance mismatch. This, combined with the technical overhead in the type, design, and bandwidth of the dual DAC, poses a significant challenge, especially when integrating electronic circuits inside the DR.

Summary of the Invention

[0003] Some embodiments provide a method of using Josephson junctions to convert the envelope of a radio frequency signal into a baseband control pulse. The system injects a bias current into an envelope detection circuit. The bias current is specified based on first and second critical currents of superconducting devices within the envelope detection circuit. The first critical current corresponds to the envelope detection circuit not receiving an RF signal. The second critical current corresponds to the envelope detection circuit receiving a maximum RF signal. The system receives an amplitude modulated RF signal at the input to the envelope detection circuit. The output of the envelope detection circuit is a voltage waveform that reconstructs the amplitude envelope of the detected RF signal. The output of the envelope detection circuit is configured to drive a suitable load. In some embodiments, the envelope detection circuit includes a plurality of Josephson junction (JJ) devices arranged in a parallel stack of one or more JJ devices for supplying an output current and an output voltage for the output load. The parallel stack of JJ devices is interconnected to a bias current source at a concentrated node. When the envelope detection circuit is not receiving an RF signal, the JJ devices are in a supercurrent state with zero static power dissipation. When the envelope detection circuit is receiving an RF signal, the JJ devices are in a voltage state.

[0004] In some embodiments, the output load includes a quantum processing unit (QPU) housed within a cryostat, and the envelope detection circuit is physically within the cryostat. The output of the envelope detection circuit may be used as a current pulse mutually coupled to a superconducting quantum interference device (SQUID). In some embodiments, the system applies a low pass filter to the output of the envelope detection circuit.

[0005] Since the static dissipation is almost zero, the envelope detector can be physically brought closer to the computing payload (e.g., inside the cryostat that houses the qubits). By bringing the envelope detector closer to the payload, the dispersion and distortion of the detected baseband signal are substantially reduced (e.g., minimized). Also, by using the JJ envelope detection circuit, it is not necessary to use separate digital - analog converters (DACs) for RF signals and baseband signals.

[0006] The foregoing summary is intended to serve as a brief introduction to some embodiments of the present disclosure. It is not intended to be an introduction or summary of all inventive subject matter disclosed in this document. The following detailed description and the drawings referred to in the detailed description further explain the embodiments described in the summary and other embodiments. Accordingly, the summary, detailed description, and drawings are provided to understand all embodiments described by this document. Furthermore, the claimed subject matter is not limited by the exemplary details of the summary, detailed description, and drawings, but rather is defined by the appended claims. This is because the claimed subject matter can be embodied in other specific forms without departing from the spirit of the subject matter.

Brief Description of the Drawings

[0007] The drawings are of exemplary embodiments. These drawings do not illustrate all embodiments. Other embodiments may be used additionally or instead. Details that may be obvious or unnecessary may be omitted for space savings or more effective illustration. Some embodiments may be practiced using additional components or steps, or without using all of the illustrated components and / or steps, or both. If the same numbers are shown in different drawings, they refer to the same or similar components or steps.

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[0014] In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the relevant teachings. It will be apparent, however, that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and / or circuits have been described at a relatively high level without detail in order to avoid unnecessarily obscuring aspects of the present teachings.

[0015] Some embodiments of the present disclosure provide a Josephson Junction (JJ) circuit used as an envelope detector to detect amplitude modulation of a high-frequency radio frequency (RF) incoming signal. Control of the amplitude modulation is performed via an RF trigger or input. The detected amplitude modulation is used as a baseband signal for a quantum computing payload (such as qubit control pulses and flux pulses for a SQUID system). The JJ circuit is current-biased to minimize its static dissipation. This allows the envelope detector to be physically closer to the computing payload (e.g., inside a cryostat housing qubits). Bringing the envelope detector closer to the payload substantially reduces (e.g., minimizes) the dispersion and distortion of the detected baseband signal.

[0016] FIG. 1 conceptually shows a quantum computing system 100 in which a JJ circuit is used as an RF envelope detector for extracting a baseband signal from an amplitude-modulated RF signal, in accordance with an exemplary embodiment.

[0017] As shown, a signal generator 105 at room temperature (T ~ 300 Kelvin) generates an RF signal 120. (The signal generator 105 may operate at other temperatures.) The RF signal 120 may be amplitude modulated according to a modulation signal 115 that may include control pulses or magnetic flux pulses to the quantum processing unit (QPU) 140. An RF envelope detector 110 receives the modulated RF signal 120, performs envelope detection, and outputs the detected envelope as a baseband signal 130. The RF envelope detector 110 is a JJ-based circuit that may operate at cryogenic temperatures (e.g., T < 4 Kelvin) and is current biased to operate in a supercurrent state when not receiving an RF signal, so that the quiescent dissipation is zero or near zero. The baseband signal 130 is then provided to the QPU 140. In one embodiment, the QPU 140 operates at millikelvin temperatures within a cryostat. Since the RF envelope detector 110 has zero quiescent dissipation, it can be physically placed near or inside the cryostat that houses the QPU 140. Thereby, the baseband signal 130 can be applied to the QPU 140 with substantially reduced (e.g., minimal) distortion and dispersion.

[0018] FIG. 2 is a diagram showing an exemplary JJ envelope detection circuit 200 that may be configured to have zero quiescent dissipation when not receiving an RF signal. In some embodiments, the JJ envelope detection circuit 200 is an implementation example of the RF envelope detector 110. As shown, the JJ envelope detection circuit 200 includes a bias current source 210, a JJ stack array 220, and input impedance 230 and output impedance 240. The JJ envelope detection circuit 200 receives an RF signal (e.g., RF signal 120 from the RF signal source 105) and reproduces the envelope of the incoming high-frequency (~GHz) signal as a baseband output current driven into a load (e.g., a 50-ohm system). A large output inductance

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[0019] It is known that individual JJs generate a small voltage and have a very limited current supply capacity. When placed in a typical 50-ohm impedance environment, this small voltage and current supply capacity may limit the performance of the device. To avoid such limitations, the JJ envelope detection circuit 200 employs a number of JJs to meet the voltage and current requirements. As shown, the JJ stack array 220 includes a plurality of JJ paths stacked in series in parallel. The JJs stacked in series serve to increase the voltage when the JJ switches to a finite voltage state during RF application. The parallel stack of JJs serves to increase the overall current supply capacity of the device.

[0020] The JJ stack array 220 is an array of one or more parallel stacks of nominally identical JJs connected in series. The stacks of different JJs are connected to a centralized node 205, at which a DC current is injected from a bias current source 210 to bias the array of stacks up to 90%+ of the critical current of the individual JJs. The output voltage increases by stacking JJ devices. The characteristic voltage of each JJ is Vc~700uV. For a 50-ohm load, more than 70 JJs can be connected in series per stack. The stacks of JJs jointly supply the output current to the load in parallel. Thus, for example, to supply ~1mA, 70 JJs are required per series stack to generate the 50mV voltage necessary to drive a 50-ohm load. To supply the appropriate current, multiple parallel stacks are required such that the supply load is shared. For example, when implementing 10 parallel stacks, each stack only needs to supply 100uA, significantly reducing the supply load of each stack. The voltage generated by the JJ stack is configured to supply a current (~1mA) to a load / environment with Z = 50 ohms and corresponds to SQUIDs coupled to each other (1~2pH). Thereby, the output voltage of the JJ envelope detection circuit 200 can drive a significant output current and operate as an RF-DC flux bias circuit.

[0021] The amplitude-modulated RF is supplied to the JJ stack array 220 via a secondary high-bandwidth line 215 connected to the centralized bias point 205. As described above, the JJ envelope detection circuit 200 is biased such that the static power dissipation is zero, i.e., when no RF signal enters the JJ envelope detection circuit 200, the JJ devices within the JJ stack array 220 are in a supercurrent state where they can conduct current without power dissipation.

[0022] In some embodiments, the JJ envelope detector circuit 200 is DC biased according to or near the critical current of the JJ devices in the JJ stack array 220. The critical current is defined as the maximum supercurrent that a superconducting device can carry before switching from the supercurrent state to the normal conducting state (the state in which the JJ device operates according to the voltage regime). Since the JJ stack array 220 is current biased near the critical current, the JJs in the stack array 220 remain in the supercurrent state when there is no RF signal and switch to the normal voltage state when receiving an RF signal.

[0023] JJs biased with current near the critical current respond to an amplitude-modulated RF input signal by switching to the voltage state due to a decrease in the critical current. In one embodiment, when an amplitude-modulated RF wave is applied to the JJ, the critical current of the JJ decreases in proportion to the time-dependent amplitude of the RF signal. In combination with the current bias, this decrease in the critical current forces the JJ to switch to a finite voltage state where the amplitude of the voltage output is proportional to the amplitude of the incoming RF signal. Thereby, the envelope detector circuit 200 extracts the envelope of the RF input.

[0024] Thus, when the bias current source 210 provides a DC current that biases the JJ stack array 220 near the critical current of the JJ stack, the RF signal 120, together with the DC bias current, forces the JJ stack array 220 into a voltage regime where the output voltage 130 of the JJ envelope detector circuit 200 mirrors that of the RF amplitude envelope. Thereby, the JJ stack array can operate as an envelope detector in its voltage state.

[0025] FIG. 3 conceptually shows the voltage-current behavior of the JJ stack array 220 biased near the critical current. FIG. 3 includes two I-V plots 301 and 302. The I-V plot 301 shows the voltage-current behavior when the envelope detection circuit 200 is not receiving an RF signal. The I-V plot 302 shows the voltage-current behavior when the envelope detection circuit 200 is receiving the maximum RF signal (having the maximum amplitude). As shown in the I-V plots, the JJ circuit enters a supercurrent state with no voltage drop (no power dissipation) when the bias current is below the critical current, and enters a voltage state with a voltage drop (with power dissipation) when the bias current exceeds the critical current. The critical current I cA (when no RF signal is input) is the critical current I cB is higher than that (when the RF signal has the maximum amplitude), and the critical current decreases in the presence of an RF input signal.

[0026] In some embodiments, the DC bias current I (such as generated by the bias current source 210) bias is, I cA >I bias >I cB is selected to be in the range. In other words, the JJ stack array 220 is biased to enter a supercurrent state when no RF signal is present and a voltage state when the RF signal is greater than a threshold amplitude. Thereby, the JJ envelope detection circuit 200 can detect the envelope of the target RF signal and output the detected envelope as the output voltage. Also, thereby, the quiescent power dissipation of the JJ envelope detection circuit 200 when no RF signal is present can be made zero.

[0027] FIG. 4 is a diagram showing the decrease in the critical current of a Josephson junction device due to the presence of an RF signal. As described above, when an amplitude-modulated RF wave is applied to the JJ, the critical current of the JJ decreases in proportion to the time-dependent amplitude of the RF signal. FIG. 4 shows an amplitude-modulated RF signal 400 and an I-V graph 405 of a JJ device (e.g., JJ stack array 220) that has received the RF signal. In FIG. 4, four different envelope amplitudes 410, 411, 412, 413 of the RF signal 400 are identified. The I-V chart 405 shows four different I-V curves 420-423 corresponding to the four amplitudes 410-413, respectively. Specifically, each I-V curve represents the measured values of the JJ device when an RF tone of the corresponding amplitude is applied. The different envelope amplitudes 410-413 also correspond to four different critical current levels Ic0, Ic1, Ic2, and Ic3, respectively. Ic0 represents the original critical current level when there is no RF signal (amplitude 410). Ic1, Ic2, and Ic3 represent the critical currents decreased due to the RF signals of amplitudes 411, 412, and 413, respectively.

[0028] FIG. 5 is a diagram showing a simulated incoming RF signal and a corresponding output signal generated based on the detected envelope. FIG. 5 shows voltage or current graphs 501, 502, and 503 in three time domains. Graph 501 shows an example of an amplitude-modulated 5 GHz signal applied to the JJ envelope detection circuit 200 (e.g., RF signal 120 in FIG. 1). Graph 502 shows the output of the JJ envelope detection circuit 200 to a 50 ohm load. This output is generated based on the detected envelope of the example incoming modulated RF signal. In some embodiments, a low-pass filter can be applied to remove high-frequency components from the output of the JJ envelope detection circuit 200. Graph 503 shows the simulated output after applying a 100 MHz low-pass filter. Therefore, the JJ envelope detection circuit 200 is something like a voltage source whose amplitude of the voltage driving the input load depends on the amplitude of the RF wave.

[0029] FIG. 6 conceptually illustrates a process 600 for generating control pulses for a quantum computing payload based on an incoming modulated RF signal using a JJ device, in accordance with an exemplary embodiment. In some embodiments, process 600 describes operations performed by a quantum computing system 100 that uses an envelope detection circuit to convert a modulated RF signal into a control pulse or a magnetic flux pulse to a SQUID.

[0030] The system injects a bias current (at block 610) into the envelope detection circuit. The bias current may be specified based on first and second critical currents of superconducting devices within the envelope detection circuit. The first critical current may correspond to the envelope detector not receiving an RF signal. The second critical current may correspond to the envelope detection circuit receiving a maximum RF signal. The critical current of the superconducting device in the envelope detection circuit decreases in proportion to the time-dependent amplitude of the RF signal. In some embodiments, the envelope detection circuit includes a plurality of Josephson junction (JJ) devices arranged as a parallel stack of one or more JJ devices for supplying an output current and an output voltage for an output load. The parallel stack of JJ devices is interconnected to a bias current source at a concentrated node.

[0031] The system determines (at block 620) whether the envelope detection circuit is receiving an RF signal in the envelope detection circuit. When the envelope detection circuit is not receiving an RF signal, the JJ devices in the envelope detection circuit remain in a supercurrent state (at block 630) with zero static power dissipation.

[0032] When the envelope detection circuit is receiving an RF signal, the JJ device in the envelope detection circuit switches to a normal voltage state (at block 640). The envelope detection circuit may detect the envelope of the amplitude-modulated RF signal (at block 650). Thereafter, the envelope detection circuit generates an output based on the envelope detected by the envelope detection circuit (at block 660). The system may apply a low-pass filter to the output of the envelope detection circuit (at block 665). The system drives an output load using the output of the envelope detection circuit (at block 670). The output load may include a quantum processing unit (QPU) housed within a cryostat, and the envelope detection circuit is physically within the cryostat. The output of the envelope detection circuit may be used as a magnetic flux pulse or a control pulse for a superconducting quantum interference device (SQUID).

[0033] The flowchart of FIG. 6 illustrates the operation of a possible implementation of a system, method, or computer program product according to various embodiments of the present disclosure. In this regard, each block in the flowchart can represent a module, segment, or portion of instructions for performing the specified operation. In some alternative implementations, the operations described in the blocks may occur out of the order described in FIG. 6. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or depending on the related operations, the blocks may be executed in the reverse order.

[0034] The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or a technical improvement found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

[0035] The descriptions of the various embodiments of the present teachings have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application, or the technical improvements made to the technologies found in the marketplace, or to enable other skilled artisans to understand the embodiments disclosed herein.

[0036] Although the above has described what is considered to be the best mode or other examples or both, it is understood that various modifications can be made therein, that the subject matter disclosed herein can be implemented in various forms and examples, and that the teachings can be applied to many uses, only some of which are described herein. The following claims are intended to claim any use, modification, and variation that falls within the true scope of the present teachings.

[0037] The components, steps, features, objects, benefits, and advantages described herein are merely illustrative. None of these, nor the descriptions associated with them, are intended to limit the scope of protection. Although various advantages have been described herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise specified, all measurements, values, ratings, positions, sizes, dimensions, and other specifications described herein, including the following claims, are approximate and not exact. They are intended to have a reasonable range consistent with the functions to which they relate and what is customary in the technical fields to which they relate.

[0038] Many other embodiments are also contemplated. These include embodiments having fewer, additional, and / or different components, steps, features, objects, benefits, and advantages. These also include embodiments in which the components and / or steps are arranged in different arrangements and / or orders.

[0039] The foregoing has been described in conjunction with exemplary embodiments, but it is understood that the term "exemplary" means merely an example and not the best or optimal. Except as described immediately above, nothing described or illustrated is intended to, nor should it be construed to, provide to the public any component, step, feature, object, benefit, advantage, or equivalent, whether or not within the scope of the claims.

[0040] It is to be understood that the terms and expressions used herein have the ordinary meaning ascribed to such terms and expressions in each respective field of inquiry and study, unless otherwise specifically defined herein. Relative terms such as first and second are used only to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual relationship or order between such entities or actions. The terms "comprises," "comprising," or other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not inherent to or explicitly listed in such process, method, article, or apparatus. An element preceded by "a" or "an" does not, without further constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0041] A summary of the disclosure is provided to enable a reader to quickly ascertain the nature of the technical disclosure. The summary is presented on the understanding that it is not to be used to interpret or limit the scope or meaning of the claims. Also, in the detailed description of the invention, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure should not be construed as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims represent, the subject matter of the invention lies in less than all of the features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the detailed description of the invention, and each claim stands on its own as a separately claimed subject matter.

Claims

1. An envelope detection circuit configured to receive an amplitude-modulated radio frequency (RF) signal and detect an envelope of the received RF signal; A bias current source configured to inject a bias current into the envelope detection circuit, where the bias current is specified based on first and second critical currents of a superconducting device within the envelope detection circuit; and An output load configured to receive an output of the envelope detection circuit generated based on the detected envelope A device comprising.

2. The device according to claim 1, wherein the envelope detection circuit comprises a plurality of Josephson junction (JJ) devices.

3. The device according to claim 2, wherein the plurality of JJ devices comprises a stack of series JJ devices for supplying an output voltage to the output load.

4. The plurality of JJ devices are arranged as a plurality of parallel stacks of JJ devices for supplying an output current to the output load; and The parallel stacks of JJ devices are interconnected to a bias current source at a concentrated node The device according to claim 3.

5. The device according to any one of claims 2 to 4, wherein the plurality of JJ devices are configured to be in a supercurrent state when no RF signal is being received by the envelope detection circuit.

6. The device according to any one of claims 2 to 5, wherein the plurality of JJ devices are configured such that static power dissipation is zero when no RF signal is being received by the envelope detection circuit.

7. The device according to any one of claims 2 to 6, wherein the plurality of JJ devices are configured to be in a voltage state when an RF signal is being received by the envelope detection circuit.

8. The device according to any one of claims 2 to 7, wherein the plurality of JJ devices are critically damped by a shunt resistor.

9. The device according to any one of the preceding claims, wherein the output load comprises a quantum processing unit (QPU) housed within a cryostat.

10. The device according to claim 9, wherein the envelope detection circuit is physically within the cryostat.

11. The device according to any one of the preceding claims, wherein the first critical current corresponds to the envelope detection circuit not receiving an RF signal, and the second critical current corresponds to the envelope detection circuit receiving an almost maximum RF signal.

12. The apparatus according to any one of the preceding claims, wherein the critical current of the superconducting device in the envelope detection circuit decreases in proportion to the time-dependent amplitude of the RF signal.

13. The apparatus according to any one of the preceding claims, further comprising a low-pass filter configured to filter the output of the envelope detection circuit.

14. The apparatus according to any one of the preceding claims, wherein the output of the envelope detection circuit is used as a magnetic flux pulse to a superconducting quantum interference device (SQUID).

15. Injecting a bias current into the envelope detection circuit, wherein the bias current is specified based on first and second critical currents of a superconducting device in the envelope detection circuit; Receiving a modulated radio frequency (RF) signal in the envelope detection circuit; Detecting an envelope of the received RF signal based on the received RF signal; and Driving an output load using the output of the envelope detection circuit, wherein the output is generated based on the envelope detected by the envelope detection circuit. A method comprising.

16. The method according to claim 15, wherein the envelope detection circuit comprises a plurality of Josephson junction (JJ) devices arranged as a parallel stack of one or more JJ devices for supplying an output current and an output voltage for the output load, wherein the parallel stack of JJ devices is interconnected to a bias current source at a concentrated node.

17. The plurality of JJ devices are in a supercurrent state with zero static power dissipation when the envelope detection circuit is not receiving an RF signal; The plurality of JJ devices are in a voltage state when the envelope detection circuit is receiving an RF signal. The method according to claim 16.

18. The method according to any one of claims 15 to 17, wherein the first critical current corresponds to the envelope detection circuit not receiving an RF signal, and the second critical current corresponds to the envelope detection circuit receiving a substantially maximum RF signal.

19. The method according to any one of claims 15 to 18, further comprising applying a low-pass filter to the output of the envelope detection circuit.

20. Using the output of the envelope detection circuit as a magnetic flux pulse to a quantum processing unit (QPU); accommodating the quantum processing unit (QPU) in a cryostat; and accommodating the envelope detection circuit in the cryostat The method according to any one of claims 15 to 19, further comprising the steps of.

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