Track plan for improving clock skew

Abstract

A track plan for improving clock skew arcs is disclosed. In one aspect, a node array includes a plurality of nodes having a clock distribution circuit configured to distribute a clock signal to each of the nodes. The clock signal propagates in at least a first direction between adjacent nodes. The node (202) further includes a track plan including a plurality of wires for transmitting communication signals propagating between the adjacent nodes. The plurality of wires includes a first wire (404) configured to transmit the first communication signal in a direction opposite to the first direction and a second wire (402) configured to transmit the second communication signal in the first direction, the first wire having a width greater than a width of the second wire.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 371,951, filed August 19, 2022, the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0002] The present disclosure relates generally to distributed clocks, and more particularly to techniques for reducing clock skew. [Background technology]

[0003] Artificial intelligence (AI) processors can be built using an array of processing nodes. The nodes that form the array can communicate with their neighboring nodes to perform processing tasks. A clock signal can be provided to each node, thereby synchronizing the nodes and enabling communication between them. One technique for providing a clock signal to an array of nodes is distributed clocking. Summary of the Invention [Means for solving the problem]

[0004] In one aspect, a node array having a track plan for improving clock skew is provided, the node array including: a first node including a computational circuit and a plurality of wires configured to transmit a communication signal generated by the first node to neighboring nodes of the node array; a second node being one of the neighboring nodes; and a third node being one of the neighboring nodes, wherein a clock signal propagates in a first direction from the second node to the first node to the third node; and wherein the plurality of wires of the first node include a first wire configured to transmit the first communication signal to the second node in a direction opposite to the first direction and a second wire configured to transmit the second communication signal to the third node in the first direction, wherein the first wire has a width greater than a width of the second wire.

[0005] In certain embodiments, the width of the first wire and the width of the second wire contribute to meeting the setup and hold times of the electronic components of the second and third nodes.

[0006] In a particular embodiment, the plurality of wires further includes a plurality of first wires extending in a first direction and including first wires, the plurality of first wires configured to transmit the plurality of first communication signals in a direction opposite to the first direction to a second node, and a plurality of second wires extending in the first direction and including second wires, the plurality of second wires configured to transmit the plurality of second communication signals in the first direction to a third node, wherein the plurality of first wires are interleaved with the plurality of second wires.

[0007] In a particular embodiment, the node array further includes a fourth node that is one of the neighboring nodes and a fifth node that is one of the neighboring nodes, wherein the clock signal propagates from the fourth node to the first node to the fifth node in a second direction perpendicular to the first direction, and wherein the plurality of wires of the first node further include a third wire extending in the second direction and configured to transmit a third communication signal to the fourth node in a direction opposite to the second direction, and a fourth wire extending in the second direction and configured to transmit a fourth communication signal to the fifth node in the second direction, wherein the third wire has a width greater than a width of the fourth wire.

[0008] In certain embodiments, each of the first node, second node, third node, fourth node, and fifth node has a length in a first direction greater than a length in a second direction, a width of the first wire greater than a width of the third wire, and a width of the second wire greater than a width of the fourth wire.

[0009] In a particular embodiment, the plurality of wires further includes a plurality of third wires extending in the second direction and including third wires, the plurality of third wires configured to transmit the plurality of third communication signals in a direction opposite to the second direction to a fourth node, and a plurality of fourth wires extending in the second direction and including fourth wires, the plurality of fourth wires configured to transmit the plurality of fourth communication signals in the second direction to a fifth node, wherein the plurality of third wires are interleaved with the plurality of fourth wires.

[0010] In certain embodiments, the clock signal has a substantially fixed delay as it propagates between neighboring nodes.

[0011] In certain embodiments, nodes of a node array are configured to operate with a timing offset relative to other nodes based on when the node receives a clock signal.

[0012] In another aspect, a node of a node array is provided having a track plan for improving clock skew within the node array, the node including a computational circuit configured to generate a communication signal and a plurality of wires configured to enable the communication signal to propagate to adjacent nodes of the node array, the node of the node array being configured to receive a distributed clock signal propagating in at least a first direction between adjacent nodes, the plurality of wires including a first wire configured to transmit a first communication signal in a direction opposite to the first direction and a second wire configured to transmit a second communication signal in the first direction, the first wire having a width greater than a width of the second wire.

[0013] In certain embodiments, the width of the first wire and the width of the second wire contribute to meeting setup and hold times of electronic components at the destination nodes of the first communication signal and the second communication signal, respectively.

[0014] In certain embodiments, the plurality of wires further includes a plurality of first wires extending in a first direction and including first wires, the plurality of first wires configured to transmit a plurality of first communication signals in a direction opposite the first direction, and a plurality of second wires extending in the first direction and including second wires, the plurality of second wires configured to transmit a plurality of second communication signals in the first direction, wherein the plurality of first wires are interleaved with the plurality of second wires.

[0015] In a particular embodiment, the clock signal further propagates in a second direction between adjacent nodes, the second direction being perpendicular to the first direction, and the plurality of wires further includes a third wire extending in the second direction and configured to transmit a third communication signal in a direction opposite to the second direction, and a fourth wire extending in the third direction and configured to transmit a fourth communication signal in the second direction, wherein the third wire has a width greater than a width of the fourth wire.

[0016] In certain embodiments, the node has a length in a first direction greater than a length in a second direction, a width of the first wire greater than a width of the third wire, and a width of the second wire greater than a width of the fourth wire.

[0017] In certain embodiments, the plurality of wires further includes a plurality of third wires extending in the second direction and including third wires, the plurality of third wires configured to transmit a plurality of third communication signals in a direction opposite the second direction, and a plurality of fourth wires extending in the second direction and including fourth wires, the plurality of fourth wires configured to transmit a plurality of fourth communication signals in the second direction, wherein the plurality of third wires are interleaved with the plurality of fourth wires.

[0018] In certain embodiments, the clock signal is further configured to be distributed with a substantially fixed delay as it propagates between adjacent nodes.

[0019] In certain embodiments, a node is configured to operate at a timing offset relative to other nodes in the node array based on when the node receives a clock signal.

[0020] In yet another aspect, a method of fabricating a node array is provided, the method including forming a first node including a computational circuit and a plurality of wires configured to transmit a communication signal generated by the first node to neighboring nodes of the node array, forming a second node that is one of the neighboring nodes, and forming a third node that is one of the neighboring nodes, wherein a clock signal propagates in a first direction from the second node to the first node to the third node, and the plurality of wires of the first node include a first wire configured to transmit the first communication signal to the second node in a direction opposite to the first direction and a second wire configured to transmit a second communication signal in the first direction, wherein the first wire has a width greater than a width of the second wire.

[0021] In a particular embodiment, the width of the first wire and the width of the second wire are selected to meet the setup and hold times of the electronic components of the second node and the third node.

[0022] In a particular embodiment, the plurality of wires further includes a plurality of first wires extending in a first direction and including first wires, the plurality of first wires configured to transmit the plurality of first communication signals in a direction opposite to the first direction to a second node, and a plurality of second wires extending in the first direction and including second wires, the plurality of second wires configured to transmit the plurality of second communication signals in the first direction to a third node, wherein the plurality of first wires are interleaved with the plurality of second wires.

[0023] In a particular embodiment, the node array further includes a fourth node that is one of the neighboring nodes and a fifth node that is one of the neighboring nodes, wherein the clock signal propagates from the fourth node to the first node to the fifth node in a second direction perpendicular to the first direction, and wherein the plurality of wires of the first node further include a third wire extending in the second direction and configured to transmit a third communication signal to the fourth node in a direction opposite to the second direction, and a fourth wire extending in the second direction and configured to transmit a fourth communication signal to the fifth node in the second direction, wherein the third wire has a width greater than a width of the fourth wire. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a schematic block diagram of an exemplary chip according to aspects of the present disclosure.

[0025] [Figure 2] 2 is a node clock level map associated with an exemplary node array, such as the node array of FIG. 1.

[0026] [Figure 3] FIG. 1 illustrates a portion of a node array including an exemplary clock propagation direction according to aspects of the present disclosure.

[0027] [Figure 4A] FIG. 2 illustrates exemplary clock and signal propagation directions for nodes of an array according to aspects of the present disclosure. [Figure 4B] FIG. 2 illustrates exemplary clock and signal propagation directions for nodes of an array according to aspects of the present disclosure.

[0028] [Figure 5A] FIG. 1 illustrates multiple exemplary signal propagation directions for nodes of an array according to aspects of the present disclosure. [Figure 5B] FIG. 1 illustrates multiple exemplary signal propagation directions for nodes of an array according to aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0029] The following description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein may be embodied in many different ways, for example, as defined and encompassed by the claims. This description refers to the drawings, where like reference numbers may indicate identical or functionally similar elements. It will be understood that the elements depicted in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that certain embodiments may include more elements and / or a subset of the elements depicted in the drawings. Furthermore, some embodiments may incorporate any suitable combination of features from two or more drawings. The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims.

[0030] Node Array Overview The present disclosure relates to clock distribution networks with clock signals arriving at different times at various nodes of a node array. Clocking with a fixed offset can be referred to as mesochronous clocking. Embodiments disclosed herein relate to mesochronous clock networks that can be modularly constructed from common circuitry. Clock signals in such networks can be locally low-skew and mesochronous at a coarser level.

[0031] Traditionally, clock signals are built and routed at the top level of a chip, adding effort, area, and power costs to the design. In such cases, clock distribution is custom designed at the top level of the chip. One way to do this is to route the clock signal with channels between sub-blocks, which can partition the design and consume area. Another way is to push the top-level clock down to the sub-blocks, which can slow the design process and cause identical parts of the design to fork, creating unique copies. With traditional approaches, the clock signal can arrive at all receivers at nearly the same time, allowing the circuit to operate in lockstep.

[0032] In the clock distribution network disclosed herein, the clock arrives at various receivers at different times. The clock signal can be distributed through a two-dimensional (2D) array of nodes such that the clock signal arrives at different nodes with different timing offsets. The clock distribution structure allows the arrival times to be grouped into a contour or wave across the die. At a local level, the circuits of a node can operate in lockstep. More globally, the circuits within different nodes of the node array can operate with timing offsets relative to each other. Peak currents from the power grid can be reduced by having different nodes perform calculations with timing offsets relative to each other. Such calculations can also improve the quality of the power signal. Computational circuits can be designed to handle differences in the arrival times of the clock signals.

[0033] The clock distribution network disclosed herein can simplify the top-level design and clock circuitry of a chip. Clocking with a fixed offset can be referred to as mesochronous clocking. The embodiments disclosed herein enable the construction of mesochronous clock networks in a modular manner from instances of common subsection designs. The clock signals of such networks can be locally low-skew and mesochronous at a coarser level.

[0034] The clock distribution disclosed herein can be applied to any suitable chip. In particular applications, the clock distribution disclosed herein can be applied to a chip that includes an array of smaller computational nodes. The computational nodes can be referred to as processors or cores. In this manner, a clock signal can form an arrival time wave across the array. Each computational node can receive a low-skew clock signal. The computational nodes of the array can be designed with only interfaces to adjacent computational nodes that account for the arrival time difference (skew) of the mesochronous clock phases. A chip with the clock distribution network disclosed herein can have, for example, a 35-phase mesochronous clock or a 41-phase mesochronous clock. The clock distribution described herein can be used with a square (equal rows and columns) node array or a rectangular node array with a different number of rows than columns.

[0035] FIG. 1 is a schematic block diagram of an exemplary chip 100 according to aspects of the present disclosure. The chip 100 may be an integrated circuit die. The chip 100 may include a node array 102 (also referred to as a compute node array) with a distributed clock, one or more serializer / deserializer (SerDes) clock blocks 104, a clock generator 106, and a clock controller 108. The SerDes clock block 104 may interface with other chips 100 to form an array of chips 100. In certain applications, the node array 102 may be included in a chip 100 in a system-on-wafer system, an array of chips 100 on a printed circuit board, etc. In certain applications, the node array 102 of FIG. 1 may be implemented in a system-on-wafer packaged in a wafer-level packaging structure. As shown in the embodiment of FIG. 1, the clock generator 106 may be implemented external to the node array 102. In some embodiments, the clock generator 106 may include a phase-locked loop (PLL). The clock generator 106 can be positioned to provide clock signals to the computational nodes at the corners of the node array 102. The clock controller 108 can also be implemented external to the node array 102. The nodes within the node array 102 can include inter-node interfaces that can be configured to communicate synchronously. The core-to-serializer / deserializer (SerDes) interface can be asynchronous.

[0036] In the node array 102 with distributed clocks of FIG. 1, each node can be an instance of a computational circuit (also referred to as a processing core or computational node). In certain applications, most of the nodes can be implemented as instances of a computational circuit, and one or more of the nodes can be implemented as instances of a different circuit. Each node of the node array 102 can include an instance of substantially the same clock distribution circuit, even if at least some other circuitry of the node differs from the circuitry of the other nodes. In the node array 102, the nodes can be tiled and abutted. For example, each node of the node array 102 can be self-contained and interconnected to adjacent node(s). At the same time, the node array 102 can be implemented without using top-level wires or gates. Thus, nodes can be configured to communicate with neighboring nodes using low-level wires over short connections. In some embodiments, the nodes of the node array 102 can be tiered without mirroring or rotation. In certain implementations, the nodes can be powered by a power supply line (V DD / V SS ) grid pitch. For example, the height and width of each node can be a multiple of the pitch of the power grid. The pitch of the power grid can be further aligned to the bump pitch.

[0037] Each node in the node array 102 may include a substantially identical instance of clock distribution circuitry. Nodes may be designed so that the output clock wires of a node align with the input clock wires of its neighboring nodes. Nodes may be tiered and tiled within the node array so that the clock output wires align with and electrically connect to the clock input wires of neighboring nodes located downstream to receive the clock signal. Such electrical connections allow the node array to be implemented without channels or top-level wiring for clock distribution. In certain embodiments, the fanout of the clock distribution circuitry may be balanced relative to inverters.

[0038] As described herein, a clock signal received at a root node may propagate from the root node to two neighboring nodes with one unit delay. The root node may be located at a corner of the node array 102. The unit of delay may be a fixed offset for a given node array. The unit of delay may correspond to a delay from buffering the clock signal (e.g., using an inverter) and a wire delay associated with the clock signal propagating to its neighboring node(s).

[0039] One of the two neighboring nodes may be located in the same row as the root node, and the other of the two neighboring nodes may be located in the same column as the root node. Neighboring nodes are adjacent to the root node. As an example, in FIG. 2, the neighboring nodes are located south and east of the root node. In this example, the clock signal continues to propagate from the two neighboring nodes of the root node in the node array to the neighboring nodes south and east with an additional unit delay. Such clock signal propagation continues through the clock distribution network in the node array 102 until the clock signal reaches a node in the node array 102 at the opposite corner from the root node. In this example, a signal routed from the originating node to a neighboring node north or west of the originating node may travel upstream and lose one unit delay in the node array 102, while a signal routed from the originating node to a neighboring node south or east may travel downstream and gain one unit delay in the node array 102. Signals traveling upstream may be routed faster than signals traveling downstream to account for the unit delay and meet setup and hold time specifications.

[0040] FIG. 2 is a node clock level map associated with an exemplary node array, such as the node array 102 of FIG. 1. The exemplary node array 102 has 18 rows and 18 columns. With 18 rows and 18 columns, there can be 324 nodes. As another example, the node array 102 can include 360 nodes arranged in rows and columns. This clock map includes the number of unit delays of the clock signal outputs of the nodes in the array. For example, the root node in the northwest corner has a 1 unit delay. Two neighboring nodes receiving a clock signal from the root node have a 2 unit delay. Nodes on the diagonal from southwest to northeast can have the same unit delay. Using the clock distribution circuitry described herein, the unit delays can be fixed offsets. Nodes along these diagonals can receive clock signals with substantially the same timing delay. These diagonals can be referred to as phases or waves. The phases correspond to different clock signal arrival times at the nodes. The clock signal distribution corresponding to the map in FIG. 2 can implement a mesochronous phase clock with 35 phases. The number of phases of the mesochronous clock signal in a node array having clock distribution circuitry as described herein may be the number of rows plus the number of columns minus one.

[0041] In particular embodiments, rather than a clock signal traversing node array 102 with a wave formed along the diagonal of the node array, the clock signal may propagate as a wave traversing node array 102 in a row-wise or column-wise manner. For example, rather than outputting a clock signal to the south and east, each node may output a clock signal to either the south or east. In this manner, the clock signal may propagate in a wave traveling south or east. However, aspects of the present disclosure are not limited to a particular direction of travel of the clock signal, and the clock signal may propagate along other diagonals and / or north or west.

[0042] The offsets in Figure 2 can be taken into account when routing signals between nodes. A signal routed from the originating node that generates the signal to a node to the north or west travels upstream and may lose one unit delay in the node array corresponding to Figure 2. A signal routed from the originating node to a node to the south or east travels downstream and may gain one unit delay in the node array corresponding to Figure 2. Signals traveling upstream can be routed faster than signals traveling downstream to account for the unit delay and meet setup and hold time specifications.

[0043] In particular embodiments, each node in the node array 102 may be an instance of a computational circuit. In certain applications, a majority of the nodes include instances of a computational circuit, while one or more of the remaining nodes include instances of a different circuit, such as a global node. A global node may refer to a node that does not include circuitry for performing processing tasks. In some implementations, both the computational node and the global node may include a communication interface that enables communication with neighboring nodes. In some implementations, the communication interface of a computational node may be the same as the communication interface of a global node.

[0044] Track plan to reduce clock skew Aspects of the present disclosure relate to track plans (also called wiring plans) for communication of signals between "clock offset-aware" nodes. The track plans described herein can improve upstream and downstream signal timing to reduce or eliminate skew resulting from the direction in which a signal travels relative to the direction in which a clock signal propagates.

[0045] Further aspects of the present disclosure provide techniques for defining metal track widths for highly replicated functional designs using mesh clock distribution. Certain electronic design automation tools enable track definition by selecting the width, spacing, and / or location of metal tracks using guidance from foundry design rule manuals. Aspects of the present disclosure also provide methods for defining a track plan for a functional design unit and assigning tracks to signals based on the direction of communication traffic. For example, signals traveling with (e.g., in the same direction as) a clock signal can be routed on tracks with smaller widths, while signals traveling relative to (e.g., in the opposite direction from) the clock signal can be routed on tracks with larger widths. Some or all of these signals can also be directionally interleaved with each other (alternating signal direction), which can reduce or minimize signal integrity issues (e.g., crosstalk). For example, in certain applications, all signals can be directionally interleaved.

[0046] Typically, when the direction of signal travel is not considered, the tracks along which communication signals travel can have substantially the same width and spacing. This width and spacing can be sized relative to the longest and / or shortest expected delay times. Such widths and spacing can be designed to meet setup and hold time specifications. The use of tracks for interleaved signals as described herein can further enable both higher frequency designs and reduced area used by the tracks by minimizing the size of the wires (also called tracks) used to meet design goals. This can reduce design costs and also allow more replicated blocks to fit into the same physical area, thereby improving performance per die.

[0047] FIG. 3 is a diagram illustrating a portion of a node array 102 including exemplary clock propagation directions according to aspects of the present disclosure. As shown in FIG. 3, the portion of the node array 102 includes a plurality of nodes 202. The nodes 202 are arranged in rows and columns. In some embodiments, a clock signal can propagate through the node array 102 in both vertical and horizontal directions. As shown in FIG. 3, the clock signal can propagate from top to bottom between the nodes 202 in a first direction 204, and the clock signal can propagate from left to right between the nodes 202 in a second direction 206. As shown in FIG. 3, the clock signal can propagate in two orthogonal directions within the node array 102. The clock signal can propagate through the node array 102 with a delay as shown in FIG. 2.

[0048] 4A and 4B are diagrams illustrating exemplary clock and signal propagation directions for nodes 202 of an array 102 according to an embodiment of the present disclosure. In particular, FIG. 4A illustrates horizontal wires configured to allow communication signals to propagate horizontally, and FIG. 4B illustrates vertical wires configured to allow communication signals to propagate vertically.

[0049] 4A, node 202 includes a first horizontal wire 402 configured to propagate communication signals between the nodes from left to right in second direction 206. Node 202 further includes a second horizontal wire 404 configured to propagate communication signals between the nodes from right to left in a direction opposite second direction 206. The arrows at the ends of horizontal wires 402 and 404 in the figure are for illustrative purposes only to indicate the signal propagation direction.

[0050] 4B, node 202 further includes a first vertical wire 406 configured to propagate communication signals between the nodes from top to bottom in first direction 204. Node 202 further includes a second vertical wire 408 configured to propagate communication signals between the nodes from bottom to top in a direction opposite first direction 204. The arrows at the ends of vertical wires 406 and 408 in the figure are for illustrative purposes only to indicate the signal propagation direction.

[0051] In certain embodiments, the first horizontal wire 402 and the second horizontal wire 404 can be formed in a different layer than the first vertical wire 406 and the second vertical wire 408. The vertical wires 406 and 408 extend 404 in a first direction 204 that is orthogonal to the second direction 206 in which the horizontal wire 402 extends.

[0052] Communication signals between nodes 202 are designed to arrive at a destination node 202 (e.g., abutting a neighboring node to the node 202 from which it originates) to meet setup and hold time specifications. As used herein, setup time generally refers to the minimum amount of time for an input to an electronic component to stabilize before a clock edge to ensure the component can read that input correctly. Hold time, as used herein, generally refers to the minimum amount of time for an input to an electronic component to stabilize after a clock edge to ensure the component can read that input correctly. Setup and hold times can be defined for any electrical component that reads an input signal at a timing defined by a clock signal, including, for example, flip-flops, registers, memories, processors, multiplexers, decoders, etc.

[0053] 4A along the second direction 206 (e.g., via the first horizontal wire 402), these signals have a longer propagation delay and can still meet setup and hold times because they are propagating in the second direction 206. The timing at which the communication signal stabilizes at the input of the node 202 to meet the setup and hold times of the node 202 depends on the time at which the clock signal arrives at the node 202. For example, because communication signals traveling along the first horizontal wire 402 propagate in the second direction 206, communication signals propagating along the first horizontal wire 402 can reach neighboring nodes at an earlier time than the clock signal propagating to the neighboring nodes along the second direction 206 than communication signals propagating along the second horizontal wire 404, which travel in the opposite direction of the clock signal.

[0054] Communication signals propagating in the opposite direction to the clock signal (e.g., along the second horizontal wire 404 or the second vertical wire 408) can be designed to have a shorter propagation delay compared to communication signals propagating in the same direction as the clock signal (e.g., along the first horizontal wire 402 or the first vertical wire 406). Thus, communication signals propagating in the same direction as the clock signal can be considered to have a clock propagation time advantage, while communication signals propagating in the opposite direction to the clock signal can be considered to have a clock propagation time penalty.

[0055] To provide longer propagation delays for communication signals propagating in the same direction as the clock signal and shorter propagation delays for communication signals propagating in the opposite direction to the clock signal, aspects of the present disclosure relate to techniques for adjusting wire delays to meet setup and hold time specifications in a node array 102 having a mesochronous clock.

[0056] The propagation delay along the communication wires 402-408 may be related to the RC delay of the wires 402-408. In some embodiments, the length of the wires 402-408 may be determined by the spacing of the nodes 202, and the height of the wires 402-408 may be determined by the process used to form the wires (e.g., lithography) and metal layers. Thus, the width of the wires 402-408 is one design parameter that can be used to adjust the propagation delay introduced by the wires 402-408. In some embodiments, the first horizontal wire 402 and the first vertical wire 406, which are used to communicate signals in the same direction as the clock propagation, can be formed with a relatively small width to increase the propagation delay, while the second horizontal wire 404 and the second vertical wire 408, which are used to communicate signals in the opposite direction to the clock propagation, can be formed with a relatively large width to decrease the propagation delay. The particular widths of the wires 402-408 can be formed so that signals propagating on the wires 402-408 meet the setup and hold times of electrical components within the destination node 202. In one embodiment, the widths of the wires 402-408 may be selected so that communication signals propagating on the wires 402-408 reach a substantial midpoint between the setup and hold times, although aspects of the present disclosure are not limited in this respect.

[0057] In certain embodiments, the nodes 202 may not have a square shape, and therefore the time it takes for a signal to travel vertically across a given node 202 may not be the same as the time it takes for the signal to travel horizontally across the node 202. For example, in certain embodiments, the node 202 may have a larger horizontal length than it does vertically. In these embodiments, the width of the first horizontal wire 402 may be larger than the width of the first vertical wire 406, and the width of the second horizontal wire 404 may be larger than the width of the second vertical wire 408. However, if the amount of delay introduced by the difference in the relative lengths of the horizontal and vertical lengths of the node is negligible, then wires traveling in the same direction relative to the clock signal, whether horizontal or vertical, may be substantially the same.

[0058] 5A and 5B illustrate a number of exemplary wires with signal propagation directions for nodes 202 of a node array 102 according to an embodiment of the present disclosure. Referring to FIG. 5A, each node 202 may be connected to its horizontal neighbors 202 by a number of horizontal communication wires 402 and 404. As shown in FIG. 5B, each node 202 may be connected to its vertical neighbors 202 by a number of vertical communication wires 406 and 408.

[0059] The proximity of adjacent communication wires 402-408 can lead to crosstalk between the wires 402-408. For example, if two signals are propagating in the same direction, induced currents between the wires 402-408 can result in crosstalk along the length of the wires 402-408. One technique for reducing this source of crosstalk is to space the communication wires 402-408 further apart. However, increasing the spacing between the communication wires 402-408 can reduce the amount of bandwidth available for communication between nodes 202. Therefore, aspects of the present disclosure relate to interleaving the communication wires 402-408 based on the direction of the signals propagating therethrough, as shown in FIGS. 5A and 5B. For example, each first horizontal wire 402 is adjacent to one or more second horizontal wires 404, and vice versa, such that signals on any two adjacent wires 402 and 404 propagate in opposite directions. Similarly, each first vertical wire 406 is adjacent to one or more second vertical wires 408, such that signals on any two adjacent wires 406 and 408 propagate in opposite directions, and vice versa. By interleaving the horizontal wires 402 and 404 and / or vertical wires 406 and 408 based on the direction of the signals propagating thereon, crosstalk between adjacent wires 402 and 404 and / or 406 and 408 may be limited to a single location along the propagation path (e.g., the point where opposing signals meet as they travel between nodes 202) in certain applications.

[0060] Depending on the implementation, thousands of wires 402-408 may be used across blocks of the stack plan design. These communication wires 402-408 may connect adjacent nodes 202 in the tiled and stepped node array 102. In particular embodiments, the communication wires 402-408 may connect nodes 202 in the lower levels of metal.

[0061] In some implementations, track plans for communication wires 402-408 can be generated in an automated manner by redefining the track plan in a design and assigning those tracks (e.g., wires 402-408) based on the directionality of the signals communicated thereon. Compared to other track plans, track plans designed in accordance with aspects of the present disclosure can achieve a greater number of wires 402-408 per length of a given node 202, which can translate into higher bandwidth designs. Furthermore, track plans can also address the inherent clock skew associated with mesochronous clocking in node arrays by adjusting the delays introduced by communication wires 402-408. Furthermore, the use of appropriately sized wires can also enable the use of higher frequency designs, which can provide lower latency and / or higher performance.

[0062] Furthermore, other attempts to address signal delay and / or crosstalk include designing wire sizes and / or spacing for worst-case scenarios. This results in wires that are wider than necessary to meet setup and hold time specifications, and lower wire density than can be achieved in accordance with aspects of the present disclosure. Compared to such designs, aspects of the present disclosure can provide higher bandwidth (e.g., by using a greater number of communication wires in the same area) and lower latency signals (e.g., by reducing crosstalk by directionally interleaving wires).

[0063] In some embodiments, the clock distribution network can be configured to propagate the clock signal row-wise or column-wise such that the clock signal does not traverse the node array 102 along a diagonal as shown in Figure 2. In these embodiments, the track plan can include wires having different widths when they extend in the same or opposite direction as the clock signal, as well as wires having substantially the same width when they extend in a direction perpendicular to the propagation direction of the clock signal.

[0064] ·Conclusion The foregoing disclosure is not intended to limit the disclosure to the precise form or particular field of use disclosed. Accordingly, various alternative embodiments and / or modifications to the disclosure, whether expressly described or implied herein, are contemplated in light of the present disclosure. Having thus described embodiments of the present disclosure, those skilled in the art will recognize that changes in form and detail can be made without departing from the scope of the present disclosure. Accordingly, the present disclosure is limited only by the scope of the claims.

[0065] In the foregoing specification, the present disclosure has been described with reference to specific embodiments. However, as will be understood by those skilled in the art, the various embodiments disclosed herein can be modified or embodied in various other ways without departing from the spirit and scope of the present disclosure. Accordingly, this description is to be considered illustrative and is for the purpose of teaching those skilled in the art how to make and use various embodiments of the disclosed ventilation vent assembly. It should be understood that the forms of the disclosure shown and described herein are to be construed as representative embodiments. Equivalent elements, materials, processes, or steps may be substituted for those typically shown and described herein. Furthermore, certain features of the present disclosure can be utilized independently of the use of other features, as will become apparent to those skilled in the art after having the benefit of this description of the present disclosure. The terms "including," "comprising," "incorporating," "consisting of," "have," "is," and the like, used to describe and claim the present disclosure, are intended to be construed in a non-exclusive manner, i.e., allowing for the presence of items, components, or elements not expressly recited. References to the singular are also to be construed as relating to the plural.

[0066] Furthermore, the various embodiments disclosed herein should be construed in an exemplary and explanatory sense and not as limiting the present disclosure in any way. All coupling references (e.g., attached, secured, coupled, connected, etc.) are used solely to aid the reader's understanding of the present disclosure and do not create any limitations with respect to the position, orientation, or use of the systems and / or methods disclosed herein, among other things. Accordingly, coupling references, if any, should be interpreted broadly. Moreover, such coupling references do not necessarily imply that two elements are directly connected to one another. Furthermore, all numerical terms, such as, but not limited to, "first," "second," "third," "primary," "secondary," "main," or any other conventional and / or numerical term, should be used solely as identifiers to aid the reader's understanding of the various elements, embodiments, variations, and / or modifications of the present disclosure, and do not create any limitations, particularly with respect to the order or priority of, or of, other elements, embodiments, variations, and / or modifications.

[0067] It will also be understood that one or more elements shown in the drawings / diagrams may be implemented in a more separated or integrated manner, or even removed or rendered inoperable in some cases, as may be useful depending on the particular application.

Claims

1. 1. A node array having a track plan for improving clock skew, the node array comprising: a first node including a computational circuit and a plurality of wires configured to transmit communication signals generated by the first node to neighboring nodes in the node array; a second node that is one of the neighboring nodes; a third node that is one of the neighboring nodes, wherein a clock signal propagates in a first direction from the second node to the first node to the third node; The plurality of wires of the first node include: a first wire configured to transmit a first communication signal to the second node in a direction opposite to the first direction; a second wire configured to transmit a second communication signal to the third node in the first direction; The node array, wherein the first wires have a width greater than a width of the second wires.

2. 2. The node array of claim 1, wherein the width of the first wire and the width of the second wire contribute to meeting setup and hold times of electronic components of the second node and the third node.

3. The plurality of wires a plurality of first wires extending in the first direction and including the first wire, the plurality of first wires configured to transmit a plurality of first communication signals to the second node in a direction opposite to the first direction; a plurality of second wires extending in the first direction and including the second wire, the plurality of second wires configured to transmit a plurality of second communication signals in the first direction to the third node; The node array of claim 1 , wherein the plurality of first wires are interleaved with the plurality of second wires.

4. The node array includes: a fourth node that is one of the neighboring nodes; a fifth node that is one of the neighboring nodes, wherein the clock signal propagates from the fourth node to the first node to the fifth node in a second direction perpendicular to the first direction; The plurality of wires of the first node include: a third wire extending in the second direction and configured to transmit a third communication signal to the fourth node in a direction opposite the second direction; a fourth wire extending in the second direction and configured to transmit a fourth communication signal in the second direction to the fifth node; The node array of claim 1 , wherein the third wire has a width greater than a width of the fourth wire.

5. each of the first node, the second node, the third node, the fourth node, and the fifth node has a length in the first direction greater than a length in the second direction; the width of the first wire is greater than the width of the third wire; The node array of claim 4 , wherein the width of the second wire is greater than the width of the fourth wire.

6. The plurality of wires a plurality of third wires extending in the second direction and including the third wire, the plurality of third wires configured to transmit a plurality of third communication signals to the fourth node in a direction opposite to the second direction; a plurality of fourth wires extending in the second direction and including the fourth wire, the plurality of fourth wires configured to transmit a plurality of fourth communication signals in the second direction to the fifth node; The node array of claim 4 , wherein the plurality of third wires are interleaved with the plurality of fourth wires.

7. The node array of claim 1 , wherein the clock signal has a substantially fixed delay as it propagates between neighboring nodes.

8. 10. The node array of claim 1, wherein nodes of the node array are configured to operate with a timing offset relative to other nodes based on when the node receives the clock signal.

9. A node of a node array having a track plan for improving clock skew within the node array, the node comprising: a computational circuit configured to generate a communication signal; a plurality of wires configured to allow the communication signals to propagate to adjacent nodes of the node array, the nodes of the node array being configured to receive a distributed clock signal propagating in at least a first direction between the adjacent nodes; The plurality of wires a first wire configured to transmit a first communication signal in a direction opposite to the first direction; a second wire configured to transmit a second communication signal in the first direction; The first wire has a width greater than a width of the second wire.

10. 10. The node of claim 9, wherein the width of the first wire and the width of the second wire contribute to meeting setup and hold times of electronic components at destination nodes of the first communication signal and the second communication signal, respectively.

11. The plurality of wires a plurality of first wires extending in the first direction and including the first wire, the plurality of first wires configured to transmit a plurality of first communication signals in a direction opposite the first direction; a plurality of second wires extending in the first direction and including the second wire, the plurality of second wires configured to transmit a plurality of second communication signals in the first direction; The node of claim 9 , wherein the plurality of first wires are interleaved with the plurality of second wires.

12. the clock signal further propagates between the adjacent nodes in a second direction, the second direction being perpendicular to the first direction; The plurality of wires a third wire extending in the second direction and configured to transmit a third communication signal in a direction opposite the second direction; a fourth wire extending in the third direction and configured to transmit a fourth communication signal in the second direction; The node of claim 9 , wherein the third wire has a width greater than a width of the fourth wire.

13. The node has a length in the first direction greater than a length in the second direction, the width of the first wire is greater than the width of the third wire; The node of claim 12 , wherein the width of the second wire is greater than the width of the fourth wire.

14. The plurality of wires a plurality of third wires extending in the second direction and including the third wire, the plurality of third wires configured to transmit a plurality of third communication signals in a direction opposite to the second direction; a plurality of fourth wires extending in the second direction and including the fourth wire, the plurality of fourth wires configured to transmit a plurality of fourth communication signals in the second direction; The node of claim 12 , wherein the plurality of third wires are interleaved with the plurality of fourth wires.

15. 10. The node of claim 9, further configured to distribute the clock signal with a substantially fixed delay as it propagates between adjacent nodes.

16. 10. The node of claim 9, wherein the node is configured to operate with a timing offset relative to other nodes in the node array based on when the node receives the clock signal.

17. 1. A method of manufacturing a node array, comprising: forming a first node including a computational circuit and a plurality of wires configured to transmit communication signals generated by the first node to neighboring nodes in the array of nodes; forming a second node that is one of the neighboring nodes; forming a third node that is one of the neighboring nodes, wherein a clock signal propagates in a first direction from the second node to the first node to the third node; The plurality of wires of the first node include: a first wire configured to transmit a first communication signal to the second node in a direction opposite to the first direction; a second wire configured to transmit a second communication signal in the first direction; The method, wherein the first wire has a width greater than a width of the second wire.

18. 18. The method of claim 17, wherein the width of the first wire and the width of the second wire are selected to meet setup and hold times of electronic components at the second node and the third node.

19. The plurality of wires a plurality of first wires extending in the first direction and including the first wire, the plurality of first wires configured to transmit a plurality of first communication signals to the second node in a direction opposite to the first direction; a plurality of second wires extending in the first direction and including the second wire, the plurality of second wires configured to transmit a plurality of second communication signals in the first direction to the third node; 20. The method of claim 17, wherein the plurality of first wires are interleaved with the plurality of second wires.

20. The node array includes: a fourth node that is one of the neighboring nodes; a fifth node that is one of the neighboring nodes, wherein the clock signal propagates from the fourth node to the first node to the fifth node in a second direction perpendicular to the first direction; The plurality of wires of the first node include: a third wire extending in the second direction and configured to transmit a third communication signal to the fourth node in a direction opposite the second direction; a fourth wire extending in the second direction and configured to transmit a fourth communication signal in the second direction to the fifth node; 18. The method of claim 17, wherein the third wire has a width greater than a width of the fourth wire.

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