Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes an insulating layer and an electrode portion arranged within the insulating layer, the electrode portion including a first electrode, a second electrode arranged on the first electrode, and first and second via electrodes arranged between the first electrode and the second electrode, the first via electrode being connected to the first electrode and the second electrode, and the vertical length of the second via electrode being smaller than the vertical length of the first via electrode.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board, and more particularly to a circuit board with improved adhesion between an insulating layer and an electrode portion, and a semiconductor package including the same. [Background technology]

[0002] As the performance of electrical / electronic products continues to improve, technologies for arranging more semiconductor elements on a semiconductor package substrate with limited size are being proposed and researched.However, since a typical semiconductor package is basically designed to mount only one semiconductor element, there is a limit to how much performance can be achieved.

[0003] Recently, semiconductor packages have been developed that use multiple substrates to arrange multiple semiconductor devices. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. This allows for efficient use of the mounting area of the semiconductor devices and allows for high-speed signal transmission through short signal transmission paths between the semiconductor devices.

[0004] Due to these advantages, the above-described semiconductor package is widely used in mobile devices and the like.

[0005] In addition, semiconductor packages applied to products that provide the Internet of Things (IOT), autonomous vehicles, and high-performance servers are becoming more highly integrated, and the number of semiconductor elements and / or the size of each semiconductor element are increasing, or the functional parts of the semiconductor element are being divided, expanding the concept to semiconductor chiplets.

[0006] This has made intercommunication between semiconductor devices and / or semiconductor chiplets important, leading to a trend toward placing an interposer between the substrate of a semiconductor package and the semiconductor device.

[0007] The interposer functions as a redistribution layer that gradually increases the width of a circuit pattern from the semiconductor device toward the semiconductor package in order to facilitate intercommunication between semiconductor devices and / or semiconductor chiplets or to interconnect the semiconductor device and a semiconductor package substrate, thereby enabling smooth transmission of electrical signals between the semiconductor device and a semiconductor package substrate having a circuit pattern that is relatively larger than the circuit pattern of the semiconductor device.

[0008] The interposer may have an area equal to or larger than the entire area of the semiconductor devices and / or semiconductor chiplets to mount the semiconductor devices and / or semiconductor chiplets as a whole, or may be disposed only in the area for interconnecting the semiconductor devices and / or semiconductor chiplets. That is, the area of the interposer may or may not increase as the number of semiconductor devices and / or semiconductor chiplets increases. However, as the number of semiconductor devices and / or semiconductor chiplets increases, the area of the substrate of the semiconductor package tends to increase.

[0009] Therefore, as the area of a semiconductor package increases, the area of the electrode portion also increases. In this case, when the area of the electrode portion increases, a problem occurs in that gas generated in the insulating layer in contact with the electrode portion is not sufficiently discharged. Furthermore, if the gas is not discharged, the surface of the electrode portion may swell due to the gas, which may cause the electrode portion to peel off from the insulating layer.

[0010] To address the above-described problems, the electrode unit of the related art may be provided with through-holes corresponding to gas exhaust ports for discharging gas. However, when through-holes are provided in the electrode unit, the area of the electrode unit is reduced by the through-holes, which reduces the rigidity of the semiconductor package. Furthermore, the reduced rigidity can cause the semiconductor package to warp significantly in a specific direction. Furthermore, the electrode unit of the semiconductor package may include an impedance matching unit that performs an impedance matching function. In this case, the impedance matching unit and / or the electrode unit adjacent to the impedance matching unit vertically or horizontally may not be provided with through-holes corresponding to the gas exhaust ports. For example, when through-holes are provided in the impedance matching unit and / or the electrode unit adjacent thereto, the through-holes can change the impedance matching characteristics, resulting in a problem of degraded electrical characteristics of the semiconductor package. Summary of the Invention [Problem to be solved by the invention]

[0011] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0012] Furthermore, the embodiments provide a circuit board with improved adhesion between an insulating layer and an electrode portion, and a semiconductor package including the same.

[0013] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0014] A circuit board according to an embodiment includes an insulating layer and an electrode portion arranged within the insulating layer, the electrode portion including a first electrode, a second electrode arranged on the first electrode, and first and second via electrodes arranged between the first electrode and the second electrode, and the vertical length of the second via electrode is smaller than the vertical length of the first via electrode.

[0015] In addition, the second via electrode is connected to the second electrode.

[0016] The second via electrode is spaced apart from the first via electrode in the horizontal direction.

[0017] The second via electrode extends from the second electrode toward the first electrode.

[0018] Moreover, the upper surface of the second via electrode is located on the same plane as the upper surface of the first via electrode, and the lower surface of the second via electrode is located higher than the lower surface of the first via electrode.

[0019] Moreover, the vertical length of the second via electrode is in the range of 30% to 70% of the vertical length of the first via electrode.

[0020] Moreover, the horizontal width of the second via electrode is smaller than the horizontal width of the first via electrode.

[0021] The second via electrode has a slope such that its horizontal width gradually changes as it moves away from the second electrode.

[0022] The first via electrode has a slope such that the width in the horizontal direction gradually changes from the second electrode toward the first electrode.

[0023] Moreover, the inclination of the second via electrode is the same as the inclination of the first via electrode.

[0024] Moreover, the first via electrode includes a first portion that overlaps the second via electrode in the horizontal direction within the insulating layer, and a second portion that does not overlap the second via electrode in the horizontal direction.

[0025] On the other hand, a semiconductor package according to an embodiment includes the circuit board and includes a connection portion disposed on a second electrode on the circuit board.

[0026] In addition, the second via electrode extends from the second electrode and is disposed within the insulating layer, the second electrode further includes a bonding portion that extends outside the insulating layer and does not horizontally overlap the insulating layer, and the connection portion is disposed on the bonding portion.

[0027] The bonding portion extends from the second electrode in a direction opposite to the direction in which the second via electrode extends.

[0028] The semiconductor package also includes an interposer disposed on the connection portion, the interposer including at least one of an active interposer and a passive interposer.

[0029] The semiconductor package further includes a semiconductor element disposed on the connection portion. [Effects of the Invention]

[0030] A circuit board according to an embodiment may include an insulating layer and an electrode portion disposed within the insulating layer. The electrode portion may include a first electrode, a second electrode disposed on the first electrode, and a first via electrode vertically connecting the first electrode and the second electrode. The electrode portion may also include a second via electrode extending vertically, and the vertical length of the second via electrode may be shorter than the vertical length of the first via electrode. The second via electrode extends vertically from the second electrode, thereby improving adhesion between the insulating layer and the electrode portion. For example, the second via electrode may function as an anchor that firmly fixes the electrode portion to the insulating layer. This improves adhesion between the insulating layer and the electrode portion. Therefore, the embodiment may solve the physical reliability problem of the electrode portion peeling off from the insulating layer.

[0031] At this time, gas may be generated from the insulating layer during the curing process. If the gas is not completely removed from the insulating layer, the electrode portion may bulge out of the insulating layer due to the gas. To solve this problem, through-holes may be formed in the electrode portion to allow gas to escape. However, if through-holes are provided in the electrode portion, this may change the electrical characteristics (e.g., impedance characteristics) of the electrode portion, which may result in electrical reliability issues. Furthermore, if through-holes are provided in the electrode portion, the area of the electrode portion is reduced by the area of the through-holes, which may reduce the rigidity of the circuit board and semiconductor package. This may result in significant warping of the circuit board and semiconductor package in a specific direction.

[0032] In contrast, the embodiment includes a second via electrode in the electrode portion, which can improve the adhesion between the electrode portion and the insulating layer while maintaining the rigidity of the circuit board and the semiconductor package without changing the electrical characteristics of the electrode portion, thereby improving the overall product reliability of the circuit board and the semiconductor package.

[0033] Furthermore, as the number of input and output terminals of semiconductor devices increases, the width and / or spacing of the terminals of semiconductor devices and / or semiconductor chiplets also tends to become narrower. Accordingly, the width and / or spacing of electrodes provided on circuit boards is also becoming finer. Furthermore, as the width and / or spacing of electrodes becomes finer, the contact area between the electrodes and the insulating layer decreases, which can lead to mechanical reliability issues such as the electrodes easily peeling off from the insulating layer. Furthermore, to reduce the width and / or spacing of electrodes, the insulating layer can contain a photosensitive material. For example, the photosensitive material can be a photoimageable dielectric (PID). The insulating layer containing the photosensitive material can be formed into the shape of the electrodes using a photolithography process, which can advantageously reduce the width and / or spacing of the electrodes. In this regard, the photosensitive material has a lower adhesion strength with the electrodes than a thermosetting material. As a result, the embodiment can solve the mechanical reliability problem of the electrodes peeling off from the insulating layer when the width and / or spacing of the electrodes is reduced by using the protrusions provided on the electrode portion or when the insulating layer contains a photosensitive material, thereby improving the overall product reliability of the circuit board and semiconductor package.

[0034] Furthermore, the rigidity of the insulating layer made of a photosensitive material may be lower than the rigidity of a thermosetting material with a reinforcing member. As a result, a circuit board with a photosensitive material may have a problem of large warping in a specific direction. In this case, in the embodiment, the rigidity of the circuit board can be improved by using protrusions provided on the electrodes, thereby preventing the circuit board and the semiconductor package from large warping in a specific direction. [Brief explanation of the drawings]

[0035] [Figure 1a] 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 1b] FIG. 10 is a cross-sectional view showing a semiconductor package according to a second embodiment. [Figure 1c]FIG. 10 is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 1d] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. [Figure 1e] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fifth embodiment. [Figure 1f] FIG. 10 is a cross-sectional view showing a semiconductor package according to a sixth embodiment. [Figure 1g] FIG. 13 is a cross-sectional view showing a semiconductor package according to a seventh embodiment. [Figure 2a] FIG. 1 is a cross-sectional view showing a circuit board according to a first embodiment. [Figure 2b] FIG. 10 is a cross-sectional view showing a circuit board according to a second embodiment. [Figure 3] 1A and 1B are diagrams for explaining problems with a circuit board according to a conventional technique. [Figure 4] FIG. 2 is a cross-sectional view showing the arrangement of the electrode portion according to the first embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing the arrangement of the electrode portion according to the second embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing the arrangement of the electrode portion according to the third embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing the arrangement of the electrode portion according to the fourth embodiment. [Figure 8a] FIG. 2 is a plan view for explaining the arrangement structure of the electrode portion according to the embodiment. [Figure 8b] FIG. 2 is a cross-sectional view illustrating the arrangement of the electrode portion according to the embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing the arrangement of the electrode portion according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0036] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Identical or similar components are designated by the same reference numerals, regardless of their reference numerals, and redundant descriptions will be omitted. The suffixes "module" and "section" used in the following description are used solely for the convenience of drafting the specification and do not have any distinguishing meanings or functions. Furthermore, when describing the embodiments disclosed herein, if a detailed description of related publicly known technology is deemed to obscure the gist of the embodiments disclosed herein, that detailed description will be omitted. Furthermore, the accompanying drawings are intended to facilitate understanding of the embodiments disclosed herein, and the technical concepts disclosed herein should not be limited by the accompanying drawings. It should be understood that the accompanying drawings include all modifications, equivalents, and alternatives within the spirit and scope of the present invention.

[0037] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0038] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that it may be directly coupled or connected to the other component, but that there may be other components in between. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components in between.

[0039] The singular expression includes the plural expression unless the context clearly indicates otherwise.

[0040] In this application, the use of terms such as "comprises" or "having" is intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described herein, and should be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0041] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0042] -Electronic Devices-

[0043] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments can be applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various semiconductor elements may be mounted in the semiconductor package.

[0044] The semiconductor device may include active and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0045] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

[0046] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0047] Furthermore, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0048] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package according to the embodiment may have various package structures including the circuit board described below.

[0049] And, the circuit board in one embodiment may be the first board described below.

[0050] In other embodiments, the circuit board may be the second board described below.

[0051] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, and Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0052] Referring to FIG. 1 a, the semiconductor package of the first embodiment may include a first circuit board 1100 , a second circuit board 1200 , and a semiconductor device 1300 .

[0053] The first circuit board 1100 may refer to a package substrate.

[0054] For example, the first circuit board 1100 may provide a space to which at least one external board is coupled. The external board may refer to the second circuit board 1200 coupled on the first circuit board 1100. Alternatively, the external board may refer to a main board included in an electronic device coupled to the lower part of the first circuit board 1100.

[0055] Although not shown in the drawings, the first circuit board 1100 may provide a space in which at least one semiconductor device is mounted.

[0056] The first circuit board 1100 may include at least one insulating layer and an electrode portion disposed on the at least one insulating layer.

[0057] A second circuit board 1200 may be disposed on the first circuit board 1100 .

[0058] The second circuit board 1200 may be an interposer. For example, the second circuit board 1200 may provide a space in which at least one semiconductor device is mounted. The second circuit board 1200 may be connected to at least one semiconductor device 1300. For example, the second circuit board 1200 may provide a space in which a first semiconductor device 1310 and a second semiconductor device 1320 are mounted. The second circuit board 1200 may electrically connect the first semiconductor device 1310 and the second semiconductor device 1320, and may also electrically connect the first and second semiconductor devices 1310 and 1320 to the first circuit board 1100. That is, the second circuit board 1200 may function as a horizontal connection between multiple semiconductor devices and a vertical connection between the semiconductor devices and a package substrate.

[0059] 1a illustrates two semiconductor elements 1310 and 1320 disposed on the second circuit board 1200, but is not limited to this. For example, one semiconductor element may be disposed on the second circuit board 1200, or alternatively, three or more semiconductor elements may be disposed on the second circuit board 1200.

[0060] The second circuit board 1200 may be disposed between at least one semiconductor device 1300 and the first circuit board 1100 .

[0061] In one embodiment, the second circuit board 1200 may be an active interposer that performs the function of a semiconductor device. When the second circuit board 1200 performs the function of a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first circuit board 1100 and may perform the function of multiple logic chips. Having the function of a logic chip may mean having the functions of both active and passive devices. Unlike passive devices, active devices do not need to have linear current-voltage characteristics. In the case of an active interposer, the active interposer may have the function of an active device. Furthermore, the active interposer may perform the function of a logic chip while also performing the function of transmitting signals between the second logic chip disposed thereon and the first circuit board 1100.

[0062] According to another embodiment, the second circuit board 1200 may be a passive interposer. For example, the second circuit board 1200 may function as a signal relay between the semiconductor device 1300 and the first circuit board 1100 and may have passive element functions such as a resistor, capacitor, or inductor. For example, the number of terminals on the semiconductor device 1300 is gradually increasing due to factors such as 5G, the Internet of Things (IOT), improved image quality, and increased communication speed. That is, the number of terminals provided on the semiconductor device 1300 is increasing, and as a result, the width of the terminals and the spacing between the terminals are decreasing. In this case, the first circuit board 1100 may be connected to a main board of an electronic device. Therefore, in order for the electrodes provided on the first circuit board 1100 to have the width and spacing required for connection to the semiconductor device 1300 and the main board, respectively, the thickness of the first circuit board 1100 increases or the layer structure of the first circuit board 1100 becomes complex. Therefore, in the first embodiment, the second circuit board 1200 may be disposed on the first circuit board 1100 and the semiconductor device 1300. The second circuit board 1200 may include electrodes having fine widths and intervals corresponding to the terminals of the semiconductor device 1300.

[0063] The semiconductor device 1300 may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific integrated circuit (ASIC), or the like, or a chipset including a specific combination of the foregoing. The memory chip may be a stacked memory such as HBM. The memory chip may also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0064] On the other hand, the semiconductor package of the first embodiment can include a connecting portion.

[0065] For example, the semiconductor package may include a first connection portion 1410 disposed between the first circuit board 1100 and the second circuit board 1200. The first connection portion 1410 may couple the second circuit board 1200 to the first circuit board 1100 and electrically connect them together.

[0066] For example, the semiconductor package may include a second connection portion 1420 disposed between the second circuit board 1200 and the semiconductor device 1300. The second connection portion 1420 may electrically couple the semiconductor device 1300 to the second circuit board 1200 while coupling the semiconductor device 1300 to the second circuit board 1200.

[0067] The semiconductor package may include a third connection portion 1430 disposed on the lower surface of the first circuit board 1100. The third connection portion 1430 may couple the first circuit board 1100 to the main board and electrically connect them.

[0068] In this case, the first connecting unit 1410, the second connecting unit 1420, and the third connecting unit 1430 can electrically connect the multiple components using at least one bonding method of wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connecting unit 1410, the second connecting unit 1420, and the third connecting unit 1430 have the function of electrically connecting the multiple components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as the electrically connected part, not the solder or wire.

[0069] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material including at least one of Sn, Ag, and Cu. The direct inter-metal bonding method may refer to directly bonding multiple components through recrystallization by applying heat and pressure between the multiple components without using a material such as solder, wire, or conductive adhesive. The direct inter-metal bonding method may refer to a bonding method using the second connecting member 1420. In this case, the second connecting member 1420 may refer to a metal layer formed between the multiple components through recrystallization.

[0070] Specifically, the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 may be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 by applying heat and pressure to the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430.

[0071] In this case, in at least one of first circuit board 1100 and second circuit board 1200, the electrodes on which first connecting portion 1410, second connecting portion 1420, and third connecting portion 1430 are arranged may be provided with protrusions that protrude outward away from the insulating layer of the board. The protrusions may protrude outward from first circuit board 1100 or second circuit board 1200.

[0072] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode of the second circuit board 1200 on which a second connection portion 1420 for coupling to the semiconductor device 1300 is disposed. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, short circuits may occur between the plurality of second connection portions 1420 respectively connected to the plurality of terminals of the semiconductor device 1300 by a conductive adhesive such as solder. Therefore, in this embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion 1420. As a result, in the embodiment, the electrode of the second circuit board 1200 on which the second connection portion 1420 is disposed may include a protrusion in order to ensure the degree of matching, the diffusion force, and the diffusion prevention force that prevents the intermetallic compound (IMC) formed between the conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0073] Meanwhile, referring to FIG. 1B, the semiconductor package of the second embodiment may differ from the semiconductor package of the first embodiment in that a connecting member 1210 is disposed on a second circuit board 1200. The connecting member 1210 may be referred to as a bridge substrate. For example, the connecting member 1210 may include a redistribution layer. The connecting member 1210 may electrically connect a plurality of semiconductor devices horizontally to each other. Exemplarily, since a semiconductor device generally requires a large area, the connecting member 1210 may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width of the circuit pattern, etc., a buffering function for the circuit pattern is required for electrical connection. The buffering function may mean having an intermediate size between the width of the circuit pattern of the semiconductor package and the width of the circuit pattern of the semiconductor device, and the redistribution layer may have a buffering function.

[0074] In one embodiment, the connecting member 1210 may be a silicon bridge, i.e., the connecting member 1210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.

[0075] In other embodiments, the connecting member 1210 can be an organic bridge. For example, the connecting member 1210 can include an organic material. For example, the connecting member 1210 can include an organic substrate that includes an organic material instead of a silicon substrate.

[0076] The connecting member 1210 may be, but is not limited to, embedded in the second circuit board 1200. For example, the connecting member 1210 may be disposed on the second circuit board 1200 with a protruding structure.

[0077] Additionally, the second circuit board 1200 may include a cavity, and the coupling member 1210 may be disposed within the cavity of the second circuit board 1200 .

[0078] The connecting member 1210 can horizontally connect a plurality of semiconductor elements arranged on the second circuit board 1200 together.

[0079] 1c, the semiconductor package of the third embodiment may include a second circuit board 1200 and a semiconductor device 1300. In this case, the semiconductor package of the third embodiment may have a structure in which the first circuit board 1100 is omitted compared to the semiconductor package of the second embodiment.

[0080] That is, the second circuit board 1200 of the third embodiment can function as both an interposer and a package substrate.

[0081] The first connection portion 1410 disposed on the bottom surface of the second circuit board 1200 can couple the second circuit board 1200 to a main board of an electronic device.

[0082] Referring to FIG. 1 d, the semiconductor package of the fourth embodiment may include a first circuit board 1100 and a semiconductor device 1300 .

[0083] In this case, the semiconductor package of the fourth embodiment may have a structure in which the second circuit board 1200 is omitted compared to the semiconductor package of the second embodiment.

[0084] That is, the first circuit board 1100 of the fourth embodiment can function as a package substrate and also as a connection between the semiconductor devices 1300 and the main board. To this end, the first circuit board 1100 can include a connecting member 1110 for connecting between the plurality of semiconductor devices. The connecting member 1110 can be a silicon bridge or an organic bridge for connecting between the plurality of semiconductor devices.

[0085] Referring to FIG. 1e, the semiconductor package of the fifth embodiment may further include a third semiconductor element 1330 compared to the semiconductor package of the fourth embodiment.

[0086] For this purpose, a fourth connection portion 1440 may be disposed on the lower surface of the first circuit board 1100.

[0087] The third semiconductor element 1330 may be disposed on the fourth connection portion 1440. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor elements are mounted on both the upper and lower sides.

[0088] In this case, the third semiconductor element 1330 may have a structure in which it is disposed on the lower surface of the second circuit board 1200 in the semiconductor package of FIG. 1c.

[0089] 1f, the semiconductor package of the sixth embodiment may include a first circuit board 1100. A first semiconductor element 1310 may be disposed on the first circuit board 1100. To this end, a first connection part 1410 may be disposed between the first circuit board 1100 and the first semiconductor element 1310.

[0090] The first circuit board 1100 may also include a conductive coupling part 1450. The conductive coupling part 1450 may further protrude from the first circuit board 1100 toward the second semiconductor device 1320. The conductive coupling part 1450 may be referred to as a bump, or alternatively as a post. The conductive coupling part 1450 may be disposed in a protruding structure on an electrode disposed on the top side of the first circuit board 1100.

[0091] A second semiconductor element 1320 may be disposed on the conductive coupling part 1450. In this case, the second semiconductor element 1320 may be connected to the first circuit board 1100 via the conductive coupling part 1450. In addition, a second connection part 1420 may be disposed on the first semiconductor element 1310 and the second semiconductor element 1320.

[0092] Thus, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 via the second connection portion 1420 .

[0093] That is, the second semiconductor device 1320 may be connected to the first circuit board 1100 through the conductive coupling portion 1450 and also connected to the first semiconductor device 1310 through the second connection portion 1420 .

[0094] At this time, the second semiconductor device 1320 may be supplied with a power signal and / or power via the conductive coupling part 1450. In addition, the second semiconductor device 1320 may transmit and receive communication signals to and from the first semiconductor device 1310 via the second connection part 1420.

[0095] The semiconductor package of the sixth embodiment may be able to provide sufficient power for driving the second semiconductor element 1320 and smoothly control the power supply operation by supplying a power signal and / or power to the second semiconductor element 1320 via the conductive coupling portion 1450.

[0096] As a result, the embodiment may improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment may solve the problem of insufficient power provided to the second semiconductor device 1320. Furthermore, the embodiment may provide at least one of the power signal, power, and communication signal of the second semiconductor device 1320 via different paths via the conductive coupling part 1450 and the second connection part 1420. As a result, the embodiment may solve the problem of loss of the communication signal due to the power signal. For example, the embodiment may minimize mutual interference between the power signal and the communication signal.

[0097] Meanwhile, in the sixth embodiment, the second semiconductor device 1320 may have a package-on-package (POP) structure in which a plurality of package substrates are stacked, and may be disposed on the first circuit board 1100. For example, the second semiconductor device 1320 may be a memory package including a memory chip. The memory package may be coupled to the conductive coupling part 1450. In this case, the memory package may not be connected to the first semiconductor device 1310.

[0098] Referring to FIG. 1g, the semiconductor package of the seventh embodiment may include a first circuit board 1100, a first connecting portion 1410, a second connecting portion 1420, a semiconductor element 1300, and a third connecting portion 1430.

[0099] The semiconductor package of the seventh embodiment may differ from the semiconductor package of the fourth embodiment in that the connecting member 1110 is omitted and the first circuit board 1100 includes a plurality of substrate layers.

[0100] The first circuit board 1100 may include multiple substrate layers, such as a first substrate layer 1100A corresponding to a package substrate and a second substrate layer 1100B corresponding to a connecting member.

[0101] In other words, the semiconductor package of the seventh embodiment may include a first substrate layer 1100A and a second substrate layer 1100B in which the first circuit board 1100 (package substrate) and the second circuit board 1200 (interposer) disclosed in FIG. 1A are integrally formed. The material of the insulating layer of the second substrate layer 1100B may be different from the material of the insulating layer of the first substrate layer 1100A. For example, the material of the insulating layer of the second substrate layer 1100B may include a photo-curable material. For example, the second substrate layer 1100B may be a photo-imageable dielectric (PID). Furthermore, the second substrate layer 1100B may include a photo-curable material, thereby enabling miniaturization of electrodes. Therefore, in the seventh embodiment, the second substrate layer 1100B may be formed by sequentially stacking insulating layers of a photo-curable material on the first substrate layer 1100A and then forming miniaturized electrodes on the insulating layers of the photo-curable material. Thus, the second substrate 1100B may have a function of a redistribution layer including miniaturized electrodes, and may have a function of horizontally connecting the plurality of semiconductor elements 1310 and 1320.

[0102] Prior to describing the circuit board of the embodiments, the circuit board described below may refer to any one of the plurality of circuit boards included in the semiconductor package described above. For example, the circuit board described below may refer to any one of the first circuit board 1100 and the second circuit board 1200 provided in the semiconductor packages of the first to seventh embodiments.

[0103] Figure 2a is a cross-sectional view showing a circuit board according to the first embodiment, Figure 2b is a cross-sectional view showing a circuit board according to the second embodiment, Figure 3 is a diagram for explaining problems with circuit boards according to conventional technology, Figure 4 is a cross-sectional view showing the electrode section arrangement structure according to the first embodiment, Figure 5 is a cross-sectional view showing the electrode section arrangement structure according to the second embodiment, Figure 6 is a cross-sectional view showing the electrode section arrangement structure according to the third embodiment, Figure 7 is a cross-sectional view showing the electrode section arrangement structure according to the fourth embodiment, Figure 8a is a plan view for explaining the electrode section arrangement structure according to the embodiments, Figure 8b is a cross-sectional view for explaining the electrode section arrangement structure according to the embodiments, and Figure 9 is a cross-sectional view showing the electrode section arrangement structure according to the fourth embodiment.

[0104] The circuit board according to the embodiment will be specifically described below with reference to FIGS. 2a to 9. FIG.

[0105] 2a, the circuit board 100 according to the first embodiment may include an insulating layer 110, a first resist layer 116, a second resist layer 117, an electrode unit 120, and an insulating member 140. The electrode unit 120 may include a second via electrode 130.

[0106] 2b, the circuit board 100 according to the second embodiment may include an insulating layer 110, a first resist layer 116, a second resist layer 117, an electrode portion 120, and an insulating member 140. The electrode portion 120 may include a second via electrode 130 and a bonding portion 125.

[0107] Specifically, FIGS. 2A and 2B may be distinguished based on whether or not they include a bonding portion 125. The second via electrode 130 and the bonding portion 125 are components of the electrode unit 120 and may be distinguished based on the direction and / or function of their protrusion from an electrode constituting the electrode unit 120. For example, the second via electrode 130 may be a part of an electrode disposed within the insulating layer 110. The bonding portion 125 may be a part of an electrode that is not disposed within the insulating layer 110. For example, the bonding portion 125 may be located outside the insulating layer 110. For example, the second via electrode 130 may be located inside the insulating layer 110, and the bonding portion 125 may be located outside the insulating layer 110. Below, a circuit board according to an embodiment will be described with reference to FIG. 2B.

[0108] The second via electrode 130 and the bonding part 125 are one component of the electrode part 120 and may be classified according to the direction in which they protrude from one electrode constituting the electrode part 120 and / or their functions.

[0109] The insulating layer 110 of the circuit board 100 may have a layer structure of at least one layer. Preferably, the insulating layer 110 of the circuit board 100 may have a multi-layer structure. The layer structure may be divided by the electrode portion 120, and may be divided by the difference in width between the first electrode 121, the second electrode 122, and the first via electrode 123 of the electrode portion 120.

[0110] That is, the width of each of the first electrode 121 and the second electrode 122 of the electrode unit 120 may be greater than the width of the first via electrode 123, thereby dividing the stacked structure. Through the above-described stacked structure, the circuit board 100 of the embodiment may efficiently electrically connect at least one semiconductor device and / or the second board to the main board.

[0111] 2a and 2b, the insulating layer 110 of the circuit board 100 is shown as having a five-layer structure, but is not limited thereto. For example, the insulating layer 110 of the circuit board 100 may have four or fewer layers, or six or more layers. Furthermore, if the multiple insulating layers 110 of the circuit board 100 contain the same insulating material, it may be difficult to distinguish the interfaces between the multiple insulating layers. In this case, the stacked structure can be distinguished by the first electrode 121, the second electrode 122, and the first via electrode 123 of the electrode unit 120.

[0112] Meanwhile, when the insulating layer 110 of the circuit board 100 has a multi-layer structure, the multiple insulating layers of the circuit board 100 may contain the same insulating material, but are not limited to this. For example, at least one of the multiple insulating layers of the circuit board 100 may contain an insulating material different from at least one of the other insulating layers.

[0113] The insulating layer 110 of the circuit board 100 may be rigid or flexible. For example, the insulating layer 110 of the circuit board 100 may include glass or plastic. For example, the insulating layer 110 of the circuit board 100 may include chemically strengthened / semi-strengthened glass, such as soda lime glass or aluminosilicate glass. For example, the insulating layer 110 of the circuit board 100 may include reinforced or ductile plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer 110 of the circuit board 100 may include sapphire. For example, the insulating layer 110 of the circuit board 100 may include an optically isotropic film. For example, the insulating layer 110 of the circuit board 100 may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 110 of the circuit board 100 may be formed of a material including an inorganic filler and an insulating resin. For example, the insulating layer 110 of the circuit board 100 may have a structure in which inorganic filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0114] The insulating layer 110 may have a structure in which a plurality of different insulating materials are stacked, and an exemplary arrangement structure will be described in more detail below.

[0115] In one embodiment, the insulating layer may include a first layer corresponding to a core layer including a reinforcing member. Here, the core layer may refer to an insulating layer including a reinforcing member and having a vertical thickness of more than 100 μm. The insulating layer may also include multiple second layers disposed above and below the core layer and not including a reinforcing member. In this case, the circuit board 100 may be a core board. The reinforcing member may also be referred to as a reinforcing fiber or glass fiber.

[0116] The reinforcing member may refer to glass fiber material extending horizontally in the insulating layer, and may have a different meaning from inorganic fillers spaced apart from each other. That is, the reinforcing member of the first layer may have a different length or width in the horizontal direction from the filler of the second layer. For example, the glass fiber may extend to have a width equal to or greater than the width of the first layer. Here, having a width equal to or greater than the width of the first layer may mean that the glass fiber may be arranged in a curved shape in the horizontal direction. Furthermore, even if the second layer contains a filler, the reinforcing member is not as effective in preventing problems such as warping as the glass fiber of the first layer, and therefore the reinforcing member will be described separately from the filler of the second layer.

[0117] In another embodiment, the insulating layer 110 of the circuit board 100 may be a coreless substrate that does not include a core layer. For example, the insulating layer 110 of the circuit board 100 may include an organic material that does not include a reinforcing member, which allows for excellent processability, slimming of the circuit board 100, and miniaturization of the electrode portion 120 of the circuit board 100. For example, the insulating layer 110 of the circuit board 100 may be made of Ajinomoto Build-up Film (ABF), a product sold by Ajinomoto Co., Inc., or may include FR-4, bismaleimide triazine (BT), photoimageable dielectric resin (PID), BT, etc. For example, the insulating layer 110 may include multiple layers made of ABF.

[0118] In this case, if the insulating layer 110 of the circuit board 100 is made of only ABF without a reinforcing member, the warpage characteristics of the circuit board 100 may be reduced. Therefore, the insulating layer 110 of the circuit board 100 is made of ABF (Ajinomoto Build-up Film), and at least one of the ABFs constituting the multiple insulating layers of the circuit board 100 may include a reinforcing member that can improve the warpage characteristics.

[0119] For example, the insulating layer 110 of the circuit board 100 may include a first layer made of a first ABF containing a resin and a filler. Alternatively, the insulating layer 110 of the circuit board 100 may include a layer made of a second ABF, which is the first ABF plus a reinforcing member. In this case, the reinforcing member included in the second ABF may include, but is not limited to, a GCP (Glass Core Primer) material.

[0120] Furthermore, the insulating layer 110 may be formed using PID, which is advantageous for miniaturizing the width and / or pitch of the electrodes. PID allows electrodes to be formed on the insulating layer 110 using an exposure and development process, thereby miniaturizing the width and / or pitch of the electrodes. When the insulating layer 110 is formed using PID, problems with mechanical reliability may occur due to reduced adhesion between the insulating layer 110 and the electrodes. However, in this embodiment, protrusions formed on the electrodes, as described below, are used to improve adhesion between the insulating layer and the electrodes, thereby improving electrical reliability and / or mechanical reliability.

[0121] The layer of the insulating layer 110 of the circuit board 100 that does not include a reinforcing member may have a thickness in the range of 10 μm to 40 μm. Preferably, the layer of the insulating layer 110 of the circuit board 100 that does not include a reinforcing member may have a thickness in the range of 15 μm to 35 μm. More preferably, the layer of the insulating layer 110 of the circuit board 100 that does not include a reinforcing member may have a thickness in the range of 18 μm to 32 μm. If the thickness of the layer of the insulating layer 110 of the circuit board 100 that does not include a reinforcing member is less than 10 μm, the warpage characteristics of the circuit board 100 may be reduced. Furthermore, if the thickness of the layer of the insulating layer 110 of the circuit board 100 that does not include a reinforcing member is less than 10 μm, the electrode portion 120 of the circuit board 100 may not be reliably protected, which may result in reduced electrical reliability. Furthermore, if the thickness of the layer of the insulating layer 110 of the circuit board 100 that does not include a reinforcing member exceeds 40 μm, the overall thickness of the circuit board 100 increases, which may result in an increase in the thickness of the semiconductor package. Furthermore, if the thickness of the insulating layer 110 of the circuit board 100, excluding the reinforcing member, exceeds 40 μm, it may be difficult to miniaturize the electrode portions 120 of the circuit board 100.

[0122] The thickness may correspond to the vertical distance between electrodes arranged on different layers of the substrate. That is, the thickness may refer to the length from the top to the bottom of the circuit board 100 or from the bottom to the top, and may refer to the vertical length of the substrate. Here, the top may refer to the highest position in the vertical direction of each component, and the bottom may refer to the lowest position in the vertical direction of each component. These positions may be referred to inversely.

[0123] Meanwhile, the semiconductor package of the embodiment may include a first resist layer 116 disposed on the upper surface of the circuit board 100. The semiconductor package may also include a second resist layer 117 disposed on the lower surface of the circuit board 100. The first resist layer 116 and the second resist layer 117 may refer to "insulating layers" other than the insulating layer 110 of the circuit board 100. In this case, the insulating layer 110 may be referred to as the "first insulating layer," the first resist layer 116 may be referred to as the "second insulating layer," and the second resist layer 117 may be referred to as the "third insulating layer." Therefore, the insulating layers of the circuit board 100 may include not only the insulating layer 110 but also the first resist layer 116 and the second resist layer 117.

[0124] In this case, the upper surface of the circuit board 100 may refer to the upper surface of the insulating layer 110, more specifically, the upper surface of the insulating layer disposed at the top among the plurality of insulating layers. The lower surface of the circuit board 100 may refer to the lower surface of the insulating layer 110, more specifically, the lower surface of the insulating layer disposed at the bottom among the plurality of insulating layers.

[0125] The first resist layer 116 and the second resist layer 117 can function to protect the upper and lower surfaces of the circuit board 100. As a result, the first resist layer 116 and the second resist layer 117 can be functionally referred to as a first protective layer and a second protective layer, respectively.

[0126] The first resist layer 116 and the second resist layer 117 may be solder resist layers containing an organic polymer material. For example, the first resist layer 116 and the second resist layer 117 may contain an epoxy acrylate resin. In particular, the first resist layer 116 and the second resist layer 117 may contain a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the first resist layer 116 and the second resist layer 117 may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0127] For example, when the bonding portion 125 of the electrode unit 120 is bonded to a semiconductor device via solder, the solder and the solder resist layer have poor wettability with each other, which can prevent the solder from causing an electrical short between two adjacent bonding portions of the plurality of bonding portions 125. In this case, the bonding portion 125 may be configured to be connected to a terminal of the semiconductor device or an electrode of an interposer via a connecting portion such as solder. The bonding portion 125 may also refer to a configuration distinct from the second via electrode 130 described below.

[0128] The thickness of each of the first resist layer 116 and the second resist layer 117 may be 1 μm to 20 μm. The thickness of each of the first resist layer 116 and the second resist layer 117 may be 1 μm to 15 μm. For example, the thickness of each of the first resist layer 116 and the second resist layer 117 may be 5 μm to 20 μm. In this case, the thickness of the first resist layer 116 may refer to the vertical distance from the upper surface of the uppermost electrode unit 120 to the upper surface of the first resist layer 116. Furthermore, the thickness of the second resist layer 117 may refer to the vertical distance from the lower surface of the lowermost electrode unit 120 to the lower surface of the second resist layer 117.

[0129] If the thickness of each of the first resist layer 116 and the second resist layer 117 exceeds 20 μm, the thickness of the semiconductor package increases, making it difficult to thin the package, or increasing stress may be applied to the insulating layer disposed between the first resist layer 116 and the second resist layer 117. If the thickness of each of the first resist layer 116 and the second resist layer 117 is less than 1 μm, the electrode unit 120 included in the circuit board 100 may not be stably protected, and electrical or physical reliability may be reduced.

[0130] The circuit board 100 may include an electrode portion 120. The electrode portion 120 may be disposed on the insulating layer 110 of the circuit board 100. For example, the electrode portion 120 may be disposed within the insulating layer of the circuit board 100. In this case, being disposed within the insulating layer may mean that the electrode portion 120 is disposed within the insulating layer including the insulating layer 110, the first resist layer 116, and the second resist layer 117.

[0131] The electrode section 120 may include multiple electrodes depending on their positions or functions.

[0132] For example, the electrode unit 120 may include a first electrode 121 and a second electrode 122 disposed on the first electrode 121. The electrode unit 120 may also include a first via electrode 123 that connects the first electrode 121 and the second electrode 122 along the vertical direction of the circuit board 100. That is, the first via electrode 123 may be disposed between the first electrode 121 and the second electrode 122, thereby electrically connecting the first electrode 121 and the second electrode 122.

[0133] In this case, when the insulating layer 110 of the circuit board 100 has a five-layer structure, the first via electrodes 123 of the electrode unit 120 may have a five-layer structure along the vertical direction. The first electrodes 121 or the second electrodes 122 may be disposed between the five layers of the first via electrodes 123.

[0134] At least one of the first electrode 121 and the second electrode 122 of the electrode unit 120 may have an ETS (Embedded Trace Substrate) structure. For example, the first electrode 121 of the electrode unit 120 arranged on the uppermost side of the circuit board 100 may have the ETS structure. For example, the first electrode 121 of the electrode unit 120 arranged on the uppermost side of the circuit board 100 may be disposed in a recess provided on the upper surface of the uppermost insulating layer. The ETS structure may also be referred to as an embedded structure. The ETS structure is advantageous for miniaturization compared to electrodes having a general protruding structure. As a result, the embodiment enables electrodes to be formed in accordance with the size and pitch of terminals provided on a semiconductor device. As a result, the embodiment may improve circuit integration. Furthermore, the embodiment may minimize the transmission distance of signals transmitted through a semiconductor device, thereby minimizing signal transmission loss.

[0135] In this case, the first electrode 121 and the second electrode 122 of the electrode unit 120 may be referred to as opposite electrodes. For example, the first electrode 121 of the electrode unit 120 may be referred to as the second electrode 122 depending on the position of the first via electrode 123 serving as a reference. Also, the second electrode 122 of the electrode unit 120 may be referred to as the first electrode 121 depending on the position of the first via electrode 123 serving as a reference.

[0136] For example, the first via electrode 123 may include a 3-1 electrode arranged on a first layer of the insulating layer 110, a 3-2 electrode arranged on a second layer on the first layer, and a 3-3 electrode arranged on a third layer on the second layer.

[0137] In this case, the electrode disposed between the 3-1 electrode and the 3-2 electrode can be the "second electrode" based on the 3-1 electrode, and can be the "first electrode" based on the 3-2 electrode.

[0138] In addition, an electrode placed between the 3-2 electrode and the 3-3 electrode can be the "second electrode" based on the 3-2 electrode, and can be the "first electrode" based on the 3-3 electrode.

[0139] The first electrode 121 and the second electrode 122 may function to transmit signals in a horizontal direction on the insulating layer 110. The first via electrode 123 is connected to the first electrode 121 and the second electrode 122 and may function to transmit signals in a vertical direction between them. The first via electrode 123 may also be referred to as a through electrode or a via.

[0140] Meanwhile, the electrode unit 120 may include a second via electrode 130. Preferably, the second electrode 122 of the electrode unit 120 may include the second via electrode 130. Here, although it has been described that the second via electrode 130 is included in the second electrode 122, this is not limiting. That is, as described above, the second electrode 122 may be the first electrode 121 through the first via electrode 123 serving as a reference. Thus, the second via electrode 130 may be included in the first electrode 121.

[0141] For convenience of explanation, the following description will be given assuming that the second via electrode 130 is a component of the second electrode 122 of the electrode section 120.

[0142] The second via electrode 130 may extend vertically from the second electrode 122 of the electrode unit 120. The second via electrode 130 may be disposed between the first electrode 121 and the second electrode 122. The second via electrode 130 may be disposed between the first electrode 121 and the second electrode 122 and spaced apart from the first via electrode 123 in the horizontal direction.

[0143] The first via electrode 123 may extend in a vertical direction from the second electrode 122. In this case, the vertical length of the second via electrode 130 may be different from the vertical length of the first via electrode 123.

[0144] That is, the first via electrode 123 may function to electrically connect the first electrode 121 and the second electrode 122 together.

[0145] Accordingly, the first via electrode 123 may be connected to the first electrode 121 and the second electrode 122. The first via electrode 123 may electrically connect the first electrode 121 and the second electrode 122. In contrast, the second via electrode 123 may not electrically connect the first electrode 121 and the second electrode 122. Exemplarily, the second via electrode 123 may be connected to one of the first electrode 121 and the second electrode 122, but not to the other one.

[0146] Therefore, the vertical length of the first via electrode 123 can correspond to the vertical distance between the first electrode 121 and the second electrode 122.

[0147] In contrast, the second via electrode 130 can function to improve the adhesive strength between the second electrode 122 and the insulating layer 110.

[0148] That is, the second via electrode 130 increases the contact area between the insulating layer 110 and the electrode unit 120, thereby solving the problem of the electrode unit 120 peeling off from the insulating layer 110. In addition, the second via electrode 130 can prevent the circuit board 100 from warping significantly in a specific direction.

[0149] Specifically, as the number of input and output terminals of a semiconductor device increases, the width and / or spacing of the terminals of the semiconductor device and / or semiconductor chiplet tends to become narrower. Accordingly, the width and / or spacing of electrodes provided on a circuit board is also becoming finer. Furthermore, as the width and / or spacing of the electrodes becomes finer, the contact area between the electrode unit 120 and the insulating layer 110 decreases, which can lead to mechanical reliability issues such as the electrode unit 120 easily peeling off from the insulating layer 110. Furthermore, to reduce the width and / or spacing of the electrodes, the insulating layer may contain a photosensitive material. For example, the photosensitive material may be a photoimageable dielectric (PID). The insulating layer containing the photosensitive material can be formed into the shape of the electrodes using a photolithography process, which may be advantageous in reducing the width and / or spacing of the electrodes. In this regard, the photosensitive material has a lower adhesion strength with the electrodes than a thermosetting material. As a result, the embodiment can solve the mechanical reliability problem of the electrode peeling off from the insulating layer when the width and / or spacing of the electrode is miniaturized using the second via electrode 130 provided in the electrode portion or when the insulating layer contains a photosensitive material, thereby improving the overall product reliability of the circuit board and semiconductor package.

[0150] Furthermore, the rigidity of the insulating layer made of the photosensitive material may be lower than the rigidity of the thermosetting material with the reinforcing member. As a result, the circuit board with the photosensitive material may have a problem of large warping in a specific direction. In this case, the embodiment can improve the rigidity of the circuit board by using the protrusions provided on the electrodes, thereby preventing the circuit board and the semiconductor package from large warping in a specific direction.

[0151] In addition, the second via electrode 130 can solve the problem of the electrode unit 120 peeling off from the insulating layer 110 due to gas generated in the insulating layer 110. For example, in brief, in the manufacturing process of the circuit board 100, the insulating layer 110 may be provided in a semi-cured state. Then, the electrode unit 120 may be disposed on the semi-cured insulating layer 110. Then, after the electrode unit 120 is disposed, a process of fully curing the insulating layer 110 may be performed.

[0152] At this time, when a process of completely curing the insulating layer 110 is performed, gas may be generated in the insulating layer 110. At this time, the generated gas must be discharged from the insulating layer 110 to the outside of the circuit board 100. At this time, the electrode unit 120 is disposed on the insulating layer 110. As a result, a problem may occur in that the gas generated in the insulating layer 110 is not discharged to the outside of the circuit board 100 by the electrode unit 120, but remains in the insulating layer 110.

[0153] Therefore, the electrode unit 120 of the embodiment may include the second via electrode 130. The second via electrode 130 increases the adhesive force between the electrode unit 120 and the insulating layer 110, thereby preventing the electrode unit 120 from peeling off from the insulating layer 110 due to the generated gas.

[0154] For example, if the electrode unit 120 does not include the second via electrode 130, a problem may occur in that the electrode unit 120 bulges on the insulating layer 110 due to gas generated in the insulating layer 110.

[0155] For example, referring to FIG. 3 , the electrode portion of the comparative substrate may not include a second via electrode. Furthermore, the electrode portion of the comparative substrate may not include a through-hole for gas discharge for various reasons described above. As a result, the comparative substrate may experience a problem in which gas generated in the insulating layer 10 is not discharged to the upper side of the electrode portion 20. As a result, the comparative substrate may experience a problem in which the electrode portion 20 bulges due to gas. For example, the electrode portion 20 of the comparative substrate may include a convex region A that bulges upward from the insulating layer 10. The electrode portion 120 in the convex region A may not contact the insulating layer 10. As a result, the convex region A reduces the adhesion between the electrode portion 20 and the insulating layer 10, which may result in a physical reliability problem in which the electrode portion 20 is separated from the insulating layer 10.

[0156] In contrast, in the embodiment, the second electrode 122 of the electrode unit 120 may be provided with a second via electrode 130. The second via electrode 130 may function to improve adhesion between the electrode unit 120 and the insulating layer 110. For example, the second via electrode 130 may function as an anchor that firmly fixes the electrode unit 120 to the insulating layer 110. As a result, the embodiment may improve adhesion between a plurality of insulating layers and adhesion between the insulating layer and the electrode unit. As a result, the embodiment may improve the physical reliability of the substrate.

[0157] Meanwhile, the second via electrode 130 may be provided in a region of the second electrode 122 that should not be connected to the first electrode 121 .

[0158] However, the second via electrode 130 may be provided in a region of the second electrode 122 that is electrically connected to the first electrode 121, thereby connecting the first electrode 121 and the second electrode 122. However, when the second via electrode 130 connects the first electrode 121 and the second electrode 122, this may correspond to the function and structure of the first via electrode 123.

[0159] That is, the first via electrode 123 may extend vertically from the second electrode 122 together with the second via electrode 130. The first via electrode 123 may electrically connect the first electrode 121 and the second electrode 122, as well as improve adhesion between the insulating layer 110 and the electrode unit 120. Therefore, the first via electrode 123 may be disposed over the entire area of the insulating layer 110 instead of the second via electrode 130. However, the electrode unit 120 may also have areas where the first electrode 121 and the second electrode 122 should not be electrically connected to each other, and the first via electrode 123 may not be disposed in these areas. Furthermore, if only the first via electrode 123 is included instead of the second via electrode 130, plating the first via electrode 123 may require a lot of time, cost, and materials. Furthermore, as the number of first via electrodes 123 increases, the flatness of the second electrodes 122 plated together with the first via electrodes 123 may decrease. For example, the second electrodes 122 may be plated together with the first via electrodes 123. In this case, if the number of first via electrodes 123 increases, a step may exist in the second electrodes 122 between a region that vertically overlaps with the first via electrodes 123 and a region that does not vertically overlap with the first via electrodes 123. The step may act as a factor that reduces the physical reliability and electrical reliability of the substrate.

[0160] Therefore, in this embodiment, at least one second via electrode 130 is provided in the electrode unit 120 .

[0161] The second electrode 122 should not be electrically connected to the first electrode 121 through the second via electrode 130. In this case, if the second via electrode 130 of the second electrode 122 has the same vertical length as the first via electrode 123, the second via electrode 130 may be electrically connected to the first electrode 121 that overlaps it in the vertical direction. Therefore, the vertical length of the second via electrode 130 may be shorter than the vertical length of the first via electrode 123. Here, the vertical length of the first via electrode 123 will be described depending on the arrangement of the first electrode 121 and the second electrode 122. That is, the positions and structures of the first electrode 121, the second electrode 122, the first via electrode 123, and the second via electrode 130 of the electrode unit 120 may vary based on any one specific insulating layer of the insulating layers 110 of the circuit board 100.

[0162] That is, referring to FIG. 4 , the first electrode 121 may be embedded in the insulating layer 110. For example, the first electrode 121 may be disposed in a recess (not shown) provided in the lower surface of the insulating layer 110. The second electrode 122 may be disposed on the insulating layer 110. For example, the second electrode 122 may protrude above the upper surface of the insulating layer 110. Meanwhile, the first via electrode 123 may be disposed in the insulating layer 110. The first via electrode 123 may be disposed between the first electrode 121 and the second electrode 122. The first via electrode 123 may extend from the first electrode 121 to the second electrode 122 in the vertical direction. The first via electrode 123 may extend from the second electrode 122 to the first electrode 121 in the vertical direction. In this case, the vertical length of the first via electrode 123 may be smaller than the vertical length of the insulating layer 110. For example, the vertical length of the first via electrode 123 may correspond to the vertical distance from the upper surface of the first electrode 121 to the lower surface of the second electrode 122. Furthermore, the second via electrode 130 may extend vertically from the second electrode 122 toward the first electrode 121. In this case, the vertical length of the second via electrode 130 may be different from the vertical length of the first via electrode 123. Preferably, the vertical length of the second via electrode 130 may be smaller than the vertical length of the first via electrode 123. For example, the lower surface of the second via electrode 130 may be located higher than the lower surface of the first via electrode 123. Furthermore, the upper surface of the second via electrode 130 may be located on the same plane as the upper surface of the first via electrode 123.

[0163] 5, the first electrode 121 may be disposed below the insulating layer 110. For example, the first electrode 121 may protrude below the lower surface of the insulating layer 110. The second electrode 122 may be embedded in the insulating layer 110. For example, the second electrode 122 may be disposed in a recess (not shown) provided in the upper surface of the insulating layer 110. Meanwhile, the first via electrode 123 may be disposed within the insulating layer 110. The first via electrode 123 may be disposed between the first electrode 121 and the second electrode 122. The first via electrode 123 may extend from the first electrode 121 to the second electrode 122 in the vertical direction. Also, the first via electrode 123 may extend from the second electrode 122 to the first electrode 121 in the vertical direction.

[0164] 6, the first electrode 121 may be embedded in the insulating layer 110. For example, the first electrode 121 may be disposed in a recess (not shown) provided in the lower surface of the insulating layer 110. The second electrode 122 may be embedded in the insulating layer 110. For example, the second electrode 122 may be disposed in a recess (not shown) provided in the upper surface of the insulating layer 110. Meanwhile, the first via electrode 123 may be disposed in the insulating layer 110. The first via electrode 123 may be disposed between the first electrode 121 and the second electrode 122. The first via electrode 123 may extend from the first electrode 121 to the second electrode 122 in the vertical direction. Furthermore, the first via electrode 123 may extend from the second electrode 122 to the first electrode 121 in the vertical direction.

[0165] 7, the first electrode 121 may be disposed below the insulating layer 110. For example, the first electrode 121 may protrude below the lower surface of the insulating layer 110. The second electrode 122 may be disposed on the insulating layer 110. For example, the second electrode 122 may protrude above the upper surface of the insulating layer 110. Meanwhile, the first via electrode 123 may be disposed within the insulating layer 110. The first via electrode 123 may be disposed between the first electrode 121 and the second electrode 122. The first via electrode 123 may extend from the first electrode 121 to the second electrode 122 in the vertical direction. The first via electrode 123 may extend from the second electrode 122 to the first electrode 121 in the vertical direction.

[0166] 8A and 8B, the vertical length T1 of the first via electrode 123 in the embodiment may correspond to the vertical distance between the first electrode 121 and the second electrode 122. In this case, in the case of FIG. 4, the vertical length T1 of the first via electrode 123 may correspond to the value obtained by subtracting the thickness of the first electrode 121 from the thickness of one insulating layer. In addition, in the case of FIG. 5, the vertical length T1 of the first via electrode 123 may correspond to the value obtained by subtracting the thickness of the second electrode 122 from the thickness of one insulating layer. In addition, in the case of FIG. 6, the vertical length T1 of the first via electrode 123 may correspond to the value obtained by subtracting the thickness of the first electrode 121 and the thickness of the second electrode 122 from the thickness of one insulating layer. In addition, in the case of FIG. 7, the vertical length T1 of the first via electrode 123 may correspond to the thickness of one insulating layer.

[0167] The vertical length T2 of the second via electrode 130 may be different from the vertical length T1 of the first via electrode 123. Preferably, the vertical length T2 of the second via electrode 130 may be smaller than the vertical length T1 of the first via electrode 123. For example, the vertical length T2 of the second via electrode 130 may be in the range of 30% to 70% of the vertical length T1 of the first via electrode 123. Preferably, the vertical length T2 of the second via electrode 130 may be in the range of 35% to 65% of the vertical length T1 of the first via electrode 123. More preferably, the vertical length T2 of the second via electrode 130 may be in the range of 40% to 60% of the vertical length T1 of the first via electrode 123.

[0168] If the vertical length T2 of the second via electrode 130 is less than 30% of the vertical length T1 of the first via electrode 123, the effect of increasing the adhesion between the insulating layer 110 and the electrode unit 120 caused by the second via electrode 130 may be insufficient. This may result in a physical reliability problem in which the electrode unit 120 peels off from the insulating layer 110. If the vertical length T2 of the second via electrode 130 exceeds 70% of the vertical length T1 of the first via electrode 123, the second via electrode 130 and the first electrode 121 may be electrically connected due to a process error, which may result in a circuit short. If the vertical length T2 of the second via electrode 130 exceeds 70% of the vertical length T1 of the first via electrode 123, time, materials, and costs for forming the second via electrode 130 may be wasted. If the vertical length T2 of the second via electrode 130 exceeds 70% of the vertical length T1 of the first via electrode 123, the flatness of the second electrode 122 may decrease.

[0169] On the other hand, the width of the second via electrode 130 may be different from the width of the first via electrode 123. Preferably, the width of the second via electrode 130 may be smaller than the width of the first via electrode 123.

[0170] For example, the second via electrode 130 may have a slope 130S whose width gradually decreases from the region adjacent to the second electrode 122 toward the first electrode 121.

[0171] In addition, the first via electrode 123 may have a slope 123S in which the width gradually decreases from the region adjacent to the second electrode 122 toward the first electrode 121.

[0172] In this case, the slope 130S of the second via electrode 130 can correspond to the slope 123S of the first via electrode 123.

[0173] For example, the second via electrode 130 may be formed by filling a recess formed in the insulating layer 110. The first via electrode 123 may be formed by filling a through hole penetrating the insulating layer 110. In this case, the recess filled with the second via electrode 130 may be formed in the same process or with the same equipment as the through hole filled with the first via electrode 123. For example, the recess may be formed together with the through hole when the through hole is formed. For example, the recess may be formed using the same equipment as that used to form the through hole. Therefore, the slope 123S of the first via electrode 123 may correspond to the slope 130S of the second via electrode 130.

[0174] The width of the widest region of the entire region of the second via electrode 130 may be smaller than the width of the widest region of the entire region of the first via electrode 123. As a result, in this embodiment, the second via electrode 130 can increase the adhesion between the electrode unit 120 and the insulating layer 110 without changing the electrical characteristics of the second electrode 122.

[0175] On the other hand, referring to FIG. 9, the insulating layer 110 is composed of a plurality of layers, and it may be difficult to distinguish the interfaces between these layers.

[0176] Therefore, a plurality of electrode portions can be provided in the insulating layer 110 where the interface is not divided.

[0177] For example, a first electrode portion 120a and a second electrode portion 120b may be provided in the insulating layer 110 in the vertical direction.

[0178] The second electrode portion 120b may be disposed within the insulating layer 110 on the first electrode portion 120a.

[0179] The first electrode unit 120a may include a first electrode 121a, a second electrode 122a, a first via electrode 123a, and a second via electrode 130a.

[0180] In addition, the second electrode unit 120b may include a first electrode 121b, a second electrode 122b, a first via electrode 123b, and a second via electrode 130b.

[0181] As a result, the first electrode, the second electrode, the first via electrode, and the second via electrode of the electrode portion can all be provided within the insulating layer.

[0182] Meanwhile, the electrode unit 120 may include a bonding portion 125. The bonding portion 125 may protrude from the circuit board 100 in a direction away from the circuit board 100. The bonding portion 125 may be provided on the second electrode 122 disposed on the uppermost side of the electrode unit 120. However, the embodiment is not limited thereto. The bonding portion 125 may also be provided below the first electrode 121 disposed on the lowermost side of the electrode unit 120.

[0183] As a result, the second electrode 122 of the electrode portion 120 arranged on the top side of the circuit board 100 can be provided with a second via electrode 130 extending vertically toward the inside of the insulating layer 110 and a bonding portion 125 extending vertically toward the outside of the insulating layer 110.

[0184] The bonding portion 125 may be referred to as a bump. The bonding portion 125 may also be referred to as a post. The bonding portion 125 may also be referred to as a pillar. A semiconductor device may be disposed on the electrode portion 120 of the circuit board 100. Alternatively, an interposer coupled to the semiconductor device may be coupled to the electrode portion 120 of the circuit board 100. In this case, as the pitch of the terminals of the semiconductor device or the electrodes of the interposer becomes finer, a problem of short-circuiting between the conductive connectors disposed on the multiple terminals or electrodes may occur. Therefore, the electrode portion 120 may include a protrusion 125 to reduce the volume of the conductive connectors disposed on the multiple terminals or electrodes. In addition, when using thermal compression bonding, which applies heat and pressure to the conductive connectors disposed between the circuit board 100 and the semiconductor device or the interposer, the bonding portion 125 may improve the degree of alignment between the electrode portion 120 and the terminals of the semiconductor device or the electrodes of the interposer. Additionally, the bonding portion 125 can also function to prevent the conductive connection from diffusing.

[0185] The electrode unit 120 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The electrode unit 120 of the circuit board 100 may also be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first electrode unit 120 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0186] Each of the first electrode 121 and the second electrode 122 of the electrode unit 120 may have a thickness in the range of 7 μm to 20 μm. For example, each of the first electrode 121 and the second electrode 122 of the electrode unit 120 may have a thickness in the range of 9 μm to 17 μm. Each of the first electrode 121 and the second electrode 122 of the electrode unit 120 may have a thickness in the range of 10 μm to 13 μm. If the thickness of each of the first electrode 121 and the second electrode 122 of the electrode unit 120 is less than 7 μm, the resistance of the electrode unit 120 increases, and the allowable current of transmittable signals may decrease. Furthermore, if the thickness of each of the first electrode 121 and the second electrode 122 of the electrode unit 120 exceeds 20 μm, it may be difficult to miniaturize the electrode unit 120 and to thin the circuit board 100.

[0187] Meanwhile, when the electrode unit 120 includes the bonding portion 125, the width of the bonding portion 125 may be in the range of 40 μm to 70 μm. If the width of the bonding portion 125 is smaller than 40 μm, the bonding portion 125 may be too narrow and may collapse during thermocompression bonding. Also, if the width of the bonding portion 125 is larger than 70 μm, it may be difficult to accommodate the fine pitch of the terminals of the semiconductor element or the electrodes of the interposer.

[0188] Meanwhile, the first via electrode 123 of the electrode unit 120 may be formed by filling a through hole provided in the insulating layer 110 with a conductive material. The through hole may be formed by any one of mechanical, laser, and chemical processing. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing may be used. When the through hole is formed by laser processing, a UV or CO2 laser method may be used. When the through hole is formed by chemical processing, a chemical containing aminosilane, ketones, etc. may be used. The through hole corresponding to the first via electrode 123 may be formed together with a recess corresponding to the second via electrode 130, but is not limited to this.

[0189] Meanwhile, once the through holes and recesses are formed, the first via electrodes 123 and the second via electrodes 130 of the circuit board 100 can be formed by filling the through holes and recesses with a conductive material.

[0190] Meanwhile, when the insulating layer 110 includes a core layer, the core layer may be provided with an insulating member 140. The insulating member 140 may be provided by filling a portion of a through-hole penetrating the core layer. The insulating member 140 may also be referred to as a hole plugging member. The insulating member 140 may include an insulating material provided in the through-hole of the core layer. For example, the insulating member 140 may include a paste of an insulating ink material. For example, the insulating member 140 may include a plugging ink. However, the embodiment is not limited thereto. For example, the insulating member 140 may include a conductive material. Specifically, the insulating member 140 may include a conductive paste containing a conductive metal powder.

[0191] Meanwhile, when a semiconductor package having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect a semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical shorts between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it functions as a signal transmission device, it can solve noise problems. As a result, a circuit board having the above-described inventive features can maintain stable functionality in IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0192] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0193] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0194] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. an insulating layer; an electrode portion disposed in the insulating layer, The electrode portion is A first electrode; a second electrode disposed on the first electrode; first and second via electrodes disposed between the first electrode and the second electrode; the first via electrode is connected to the first electrode and the second electrode; The vertical length of the second via electrode is smaller than the vertical length of the first via electrode.

2. The circuit board of claim 1 , wherein the second via electrode is connected to the second electrode.

3. The circuit board according to claim 1 , wherein the second via electrode is spaced apart from the first via electrode in a horizontal direction.

4. The circuit board according to claim 1 , wherein the second via electrode extends from the second electrode toward the first electrode.

5. an upper surface of the second via electrode is located on the same plane as an upper surface of the first via electrode; The circuit board according to claim 1 , wherein a lower surface of the second via electrode is positioned higher than a lower surface of the first via electrode.

6. The length of the second via electrode in the vertical direction is The circuit board according to claim 1 , wherein the first via electrode has a length in the vertical direction of 30% to 70%.

7. The horizontal width of the second via electrode is The circuit board according to claim 1 , wherein the width is smaller than the horizontal width of the first via electrode.

8. The second via electrode is 8. The circuit board according to claim 1, wherein the circuit board has a slope in which the horizontal width gradually changes with increasing distance from the second electrode.

9. The first via electrode is The circuit board according to claim 8 , wherein the width in the horizontal direction gradually changes from the second electrode toward the first electrode.

10. The circuit board according to claim 9 , wherein the second via electrode has the same inclination as the first via electrode.

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