Spread spectrum video transmission via orthogonal frequency division multiplexing and OFDM video transmission.

Abstract

An orthogonal frequency division multiplexing (OFDM) transmitter maps digital levels to I and Q components. The transmitter alternates between using each digital level as the I or Q component, or splits the MSB and LSB of a digital level into I and Q components. An analog OFDM transmitter uses a pair of input analog levels as the I and Q components. The inverse FFT outputs complex values, and an OFDM symbol is transmitted. The inverse FFT can also output real values ​​using the complex conjugate. An optional encoder encodes the digital or analog samples into L levels using N orthogonal codes before inputting them to the OFDM transmitter. The OFDM receiver receives the OFDM signal and outputs digital or analog samples. The video signal is input to a splitter, which splits the analog or digital samples into vectors. Each vector is input to the OFDM transmitter and transmitted to the corresponding receiver.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED DOCUMENTS: This application claims priority to U.S. Provisional Patent Application No. 63 / 398,460 ([P008P]), filed August 16, 2022, entitled "Spread Spectrum Video Transmission Using Orthogonal Frequency Division Multiplexing," U.S. Provisional Patent Application No. 63 / 421,062 ([P008P2]), filed October 31, 2022, entitled "Spread Spectrum Video Transmission With Orthogonal Frequency Division Multiplexing and OFDM Video Transmission," and U.S. Provisional Patent Application No. 63 / 500,341 ([P0015P2]), filed May 5, 2023, entitled "Analog Video Transport to a Display Panel and Source Driver Integration With a Display Panel," all of which are incorporated herein by reference.

[0002] This application is a continuation of U.S. application Ser. No. 15 / 925,123 (case number HYFYP001), filed March 19, 2018; U.S. application Ser. No. 10,158,396, filed December 18, 2018; U.S. application Ser. No. 16 / 494,901 (case number HYFYP002), filed September 17, 2019; U.S. application Ser. No. 17 / 879,499 (case number HYFYP003), filed August 2, 2022; U.S. application Ser. No. 17 / 686,790 (case number HYFYP004AX1), filed March 4, 2022; U.S. application Ser. No. 17 / 887,849 (case number HYFYP006), filed August 15, 2022; U.S. application Ser. No. 17 / 887,849 (case number HYFYP007), filed June 28, 2022; U.S. Application No. 17 / 851,821 (Docket No. HYFYP007), filed August 31, 2022; U.S. Application No. 17 / 900,570 (HYFYP009), filed August 16, 2022; U.S. Application No. 17 / 946,479 (Docket No. HYFYP010), filed August 16, 2022; U.S. Application No. 18 / 095,801 (Docket No. HYFYP011), filed January 11, 2023; U.S. Application No. 18 / 098,612 (HYFYP013), filed January 18, 2022; and U.S. Application No. 18 / 117,288 (HYFYP014), filed March 3, 2023, are all incorporated herein by reference.

[0003] The present invention relates generally to the transmission of sampled signals over electromagnetic paths, and more particularly to the encoding and transmission of video signals using orthogonal frequency division multiplexing (OFDM) or OFDM alone. [Background technology]

[0004] Image sensors, display panels, and video processors are constantly racing to achieve larger formats, deeper color depth, higher frame rates, and higher resolutions. Video transmission (within sensors, devices, display sets, in the built environment surrounding people, in vehicles, or over longer distances) necessarily involves transmitting media signals (e.g., video signals) over one or more electromagnetic (EM) paths.

[0005] Every electromagnetic path degrades the electromagnetic signal propagating along it due to phenomena such as attenuation, reflections due to impedance mismatches, and colliding signals. This means that the measured value of an electromagnetic signal at a receiving terminal will differ to some extent from the level, characteristics, and parameters available at the corresponding transmitting terminal. Therefore, every electromagnetic path can be considered an imperfect electromagnetic wave propagation path. The quality of any electromagnetic path can be characterized by comparing the level measured at the receiving terminal after propagation through the electromagnetic path with the level available at the transmitter.

[0006] U.S. Patent No. 10,158,396 discloses systems and techniques for encoding analog or digital samples and transmitting them over electromagnetic paths for corresponding decoding and use of the encoded samples. U.S. Application No. 16 / 494,901 discloses systems and techniques for distributing and transmitting encoded samples over multiple electromagnetic paths for eventual decoding and use. Meanwhile, U.S. Application No. 63 / 232,486 discloses systems and techniques for distributing, staging, and ordering samples (with subsequent corresponding decoding, staging, ordering, and collection of samples) prior to encoding and transmission over one or more electromagnetic paths. U.S. Application No. 17 / 686,790 discloses specific embodiments for constructing a transmitter with an encoder (and a receiver with a decoder) for transmitting encoded analog or digital samples over electromagnetic paths. US Application Nos. 63 / 317,746 and 63 / 280,017 disclose respective transmitters and receivers within a display unit that transmit video using SSVT technology.

[0007] Given that the above disclosures use certain techniques for transmitting samples over electromagnetic paths, because electromagnetic paths are inherently imperfect, additional techniques are required to improve the quality of the electromagnetic signal transmitted from the transmitting terminal to the receiving terminal. Summary of the Invention

[0008] To achieve the above objects and in accordance with the purpose of the present invention, a technique is disclosed that uses an improved Orthogonal Frequency Division Multiplexing (OFDM) technique to modulate optionally encoded analog or digital samples and demodulate the received OFDM signal back into analog or digital samples for transmission from a transmitting terminal to a receiving terminal. The input samples to an OFDM transmitter may be analog or digital, and may be encoded or unencoded.

[0009] In one embodiment, an orthogonal frequency division multiplexing (OFDM) transmitter for transmitting digital levels separates an input digital level into an I component and a Q component. An encoder sequentially encodes a vector of N samples using N codes of length L to generate the digital level.

[0010] In a second embodiment, an Orthogonal Frequency Division Multiplexing (OFDM) receiver receives an OFDM modulated signal and outputs digital levels. A decoder sequentially decodes the L levels using N codes of length L to generate a vector of N samples.

[0011] In a third embodiment, an orthogonal frequency division multiplexing (OFDM) transmitter for transmitting analog levels uses a pair of input analog levels as I and Q components. An encoder sequentially encodes a vector of N samples using N codes of length L to generate the analog levels.

[0012] In a fourth embodiment, an orthogonal frequency division multiplexing (OFDM) receiver receives an OFDM modulated signal and outputs analog levels. A decoder sequentially decodes the L levels using N codes of length L to generate a vector of N samples.

[0013] In a fifth embodiment, an orthogonal frequency division multiplexing (OFDM) transmitter for transmitting digital video samples maps input digital samples to I and Q components and outputs a signal using OFDM that represents the video samples.

[0014] In a sixth embodiment, an orthogonal frequency division multiplexing (OFDM) receiver receives an OFDM modulated signal and outputs digital samples. An inverse mapping maps the I and Q components to a stream of output digital samples.

[0015] In a seventh embodiment, an orthogonal frequency division multiplexing (OFDM) transmitter for transmitting analog video samples maps input analog samples to I and Q components and outputs a signal using OFDM that represents the video samples.

[0016] In an eighth embodiment, an orthogonal frequency division multiplexing (OFDM) receiver receives an OFDM modulated signal and outputs analog samples. A circuit combines the I and Q components to generate a stream of output analog samples.

[0017] In a ninth embodiment, the source driver of the display unit includes a receiver that receives analog video samples, a register, and an amplifier that supplies the samples to a column of the display panel. The source driver does not include a DAC.

[0018] In a tenth embodiment, an apparatus includes a distributor that distributes digital video samples to OFDM transmitters, each transmitter mapping the digital samples to a constellation and generating an OFDM signal.

[0019] In an eleventh embodiment, the video transmitter includes a splitter that splits the digital video samples into multiple paths, each path including a digital-to-analog converter followed by an OFDM transmitter.

[0020] In a twelfth embodiment, a video receiver includes an OFDM receiver that outputs analog video samples, followed by a collector that outputs the samples to a plurality of column drivers.

[0021] In a thirteenth embodiment, a video transmitter includes a divider that divides digital video samples into input vectors and outputs samples from each input vector to an OFDM transmitter.

[0022] In a fourteenth embodiment, a video receiver includes an OFDM receiver that outputs digital video samples, followed by a digital-to-analog converter, followed by a collector, which outputs analog video samples to a plurality of column drivers.

[0023] In a fifteenth embodiment, the video transmitter includes a divider that divides analog video samples into input vectors and outputs samples from each input vector to the OFDM transmitter.

[0024] The present invention is particularly applicable to displays used in computer systems, televisions, monitors, gaming displays, home theater displays, point-of-sale displays, outdoor displays, and the like. The present invention is also applicable to video transmission within vehicles, such as automobiles, trains, aircraft, and ships, including video transmission from a transmitter to a vehicle display or monitor, as well as within such displays or monitors. In particular embodiments, the present invention is useful within display units used to transmit and receive video signals. For example, a transmitter of the present invention can be used to implement the transmitter described in U.S. Application No. 63 / 317,746, and a receiver of the present invention can be used to implement the receiver described in U.S. Application No. 63 / 280,017. [Brief explanation of the drawings]

[0025] The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in which: [Figure 1] 1 illustrates an OFDM method for transmitting data using complex inputs. [Figure 2] 1 shows an example of an OFDM transmitter. [Figure 3A] 10 illustrates an embodiment showing how the division of MSB and LSB occurs within the mapping circuit. [Figure 3B] 1 is a graph showing how values ​​represent points on the complex QAM plane. [Figure 3C] An example of a QAM constellation is shown below. [Figure 4A] 10 illustrates another embodiment showing how digital samples are mapped within a mapping circuit. [Figure 4B] 1 is a graph showing how values ​​represent points on the complex QAM plane. [Figure 5] This shows a constellation mapping that is useful in explaining how OFDM uses analog input levels. [Figure 6] 1 shows an improved OFDM transmitter for use with analog input values. [Figure 7A] 1 shows an OFDM transmitter with a digital input. [Figure 7B] 1 shows an OFDM transmitter with an analog input. [Figure 7C] Indicates the IFFT bins used to generate the real output. [Figure 8] It shows the digital encoding of the sampled signal before it enters the OFDM transmitter. [Figure 9] 1 illustrates a logical block diagram of a particular embodiment of an SSVT transmitter. [Figure 10] This is a simplified example showing how signal samples (in this case analog values) are encoded in an encoder and then transmitted over an electromagnetic path. [Figure 11] It is shown that this novel encoding technique can be applied to signal samples that are digital values. [Figure 12] 11 shows the decoding of an analog input level encoded using the encoder of FIG. 10. [Figure 13A] Demonstrates the use of analog encoders and corresponding analog decoders. [Figure 13B] Demonstrates the use of a digital encoder and a corresponding analog decoder. [Figure 13C]Demonstrates the use of a digital decoder to decode an encoded analog signal that arrives via an electromagnetic path on a transmission medium. [Figure 14] 1 shows a simulation of the SSVT waveform transmitted over an electromagnetic path. [Figure 15] Demonstrates the transmission of digital video samples from a video source to a video sink using an OFDM transmitter and an OFDM receiver. [Figure 16] This example demonstrates the transmission of analog video samples from a video source to a video sink using an OFDM transmitter and an OFDM receiver. [Figure 17] An embodiment is shown in which both the OFDM transmitter and OFDM receiver are located within a display unit 840, such as a large screen television or screen. [Figure 18] A digital OFDM receiver with analog outputs placed on the source driver is shown. [Figure 19] An analog OFDM receiver with analog outputs placed on the source driver is shown. [Figure 20] 8 shows the source driver architecture of a display panel 850 that accepts analog video samples output from an OFDM receiver. [Figure 21] 1 illustrates a transmitter architecture that may be located external or internal to the display unit. [Figure 22] A preferred architecture for source drivers is shown, where each distributor amplifier drives an adjacent column and all control signals are processed by a single amplifier. [Figure 23] Shows source driver inputs for source drivers for interleaving multiple input amplifiers. [Figure 24] Figure 22 shows an overview of the pixel transmission order, which shows how pixels and control signals are transmitted from the transmitter input vector to the source driver. [Figure 25]FIG. 24 shows a block diagram of the transmitter input vectors with a predetermined permutation that provides the required sub-pixel transmission permutation. [Figure 26] Shows the video transmission system within the display unit. DETAILED DESCRIPTION OF THE INVENTION

[0026] As discussed above, various embodiments of the present invention disclose that analog signals are used to transmit video information locally (e.g., within a display unit) or over long distances. For purposes of this disclosure, an electromagnetic signal (EM signal) is a variable represented as electromagnetic energy whose amplitude varies with time. EM signals propagate from a transmitter terminal to a receiver terminal through an EM path, such as a wire pair (or cable), free space (or radio), or optical fiber or waveguide (fiber). EM signals can be characterized as continuous or discrete in two dimensions: time and amplitude, independently. A "pure analog" signal is a continuous-time, continuous-amplitude EM signal. A "digital" signal, on the other hand, is a discrete-time, discrete-amplitude EM signal. Discrete-time, continuous-amplitude electromagnetic signals are sometimes referred to as "sampled analog" signals (although the signal need not necessarily be sampled, and the discrete-time values ​​may be inherent in the source), "discrete-time analog" signals, "clocked analog" signals, or "pulsed" signals. Continuous-time, discrete-amplitude EM signals are sometimes called "discrete-amplitude analog" signals or "neuronal" signals. Analog levels, analog samples, and analog video samples referred to herein are preferably discrete-time analog signals.

[0027] As noted above, electromagnetic paths are inherently imperfect. In order to identify how the quality of an electromagnetic signal degrades as it travels from a transmitter to a receiver and to improve that transmission in the context of transmitting encoded analog or digital samples, the inventors of the present disclosure have come to the following realization.

[0028] The signal-to-noise ratio (SNR) of an electromagnetic signal is crucial for the transmission of encoded analog or digital samples, especially in electromagnetic paths such as cables. Various degradation mechanisms have been identified that can degrade SNR, including crosstalk, attenuation, thermal noise, and nonlinear distortion. Regarding crosstalk, far-side crosstalk (FEXT) is particularly problematic, especially in shielded cables, and is perceived as noise by the receiver. Furthermore, for cables such as Cat-5, Cat-6, and Cat-7, SNR is frequency-dependent and significantly decreases with increasing frequency and cable length. At these higher frequencies and longer cable lengths, signal attenuation and crosstalk increase, both of which reduce SNR. The second mechanism that degrades the SNR of an electromagnetic signal is thermal noise. These effects cause signal attenuation within the cable, which pushes the signal closer to a certain noise floor, resulting in a lower SNR. The third mechanism that contributes to SNR degradation is nonlinear distortion. Furthermore, SNR degradation is known to occur in other channels as well, such as wireless (radio links, e.g., point-to-point backhaul, LTE, Wi-Fi, etc.) and fiber optics.

[0029] Knowing the importance of SNR when transmitting samples, the inventors analyzed possible modulation techniques for sample transmission that would take advantage of the resilience provided by SSVT to increase information density. One such modulation technique is orthogonal frequency division multiplexing (OFDM). Considering the encoding and transmission of digital or analog samples, it can be seen that OFDM combined with SSVT increases information density while improving electrical robustness. Therefore, the inventors concluded that improving OFDM by integrating it with the encoding and transmission of analog and digital samples would offer significant advantages.

[0030] The combination of OFDM and SSVT power is particularly advantageous when using electromagnetic paths with strong path-length dependencies and nonlinearities, such as cables and other media, optical fiber, and systems that operate in noisy environments or require greater use of available bandwidth. Furthermore, in the absence of noisy or hostile environments, the performance gains of the OFDM / SSVT combination translate directly into increased communication distances in more ideal environments.

[0031] Furthermore, it is recognized that OFDM is used in many high data rate wireless systems (and other electromagnetic paths) because of its many advantages, and that the OFDM / SSVT combination also offers these advantages. These advantages include: Resistance to frequency-selective fading: OFDM is more tolerant to frequency-selective fading than single-carrier systems because OFDM splits the overall channel into multiple narrowband signals, which are affected individually as flat-fading subchannels. Resistance to interference: Interference appearing in the channel may be bandwidth-limited and not affect all sub-channels, meaning that not all data is lost. Spectral efficiency: OFDM makes efficient use of the available spectrum. Resistance to ISI: OFDM is highly tolerant to inter-symbol and inter-frame interference due to the low data rate of each subchannel. Resistance to narrowband effects: By using appropriate channel coding and interleaving, it is possible to recover symbols lost due to frequency selectivity of the channel or narrowband interference. Not all data is lost. Simpler channel equalization: One of the problems with CDMA systems was the complexity of channel equalization, which had to be applied across the entire channel. The advantage of OFDM is that by using multiple subchannels, channel equalization becomes simpler. As will be explained in more detail below, video transmission using improved OFDM techniques (without SSVT input) has been found to be advantageous in a variety of implementations. Complex Input OFDM Transmitter

[0032] FIG. 1 illustrates an OFDM scheme 1 for transmitting data using complex inputs. Other schemes for implementing an OFDM transmitter may also be used. As known to those skilled in the art, orthogonal frequency division multiplexing (OFDM) is a multi-carrier modulation technique that uses multiple subcarriers within a channel. Each subcarrier is modulated with a specific modulation scheme. OFDM is a form of conventional frequency division multiplexing (FDM), but differs in that the multiple subcarriers are orthogonal to one another. Typically, OFDM transmitters output complex values ​​from the IFFT, but the present invention also contemplates certain OFDM schemes that output real values ​​from the inverse FFT, as described in more detail below.

[0033] Although not shown in FIG. 1 , the input to the transmitter can be a digital input of a bit stream or an analog input of analog levels, both of which are described in more detail below. In the case of a digital input, the input bit stream may be encoded, interleaved, and grouped before being mapped to a particular constellation to generate a stream of complex numbers. A digital modulation scheme, such as BPSK, QPSK, or QAM, may be used, with QAM being preferred due to its superior performance. As described in more detail below, embodiments disclose novel techniques for mapping digital or analog output levels from an encoder to a complex stream 7 for use in an OFDM transmitter. The encoder encodes digital or analog samples (e.g., video samples).

[0034] In another embodiment, for fixed channels that do not change over time (or do not change frequently), a technique called "bin loading" can be used. In the case of digital modulation, attenuated bins (due to the channel) are either disabled or mapped to a lower modulation order (e.g., QPSK instead of 64QAM). Bin loading requires a negotiation period between the receiver and transmitter. The receiver informs the transmitter of the state of each bin in the channel estimate.

[0035] As shown in Figure 1, an OFDM scheme 1 has a particular channel bandwidth 3 and uses any number, K, of orthogonal subcarriers 5, which may overlap. The input to the OFDM transmitter is a complex number stream 7 (the generation of which is described in more detail below), which is used to load any number of FFT bins 9; that is, one complex number corresponds to one bin. Each of these complex numbers (or source symbols) is treated as being in the frequency domain and input to an inverse fast Fourier transform (IFFT) block 10 to transform the data into the time domain. Thus, each complex number specifies both the amplitude and phase of a sinusoid for a particular subcarrier. The number of orthogonal subcarriers used, and therefore the number of bins 9, will vary depending on the particular implementation.

[0036] Generally, not all bins contain input data. Some bins are pilot bins, and zero bins contain no input data. Additionally, some bins at the high and low end of the spectrum are also nulled and are called guard bins. These guard bins are intended to reduce interference with adjacent channels. With current technology, especially when using low-phase-noise frequency sources, the number of guard bins is approximately four on each side. The IFFT size is typically a power of two (e.g., 64, 128, 256), and to reduce implementation complexity, it is often a power of four (e.g., 64, 256, 1024). As mentioned above, the zero subcarrier (bin), which is the center frequency (or DC), is unused and always nulled. Pilot bins may be added during reception for phase tracking and channel estimation tracking (when the channel is not fixed). Other standards that assume a channel with little fading (quasi-fixed channel) typically allocate a pilot bin every 15 data bins. In fixed channels, pilot bins are redundant and may not be used at all.

[0037] Once all bins of the IFFT block 10 are loaded (with complex numbers from the input stream), the inverse FFT takes this frequency-domain input data (i.e., complex numbers representing subcarriers) and converts it into time-domain output data. That is, each subcarrier is independently modulated with its corresponding complex data. Each block 11 of K output samples is considered a single OFDM symbol. Each OFDM symbol 11 may be clocked out at a specific rate, providing an OFDM waveform of a specific duration. Once in the time domain, a guard interval 13 of a specific duration is typically added between each OFDM symbol (usually at the beginning of each waveform). This prevents inter-symbol interference at the receiver. Thus, an OFDM symbol consists of the IFFT OFDM waveform and the guard interval.

[0038] Further processing of each OFDM symbol is performed, and the above process is repeated to successively create OFDM symbols 11 from the input data. Prior to transmission, multiple OFDM symbols are concatenated (15) and a preamble is added (to aid in receiver synchronization due to imperfections in transmission) to form a single time-domain burst signal. This burst signal (or component baseband signals) may be used, for example, to modulate a primary RF carrier for transmission to an OFDM receiver as an OFDM burst. This is well known in the art. As will be known to those skilled in the art, an OFDM receiver performs an FFT on the received OFDM symbols to convert them back to the frequency domain.

[0039] To recover the original data (digital or analog output levels from the encoder) input to the OFDM transmitter, the inverse of the novel mapping technique is performed, as described in more detail below, followed by decoding at the digital or analog level to recover the original digital or analog samples (e.g., video samples) that were input to the encoder.

[0040] The number of concatenated OFDM symbols depends on the system requirements. For example, it depends on how quickly the system needs to resynchronize to the stream if the connection is lost. If fast locking is required, the preamble may appear more frequently. If the receiver needs to lock on the first preamble it receives, a preamble with a good autocorrelation peak should be selected. Otherwise, a shorter and simpler preamble can be used.

[0041] In general, all input samples to the IFFT are used to calculate a single output of the IFFT. Each output is the sum of all samples at the input, each multiplied by a different coefficient depending on the input / output index. Thus, to calculate K output samples, all K bin components are used. After the K input bins are filled, they are all used to calculate K output samples in the time domain. The K output samples represent the signal waveform of K consecutive samples, and each output is complex-valued (for complex IFFTs; real IFFTs are discussed later). These K output samples are collectively called an OFDM symbol.

[0042] Typically, a cyclic prefix (or guard interval) is added to the beginning of an OFDM symbol by copying M samples from the end of the K IFFT output samples to cancel inter-symbol interference. In most cases, the K IFFT output samples plus the M guard interval samples are referred to as an OFDM symbol, rather than just the K IFFT output samples. OFDM transmitter that maps digital input to complex numbers

[0043] The following embodiments use SSVT followed by OFDM, with either digital or analog samples input to an OFDM transmitter (e.g., Figures 2 and 6). This type of video transmission may be used to send video over long distances to a display, television, or monitor. It may also be used within a display to send video from the display's input to a source driver.

[0044] 2 shows an improved OFDM transmitter 80 with a digital input. As shown, the output from the encoder described herein is L digital output levels 21 (e.g., levels 161 in FIG. 8) that are input to a symbol mapping unit 30. Any of the techniques described herein can be used to map the input digital levels to complex numbers, i.e., Q component 32 and I component 36.

[0045] In one embodiment, a mapping technique from quadrature amplitude modulation (QAM) is used to generate the complex numbers used for modulation. As is well known in the art, a phase-modulated sine wave can be synthesized from two amplitude-modulated sine waves whose phases are offset by 1 / 4 cycle (π / 2 radians). These amplitude-modulated sine waves are known as the in-phase (I) and quadrature (Q) components. The digital levels 21 are received one at a time as a bit stream and first input into a serial-to-parallel converter (not shown). This converter converts the bit stream into parallel groups of bits representing digital values. For example, if the digital value to be modulated is four bits long, the converter converts the bit stream into groups of four bits. Each group is input into the mapping unit 30 in a specific manner depending on the mapping technique used. In this example, there is a single mapping unit that inputs the digital value and outputs I and Q values ​​to the inverse FFT circuit 39.

[0046] The symbol mapping unit 30 generates a Q component 32 and an I component 36. These two components represent complex numbers and are input to an inverse FFT circuit block 39 where they are processed by the IFFT described above. Although not shown, a guard interval (or cyclic prefix) insertion block may be placed within or immediately after block 39. In this way, the IFFT circuit 39 generates output samples, each of which is a complex number having a Q component 32a and an I component 36a that are input to low-pass filters 40 and 42.

[0047] The Q and I components (I and Q are real signals, and the pair {I,Q} is a complex signal) pass through low-pass filters 40 and 42, respectively, to limit the signal bandwidth. Next, an IF source 44 (essentially a numerically controlled oscillator) receives the in-phase and quadrature components, multiplies each signal by its amplitude, shifts the quadrature component 90° out of phase, and then adds them together in summer 50. The output of summer 50 is a real signal representing the original digital value input to the transmitter. DAC 51 converts that digital value to analog. A band-pass filter 60 is used to filter out unwanted spurs and harmonics, and the resulting signal 70 can be fed to a variable gain amplifier (VGA) 78 to output an OFDM signal 90 representing level 21. In another, more conventional implementation (not shown), referring to FIG. 2, DACs are present in both the I and Q paths (immediately before low-pass filters 42 and 40), and subsequent blocks are implemented analog, eliminating the need for DAC 51. This implementation requires a much lower sampling rate and potentially allows for the use of less expensive components. Typically, an amplifier 78 (and amplifiers 680, 748, and 798, described below) is used, but it need not be a VGA. Also, while the output is shown as an RF signal 90 (or 690, 749, and 799, described below), the output signal may be any electromagnetic signal that propagates through wire, cable, fiber optics, etc.

[0048] As mentioned above, it is recognized that QAM can be used to modulate the subcarriers with various modifications to the OFDM transmitter mapping, as described below. Depending on the implementation, different sizes of QAM constellations can be used. In one example, a 16-QAM constellation can be used in conjunction with transmitter 80 to map digital values ​​to complex numbers. In a 16-QAM constellation, each digital value is 4 bits. Mapping each digital value through the constellation produces a vector with an amplitude and a phase. Of course, smaller and larger constellations can also be used. For example, a 1024-QAM constellation could be used. Each digital value in this constellation would be 10 bits long. The most common QAM constellation size is 4 n These are 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, etc. Larger QAM constellation sizes are rarely used. n Other QAM constellations exist, but are more complex to encode.

[0049] In other embodiments, the OFDM transmitter may be implemented differently. For example, instead of a single mapping unit 30, there may be two mapping units 30a and 30b (each for M-ary PAM). Each group of bits representing a digital value is split, with two bits routed to unit 30a to generate the Q component and two bits routed to unit 30b to generate the I component. An inverse FFT circuit 39 outputs the Q component 32a and the I component 36a to an interpolation filter, which is used to increase the sampling rate of the input signal. Two frequency conversion components receive the output from each interpolation filter and provide an upconverter for frequency translation from baseband to the signal. An NCO (numerically controlled oscillator, instead of an IF source) interacts with the conversion components to generate an in-phase component and a quadrature component. These are summed by a summer to generate the real output signal, which is then passed to the DAC, filter, and VGA. These components may be implemented within a MAX5857 RF DAC (which includes a clock-multiplying PLL / VCO and a 14-bit RF DAC core). Actual samples are input every clock cycle, with amplitude and phase derived from the constellation map. This implementation assumes that the DAC is clocked at a frequency higher than or close to the RF frequency. An alternative is to place two DACs in the I and Q paths before the interpolation filter instead of a single DAC. The implementation described in this paragraph may be preferred over the one in Figure 2 because it is a cleaner implementation. Mapping digital values ​​to complex numbers

[0050] The mapping in unit 30 of FIG. 2 performs symbol mapping, which can be performed in any suitable manner using circuit techniques known in the art. Symbol mapping 30 can also include a mapping circuit that maps input digital levels in an improved manner, as described below. In one embodiment, for each digital output level from the encoder, the lower half of each output level's bits are transmitted over the Q path, and the upper half of each output level's bits are transmitted over the I path. In another embodiment, all odd-numbered output levels are transmitted over the Q path, and all even-numbered output levels are transmitted over the I path. In another embodiment, if each digital output level is 12 bits long and 16-QAM is used, the value is divided into three groups of four bits, each divided into an I value and a Q value of two bits each. Other division methods can also be used. In another mapping embodiment, Gray coding may be used. For digital data, Gray coding is used to reduce the probability of multiple bit errors. Gray coding means that the coding of adjacent constellation points differs by only one bit.

[0051] In a preferred embodiment, the most significant bit (MSB) of each digital output level from the encoder is divided between the I and Q paths and becomes their MSB. Meanwhile, the least significant bit (LSB) of each digital output level is divided between the I and Q paths and becomes their LSB. For example, if the digital output level is a 4-bit binary string [ABCD], where A, B, C, and D each represent a binary digit (e.g., "1" or "0"), AB represents the most significant bit, and CD represents the least significant bit. The 4 bits are distributed between the I and Q paths as follows: I=AC, Q=BD. Therefore, the most significant bit of the digital output level becomes the most significant bit on the I and Q paths, and the least significant bit of the digital output level becomes the least significant bit on the I and Q paths.

[0052] The reason for this distribution is the recognition that noise and other disturbances along the transmission medium can cause the received OFDM signal to be slightly distorted, resulting in the loss of least significant bits. However, because the digital output levels of the present invention may represent a media signal (e.g., pixel values ​​from a camera source), it is not strictly necessary for every bit to be perfectly preserved from transmitter to receiver. In contrast, the transmission of digital data (e.g., documents) between computers requires perfect preservation of every transmitted bit and sophisticated error detection. In other words, OFDM receivers are more sensitive to MSB errors than LSB errors. Therefore, this distribution protects the MSB better than the LSB. Unlike digital data transmission, where every bit is important, not all bits in this distribution have the same weight. The closer a bit is to the MSB, the more important it is. Therefore, by splitting the MSB and LSB of each digital output level into the I and Q paths, if the received OFDM signal is distorted or incorrectly received, only the LSB of the original digital output level is lost. Losing the LSB of the received media signal is not catastrophic.

[0053] 3A is an embodiment 500 showing how the division of MSB and LSB is performed within the mapping circuit. m Assuming that 510 is represented by N bits, and 510 has an arbitrary number of MSB bits 512 and an arbitrary number of LSB bits 514, the MSB bits are half or approximately half of the total number of bits. Then, assuming that N is an even number, the digital output level can be obtained by selecting the even and odd bits to obtain two digital values, XI m 530 and XQ m 520. The even bits (including 0) are assigned the value 530 and the odd bits are assigned the value 520. The new digital value, XI m and XQ mmay each be further converted to a binary representation of a signed value, with the MSB of each value being the value's sign and the remaining bits being the value's amplitude. The resulting values ​​531 and 521 are used as the values ​​for the I and Q paths of the complex QAM plane, respectively. Of course, it is also possible to assign even bits to value 520 and odd bits to value 530.

[0054] In the above scheme, the most significant bit of each digital value becomes the sign bit, but the value it represents is not lost. This means that "closer" values, such as -1 and 0, are mapped to very close constellation points. Even if the MSBs of the two values ​​are not the same, any error between them will result in the smallest possible error in the "analog" sample of "1."

[0055] Other techniques are possible for creating signed values ​​from values ​​520 and 530. As an example, instead of mapping the MSB to the sign bit, another way to map the values ​​to constellation points can be done by subtracting an offset value, which is the midpoint between the minimum and maximum values, from the unsigned value.

[0056] FIG. 3B shows a graph 540 illustrating how values ​​521 and 531 represent points 542 on the complex QAM plane.

[0057] Figure 3C shows an example QAM constellation 560. Note that because there is a finite number of bits used to represent XIm and XQm, there is also a finite number of actual values ​​Im and Qm. In this example, the original digital output level 510 is 6 bits, so Im and Qm are represented by 3 bits each, with the first bit being the sign bit, and the values ​​range from -3 to 3, as shown in the constellation. Therefore, this constellation can be used to map XIm and XQm to I and Q values ​​for the I and Q paths of an OFDM transmitter.

[0058] FIG. 4A shows another embodiment of how digital output levels can be mapped within a mapping circuit, where even and odd digital levels X m-1 and X m are directly mapped to the I and Q components, respectively, using the same binary representation to map digital levels to the QAM plane. Again, the MSB of each is treated as the sign bit. The input digital level X m 570 and subsequent Digital Level X m-1 Assume that 572 are each represented by N bits. The resulting values ​​581 and 583 can be used as the values ​​for the I and Q paths, respectively, in the complex QAM plane.

[0059] FIG. 4B shows a graph 590 illustrating how values ​​581 and 583 represent a point 592 on the complex QAM plane. OFDM transmitter that maps analog input to complex numbers

[0060] As discussed above and elsewhere herein, instead of encoding digital samples 112 to generate digital output levels 161, as shown, for example, in FIG. 8, an embodiment of the present invention may encode analog samples to generate analog output levels. Thus, the L output levels from the encoder will be analog levels, which may appear, for example, as shown in the waveforms of FIG. 14. An embodiment of the present invention may also modulate and transmit these L analog output levels using an improvement to orthogonal frequency division multiplexing (OFDM), as described below. As shown in FIG. 14, the analog levels can be positive or negative. These levels do not change how the mapping is performed. In the digital case, the idea of ​​setting the MSB as the sign bit is simply to map an "unsigned" value to a positive or negative value.

[0061] Figure 5 shows a constellation mapping 300 that is useful in explaining how OFDM uses analog output levels from an encoder as input. While this constellation still shows 16 digital values ​​304, no mapping to these values ​​is used; these values ​​are shown only to help the reader understand how the analog levels are input. While it would be possible to convert the sequence of L analog output levels from the encoder to digital output levels and input these digital levels to the OFDM transmitter, as shown in Figure 2, the implementation described here uses the analog output levels directly. That is, the analog output levels themselves can directly represent the in-phase (I) and quadrature (Q) components.

[0062] 6 shows an improved OFDM transmitter with analog input 610. Shown are L analog output levels 601 from an encoder as described herein, which are input to the transmitter 610.

[0063] The switch device 612 performs a sample-and-hold function, simultaneously presenting alternating samples (odd, even) of the received analog levels to the Q path 626 and the I path 628 as time-aligned pairs. Thus, one {I,Q} pair is generated for every two analog levels. This time alignment is necessary to ensure that the serially presented analog levels are simultaneously modulated within the constellation. The switch 612 may be any suitable hardware device used to select the destination of each level and distribute these levels to one of the paths. In a corresponding OFDM receiver, the switch 612 is replaced by a combining device or circuit that accepts the {I,Q} pairs from the FFT, combines each pair into a sequence of two analog levels, and outputs a stream of analog levels corresponding to the analog levels originally received at the OFDM transmitter 610.

[0064] As described above, switch 612 generates Q component 626 and I component 628. These two complex components are then input to inverse FFT circuit block 639 for processing by IFFT as described above. Thus, each input to IFFT circuit 639 also generates a complex number having Q component 626a and I component 628a, which are input to low pass filters 640 and 642. The Q and I components (I and Q are real signals, and {I, Q} are complex signals) pass through low pass filters 640 and 642, respectively, to limit the signal bandwidth. Next, IF source 644 (essentially a numerically controlled oscillator) receives the in-phase and quadrature components, multiplies each signal by its amplitude (which is the amplitude of the NCO, shifted by 90 degrees), shifts the quadrature component out of phase by 90 degrees, and sums them together in summer 650. The output of summer 650 is a real signal (also known as a passband signal, which is a baseband signal shifted to the NCO frequency) that represents the original two continuous analog levels input to the transmitter. A bandpass filter 660 is used to remove unwanted spurs and harmonics, and finally a variable gain amplifier 680 is used to amplify and output an OFDM signal 690 that corresponds to the original continuous input of analog output levels 601 from the encoder.

[0065] A serial-to-parallel converter can be added before the inverse FFT block 639 to align the L samples in parallel (i.e., generate parallel I and Q inputs), and then perform the IFFT. After the IFFT, a parallel-to-serial combiner is used.

[0066] As an example, given a sequence of L analog output levels 601, consider that odd-numbered values ​​are placed on the I path 628 and even-numbered values ​​are placed on the Q path 626. Of course, odd-numbered values ​​could be placed on the Q path and even-numbered values ​​on the I path. Thus, the I and Q components can each represent a different analog output level. Taking the output levels 601 as an example, the first level 602 would be placed on the I path, the second level on the Q path, the third level on the I path, and so on. To illustrate, returning to Figure 5, assume the first analog level is "2" and the second analog level is "3." Conceptually, these two values ​​(I, Q) are mapped to points 310, generating a vector with a particular amplitude and phase 312, as shown. Next, assume the third analog level is "-2" and the fourth analog level is "-0.5." These two levels are in turn mapped to points 320 that generate a vector with a particular amplitude and phase 322. In this way, a sequence of L analog output levels 601 can be input to an OFDM transmitter 610 to generate an RF signal 690. Although output 690 is shown as an RF output, output via other types of electromagnetic paths such as cable or fiber optics are also possible.

[0067] In fact, while Figure 5 shows a QAM constellation for ease of illustration, it is not necessary to map each analog level to a specific digital constellation point (e.g., point 304), since each analog level can be used directly to provide I and Q values. The amplitude and phase of the resulting vector are determined using the I and Q values, as shown.

[0068] Other techniques are possible that use direct mapping of analog output levels. With analog samples, it is useful to minimize the magnitude of the error. Therefore, it makes sense to map even and odd samples separately to I and Q. With analog samples, the least significant bits of each sample are less important than the most significant bits, so Gray coding may not be appropriate. Therefore, odd-numbered levels may be sent to the Q path 626 and even-numbered levels to the I path 628, or vice versa. OFDM transmitter with digital or analog input (with real output from IFFT)

[0069] The following embodiments generate real output values ​​from the inverse FFT. Generally, when computing the inverse FFT of N values, the output is complex. However, by ensuring that the input bins are conjugate symmetric, the inverse FFT output is only real, i.e., the I component of all N output values ​​is 0. Essentially, to generate N real values ​​at the output of the IFFT, N / 2-1 complex I and Q symbols are repeated using their conjugates. Because the output is real, this implementation does not require an NCO or frequency conversion and can be transmitted directly from the IFFT output. This has the advantage of not requiring an I / Q modulator that uses a carrier (NCO) to phase shift the I component (by 90 degrees) before adding it with the Q component. This 90-degree shift (relative to the entire signal spectrum) occurs solely through this NCO+IQ mixer mechanism. These embodiments can be used in place of the above embodiments in which the inverse FFT outputs complex values.

[0070] It would be advantageous to generate the signal directly in the spectrum of a "baseband" channel, such as an Ethernet cable. An Ethernet cable (or telephone line, etc.) carries signals starting at very low frequencies (perhaps a few hertz) up to some finite frequency. Thus, the zero bin (also called the DC bin) is zero frequency (DC) and does not map to the center frequency of the available bandwidth. Furthermore, no frequency conversion is required in this embodiment.

[0071] 7A shows an improved OFDM transmitter 700a with a digital input. As shown, the output from the encoder described herein is L digital output levels 701 that are input to a symbol mapping unit 730. Any of the techniques described herein (e.g., QAM modulation) can be used to map the input digital levels to complex numbers, namely, I component 732 and Q component 734. In block 735, N real-frequency FFT bins (corresponding to the N subcarrier frequencies) are loaded with N / 2-1 of the I,Q symbol pairs received from unit 730.

[0072] Assuming there are N FFT bins, numbered 0 through N-1, corresponding to N subcarrier symbols, block 735 can be implemented as follows: First, collect N / 2-1 symbols from the symbol mapping 730 for digital input or from the switch 780 for analog input. Each symbol x(i) is an I,Q pair representing a complex number from the mapping or switch, where x(i), i = [1:N / 2-1]. Next, set FFT bin 0 to 0 and FFT bin i to [1:N / 2-1] to obtain x(i). Next, set FFT bin N / 2 to 0 and FFT bin i to [N / 2+1:N-1] to obtain x*(Ni). Here, "*" denotes the complex conjugate operator, i.e., the bins on either side of the N / 2 bin hold the complex conjugate of each other. For example, if bin N / 2-1 holds a+bi, then bin N / 2+1 holds a-bi, and the bins on either side of these first immediate bins hold the complex conjugates, so taking the inverse FFT of these bins will produce a real output rather than a complex one.

[0073] Also, in many descriptions of FFTs, frequencies are indexed positively and negatively. Therefore, the above description may be modified to conform to those standards and written as follows: Next, set FFT bin 0 to 0, and set FFT bin i=[1:N / 2-1] to x(i). Next, set FFT bin i=[-N / 2+1:-1] to x*(-i), and set bin -N / 2 to 0. Here, "*" is the complex conjugate operator.

[0074] The resulting FFT bins from block 735 contain N-2 I,Q pairs (736 and 738), as described above, which are input to inverse FFT block 739 and processed using an inverse FFT, as described above and as is well known in OFDM transmitters. Due to the overlap of N / 2-1 complex numbers in block 735, inverse FFT 739 produces a real output rather than a complex one. A cyclic prefix (or guard interval) is added in block 740, digital-to-analog conversion is performed in block 742, a low-pass filter is applied in block 746, and finally, the signal is amplified in VGA 748 to produce a final OFDM RF signal 749, which is output via an electromagnetic path to the OFDM receiver. Blocks 739-748 can be implemented in a manner well known in the art. While output 749 is shown as an RF output, other types of electromagnetic paths, such as cable or fiber optics, are also possible.

[0075] FIG. 7B shows an improved OFDM transmitter 700b with an analog input. As shown, the output from the encoder described herein is L analog output levels 751 input to switch 780. Any of the techniques described herein (e.g., the analog mapping techniques shown and described in FIGS. 5 and 6) can be used to map the input analog levels to complex numbers, i.e., I component 782 and Q component 784. In block 785, N real-frequency FFT bins (corresponding to the N subcarrier frequencies) are loaded with N / 2-1 of the I, Q symbol pairs received from unit 780 as described immediately above. Blocks 789-798 can be implemented as described above, with the exception of DAC 742, which is not required in this embodiment. While output 799 is shown as an RF output, output via other types of electromagnetic paths, such as cable or fiber optics, is also possible. As described above in FIG. 6, IFFT 789 may be preceded by a serial-to-parallel converter and followed by a parallel-to-serial combiner. And, as mentioned above in FIG. 6, no DAC is required.

[0076] Figure 7C shows the IFFT bins used to generate the real output. An example of bins 710 with N=8 is shown. The zero bin 722 is set to 0, as is the middle bin 723. Bins 724 and 726 illustrate the use of complex conjugates for symmetric loading of the bins. OFDM Receiver and Demodulation

[0077] The foregoing describes an embodiment of an OFDM transmitter and an embodiment that transmits an OFDM electromagnetic signal to a receiver by inputting and mapping L digital output levels from an encoder and by inputting and distributing L analog output levels from the encoder. After reading this disclosure, one skilled in the art can readily implement a corresponding OFDM demodulator and receiver that accepts an OFDM electromagnetic signal and outputs L digital output levels or L analog output levels, as the case may be. This implementation uses the conventions used in the corresponding OFDM transmitter related to the digital mapping technique used or the analog distribution technique used to create the complex numbers input to the inverse FFT. Similarly, if the OFDM transmitter inputs real numbers rather than the complex numbers described above, one skilled in the art can readily implement the corresponding OFDM demodulator and receiver using the conventions used in the corresponding OFDM transmitter related to how the real numbers are input to the inverse FFT. Furthermore, just as the OFDM transmitter of FIG. 2 can be implemented with one or two DACs as described above, the OFDM receiver can be implemented with one ADC or two ADCs, one for the I path and one for the Q path, as will be appreciated by those skilled in the art. Spread Spectrum Video Signal (SSVT)

[0078] The embodiments of the present disclosure described above use a novel discrete-time, continuous-amplitude electromagnetic signal called "Spread Spectrum Video Transmission (SSVT)" that is an improvement over existing SSDS-CDMA signals. SSVT refers to the transmission of an electromagnetic (EM) video signal to a video sink over an electromagnetic path or multiple paths using the novel techniques disclosed herein.

[0079] Code division multiple access (CDMA) is a well-known channel access protocol commonly used in wireless communication technologies, including cellular telephones. CDMA is an example of multiple access, allowing multiple transmitters to simultaneously transmit information over a single communication channel. In telecommunications applications, CDMA allows multiple users to share a particular frequency band without interference from other users. CDMA employs spread-spectrum direct sequence (SSDS), which uses a unique code to encode each user's data. The unique codes allow multiple users' transmissions to be combined and transmitted without interference between them. At the receiver, the same unique code is used for each of the multiple users to demodulate the transmissions and recover each user's data. SSVT differs from CDMA, and this difference is explained in more detail below. SSVT Transmitter Splitter / Encoder

[0080] FIG. 8 illustrates digital encoding of a sampled signal prior to input to the OFDM transmitter 80. As discussed herein in U.S. Patent No. 10,158,396 and U.S. Patent Applications 16 / 494,901 and 17 / 503,984, an input vector 110 containing any number of digital or analog samples is encoded in an encoder using codes from a codebook to generate L output levels 160 for input to the OFDM transmitter 80 and transmission via an electromagnetic path. See below for details of this encoding technique. In this example, the samples are digital values, digital encoding is used, and the output levels 160 are digital values. As discussed in more detail below, analog samples, analog encoding, and analog output levels can also be used. Examples of L analog output levels input to an OFDM transmitter are shown in FIGS. 6 and 7B.

[0081] Input vector 110 contains N samples 112-118. In this example, each sample is 5 bits long, with sample 112 having the value "01101." There are N codes 122-128, each corresponding to one of the samples. Each code is L bits long and orthogonal to one another. To encode, each chip of the code corresponding to a particular sample modulates that sample (130), generating L modulation values ​​for each sample. In this simple example, modulating sample 112 with the first chip of code 122 results in modulation value 142(1). Modulating each sample with the first chip of its corresponding code results in modulation values ​​142(1)-148(1). These modulation values ​​142(1)-148(1) are then summed (150) to generate a first digital output level 161. The other modulation values ​​142(2:L)-148(2:L) are similarly summed to generate the remaining output level 160. This stream of digital output levels can be input to the OFDM transmitters of Figures 2 and 7A, as described above. Although outputs 90 and 749 are shown as RF outputs, outputs via other electromagnetic paths such as cable or fiber optics are also possible.

[0082] The output levels 160 may have any suitable bit length. In one embodiment, each output level is 10 bits long. Therefore, a 1024-QAM (e.g., 2^n QAM is used for every n bits) constellation may be used to map these values ​​for use in an OFDM transmitter that accepts digital input. Also, as noted above, if analog values ​​are input to the OFDM transmitter, no mapping to a constellation is necessary. Furthermore, the digital or analog output levels from the encoder may result in the use of real numbers (rather than complex numbers) in the OFDM transmitter. Improvements regarding digital input mapping, analog input mapping, and the use of real numbers are described in detail above.

[0083] Figure 9 shows a logical block diagram of a specific implementation of the SSVT transmitter 428. The distributor 440 includes an assembly bank 450, a staging bank 452, a presentation bank 454, and a controller 456. The encoder block 460 includes a bank of digital-to-analog converters (DACs) 462 and four encoders 442, one for each EM path of the transmission medium. As described above, a sample stream from a single source (e.g., a camera, image sensor, or other sensor) arrives at the transmitter 428 for encoding. Each encoder 442 encodes an input vector, such as input vector 110, and generates an EM signal with a sequence of output levels, such as output level 160. Therefore, there may be any number (P) of encoders 102 and corresponding OFDM transmitters, one encoder and one OFDM transmitter per EM path. It is also possible to multiplex multiple encoder outputs into a single OFDM transmitter, resulting in fewer transmitters than encoders.

[0084] The distributor 440 is configured to receive the exposure color information (e.g., RGB) of the stream of sample sets one after the other. In response, the assembly bank 450 constructs four vectors V0, V1, V2, and V3 from the exposure color information (e.g., RGB) of the incoming stream of sample sets. As the sample sets are received, they are stored in the assembly bank 450 according to a predetermined permutation. The distributor 440 can use any number of different permutations when constructing the vectors, each containing N samples.

[0085] Staging bank 452 facilitates the crossing of N samples of each of the four vectors V0, V1, V2, V3 from a first clock frequency (or first timing domain) used by the retimer to a second clock frequency (or second domain) used for encoding the resulting EM signal and transmitting it over a transmission medium. Explaining the example of N=60 and S=3, the four encoder input vectors V0, V1, V2, V3 contain samples representing exactly 80 sets of RGB samples.

[0086] In various embodiments, the first clock frequency may be faster, slower, or the same as the second clock frequency. The first clock frequency, f_pix, is determined by the video format selected by the video source. The second clock frequency, f_ssvt, is a function of f_pix, the number of EM paths in the transmission medium, P, the number of samples in each set of input / output samples, the SSVT transformation parameters, N (the number of input / output vector positions), and L (the length of each SSDS code), where f_ssvt = (f_pix * S * L) / (P * N). In this configuration, the input clock (pix_clk) oscillates at a constant rate, and the SSVT clock (ssvt_clk) oscillates at another rate. These rates may be the same or different. The encoder performs encoding while the next input vector is prepared. The presentation bank 454 presents four N samples of each of the encoder input vectors V0, V1, V2, and V3 to the encoder block 460 (e.g., vector V0 has four N samples). 0,0 Sample from 0,N-1 (including up to

[0087] A controller 456 controls the operation and timing of the assembly bank 450, the staging bank 452, and the presentation bank 454. In particular, the controller is responsible for defining the permutation and number of samples N used in constructing the four encoder input vectors V0, V1, V2, and V3. The controller 456 is also responsible for coordinating the clock domain crossing from the first clock frequency to the second clock frequency performed by the staging bank 452. The controller 456 is further responsible for coordinating the timing at which the presentation bank 454 presents the N samples of each of the encoder input vectors V0, V1, V2, and V3 to the encoder block 460.

[0088] Within the encoder block 460, there are provided a number of digital-to-analog converters (DACs) 462, each of which converts P*N samples (samples) assigned to the four encoder input vectors V0, V1, V2, and V3. 0,0 Sample from P-1,N-1 ) together. Each DAC 462 converts the received samples into a pair of differential voltage signals whose magnitude is proportional to the incoming digital value from the digital domain. The output of a DAC 462 can range from a maximum voltage to a minimum voltage.

[0089] Four encoders 442 are provided corresponding to four encoder input vectors V0, V1, V2, and V3, respectively. Each encoder 442 receives a differential signal pair for each of the N samples for that encoder input vector, modulates each of the N differential voltage signal pairs with a code chip corresponding to each sample, accumulates the modulated values, and generates a differential EM signal output. Because there are four encoders 442 in this example, there are EM signals (signal 0 through signal 3) transmitted simultaneously over the transmission medium.

[0090] The sequencer circuit 465 adjusts the operation timing of the DAC 462 and the encoder 442. The sequencer circuit 465 is responsible for clock control of the DAC 462 and the encoder 442. The sequencer circuit 465 also plays a role in generating two clock phase signals “clk1” and “clk2” that control the operation of the encoder 442.

[0091] A receiver corresponding to the transmitter 428 can be used to receive, decode, and assemble the output levels into RGB signals, as would be understood by one of ordinary skill in the art after reading this disclosure. While analog encoding is shown in this example, digital encoding (and decoding) can also be used. The DAC or ADC can be placed before or after the encoder (or decoder), depending on the case and implementation requirements. SSVT signaling, encoding, and decoding

[0092] As described above, various embodiments of the present invention disclose that an SSVT signal, which is an encoded output level (analog or digital), is input to an OFDM transmitter, or that an OFDM receiver receives an OFDM modulated signal and generates an SSVT signal for decoding. The SSVT signal will be described in more detail below, and its advantages will be presented.

[0093] In an embodiment of the present disclosure, a novel "Spread Spectrum Video Transmission" (SSVT) signal (a discrete-time, continuous-amplitude electromagnetic signal) is disclosed as an improvement over existing SSDS-CDMA signals. SSVT refers to transmitting an electromagnetic signal over an electromagnetic path or multiple paths using modified spread-spectrum direct sequence (SSDS)-based modulation.

[0094] Code division multiple access (CDMA) is a well-known channel access protocol commonly used in wireless communication technologies, including cellular telephones. CDMA is an example of multiple access, allowing multiple different transmitters to simultaneously transmit information over a single communication channel. In telecommunications applications, CDMA allows multiple users to share a particular frequency band without interference from other users. CDMA employs spread-spectrum direct sequence (SSDS) encoding, which uses a unique code to encode each user's data. The unique codes allow multiple users' transmissions to be combined and transmitted without interference between them. At the receiver, the same unique code is used for each user to demodulate the transmission and recover each user's data.

[0095] SSVT signaling differs from CDMA. For example, when a stream of input video samples is received by an encoder, SSDS-based modulation is applied to each of multiple encoder input vectors to encode them and generate an SSVT signal. The SSVT signal is then transmitted over a transmission medium. At the receiving end, the received SSVT signal is decoded by applying corresponding SSDS-based demodulation to reconstruct the encoded samples. As a result, the original stream of time-ordered video samples, including color and pixel-related information, is transmitted from a single video source to a single video sink, unlike CDMA, which distributes data from multiple users to multiple receivers.

[0096] Figure 10 shows a simplified example of how signal samples (in this case, analog values) are encoded within an encoder and transmitted over an electromagnetic path. An input vector of N analog values ​​902-908 is shown, representing the voltages of individual pixels in a video frame. These voltages represent the brightness of a black-and-white image or a specific color value of a pixel (e.g., the pixel's R, G, and B color values). That is, each value represents the amount of sensed or measured light in a specified color space. While pixel voltages are used in this example, this encoding technique may also be used with voltages representing any of a variety of signals from sensors, such as LIDAR values, sound values, tactile values, or aerosol values, and the analog values ​​may represent other samples, such as electrical currents. Signal samples that are digital values ​​may also be encoded, and this digital encoding is described below. Furthermore, while one encoder and one EM path are shown, embodiments of the present invention work well with multiple encoders, each transmitting over an EM path.

[0097] For efficiency reasons, these voltages preferably range from 0 to 1 V, but different ranges are possible. These voltages are typically derived from pixels in a row of the frame in a specific order, but other rules for selecting and ordering these pixels may be used. Whatever rule is used to select and order these pixels for encoding, the decoder at the receiving end uses the same rule to decode these voltages in the same order and place them in the appropriate positions in the resulting frame. Similarly, if the frame is color and uses RGB, this encoder might employ a rule where all R pixel voltages are encoded first, followed by G and B voltages. Alternatively, the voltages 902-906 might represent the RGB value of the pixel in that row, and the next three voltages 908-912 represent the RGB value of the next pixel. The same rule used by this encoder to order and encode the voltages is also used by the receiving decoder. The specific rule (color value, row, etc.) used to order the analog values ​​902-908 can be anything, as long as the decoder uses the same rule. As shown, using codebook 920, the number of N analog values ​​902-908 that can be presented for encoding at one time is limited only by the number of entries in the codebook.

[0098] As described above, codebook 920 contains an arbitrary number (N) of codes 932-938. In this simple example, the codebook contains four codes, meaning that four analog values ​​902-908 are encoded at a time. While a larger number of codes, such as 127 codes or 255 codes, may be used, fewer codes are preferred for practical reasons, such as circuit complexity. As is well known to those skilled in the art, codebook 920 contains N mutually orthogonal codes, each of length L. In this example, L=4. Typically, each code is an SSDS code, but as described herein, it is not necessarily a spreading code. As shown, each code is divided into L time intervals (also called "chips"), each containing the binary value of that code. While code 934 may be represented in the conventional binary format "1100," as shown in code representation 942, the same code may also be represented as "1 1 -1 -1," as shown in code representation 944, for ease of use in modulating values, as described below. Codes 932 and 936-938 can also be represented as 942 or 944. Note that each code of length L is not associated with a different computing device (such as a phone), a different person, or a different transmitter, as in CDMA.

[0099] Thus, to transmit the four analog values ​​902-908 to a receiver (with corresponding decoder) over the transmission medium 34, the following technique is used: each analog value is modulated by each chip in the representation 944 of the corresponding code. For example, value 902, i.e., "0.3," is modulated 948 by each chip in the representation 944 of code 932, sequentially in time. Modulation 948 can be a multiplication operator. Thus, modulating "0.3" with code 932 results in the sequence of values ​​"0.3, 0.3, 0.3, 0.3." Modulating "0.7" with code 934 results in "0.7, 0.7, -0.7, -0.7." The value "0" becomes "0, 0, 0, 0," and the value "1" becomes "1, -1, 1, -1." Typically, the first chip of each symbol modulates the corresponding analog value, and then the next chip of each symbol modulates that analog value, but some implementations use all chips of a symbol to modulate a particular analog value before moving on to the next analog value.

[0100] In each time interval, the modulated analog values ​​are summed at 951 (perceived vertically in this diagram) to obtain analog output levels 952-958. For example, the sum of the modulated values ​​in these time intervals results in output levels 2, 0, 0.6, and -1.4. These analog output levels 952-958 may be further normalized or amplified to conform to the voltage limitations of the transmission path and then transmitted sequentially in time in the order in which they were generated over an electromagnetic path (e.g., a differential twisted pair) on the transmission medium 34. A receiver then receives these output levels 952-958 sequentially and decodes them using the same codebook 920, using the inverse of the encoding scheme shown here. The resulting pixel voltages 902-908 are then displayed in frames on the receiving display according to the convention used. Thus, the analog values ​​902-908 are effectively synchronously encoded and transmitted over a single electromagnetic path as a sequential sequence of L analog output levels 952-958. As shown herein, multiple encoders and electromagnetic paths can also be used. Furthermore, the number of N samples that can be encoded in this manner depends on the number of orthogonal codes used in the codebook.

[0101] Advantageously, even though the use of robust SSDS techniques (e.g., spreading codes) significantly reduces bandwidth, the use of mutually orthogonal codes, modulating each sample with a chip of the corresponding code, summing, and transmitting N samples in parallel at L output levels results in a significant bandwidth increase. Whereas traditional CDMA techniques serially encode binary numbers and then sum them, the present invention first modulates the entire sample (i.e., the entire analog or digital value, rather than a single bit) with the code to which each chip corresponds, then sums those modulations at each time interval of the code to obtain the resulting analog voltage level at each particular time interval, and the resulting waveform amplitude is utilized. It is these analog output levels, not binary number representations, that are transmitted over the transmission medium. Furthermore, unlike CDMA techniques, which allow multiple accesses by different people, devices, or sources and transmit to multiple sinks, the present invention facilitates the transmission of analog voltages from one video source to another, i.e., from endpoint to endpoint. Furthermore, no compression is required for the transmission of sample values.

[0102] Figure 11 shows how this novel encoding technique can be applied to signal samples that are digital values. Here, digital values ​​902'-908' are digital representations of voltages. Using a different voltage example, value 902' is "1101," value 904' is "0011," value 906' is "0001," and value 908' is "1000." Each digital value is modulated (digitally multiplied) by a symbol representation 944. That is, it is modulated by either "1" or "-1" depending on the symbol chip corresponding to the digital value being modulated. Considering only the first time interval 940 of each symbol and adding the most significant bit (MSB), which is the sign bit, modulating "1101" yields "01101" (the "0" in the MSB indicates a positive value), modulating "0011" yields "00011," modulating "0001" yields "00001," and modulating "1000" yields "01000." These modulated values ​​are shown annotated in the first time interval. (Although not shown, modulating with a -1 chip results in negative values, which can be expressed in binary using the appropriate binary representation for negative values.)

[0103] Digitally summing these modulated values ​​for the first time interval yields digital value 952' "011001" (again, the MSB is the sign bit). Other digital values ​​954'-958', not shown in this example, are calculated in the same way. Considering this sum in decimal, we can see that the modulated values ​​13, 3, 1, and 8 sum to 25. Although not shown in this example, typically the sum may require more than five bits, so additional most significant bits are made available for the resulting levels 952'-958'. For example, if values ​​902'-908' are represented using four bits, and there are 64 possible codes (adding log2(64) bits), levels 952'-958' can be represented using a maximum of 10 bits. Alternatively, if 32 modulated values ​​are summed, five additional bits are added. The number of bits required for the output levels depends on the number of codes.

[0104] Output levels 950 are first normalized to the DAC's input requirements and then sequentially fed to DAC 959, which converts each digital value to a corresponding analog value for transmission through the EM path. DAC 959 is a MAX5857 RF DAC (including a clock-multiplying PLL / VCO and a 14-bit RF DAC core). It is also possible to bypass the composite path and access the RF DAC core directly. This is followed by a bandpass filter and variable gain amplifier (VGA), not shown. In some situations, level 950' may use more bits than DAC 959 allows. For example, level 952' is represented using 10 bits, but DAC 959 is an 8-bit DAC. In such a situation, the appropriate number of LSBs are discarded and the remaining MSBs are processed by the DAC. As a result, the visual quality of the displayed image is not compromised.

[0105] Advantageously, entire digital values ​​are modulated, and then these modulated entire digital values ​​are digitally summed to generate a digital output level for conversion and transmission. This technique differs from CDMA, which modulates each bit of a digital value and then sums these modulated bits to generate an output. For example, assuming each digital value has B bits, with CDMA there would be B x L total power levels to transmit, but with this novel digital (or analog) encoding technique there would be only L total power levels to transmit, which is an advantage.

[0106] FIG. 12 illustrates the decoding of analog input levels encoded using the encoder of FIG. 10. As shown, L input levels 950 are received via a single electromagnetic path of transmission medium 34. As discussed above, codebook 920 contains N orthogonal codes 932-938 that are used to decode input levels 950 to generate an output vector of N analog values ​​902-908, i.e., to generate the same analog values ​​902-908 encoded above. To perform the decoding, as indicated by the vertical arrows, each input level 952-958 is modulated (961) by each chip of each code corresponding to a particular index in output vector 902-908. Considering the modulation of levels 952-958 by first code 932, such modulation generates the sequence of modulated values: "2, 0, 0.6, -1.4." Modulation of levels 952-958 with second code 934 produces the sequence of modulation values ​​"2, 0, -0.6, 1.4". Modulation with third code 936 produces "2, 0, -0.6, -1.4", and modulation with fourth code 938 produces "2, 0, 0.6, 1.4".

[0107] Next, as indicated by the horizontal arrows, the values ​​of each sequence of modulation values ​​are summed to generate one of the analog values ​​902-908. For example, the first sequence is summed to generate the analog value "1.2" (which, when normalized using a scale factor of "4," becomes "0.3"). Similarly, the other three sequences of modulation values ​​are summed to generate the analog values ​​"2.8," "0," and "4," which, when normalized, generate the output vector of analog values ​​902-908. Each code may modulate an input level, and then the values ​​of its sequence may be summed. Alternatively, all sequences may modulate the input level before being summed. In this way, the output vector of N analog values ​​902-908 is transmitted in parallel using L output levels.

[0108] Although these examples do not show decoding of the digital input levels, one skilled in the art will recognize that such decoding is straightforward to perform after reading the encoding of the digital values ​​in the above description.

[0109] Figures 13A, 13B, and 13C show that the encoders and decoders can operate based on either analog or digital samples. Various analog and digital encoders and decoders are described above. As noted above, there can be multiple EM paths and, correspondingly, multiple encoder / decoder pairs, with a corresponding number of DACs or ADCs as needed.

[0110] FIG. 13A illustrates the use of an analog encoder and corresponding analog decoder. The input to analog encoder 900 is either analog samples 970 converted to analog by a DAC 972 located in the analog encoder or digital samples 971. In this manner, the analog or digital samples arriving at the analog encoder are encoded for transmission over an electromagnetic path on transmission medium 34. Analog decoder 900' decodes the encoded analog samples to produce output analog samples 970. Analog samples 970 may be used as is or converted to digital samples using an ADC (not shown).

[0111] FIG. 13B illustrates the use of a digital encoder and corresponding analog decoder. The input to digital encoder 901 is either analog samples 970 or digital samples 971 converted to digital by ADC 973 located in the digital encoder. Because the encoder is digital, DAC 959 located in the encoder converts the encoded samples to analog before transmission over the electromagnetic path. In this manner, analog or digital samples arriving at the digital encoder may be encoded for transmission over the electromagnetic path on transmission medium 34. Analog decoder 900' decodes the encoded analog samples to produce output analog samples 970. Analog samples 970 may be used directly or converted to digital samples using an ADC (not shown).

[0112] FIG. 13C illustrates the use of a digital decoder to decode an encoded analog signal arriving via an electromagnetic path on transmission medium 34. The encoded analog signal may have been transmitted using either the analog encoder or the digital encoder just described. An ADC 974 located in digital decoder 976 receives the encoded analog samples transmitted via the electromagnetic path and digitally converts the samples. These encoded digital samples are decoded by digital decoder 976 into digital samples 978 (corresponding to the values ​​of the sample input vector encoded before transmission via the electromagnetic path). Digital samples 978 may be used as is or converted to analog samples using a DAC.

[0113] FIG. 14 shows a simulation (similar to an ideal oscilloscope trace) of an SSVT waveform 602 transmitted through an electromagnetic path after being output from an analog encoder (or digitally encoded and converted by a DAC). The vertical axis is voltage, and the horizontal axis is the oscilloscope measurement time interval of 100 ps. Note that the SSVT signal 602 is an analog waveform, not a digital signal (i.e., the signal does not represent a binary number). In this embodiment, a voltage range from approximately -15 V to approximately +15 V can be transmitted. The voltage values ​​of the analog waveform are (or at least can be) fully analog. Also, the voltage is not limited to a certain maximum value, but higher values ​​are unrealistic.

[0114] As described above, analog voltage levels are transmitted sequentially over an electromagnetic path, with each level representing the sum of modulated samples for each time interval, such as analog output levels 952-958 and digital output levels 952'-958' (after passing through a DAC). When transmitted, these output levels appear as waveforms such as waveform 602. In particular, voltage level 980 represents the sum (i.e., output level) of modulated samples for a particular time interval. Using a simple example, successive voltage levels 980-986 represent the transmission of four output levels. Because 32 codes are used in this example, 32 samples can be transmitted in parallel. Thus, voltage levels 980-986 (with subsequent voltage levels depending on the number of chips, L, in the code) represent the parallel transmission of 32 encoded samples (e.g., pixel voltages from a video source). Following that transmission, the next set of L voltage levels in waveform 602 represents the transmission of the next 32 samples. In general, waveform 602 encodes analog or digital values ​​into analog output levels and transmits those levels at discrete time intervals to form a composite analog waveform.

[0115] Because every electromagnetic path degrades the electromagnetic signal propagating along it due to phenomena such as attenuation, reflections due to impedance mismatches, and collisions of aggressive signals, the input level measured at the receiving terminal will always be in error with respect to the corresponding output level available at the transmitting terminal. Therefore, scaling of the input level at the receiver (or normalization or amplification of the output level at the transmitter) may be performed to compensate, as is well known in the art. Furthermore, by processing gain (i.e., by increasing L, which also increases electrical resilience), the decoded input level at the decoder is normalized by a scale factor using the code length to restore the transmitted output level, as is well known in the art. Orthogonal Frequency Division Multiplexing Video Transmission

[0116] The above describes techniques that combine spread spectrum video transmission (SSVT) techniques with orthogonal frequency division multiplexing (OFDM) and related improvements to achieve more robust transmission of samples. It has also been shown that OFDM transmission without SSVT can offer substantial advantages and sufficient fault tolerance, especially when related improvements (e.g., improved symbol mapping of digital and analog samples, real output from the IFFT, etc.) are incorporated and when used to transmit video samples. Specific examples of these novel OFDM transmission techniques are described below.

[0117] OFDM video transmission can be used, for example, to transmit video wirelessly over relatively long distances to displays, televisions, or monitors. OFDM video transmission can be used to transmit video over high-frequency wireless channels, such as 60 GHz, which allows for a 2 GHz bandwidth, but wireless channels may require dynamic equalization due to channel variations. While digital transmission requires error-correcting codes to correct these problems, OFDM video transmission does not require such error-correcting codes.

[0118] One advantage of using OFDM transmission in the context of image capture and display is that images have traditionally been measured with inherently error-prone sensors, displayed on inherently noisy LED arrays, and viewed by the extremely complex and robust human visual system. As a result, the communication requirements for video are significantly different from those for traditional digital artifacts such as spreadsheets or email, which require bit-perfect transmission. However, in traditional video transmission, video signals are treated the same as other types of (digital) documents. However, in OFDM video transmission, video signals are transmitted in an electrically robust manner. One advantage of OFDM video transmission is that uncompensated errors in EM signal measurements at the receiver appear as broadband temporal and spatial noise in the reconstructed image. Such white noise is more acceptable to human perception than the blank screens, repeated images, and blocky compression artifacts that occur in traditional bit-serial transmission.

[0119] 15 illustrates the transmission of digital video samples from a video source to a video sink using an OFDM transmitter and an OFDM receiver. A video source 802 is shown generating digital video samples 812. The video source includes an image sensor array 804, one or more analog-to-digital converters 806, an optional image signal processor (ISP 808), and an optional video streamer 810 responsible for generating a stream of video samples 812. Video source 802 may be any device capable of acquiring image information, such as a still camera, a video camera, an infrared imager, an ultrasound imager, a magnetic resonance imaging (MRI) machine, a computed tomography (CT) scanner, or any other imaging device capable of generating video information.

[0120] Image sensor 804 is any device capable of generating an electronic signal proportional to the amount of light measured. For example, an image sensor may be a planar array of photodiodes. Each photodiode represents a pixel location in the planar array, and the number of photodiodes in a planar array varies widely and depends on the size of the image sensor. For example, a "4K" image sensor may contain a photodiode array with 3840 lines horizontally and 1080 lines vertically, for a total of 4,147,200 photodiodes. It should be understood that 4K is just an example of a resolution, and image sensor 804 may be any size, including less than 480, 480, 720, 1080, 4K, 8K, or greater.

[0121] During operation, the image sensor 804 continuously cycles through sensing intervals at a predetermined refresh rate. During each sensing interval, each photodiode in the array generates an electrical voltage that is inversely proportional to the number of photons generated by the photodiode for every pixel location. As a result, the array of photodiodes generates a series of voltages that collectively represent a frame. As the image sensor is continuously refreshed at the predetermined frame rate, multiple sets of voltages, each representing a frame, are continuously generated, one after the other.

[0122] At each pixel location, a photodiode is placed between a capacitor and ground. Just before the sensing interval, the capacitor is precharged. During sensing, the photodiode generates a current proportional to the intensity of the light received. If little or no light is sensed, very little of the capacitor discharges to ground through the photodiode. Conversely, if a lot of light is sensed, most of the capacitor's voltage is discharged. Thus, the voltage remaining on the capacitor after the exposure interval is inversely proportional to the sensed light intensity.

[0123] In an image sensor array, there is typically one analog-to-digital converter ("ADC") 806 per column. At a given frame interval, all rows of the array 804 are sampled, typically from top to bottom, sometimes referred to herein as "row-major" order. At each sample, the ADC converts the sensed voltages at pixel locations in each column of the array into digital values. A frame is completed when all rows of the array have been sampled. The above process is repeated for each frame in row-major order. The end result is a column of digital values ​​representing pixel locations within the frame. The number of bits used to represent each sample can vary significantly. For example, each voltage may be converted by the analog-to-digital converter 806 to an 8-bit or 10-bit value. The number of bits used to represent pixel voltage values ​​may be more or less than 8 or 10.

[0124] The image sensor array 804 may be either monochrome or color. In the former case, the digital values ​​generated by the ADC represent only one color. In the latter case, well-known color techniques such as Bayer filtering are commonly applied. In Bayer filtering, individual photodiodes are selectively covered with filters of a predetermined color (e.g., red, blue, or green). In alternative embodiments, CYGM (cyan, yellow, green, magenta) or CMY (cyan, magenta, yellow) filtering may be used. Regardless of the type of filter used, the intensity of the filtered light is measured at each sample location.

[0125] The ISP808 is configured to interpolate the sequence of digital values ​​received from the ADC. Through interpolation, the ISP808 takes the information contained in each pixel measurement and the digital values ​​of its geometric neighbors and estimates the color of the corresponding pixel. To output a full-color image in a specific color space (of which there are many), the ISP808 interpolates the "missing" color value at each location. That is, given only a single color measurement per pixel, the ISP algorithm estimates the "missing" color value, for example, creating an RGB or YCbCr representation of the pixel. In this way, the ISP808 generates a sample set for a specified pixel of a specified frame. Each sample set represents the color value (measured or interpolated) of a specified pixel location within the frame.

[0126] Because there are various ways to represent color, the contents of the sample sets can vary. RGB is generally considered full color, while other color spaces, such as YCbCr, are small approximations of full color that are suitable for transmission. In YCbCr, Y is the luma component, and Cb and Cr are the blue and red differential saturation values, respectively. The YCbCr color space is defined by a mathematical coordinate transformation from the related RGB color space. Another way to represent color is by an "alternating" approach. For example, every second pixel is represented by a luma (Y) value, and every other pixel is represented by a Cb (blue) or Cr (red) value. Thus, each sample set contains S, a number of sample values ​​transmitted in parallel. In RGB, S = 3 samples per sample set, while in YCbCr, S = 2.

[0127] The video streamer 810 generates a sequence of time-ordered sample sets received from the ISP 808. Generally, each simultaneously output sample set represents light measurements for one pixel location on the image sensor 804. The value and number of samples the ISP generates per pixel location vary depending on the ISP implementation, particularly the color space applied. The output of the video streamer 810 is a continuous stream of time-ordered sets of digital video samples 812 that are representative of the pixels sensed by the image sensor 804, frame by frame, in row-major order, from left to right. As the stream of digital video samples 812 is transmitted and received by the video sink 818, the samples are processed by the video sink to reconstruct the image sensed by the image sensor array 804 for each frame.

[0128] Once output from the video source 802, the digital video samples 812 are input to the OFDM transmitter 80 or OFDM transmitter 700a (described above in FIGS. 2 and 7A, respectively) and transmitted via an OFDM signal 90. The OFDM transmitter may be located in any suitable location, such as integrated with the video source 802, proximate to the video source 802, or located remotely from the video source 802. Once transmitted, the OFDM signal 90 may travel any suitable distance before being received.

[0129] In one embodiment, the transmitter does not require a DAC or DACs, and the output signal 90 is a digital signal. In a corresponding receiver, no ADC is required before the FFT circuit. If the frequency conversion is performed in the analog domain, this implementation is possible without a DAC or ADC.

[0130] Once transmitted, the OFDM signal 90 is received by an OFDM receiver 814 (which may be a receiver corresponding to transmitter 80 or transmitter 700a). Those skilled in the art will appreciate that implementing such an OFDM receiver 814 would be straightforward after reading this disclosure and understanding the operation of OFDM transmitter 80 or OFDM transmitter 700a. The location of the OFDM receiver 814 can be determined depending on the location of the OFDM transmitter and the desired distance over which the OFDM signal 90 is transmitted. The OFDM receiver 814 may be located adjacent to the video source, intermediate between the video source and the video sink, or adjacent to or even within the video sink. Digital video samples 816 are output from the OFDM receiver 814 and delivered to the video sink for display on its display panel using techniques well known to those skilled in the art.

[0131] FIG. 16 illustrates the transmission of analog video samples from a video source to a video sink using an OFDM transmitter and an OFDM receiver. A video source 822 generates analog video samples 832 as shown. The video source may be any of the video sources described above and may include an image sensor array 824 as described above. This embodiment eliminates the need for an analog-to-digital converter (ADC) in the video source, thereby reducing the cost, space required, heat generated, and complexity of the video source. An ISP may be added if desired.

[0132] The output of the video source 822 is analog video samples 832. As the stream of sets of analog video samples is transmitted and received at the video sink 838, the samples are processed by the video sink to reconstruct the image sensed by the image sensor array 824, frame by frame.

[0133] Once output from the video source 822, the analog video samples 832 are input to the OFDM transmitter 610 or OFDM transmitter 700b (described above in FIGS. 6 and 7B, respectively) and then transmitted via the OFDM signal 690. The OFDM transmitter may be located in any suitable location, such as integrated with the video source 822, proximate to the video source 822, or located remotely from the video source 822. Once transmitted, the OFDM signal 690 may travel any suitable distance before being received.

[0134] Once transmitted, the OFDM signal 690 is received by an OFDM receiver 834 (which may be a receiver corresponding to the transmitter 610 or transmitter 700b). Those skilled in the art will appreciate that implementing such an OFDM receiver 834 is straightforward after reading this disclosure and understanding the operation of the OFDM transmitter 610 or OFDM transmitter 700b. For example, if the transmitter 610 or transmitter 700b receives and operates on analog input samples, no DAC is required within the transmitter, and correspondingly, no ADC is required for the OFDM receiver 834. The transmitter outputs analog video samples corresponding to the analog video samples originally input to the transmitter. In implementations where the video sink requires digital video samples, the analog-to-digital conversion is performed at the receiver (e.g., within the video sink), allowing the ADC to be located remotely from the video source, reducing circuit complexity and cost.

[0135] The location of the OFDM receiver 834 may depend on the location of the OFDM transmitter and the distance over which it is desired to transmit the OFDM signal 690. The OFDM receiver 834 may be located close to the video source, midway between the video source and the video sink, close to the video sink, or within the video sink. Once the analog video samples 836 are output from the OFDM receiver 814, they are sent to the video sink and displayed on a display panel using techniques well known to those skilled in the art.

[0136]

[0147] FIG. 17 illustrates an embodiment in which both the OFDM transmitter and OFDM receiver are located within a display unit 840, such as a large television or screen. Signal 854 optionally provides information about the display panel to an OFDM transmitter 856 to assist in generating OFDM signals as needed from the display panel 850. Generation of gate driver power and control signals 860 may be performed by a timing controller (or other specific hardware) based on synchronization information from the source driver. Digital video samples 842 are received at the display unit and processed by a SoC and timing controller (TCON), as is well known in the art.

[0137] In this embodiment, any number of OFDM transmitters 856 transmit OFDM signals 858 to OFDM receivers 862 located in or integrated with each source driver 864 that generates source voltages for the display panel. The transmission medium for each signal 858 may be a cable (such as HDMI, flat cable, fiber optic cable, metal cable, or non-metallic carbon track flex cable) or wireless. This set of OFDM transmitters 856 may receive digital input (such as transmitters 80 and 700a) or may receive analog input (such as transmitters 610 and 700b). For transmitters that receive analog input, each transmitter is preceded by a DAC (not shown) that converts the incoming digital video samples to analog samples. Each OFDM receiver 862 may be located on a flexible PCB with each source driver 864, or may be integrated within each source driver, for example, within a single source driver chip. Typically, most display panels with more than about 1024 columns are implemented with an array of source driver chips, with one source driver per chip, due to pin-count constraints. For panels with fewer columns, it is believed that only one source driver is necessary. Depending on the OFDM transmitter used, different OFDM receivers and configurations may be used, as described below.

[0138] In embodiments in which multiple OFDM transmitters 856 are used in a display unit, a distributor similar to distributor 440 of FIG. 9 may be used to distribute the digital or analog video samples sent from the TCON to the transmitters 856. That is, an input stream of digital or analog samples is distributed to provide a sample stream for each OFDM transmitter. Any suitable permutation may be used. Thus, if there are P OFDM transmitters 856 (where P is an integer greater than or equal to 1), the samples from the TCON are distributed into P vector streams, one for each OFDM transmitter. One or more banks of distributors may be used, and each output vector stream of the distributor is preferably a serial output of samples for input to a corresponding OFDM transmitter. Similarly, if multiple OFDM transmitters are used in FIG. 15 or FIG. 16, a similar distributor may be used to distribute the input samples 812 or 832 to the multiple OFDM transmitters. If a splitter is used in FIG. 15 or FIG. 16, a corresponding collector may be used after the OFDM receiver 814 or 834 to generate the corresponding sample stream 816 or 836.

[0139] If the display unit of FIG. 17 has multiple OFDM transmitters 856, a splitter can be used and can be implemented according to splitter 440 of FIG. 9. The splitter output can be serially input to each OFDM transmitter. Alternatively, single or multiple output streams can be multiplexed or combined into a single or multiple transmitters. The number of these channels depends on the resolution and OFDM bandwidth, and a high-resolution video stream can be split into multiple streams. Each stream has a lower bandwidth than the single high-resolution stream, and samples are serialized per stream. The number of streams is implementation-dependent and can vary depending on the resolution of the video source, the number of sources, and the available bandwidth per OFDM channel.

[0140] Figure 18 shows a digital OFDM receiver with an analog output located at the source driver. When the OFDM transmitter is a transmitter that inputs digital video samples, such as transmitter 80 or transmitter 700a, an OFDM receiver 814 is used. Therefore, the receiver 814 includes at least one ADC, which performs inverse symbol mapping to output the original digital video samples input to the OFDM transmitter. Instead of the two ADCs shown, a single ADC may be placed at the input to the receiver near the antenna. Other techniques for converting the received analog signal to digital before the FFT circuitry may also be used. A DAC 870 may be added to the output of one of the source drivers 864 to provide analog video samples. The source driver 864 that accepts analog video samples is described below. Figure 18 shows a general block diagram of a digital OFDM receiver corresponding to an OFDM transmitter that inputs digital values. Because the OFDM transmitter has a digital input, an ADC is used within the digital OFDM receiver before the FFT.

[0141] FIG. 19 shows an analog OFDM receiver with analog outputs located at the source drivers. The display unit 840 is shown as an OFDM transmitter 856, which is a transmitter that inputs analog video samples, such as transmitter 610 or transmitter 700b. Therefore, a DAC 880 is added to convert the input digital video samples to analog samples. Because this OFDM transmitter inputs analog video samples, an OFDM receiver (such as receiver 834) can be used to perform inverse symbol mapping and output the original analog video samples input to the OFDM transmitter, providing these analog video samples to one of the source drivers 864. The source driver 864 that accepts the analog video samples is described below.

[0142] FIG. 20 shows an example of a source driver 864 for a display panel 850 that accepts analog video samples output from an OFDM receiver. Other source driver architectures are possible. The source driver 864 typically has 900 to 1,000 or more outputs. Multiple instances of this source driver may be present within a display. The analog video samples output from the OFDM receiver are input to an input terminal 890 and sent in parallel to a collector 891, which outputs the analog samples 892 in parallel to a column driver that typically includes level shifters 893 and amplifiers 894, before being output to columns (896).

[0143] An amplifier 894 amplifies each analog sample to generate the voltage required for the particular display panel. A polarity signal and a reference voltage (i.e., the amplifier rail voltage from gamma encoding used to generate the dynamic range of voltages expected or required by the display panel) are provided to each amplifier. Gamma processing and encoding may be performed within the SoC or timing controller chip. Output 896 is output directly to the display column, i.e., onto the display glass, to drive the source of each pixel, as is well known in the art. Advantageously, each source driver 864 does not require a DAC to convert pixel data, resulting in space savings, reduced power requirements, etc. Orthogonal frequency division multiplexing video transmission using a distributor

[0144] Above we have described OFDM transmission techniques showing a single OFDM path in Figures 15 and 16, and multiple OFDM paths in Figure 17. Below we describe an improved technique that incorporates a distributor into the transmitter (and a collector into the receiver) to facilitate multiple transmission paths within or to a display unit.

[0145] In a first variant of this embodiment, a SAVT signal or group of SAVT signals is generated from one or more video signals, and each SAVT signal is transmitted via an EM path, received by an OFDM receiver, and input to an OFDM transmitter for display.

[0146] Figure 21 shows the architecture of the transmitter 1140, which can reside external or internal to the display unit. Shown is a distributor 1240 that includes two line buffers 1241, 1242, a distributor controller 1230, multiple (P) image processors 1250-1259, digital-to-analog converters 260-269 following each image processor, and video sample streams 270-279 output from each DAC. In this example, there are 24 source drivers, so the number of streams is 24, i.e., P=24. It should be understood that there may be a single EM path (i.e., P=1) or multiple EM paths.

[0147] In operation, a video signal (e.g., RGB) containing time-sequenced digital video samples containing color values ​​and pixel-related information is received from a video source and transmitted to the transmitter 1140 (via the SoC and TCON if in a display unit). The number and content of the input video samples received from the video source depends on the color space used by the source (and the samples may be black and white). Regardless of the color space used, each video sample represents a sensed or measured amount of light in the specified color space.

[0148] Pixel values ​​may be received in row-major order for successive video frames. Multiple pixel values ​​may arrive simultaneously (e.g., two, four, etc.). Pixel values ​​are sequential in the sense that groups of pixels are transmitted sequentially from one end of a row to the other. A processing unit, such as a timing controller unpacker, can be used to unpack (or expose) these serial pixel values ​​into parallel RGB values. It should also be understood that the exposed color information in each sample set is not limited to RGB and can be any color information (e.g., Y, C, Cr, Cb, etc.). The number of output sample values ​​S in each set of pixel samples is determined by the color space applied by the video source. For RGB, S = 3; for YCbCr4:2:2, S = 2. In other situations, each sample set may have one or more than three sample values ​​S.

[0149] Typically, input digital video samples in one or more video signals (e.g., RGB) are received in row-major order (e.g., ) within the transmitter 1140. The input digital video samples are (1) repeatedly distributed to one of the output streams according to a predetermined permutation (in this example, row-major order, i.e., identity permutation), (2) optionally processed using standard image processing techniques such as gamma correction, (3) converted to analog, and (4) output as a stream of video samples, one stream per OFDM transmitter, as described below. The OFDM receiver receives each OFDM-encoded stream and outputs a stream of analog samples to the source drivers. Each source driver receives the samples at its input terminal and sequentially distributes each analog sample to the storage cells of a particular column driver via sampling circuitry, in the reverse order of the predetermined permutation used by the transmitter. Once all samples for that source driver are available, they are displayed on the display panel. The resulting original time-ordered video samples, including color and pixel-related information, are transmitted from the video source to the video sink. The reverse permutation effectively stores the input samples as rows in the storage array (shown in the panel) in the same order as the rows of samples received at the distributor.

[0150] In one embodiment, four control signals are inserted into the sample stream in the distributor for every 60 video samples sent to the source driver. As shown, each input vector 1280 in the line buffer contains 1,024 values, including four control signals for every 60 video samples. Control signals can be inserted at various locations in the input vector. For example, samples 960 through 1,023 of input vectors 1280 through 1288 may actually be control signals. The number of control signals in each input vector is arbitrary. Furthermore, while the number of control signals is arbitrary, it is finite. The more control signals transmitted, the higher the data transmission rate required. Ideally, the number of control signals is limited to fit within the blanking period, allowing for the transmission rate to correspond to the displayed lines (thus reducing the required storage capacity and additional resynchronization). Furthermore, control signals can be inserted into the sample stream at the distributor, or the control signal insertion can occur elsewhere.

[0151] The distributor 1240 is configured to receive exposed pixel color information (e.g., RGB values) in the input sample set. The distributor 1240 takes the exposed color information and writes multiple input vectors 1280-1288 into a first line buffer 1241 (one input vector per OFDM transmitter) according to a predetermined permutation. When the line buffer 1241 is full, each input vector 1280-1288 is read out to a corresponding image processor 1250-1259 via a corresponding serial output port 1281-1289. Once these input vectors from the line buffer 1241 are read out (or the line buffer 1241 is full), the next line of RGB input samples is written into the input vectors 1290-1298 of the second line buffer 1242. Thus, once the second line buffer 1242 is full (and the image processor has finished reading input vectors from the first line buffer 1241), the image processor begins reading samples from the second line buffer 1242 via serial output ports 1291-1299. This writing and reading continues in a "ping-pong" fashion for the first and second line buffers as long as input samples are arriving at the transmitter.

[0152] The distributor controller 1230 controls the operation and timing of the line buffers. In particular, the controller is responsible for defining the permutation and number of samples N used in constructing the four input vectors. In this example, N=1024. The controller 1230 may also include a permutation controller that controls the distribution of RGB samples to the positions of the input vectors. This controller is also responsible for coordinating the clock domain crossing from a first clock frequency to a second clock frequency.

[0153] In a specific embodiment, each line buffer 1241 or 1242 has three input ports for input RGB samples, with the samples clocked in at the FPIXEL frequency. Each line buffer also has 24 output ports, e.g., 1281 or 1291 (if there are 24 OFDM transmitters, each sending to one of 24 source drivers), with samples clocked out sequentially from each input vector at the sampled analog video transport (SAVT) frequency, FSAVT. It is also possible to clock in R, G, and B samples two at a time, or three at a time, rather than one at a time. In one embodiment, for 24 channels, FSAVT = 663.552 MHz.

[0154] For purposes of illustration, one possible permutation is one in which each input vector contains N color information and control signal samples. The exposed RGB samples of the sample sets in this example are assigned to the input vectors in left-to-right order. That is, the "R," "G," and "B" values ​​of the first sample set are assigned to the input vector 1280 in order (i.e., RGBRGB, etc.). Once the input vector 1280 has been assigned N samples and control signals, the above process is repeated for the other input vectors in turn until each input vector has N values. The number of N values ​​in each input vector can vary widely. As shown in this example, this predetermined permutation maintains row-major ordering of the input samples. That is, the first input vector 1280 contains sample 0 through sample 1023 of the first row, in order, and subsequent input vectors continue that permutation (including the control signals). Thus, the distributor controller 1230 performs the permutation by assigning the input samples to specific addresses within the line buffer. It should also be understood that any permutation scheme can be used in distributor 1230, and that whatever permutation scheme is used in the transmitter, its inverse is used in the control logic of each source driver to distribute the input samples to the column drivers.

[0155] Image processors 1250-1259 perform the following operations on each input vector: a) apply gamma correction to each sample; b) level-shift each gamma-corrected sample to remove DC components from the signal, mapping the range (0...255) to (-128...127); c) apply path-specific amplifier dispersion correction to each gamma-corrected, level-shifted sample, perform gain compensation for each sample, perform offset adjustment for each sample, and perform demurrage correction for each sample. Other corrections and adjustments may also be performed depending on the target display panel. Individual image processors 1250-1259 may process samples from each serial output stream (e.g., 1281 and 1291), or a single integrated image processor may process all serial outputs (e.g., 1281 and 1291, 1285 and 1295, etc.) at once. To avoid image processing on the control signals in the line buffer, the timing and position of the control signals in the buffer are known, and logic can determine not to process the control signals. As mentioned above, the image processing does not have to occur within the transmitter 1140, but may occur in the SoC or elsewhere.

[0156] After image processing (if any), the modified digital samples of each input vector are sequentially input to one of the DACs 1260-1269. Each DAC converts these modified digital samples at the FSAVT frequency, as described below, and outputs a stream of analog samples 1270-1279 to the OFDM transmitters 1290-1299. Each DAC converts the samples received from the digital domain into analog samples (e.g., a pair of differential voltage signals with magnitudes proportional to the input digital values). The output of the DAC ranges from a maximum voltage to a minimum voltage.

[0157] Although two line buffers are shown in distributor 1240 (which is preferred), a single line buffer could also be used. As samples from a particular input vector are read into its image processor (or DAC), the distributor fills that input vector with the input samples, ensuring an uninterrupted serial delivery of samples from the line buffer to the image processor. Additionally, although not preferred, it is possible to place each DAC after the distributor and before the image processor (if present) to perform image processing on the analog samples.

[0158] In this first variant, each OFDM transmitter 1290-1299 may be a transmitter that receives analog video samples and transmits an OFDM signal 690, such as transmitter 610 or 700b, as shown in FIG. 16. Signal 690 is received by an OFDM receiver 834, which outputs corresponding analog video samples to a video sink. These samples are then displayed on a display panel. Typically, the OFDM receiver is associated with a source driver for the panel, and may even be part of the panel. The following diagram shows one form of such a source driver:

[0159] FIG. 22 shows a preferred architecture for the source driver, in which each divider amplifier drives adjacent columns and all control signals are processed by a single amplifier. Input terminal 1822 demultiplexes and distributes input pixel data and control signals from OFDM receiver 834 to S / H amplifier 1824 (which receives pixel data numbered 0 through 14) and amplifier 1826, which receives the control signals. Pixel data from amplifier 1824 is forwarded to storage array A 1828 or storage array B 1830 as described above, and the control signals are processed by component 1836 and output at 1838. Pixel data from either storage array is then input to column driver 1832 and output to column 1834, as is well known in the art. Control logic for controlling the timing of the input amplifiers, storage arrays, and column drivers is not shown. Pixel data is received sequentially on a single channel (per chip) and stored sequentially (at 1Fsavt cycle intervals) in the A / B collectors, but it is also possible to store 15 subpixels in parallel from 15 SHA amplifiers in the array.

[0160] Thus, 15 interleaved S / H amplifiers receive the input pixel data, each driving 64 adjacent columns, or 64 video tracks, minimizing the range of columns driven by each amplifier. This architecture provides 15 blocks of 64 video samples and one subband channel (control signal) with 64 bits per display line (per source driver). For example, amplifier 0 drives columns 0-63, the second amplifier drives columns 64-127, and so on. The 15th amplifier drives columns 896-959, and amplifier 1826 drives the control signal. Having all the control signals on one channel means that there is no difference in amplitude, delay, or other aspects from one signal to the next (if they were on different channels). It is also possible for the control signal to arrive at channel zero (i.e., amplifier 0) rather than amplifier 15. This is advantageous because the control information arrives earlier than the pixel data. Another advantage of this architecture is that the extraction of the control signal only needs to look at one of the deinterleaved amplifier outputs, rather than being distributed across all amplifiers, making synchronization easier.

[0161] In this diagram, there are 15 video amplifiers, each driving 64 subpixels. This means there are 960 subpixels on one chip. There is one dedicated control channel, carrying 64 symbols per line (per source driver). As shown, the control channel receives a control signal at amplifier 1826. This signal is input to comparator 1836, which has a reference voltage of 0V and operates at 1 / 16th of FSAVT, or approximately 41.5MHz. Assuming the control signal ranges from -0.5V to +0.5V, the comparator detects whether the control signal is greater than 0V (representing a digital 1) or less than 0V (representing a digital 0). This digital data is output at 1838, providing one control bit every 16 samples. The control signal provides synchronization and phase adjustment, as explained below.

[0162] Typically, there are 24 such source drivers in a display panel, i.e., P equals 24. Note that the source drivers do not require an analog-to-digital converter (ADC) to convert the samples to analog for display. Table 1 shows the parameters, values, and units of the source drivers used in an 8K144 display panel. Thus, 24 source drivers each drive 960 columns, providing one row of subpixels for the display (23,040 subpixels per row). Those skilled in the art will recognize that it is easy to modify the architecture for other display sizes and speeds. By reordering the samples in the transmitter, each interleaved S / H amplifier can drive adjacent columns during rotation, as described below.

[0163] [Table 1]

[0164] Figure 23 shows the source driver inputs of source driver 1820 interleaved with multiple input amplifiers, allowing speed requirements to be met. (A single amplifier could also be used, but transmission speeds would be reduced.) Illustrated are input terminals 1822, distribution amplifiers 0-14 (1824), amplifier 1826, and associated switch 1842. This switch rotates in sequence, effectively connecting one amplifier at a time to receive either the incoming subpixels or the control signals. Thus, the inputs are interleaved 16 ways, and the switch outputs are demultiplexed into 16 channels, operating at a 1 / 16 data rate. Each of the 960 subpixels in a row is conveniently grouped into 15 groups of 64, with one channel dedicated to detecting and processing the control signals.

[0165] Figure 24 summarizes the pixel transmission order 1300, showing how pixels 0 through 959 and control signals 0 through 63 are sent from the input vector of the transmitter 1140 (via one of the OFDM transmitters 1290 through 1299) to the source driver of Figure 22 and assigned to each amplifier. The natural order of subpixels delivered via CEDS (Clock Embedded Differential Signaling) is shown. For example, subpixels are read from left to right, then top to bottom. Because the source driver interleaves the input data 16-way, the preferred way to send subpixels to the source driver is from top-left to top-bottom, then left to right. That is, the subpixel indices (and control signals) sent are 0, 64, 128, etc. The index of the S / H amplifier 1302, an example subpixel index 1304, and the control track 1306 for the 16th amplifier are shown.

[0166] In this permutation, 15 amplifiers (0-14) each drive 64 adjacent columns with a subpixel value, and amplifier 15 processes all 64 control signals. This variation minimizes the source driver hardware and minimizes the wiring load on the input amplifiers. Furthermore, this variation allows for the slowest sampled analog video transport (SAVT) transmission rates because no padding is required in the data sequence. For optimal display of text and other sharp intensity transitions, it is desirable for the sampling amplifiers to settle to a new value every 1 / Fsavt, or approximately 1.5 ns per sample. To implement this architecture, the sequence of subpixel indices for transmission at the transmitter is as follows: 0, 64, 128,...832,896; 1, 65,...897;...; 63, 127,191,...895,959.

[0167] FIG. 25 is a block diagram of a transmitter input vector 1320 with a predetermined permutation that provides the subpixel transmission permutation required in FIG. 24. As described above, when the subpixels arrive at distributor 1240, they are distributed to input vector 1320 in the order shown. Once the input vector is full, the samples in the input vector are serially output to the image processor via output port 1321, as described above, where they are converted and then transmitted to a source driver having the architecture shown in FIG. 22. The other input vectors in the line buffer are not shown. Each input vector has a similar permutation, and the other source drivers corresponding to each input vector have the same architecture as shown in FIG. 22. The above architecture of source driver 1820 and the above transmission order provide the above benefits while maintaining the slowest SAVT clock rate.

[0168] FIG. 26 illustrates a video transmission system 1700 within a display unit. In this first variation of OFDM transmission with the illustrated splitter, the input to the OFDM transmitter is analog samples, and the output from the OFDM receiver is also analog samples. Advantageously, no DACs or ADCs are required within the transmitter or receiver, nor are DACs required within the source driver array to convert pixel values. A timing controller 1702 outputs a set of color samples, as described above, in digital form, e.g., subpixel values ​​representing the luminance values ​​of an image or video to be displayed on a display panel 1710. The samples are input to a transmitter 1704, transmitted via a low-voltage wiring harness 1706 to a source driver array 1708, and displayed on the display panel 1710.

[0169] The transmitter distributor includes a line buffer 1720, any number of input vectors (or banks) 1722-1726, and a distributor controller 1728. RGB samples (or black and white, or other color space) are continuously received by the distributor and distributed to the input vectors according to a predetermined order controlled by the distributor controller 1728. In this example, row-major ordering is used, with the first portion of a row of an input video frame (or image) stored, from left to right, in input vector 1722, and similarly, the last portion of the row stored in input vector 1726. Thus, when the line buffer 1720 is full, it contains all pixel information from the first row of the video frame and is transferred to and displayed on the display panel 1710 as the first row of the video frame. Each input vector is sequentially read out to a corresponding DAC 1732-1736, and each sample is converted to analog for OFDM and transmission. As the samples continuously arrive from the timing controller 1702, they are distributed, converted, transmitted, and ultimately displayed as video on the display panel 710.

[0170] Connecting each OFDM transmitter to its corresponding OFDM receiver is a low-voltage wiring harness 1706 consisting of differential wire pairs, each carrying a continuous stream of analog samples (electromagnetic signals). Each differential wire pair terminates at the input 1760 of one of the source drivers 1752-1756. Other transmission media (cable, wireless, fiber optics, etc.) could also be used in place of the differential pairs in the wiring harness.

[0171] Each source driver (e.g., source driver 1752) in the source driver array includes an input terminal 1760, a collector 1762, and a number of column drivers 1764 (corresponding to the number of samples in each input vector, 1,024 in this example). Samples are received serially at terminal 1760 and then collected in collector 1762, which is implemented as a one-dimensional storage array or arrays with a length equal to the size of the input vector. Each collector can be implemented using the storage array shown in FIG. 22. When each collector is full, all collected samples are output in parallel to all column drivers 1764 in the source driver, amplified to the appropriate high voltage required by the display panel, and output to columns 1766 using a single-ended format. As samples continue to arrive on the wiring harness, each collector continues to collect samples and output them to the display panel, thereby affecting the display of video. In one embodiment, each collector 1762 is implemented using the A / B storage cells of FIG. 22. In other words, each column of collectors is provided with a pair of input samplers. The SHA amplifiers can be considered as part of the collectors 762.

[0172] In a second variation of OFDM transmission using a splitter, the incoming digital video samples remain digital; the input to the OFDM transmitter is digital samples, and the output from the OFDM receiver is digital video samples that can be converted to analog video samples as needed. Thus, to implement this second variation, the transmitter of FIG. 21 would be modified to remove DACs 1260-1269 so that the input to each OFDM transmitter is a sequence of digital video samples from each corresponding input vector. This transmission can be implemented for each transmitter as shown in FIG. 15. Digital video samples 812 can be input to OFDM transmitter 80 or 700a, transmitted to OFDM receiver 814, and output digital video samples 816. As shown in FIG. 18, the OFDM receiver 814 outputs digital video samples for use directly by a display panel requiring digital video samples (and capable of converting to analog), or a DAC 870 may be included within the OFDM receiver to provide analog video samples required by the display panel's source drivers. If analog video samples are output from the OFDM receiver, they are processed and displayed as described above with reference to FIGS. 22-25. If this second variation is implemented in a display unit (such as shown in FIG. 26), DACs 1732 and 1736 are unnecessary, and the inputs to the OFDM transmitters 1290-1299 are digital samples. The OFDM receiver 834 may instead be implemented as receiver 814, and may include a DAC 870 to output analog video samples to each source driver if the source driver requires analog samples.

[0173] In a third variation of OFDM transmission with a splitter, the input video signal contains analog video samples; i.e., the RGB signal in FIG. 21 contains analog video samples rather than digital samples. The input to the OFDM transmitter is analog samples, and the output from the OFDM receiver is analog video samples (which may be converted to digital video samples, if necessary). Therefore, to implement this third variation, the transmitter in FIG. 21 is modified to accept input analog video samples, DACs 1260-1269 are removed, and the input to each OFDM transmitter 1290-1299 is a sequence of analog video samples from the corresponding input vector. This transmission can be implemented for each transmitter as shown in FIG. 16. Analog video samples 832 are input to OFDM transmitter 610 or 700b and sent to OFDM receiver 834, which outputs analog video samples 836. OFDM receiver 834 outputs analog video samples that can be used directly for a display panel. These analog video samples are processed and displayed as described above with reference to Figures 22-25. If this third variant is implemented in a display unit (such as that shown in Figure 26), the samples in the RGB signals are analog video samples, DACs 1732 and 1736 are not required, and the inputs to OFDM transmitters 1290-1299 are analog samples. OFDM receiver 834 outputs analog video samples to each source driver. Other embodiments

[0174] Other embodiments include the following:

[0175] 1. A transmitter for transmitting input digital samples, comprising: an encoder that sequentially inputs an input vector of N digital samples and encodes the N digital samples using N orthogonal spreading codes, each of length L, to output L digital levels, where L>=N>=2, each of the codes being used with one of the N digital samples; a symbol mapping circuit that receives the continuous stream of L digital levels from the encoder, maps the L digital levels to points on a constellation to obtain pairs of in-phase (I) and quadrature (Q) components, and outputs each pair of I and Q components to a bin of an inverse fast Fourier transform (IFFT) block; and an orthogonal frequency division multiplexing (OFDM) circuit that performs an IFFT on the IFFT block and generates an electromagnetic signal representing the continuous stream of digital levels using OFDM.

[0176] 2. The transmitter of claim 1, wherein the N digital samples originate from a single source and the electromagnetic path terminates at a single sink.

[0177] 3. The transmitter of claim 1, wherein the electromagnetic path terminates at a display panel of a display unit, and the transmitter is disposed within the display unit.

[0178] 4. The transmitter of claim 1, wherein the encoder synchronously encodes the N digital samples into the L digital levels, and the N digital samples are represented by the L digital levels.

[0179] 5. The transmitter of claim 1, wherein the symbol mapping circuit maps each of the L digital levels to a point in the constellation to obtain the in-phase (I) component and the quadrature (Q) component.

[0180] 6. The transmitter of claim 1, wherein for each pair of the I and Q components output to a bin of the IFFT block, the complex conjugates of the I and Q components are output to corresponding bins of the IFFT block that are symmetrical about an intermediate frequency of the subcarrier frequency used in the transmitter, and the outputs of the IFFT are real values ​​and not complex values.

[0181] 7. The transmitter of claim 1, wherein each digital level received by the symbol mapping circuit includes a most significant bit (MSB) and a least significant bit (LSB), and for each digital output level received, the symbol mapping circuit distributes the MSB of each digital output level to the MSB of the in-phase (I) component and the MSB of the quadrature (Q) component, and for each digital output level received, the symbol mapping circuit distributes the LSB of each digital output level to the LSB of the in-phase (I) component and the LSB of the quadrature (Q) component, and the symbol mapping circuit outputs the I component and the Q component as complex numbers to bins of an inverse fast Fourier transform (IFFT) block until the IFFT block is full.

[0182] 8. The transmitter of claim 1, further comprising a digital-to-analog converter that receives the electromagnetic signal and outputs an analog signal in the electromagnetic path.

[0183] 9. The transmitter of claim 1, wherein the transmitter is one of a plurality (P) of transmitters, each of the P transmitters generating an electromagnetic signal, the electromagnetic signal representing a media signal from a single source.

[0184] 10. A receiver that outputs digital samples, an OFDM circuit that receives an orthogonal frequency division multiplexed (OFDM) electromagnetic signal and performs a fast Fourier transform (FFT) on the received OFDM symbols to fill each bin of the FFT block with complex digital in-phase (I) and quadrature (Q) components of each OFDM symbol; an inverse symbol mapping circuit that receives the I component and the Q component and converts the I component and the Q component successively to digital input levels according to a corresponding symbol mapping circuit of an OFDM transmitter; a decoder that sequentially inputs L of the digital input levels and decodes the L digital input levels using N orthogonal spreading codes, each of length L, to output an output vector of N digital samples, each of the codes using one of the N digital samples, where L>=N>=2.

[0185] 11. The receiver of claim 10, wherein the N digital samples originate from a single source and the electromagnetic path terminates at a single sink.

[0186] 12. The receiver of claim 10, wherein the electromagnetic path terminates at a display panel of a display unit, and the corresponding OFDM transmitter is located within the display unit.

[0187] 13. The receiver of claim 10, wherein the decoder decodes the L digital input levels synchronously with the N digital samples, the N digital samples representing the L digital input levels.

[0188] 14. The receiver of claim 10, wherein the inverse symbol mapping circuit converts each point in the constellation to one of the digital input levels.

[0189] 15. The receiver of claim 10, wherein the inverse symbol mapping circuit places the most significant bit (MSB) of each pair of digital I and Q components at the MSB of one of the digital input levels, and places the least significant bit (LSB) of each of the pairs at the LSB of one of the digital input levels.

[0190] 16. The input to the FFT is real-valued, not complex-valued. 11. The receiver of claim 10, wherein the bins of the FFT block are filled with the I and Q components on one side of an intermediate frequency of a subcarrier frequency used in the receiver, and the bins of the FFT block are symmetrically filled with complex conjugates of the corresponding I and Q components on the other side of the intermediate frequency, and the inverse symbol mapping circuit inputs the I and Q components only from the bins on the one side.

[0191] 17. The receiver of claim 10, wherein the OFDM circuitry includes at least one analog-to-digital converter that generates the digital I and Q components.

[0192] 18. A transmitter for transmitting input analog samples, comprising: an encoder that sequentially inputs an input vector of N analog samples, encodes the N analog samples using N orthogonal codes, each of length L, and outputs L analog levels, each of the codes being used with one of the N analog samples, where L>=N>=2; a switch circuit that receives the continuous stream of L analog levels and, for each received pair of analog levels, outputs a first analog level of the pair as an in-phase (I) component and a second analog level of the pair as a quadrature (Q) component to a bin of an inverse fast Fourier transform (IFFT) block; and an orthogonal frequency division multiplexing (OFDM) circuit that receives the pair of I and Q components, performs an IFFT in the IFFT block, and generates an electromagnetic signal corresponding to the continuous input of analog samples using OFDM.

[0193] 19. The transmitter of claim 18, wherein the N analog samples originate from a single source and the electromagnetic path terminates at a single sink.

[0194] 20. The transmitter of claim 18, wherein the electromagnetic path terminates at a display panel of a display unit, and the transmitter is disposed within the display unit.

[0195] 21. The transmitter of claim 18, wherein the encoder synchronously encodes the N analog samples into the L analog levels, and the N analog samples are represented by the L analog levels.

[0196] 22. The transmitter of claim 18, wherein the transmitter does not include a constellation diagram for mapping.

[0197] 23. An OFDM transmitter as described in claim 18, wherein for each pair of the I component and the Q component output to the bin of the IFFT block, the complex conjugate of the I component and the Q component is output to a corresponding bin of the IFFT block that is symmetric about a center frequency of the subcarrier frequencies used in the transmitter, and the output of the IFFT is real valued and not complex valued.

[0198] 24. The transmitter of claim 18, wherein the transmitter does not include a digital-to-analog converter.

[0199] 25. The transmitter of claim 18, wherein the transmitter is one of a plurality (P) of transmitters, each of the P transmitters generating an electromagnetic signal, the electromagnetic signal representing a media signal from a single source.

[0200] 26. A receiver that outputs analog samples, an OFDM circuit for receiving an orthogonal frequency division multiplexed (OFDM) electromagnetic signal, performing a fast Fourier transform (FFT) on the received OFDM symbols, and filling each bin of the FFT block with complex in-phase (I) and quadrature (Q) components; a combining circuit that inputs the I component and the Q component of each bin into each bin, outputs the I component and the Q component as a first analog level and a second analog level, and outputs a stream of continuous analog input levels; a decoder that sequentially inputs L of the analog input levels and decodes the L analog input levels using N orthogonal spreading codes, each of length L, to output an output vector of N analog samples, where each code is used in combination with one of the N analog samples, and where L>=N>=2.

[0201] 27. The receiver of claim 26, wherein the N analog samples originate from a single source and the electromagnetic path terminates at a single sink.

[0202] 28. The receiver of claim 26, wherein the electromagnetic path terminates at a display panel of a display unit, and the corresponding OFDM transmitter is located within the display unit.

[0203] 29. The receiver of claim 26, wherein the decoder decodes the L analog input levels synchronously with the N analog samples, the N analog samples representing the L analog input levels.

[0204] 30. The receiver of claim 26, wherein the receiver does not include a constellation for mapping.

[0205] 31. The input to the FFT is real-valued, not complex-valued. 27. The receiver of claim 26, wherein the bins of the FFT block are filled with the I and Q components on one side of an intermediate frequency of a subcarrier frequency used in the receiver, and the bins of the FFT block are symmetrically filled with complex conjugates of the corresponding I and Q components on the other side of the intermediate frequency, and the combining circuit inputs the I and Q components only from the bins on the one side.

[0206] 32. The receiver of claim 26, wherein the receiver does not include an analog-to-digital converter.

[0207] 32. The receiver of claim 26, wherein the receiver is one of a plurality (P) of receivers, each of the P receivers receiving an electromagnetic signal, the electromagnetic signal representing a media signal from a single source.

[0208] 33. A transmitter for transmitting input digital video samples, comprising: a serial-to-parallel converter configured to receive a bit-serial stream of digital video samples and generate a parallel stream of said digital video samples, said digital video samples being generated by an image sensor of a video source; a symbol mapping circuit that receives the stream of digital video samples from the serial-to-parallel converter, maps each of the digital video samples to a point on a constellation to obtain an in-phase (I) component and a quadrature (Q) component pair, and outputs each pair of I and Q components to a bin of an inverse fast Fourier transform (IFFT) block; and an orthogonal frequency division multiplexing (OFDM) circuit that performs an IFFT on the IFFT block and generates, using OFDM, an electromagnetic signal representing the stream of digital video samples.

[0209] 34. The transmitter of claim 33, wherein the OFDM circuitry is further configured to transmit the electromagnetic signal to a video sink.

[0210] 35. The transmitter of claim 33, wherein the transmitter is disposed within a display unit, and the OFDM circuitry is further configured to transmit the electromagnetic signal to a source driver of a panel of the display unit.

[0211] 36. A transmitter as described in claim 33, wherein for each pair of the I and Q components output to the bins of the IFFT block, the complex conjugates of the I and Q components are output to corresponding bins of the IFFT block that are symmetrical about an intermediate frequency of the subcarrier frequencies used in the transmitter, and the outputs of the IFFT are real values ​​and not complex values.

[0212] 37. The transmitter of claim 33, wherein each digital video sample received by the symbol mapping circuit includes a most significant bit (MSB) and a least significant bit (LSB), and for each received digital video sample, the symbol mapping circuit divides the MSB of each digital video sample into the MSB of the in-phase (I) component and the MSB of the quadrature (Q) component, and for each received digital video sample, the symbol mapping circuit divides the LSB of each digital video sample into the LSB of the in-phase (I) component and the LSB of the quadrature (Q) component, and the symbol mapping circuit outputs the I component and the Q component as complex numbers to bins of an inverse fast Fourier transform (IFFT) block until the IFFT block is full.

[0213] 38. The transmitter of claim 33, wherein the transmitter is one of a plurality (P) of transmitters that receive a stream of digital video samples, and a distributor inputs digital video samples generated by the video source and distributes the digital video samples into the stream of digital video samples.

[0214] 39. A receiver that outputs digital video samples, comprising: an OFDM circuit that receives an orthogonal frequency division multiplexed (OFDM) electromagnetic signal representing a stream of digital video samples and performs a fast Fourier transform (FFT) on the received OFDM symbols to fill each bin of the FFT block with complex digital in-phase (I) and quadrature (Q) components of each OFDM symbol; an inverse symbol mapping circuit that receives the I and Q components as inputs and converts the I and Q components successively into a stream of digital video samples according to a corresponding OFDM transmitter symbol mapping circuit; and an output circuit configured to output the stream of digital video samples, the digital video samples being generated by an image sensor of a video source.

[0215] 40. The receiver of claim 39, further comprising a parallel-to-serial converter configured to receive the stream of digital video samples and generate a bit-serial stream of the digital video samples to a video sink.

[0216] 41. The receiver of claim 39, wherein the receiver further comprises a digital-to-analog converter disposed within a display unit and configured to input the stream of digital video samples and output a stream of analog video samples to a source driver of a panel of the display unit.

[0217] 42. The receiver of claim 39, wherein the inverse symbol mapping circuit converts each point in the constellation to one of the digital video samples.

[0218] 43. The receiver of claim 39, wherein the inverse symbol mapping circuit places the most significant bit (MSB) of each pair of digital I and Q components into the MSB of one of the digital video samples, and places the least significant bit (LSB) of each of the pairs into the LSB of the one digital video sample.

[0219] 44. The input to the FFT is real-valued, not complex-valued. 40. The receiver of claim 39, wherein the bins of the FFT block are filled with the I and Q components on one side of an intermediate frequency of a subcarrier frequency used in the receiver, and the bins of the FFT block are symmetrically filled with complex conjugates of the corresponding I and Q components on the other side of the intermediate frequency, and the inverse symbol mapping circuit inputs the I and Q components only from the bins on the one side.

[0220] 45. The receiver of claim 39, wherein the receiver is one of a plurality (P) of receivers, each outputting a stream of digital video samples, and wherein a collector inputs the streams of digital video samples and combines all of the streams to output as a single stream of digital video samples to a display sink.

[0221] 46. ​​A transmitter for transmitting input analog video samples, comprising: an input circuit configured to receive a stream of analog video samples generated by an image sensor of a video source; a switch circuit that receives the stream of analog video samples and, for each pair of analog levels received, outputs a first analog level of the pair as an in-phase (I) component and a second analog level of the pair as a quadrature (Q) component to a bin of an inverse fast Fourier transform (IFFT) block; and an orthogonal frequency division multiplexing (OFDM) circuit that receives the pair of I and Q components, performs an IFFT on the IFFT block, and generates, using OFDM, an electromagnetic signal representing the stream of analog video samples.

[0222] 47. The transmitter of claim 46, wherein the OFDM circuitry is further configured to transmit the electromagnetic signal to a video sink.

[0223] 48. The transmitter is disposed within a display unit; the transmitter further comprises a digital-to-analog converter configured to input a stream of digital video samples and output the stream of analog video samples to the input circuit; 47. The transmitter of claim 46, wherein the OFDM circuitry is further configured to transmit the electromagnetic signal to a source driver of a panel of the display unit.

[0224] 49. The transmitter of claim 46, wherein the transmitter does not include a constellation for mapping.

[0225] 50. An OFDM transmitter as described in claim 46, wherein for each pair of I and Q components output to a bin of an IFFT block, the complex conjugate of the I and Q components is output to a corresponding bin of the IFFT block that is symmetric about a center frequency of the subcarrier frequencies used in the transmitter, and the outputs of the IFFT are real values ​​and not complex values.

[0226] 51. The transmitter of claim 46, wherein the transmitter does not include a digital-to-analog converter.

[0227] 52. The transmitter of claim 46, wherein the transmitter is one of a plurality (P) of transmitters each receiving a stream of analog video samples, and wherein a distributor inputs analog video samples generated by the video source and distributes the analog video samples into the stream of analog video samples.

[0228] 53. A receiver that outputs analog video samples, comprising: an OFDM circuit that receives an orthogonal frequency division multiplexed (OFDM) electromagnetic signal representing a stream of analog video samples generated by an image sensor of a video source, and performs a fast Fourier transform (FFT) on the received OFDM symbols to fill each bin of the FFT block with complex in-phase (I) and quadrature (Q) components; a combining circuit that inputs the I component and the Q component of each bin into each bin and outputs the I component and the Q component as a first analog video sample and a second analog video sample to output a stream of analog video samples, the output stream of analog video samples corresponding to the analog video samples generated by the image sensor of the video source.

[0229] 54. The receiver of claim 53, wherein the receiver is further configured to output the stream of analog video samples to a video sink.

[0230] 55. The receiver is disposed within a display unit; 54. The receiver of claim 53, wherein the receiver is further configured to output the stream of analog video samples to a source driver of a panel of the display unit.

[0231] 56. The receiver of claim 53, wherein the receiver does not include a constellation for mapping.

[0232] 57. The input to the FFT is real-valued, not complex-valued. 54. The receiver of claim 53, wherein the bins of the FFT block are filled with the I and Q components on one side of an intermediate frequency of a subcarrier frequency used in the receiver, and the bins of the FFT block are filled symmetrically with complex conjugates of the corresponding I and Q components on the other side of the intermediate frequency, and the combining circuit inputs the I and Q components only from the bins on the one side.

[0233] 58. The receiver of claim 53, wherein the receiver does not include an analog-to-digital converter.

[0234] 59. The receiver of claim 53, wherein the receiver is one of a plurality (P) of receivers, each outputting a stream of analog video samples, and wherein a collector inputs the streams of analog video samples and combines all of the streams to output as a single stream of analog video samples to a display sink.

[0235] Although the foregoing invention has been described in some detail for ease of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the described embodiments should be construed as illustrative and not restrictive, and the present invention should not be limited to the details set forth herein, but rather should be defined by the following claims and their full scope of equivalents.

Claims

1. A source driver for a display unit, comprising: an input terminal configured to receive a serial stream of analog video samples; a storage array including a plurality of registers, each configured to hold one of the analog video samples received from the input terminal; a plurality of amplifiers configured to each receive one of the analog video samples in parallel from one of the registers, amplify each of the analog video samples to a voltage within a voltage range expected by a display panel of the display unit, and output each of the amplified analog video samples to a column of the display panel; The source driver does not include a digital-to-analog converter that converts pixel data of the analog video samples.

2. 10. The source driver of claim 1, wherein the stream of analog video samples is received from an Orthogonal Frequency Division Multiplexing (OFDM) receiver within the display unit.

3. 2. The source driver of claim 1, wherein each of the amplifiers receives a reference voltage from a system-on-chip or a timing controller of the display unit to provide the voltage range.

4. 2. The source driver of claim 1, wherein the analog video samples originate from a video source.

5. 1. An apparatus for transmitting input digital video samples, comprising: a divider that receives digital video samples originating from a video source and divides the digital video samples into P bit streams of digital video samples, where P>=2; P transmitters, each receiving one of the bit streams of digital video samples, each having a serial-to-parallel converter configured to receive one of the bit streams of digital video samples and generate parallel streams of digital video samples; a symbol mapping circuit that receives the stream of digital video samples from the serial-to-parallel converter, maps each of the digital video samples to a point on a constellation to obtain an in-phase (I) component and a quadrature (Q) component pair, and outputs each I and Q component pair to a bin of an inverse fast Fourier transform (IFFT) block; an orthogonal frequency division multiplexing (OFDM) circuit that performs an IFFT on the IFFT block and generates an electromagnetic signal representing the bit stream of digital video samples using OFDM; An apparatus comprising:

6. 6. The apparatus of claim 5, wherein the OFDM circuitry of each of the transmitters is further configured to transmit the electromagnetic signal to a video sink.

7. 6. The apparatus of claim 5, wherein the apparatus is disposed within a display unit, the distributor receives the digital video samples from a TCON of the display unit, and the OFDM circuit of each transmitter is further configured to transmit the electromagnetic signals to a source driver of a panel of the display unit.

8. a distributor configured to receive a plurality of streams of digital video samples and distribute the digital video samples among a plurality of input vectors according to a predetermined permutation; a plurality of digital-to-analog converters (DACs), each configured to receive digital video samples from one of the input vectors and convert the digital video samples from one of the input vectors into a sequence of analog video samples; a plurality of orthogonal frequency division multiplexing (OFDM) transmitters, each of which receives one of the sequences of analog video samples and transmits the sequences of analog video samples as an OFDM signal over an electromagnetic path.

9. The distributor comprises: a first line buffer for storing the plurality of input vectors; a second line buffer for storing a plurality of second input vectors; Furthermore, the distributor is further configured to distribute the lines of the digital video samples alternately between the input vectors of the first line buffer and the second input vectors of the second line buffer; 9. The video transmitter of claim 8, wherein the DAC alternately receives from the first line buffer while the distributor writes to the second line buffer, and receives from the second line buffer while the distributor writes to the first line buffer.

10. 9. The video transmitter of claim 8, wherein the digital video samples are distributed to the input vectors at a first frequency, and the digital video samples are output serially from each of the input vectors at a second frequency different from the first frequency.

11. 9. The video transmitter of claim 8, wherein the predetermined permutation enables each sampling amplifier of a source driver that receives one of the series of analog video samples to output the analog video samples to consecutive storage locations.

12. each of said OFDM transmitters includes a switch circuit that receives one of said series of analog video samples; for every pair of received analog samples, the switch circuit outputs a first analog level of the pair as an in-phase (I) component and a second analog level of the pair as a quadrature (Q) component to a bin of an inverse fast Fourier transform (IFFT) block; The video transmitter of claim 8 , wherein each of the OFDM transmitters performs an IFFT on the IFFT block to generate the OFDM signal.

13. 9. The video transmitter of claim 8, wherein each OFDM transmitter does not include a constellation for mapping.

14. 9. The video transmitter of claim 8, wherein each OFDM transmitter does not include a digital-to-analog converter.

15. an Orthogonal Frequency Division Multiplexing (OFDM) receiver configured to receive an OFDM signal via an electromagnetic path and to output a sequence of analog video samples; a collector configured to receive the sequence of analog video samples and store the sequence of analog video samples; a plurality of column drivers configured to receive the series of stored analog video samples in parallel from the collector and to amplify each of the stored analog video samples onto a column of a display panel; A video receiver comprising:

16. the collector further includes a first storage array and a second storage array; the collector alternately writes the analog video samples into a first storage array or a second storage array; 16. The video receiver of claim 15, wherein the column driver alternately reads from the first storage array while the collector writes to the second storage array, and reads from the second storage array while the collector writes to the first storage array.

17. 16. The video receiver of claim 15, wherein a predetermined permutation enables the collector to store the analog video samples in consecutive storage locations.

18. 16. The video receiver of claim 15, wherein the video receiver does not include a digital-to-analog converter (DAC) used to convert video samples.

19. 16. The video receiver of claim 15, wherein the OFDM receiver comprises a combining circuit that inputs an I component and a Q component of each bin of an FFT block and outputs the I component and the Q component as a first analog value and a second analog value to output the continuous stream of analog video samples.

20. 16. The video receiver of claim 15, wherein the OFDM receiver does not include a constellation for mapping.

21. 16. The receiver of claim 15, wherein the OFDM receiver does not include an analog-to-digital converter.

22. a distributor configured to receive a plurality of video signals comprising digital video samples, to distribute the digital video samples of the video signals among a plurality of input vectors according to a predetermined permutation, and to output each of the input vectors as a sequence of digital video samples; a plurality of orthogonal frequency division multiplexing (OFDM) transmitters, each receiving one of the sequences of digital video samples and transmitting the sequences of digital video samples as an OFDM signal over an electromagnetic path; A video transmitter comprising:

23. The distributor comprises: a first line buffer for storing the plurality of input vectors; a second line buffer for storing a plurality of second input vectors; Furthermore, the distributor is further configured to distribute the lines of the digital video samples alternately between the input vectors of the first line buffer and the second input vectors of the second line buffer; 23. The video transmitter of claim 22, wherein the OFDM transmitter alternately receives from the first line buffer while the distributor writes to the second line buffer, and receives from the second line buffer while the distributor writes to the first line buffer.

24. 23. The video transmitter of claim 22, wherein the digital video samples are distributed to the input vectors at a first frequency, and the digital video samples are output serially from each of the input vectors at a second frequency different from the first frequency.

25. 23. The video transmitter of claim 22, wherein the predetermined permutation enables each sampling amplifier of a source driver that receives a sequence of analog video samples to output the analog video samples to consecutive storage locations.

26. 23. The video transmitter of claim 22, wherein each of the OFDM transmitters includes a symbol mapping circuit that maps each of the digital video samples to a point in a constellation to obtain an in-phase (I) component and a quadrature (Q) component.

27. each of said OFDM transmitters includes a symbol mapping circuit; each digital video sample received by the symbol mapping circuit includes a most significant bit (MSB) and a least significant bit (LSB); for each received digital video sample, the symbol mapping circuit distributes the MSB of each digital video sample into an MSB of an in-phase (I) component and an MSB of a quadrature (Q) component; for each received digital video sample, the symbol mapping circuit distributes the least significant bit of the digital video sample into a least significant bit of the in-phase (I) component and a least significant bit of the quadrature (Q) component; 23. The video transmitter of claim 22, wherein the symbol mapping circuit outputs the I and Q components to bins of an inverse fast Fourier transform (IFFT) block.

28. an Orthogonal Frequency Division Multiplexing (OFDM) receiver configured to receive an OFDM signal via an electromagnetic path and output a sequence of digital video samples; a digital-to-analog converter (DAC) that receives the sequence of digital video samples and outputs a sequence of analog video samples; a collector configured to receive the sequence of analog video samples and store the sequence of analog video samples; a plurality of column drivers configured to receive the series of stored analog video samples in parallel from the collector and to amplify each of the stored analog video samples onto a column of a display panel; A video receiver comprising:

29. the collector further includes a first storage array and a second storage array; the collector alternately writes the analog video samples into a first storage array or a second storage array; 29. The video receiver of claim 28, wherein the column driver alternately reads from the first storage array while the collector writes to the second storage array, and reads from the second storage array while the collector writes to the first storage array.

30. 30. The video receiver of claim 28, wherein a predetermined permutation enables the collector to store the analog video samples in consecutive storage locations.

31. 30. The video receiver of claim 28, wherein the OFDM receiver includes an inverse symbol mapping circuit that converts each point in a constellation to one of the digital video samples.

32. 29. The video receiver of claim 28, wherein the OFDM receiver includes an inverse symbol mapping circuit that places a most significant bit (MSB) of each pair of digital I and Q components into the MSB of one of the digital video samples and places a least significant bit (LSB) of each of the pairs into the LSB of the one digital video sample.

33. a distributor configured to receive a plurality of video signals comprising analog video samples, to distribute the analog video samples of the video signals among a plurality of input vectors according to a predetermined permutation, and to output each of the input vectors as a sequence of analog video samples; a plurality of orthogonal frequency division multiplexing (OFDM) transmitters, each receiving one of the sequences of analog video samples and transmitting the sequences of analog video samples as an OFDM signal over an electromagnetic path; A video transmitter comprising:

34. The distributor comprises: a first line buffer for storing the plurality of input vectors; a second line buffer for storing a plurality of second input vectors; Furthermore, the distributor is further configured to distribute the lines of analog video samples alternately between the input vectors of the first line buffer and the second input vectors of the second line buffer; 34. The video transmitter of claim 33, wherein the OFDM transmitter alternately receives from the first line buffer while the distributor writes to the second line buffer, and receives from the second line buffer while the distributor writes to the first line buffer.

35. 34. The video transmitter of claim 33, wherein the analog video samples are distributed to the input vectors at a first frequency, and the analog video samples are output serially from each of the input vectors at a second frequency different from the first frequency.

36. 34. The video transmitter of claim 33, wherein the predetermined permutation enables each sampling amplifier of a source driver that receives a sequence of analog video samples to output the analog video samples to consecutive storage locations.

37. each of said OFDM transmitters includes a switch circuit that receives one of said series of analog video samples; for every pair of received analog samples, the switch circuit outputs a first analog level of the pair as an in-phase (I) component and a second analog level of the pair as a quadrature (Q) component to a bin of an inverse fast Fourier transform (IFFT) block; 34. The video transmitter of claim 33, wherein each of the OFDM transmitters performs an IFFT on the IFFT block to generate the OFDM signal.

38. 34. The video transmitter of claim 33, wherein each OFDM transmitter does not include a constellation for mapping.

39. 34. The video transmitter of claim 33, wherein each OFDM transmitter does not include a digital-to-analog converter.

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