Backside and frontside contacts for semiconductor devices

Abstract

Provides backside and frontside contacts for semiconductor devices. Backside and frontside contact structures surrounding the source / drain regions increase the contact area for electrical connection and allow for increased silicide area. Sidewall metallization of the epitaxially grown source / drain regions provides source / drain sidewall contacts that enable the formation of wraparound contacts on both the frontside and backside of the semiconductor device layer. Frontside and backside contact metallization on the source / drain sidewall contacts enable wraparound contact structures on both sides of the device layer.

Description

[Technical Field]

[0001] The present invention relates generally to the electrical, electronic, and computer arts, and more particularly to a FET architecture having backside and frontside contacts and methods for forming such contacts. [Background technology]

[0002] As the dimensions of various integrated circuit components have decreased, both the performance and power consumption of transistors, such as field-effect transistors (FETs), have improved dramatically. These improvements can be largely attributed to the reduced dimensions of the components used therein, which generally leads to reduced capacitance and resistance and increased throughput current from the transistors. Metal oxide semiconductor field-effect transistors (MOSFETs) are well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of the device's source / drain regions, channel region, and gate electrode also decrease.

[0003] FinFETs, nanosheet FETs, and vertical transport FETs are under development for use in tight pitch applications. Nanosheet FETs contain multiple channel layers, each separated by a gate stack containing a layer of conductive gate material and a gate dielectric layer. The gate stack surrounds the channel layer on all sides, forming a gate-all-around (GAA) structure. Epitaxial regions at the edges of the nanosheet channel layer form the source / drain regions of the nanosheet FET.

[0004] The use of both front-side and back-side contacts can improve the fabrication and performance of integrated circuits. By providing contacts on both sides of the chip, the contact spacing can be greater than if only one side (e.g., the front side) contained all the contacts for the FET. The back-side power rail can be electrically connected to the back-side source / drain contacts. Summary of the Invention

[0005] A typical monolithic semiconductor structure includes a device layer having a front side and a back side; an interlayer dielectric layer; and a field effect transistor in the interlayer dielectric layer, including a channel region and first and second source / drain regions extending laterally from the channel region. Each of the first and second source / drain regions has an upper surface, a lower surface, and a sidewall surface extending between the upper and lower surfaces. The device layer further includes a first metal source / drain sidewall contact directly contacting the sidewall surface of the first source / drain region and having an upper end and a lower end, and a second metal source / drain sidewall contact directly contacting the sidewall surface of the second source / drain region, the second metal source / drain sidewall contact also having an upper end and a lower end. The backside source / drain contact directly contacts the lower surface of the first source / drain region and the lower end of the first metal source / drain sidewall contact. The frontside source / drain contact directly contacts the top surface of the second source / drain region and the top edge of the second metal source / drain sidewall contact. The backside and frontside source / drain contacts comprise metal.

[0006] The second monolithic semiconductor structure includes a device layer having a front side and a back side. The device layer includes field effect transistors and an interlayer dielectric layer. The field effect transistors are positioned within the interlayer dielectric layer. Each of the field effect transistors includes a channel region and first and second source / drain regions extending laterally from the channel region. Each of the first and second source / drain regions includes an upper surface, a lower surface, and a sidewall surface extending between the upper and lower surfaces. Metal source / drain sidewall contacts are adjacent to the sidewall surfaces of the first and second source / drain regions of each of the field effect transistors, respectively. Backside source / drain contacts extend from the backside of the device layer. Each of the backside source / drain contacts includes metal and directly contacts the lower surface of the first source / drain region of one of the field effect transistors and a lower end of one of the source / drain sidewall contacts on the sidewall surface of the first source / drain region, respectively.

[0007] In accordance with a further aspect of the present invention, a method for fabricating a monolithic semiconductor structure including a backside contact and a frontside contact is provided. The method includes obtaining a device layer including an interlevel dielectric layer and a field effect transistor within the interlevel dielectric layer. The field effect transistor includes a channel region and first and second source / drain regions extending laterally from the channel region, each of the first and second source / drain regions having an upper surface, a lower surface, and a sidewall surface extending between the upper and lower surfaces. A first metal source / drain sidewall contact is formed directly on the sidewall surface of the first source / drain region, and a second metal source / drain sidewall contact is formed directly on the sidewall surface of the second source / drain region. The first metal source / drain sidewall contact and the second metal source / drain sidewall contact each have upper and lower ends. The method further includes forming a frontside source / drain contact directly on the upper surface of the second source / drain region and on the upper edge of the second metal source / drain sidewall contact, and forming a backside source / drain contact directly on the lower surface of the first source / drain region and on the lower edge of the first metal source / drain sidewall contact.

[0008] The techniques and structures as disclosed herein may provide substantial beneficial technical effects. By way of example only and not limitation, one or more embodiments may provide one or more of the following advantages: · Manufacturing flexibility; · Advantages of backside power supply network technology; Increased backside and frontside contact / silicide area; Wrap-around backside and frontside contact.

[0009] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments, which is to be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0010] The following drawings are presented by way of example only and not by way of limitation, and in which like reference characters (where used) indicate corresponding elements throughout the several views.

[0011] [Figure 1] 1 is a plan view of a layout including a sacrificial gate on a nanosheet stack, showing x and y cross sections, according to an exemplary embodiment;

[0012] [Figure 1A] Schematic cross-sectional view along the x section of Figure 1;

[0013] [Figure 1B] Schematic cross-sectional view along the y-section;

[0014] [Figure 2A] Schematic cross-sectional view along the x-section showing the structure shown in Figure 1A after removing the bottom layer of the nanosheet stack;

[0015] [Figure 2B] Schematic cross-sectional view along the y-section;

[0016] [Figure 3A] 2B is a schematic cross-sectional view of the structure shown in FIG. 2A after forming a spacer layer and a lower dielectric isolation layer;

[0017] [Figure 3B] 3A is a schematic cross-sectional view of the structure shown in FIG. 3A along the y-section;

[0018] [Figure 4A] 3B is a schematic cross-sectional view of the structure shown in FIG. 3A after depositing and recessing an interlevel dielectric layer;

[0019] [Figure 4B] Schematic cross-sectional view along the y-section;

[0020] [Figure 5A]A schematic cross-sectional view showing the structure of Figure 4A after recessing the nanosheet stack and forming the internal spacer;

[0021] [Figure 5B] Schematic cross-sectional view along the y-section;

[0022] [Figure 6A] 5B is a schematic cross-sectional view of the structure shown in FIG. 5A after patterning the backside contact;

[0023] [Figure 6B] Schematic cross-sectional view along the y-section;

[0024] [Figure 7A] 6B is a schematic cross-sectional view of the structure shown in FIG. 6A after forming a sacrificial placeholder for the backside contact;

[0025] [Figure 7B] Schematic cross-sectional view along the y-section;

[0026] [Figure 8A] 7B is a schematic cross-sectional view of the structure shown in FIG. 7A after forming source / drain regions;

[0027] [Figure 8B] Schematic cross-sectional view along the y-section;

[0028] [Figure 9A] 8B is a schematic cross-sectional view of the structure shown in FIG. 8A along the x-section after forming a dielectric liner deposition of a dielectric fill material;

[0029] [Figure 9B] Schematic cross-sectional view along the y-section;

[0030] [Figure 10A]9B is a schematic cross-sectional view of the structure shown in FIG. 9A after replacement metal gate (RMG) processing;

[0031] [Figure 10B] Schematic cross-sectional view along the y-section;

[0032] [Figure 11A] 10B is a schematic cross-sectional view of the structure shown in FIG. 10A after recessing the metal gate and forming a dielectric gate cap layer;

[0033] [Figure 11B] Schematic cross-sectional view along the y-section;

[0034] [Figure 12A] 11B is a schematic cross-sectional view of the structure shown in FIG. 11A after recessing the dielectric fill material;

[0035] [Figure 12B] Schematic cross-sectional view along the y-section;

[0036] [Figure 13A] 12B is a schematic cross-sectional view of the structure shown in FIG. 12A after selectively removing a portion of the dielectric liner;

[0037] [Figure 13B] Schematic cross-sectional view along the y-section;

[0038] [Figure 14A] 13B is a schematic cross-sectional view of the structure shown in FIG. 13A after forming metal sidewall contacts adjacent the source / drain regions;

[0039] [Figure 14B] 14A is a schematic cross-sectional view of the structure shown in FIG. 14A along the y-section;

[0040] [Figure 15A]14B is a schematic cross-sectional view of the structure shown in FIG. 14A after forming MOL metal contacts, forming BEOL interconnect layers, and bonding a carrier wafer;

[0041] [Figure 15B] Schematic cross-sectional view along the y-section;

[0042] [Figure 16A] 15B is a schematic cross-sectional view of the structure shown in FIG. 15A after removing the semiconductor substrate layer;

[0043] [Figure 16B] Schematic cross-sectional view along the y-section;

[0044] [Figure 17A] 16B is a schematic cross-sectional view of the structure shown in FIG. 16A after removing the etch stop layer and further semiconductor substrate layers;

[0045] [Figure 17B] Schematic cross-sectional view along the y-section;

[0046] [Figure 18A] 17A is a schematic cross-sectional view of the structure shown in FIG. 17A after depositing and planarizing a backside interlevel dielectric layer;

[0047] [Figure 18B] Schematic cross-sectional view along the y-section;

[0048] [Figure 19A] 18B is a schematic cross-sectional view of the structure shown in FIG. 18A after removal of the sacrificial placeholder;

[0049] [Figure 19B] Schematic cross-sectional view along the y-section;

[0050] [Figure 20A] 19A after laterally etching the backside interlayer dielectric layer;

[0051] [Figure 20B] Schematic cross-sectional view along the y-section;

[0052] [Figure 21A] 20B is a schematic cross-sectional view of the structure shown in FIG. 20A after backside contact metallization and formation of a backside interconnect layer; and

[0053] [Figure 21B] FIG. 1 is a schematic cross-sectional view taken along the y-section.

[0054] It should be understood that elements in the figures are shown for simplicity and clarity, and that common but well-understood elements that may be useful or necessary in a commercially viable embodiment may not be shown in order to make the illustrated embodiment easier to view. DETAILED DESCRIPTION OF THE INVENTION

[0055] The principles of the present invention are described herein in the context of exemplary embodiments. It should be understood, however, that the specific embodiments and / or methods illustratively shown and described herein are to be considered exemplary and not restrictive. Moreover, it will be apparent to those skilled in the art in light of the teachings herein that numerous modifications can be made to the illustrated embodiments that are within the scope of the claims. Thus, no limitations are intended or should be inferred with respect to the embodiments shown and described herein.

[0056] The use of backside contacts in addition to frontside contacts can improve the fabrication and performance of integrated circuits, especially those with relatively small features and high packing densities. Elements employed in high-density, high-performance applications include gate-all-around (GAA) transistors, such as nanosheet transistors and fin-like field effect transistors (FinFETs).

[0057] Figure 1 and subsequent figures illustrate a typical sequence of steps that may be employed in the fabrication of an integrated circuit including a backside contact. The schematic plan view of Figure 1 provides a perspective view of the x and y cross-sectional orientation relative to the fin, including the nanosheet stack 20 and the sacrificial gate 22 extending perpendicular to the fin. It will be understood that the techniques described herein are applicable to architectures including FinFETs and architectures including nanosheet transistors.

[0058] The monolithic structure shown in Figures 1, 1A, and 1B includes a stack of nanosheets 20 including a semiconducting channel layer 21 and a sacrificial silicon germanium layer 26 formed on a substrate. The nanosheets may be formed on, for example, a bulk semiconductor substrate. Referring to Figures 1A and 1B, the substrate includes a silicon layer 24 and an etch stop layer 28 within the silicon substrate layer 24. The etch stop layer may be, for example, a buried oxide (BOX) layer or a silicon germanium layer.

[0059] In one or more exemplary embodiments, the semiconductor nanosheet (channel) layers 21 each have a thickness in the range of four to ten nanometers (4-10 nm). The number of semiconductor (channel) layers in the semiconductor layer stack can vary depending on the desired application and capabilities of the nanosheet transistor being fabricated. In some embodiments, the semiconductor channel layers 21 are essentially single-crystalline silicon layers spaced apart by ten to twenty nanometers (10-20 nm). In some embodiments, the width of each semiconductor channel layer 21 in the upper fin-shaped portion of a typical monolithic structure (as viewed in the y-cross section) is fifteen nanometers (15 nm) or greater. The channel layer dimensions and vertical spacing of the channel layers should be considered exemplary and not limiting.

[0060] Alternating silicon and silicon germanium layers 21, 26 can be epitaxially grown on a semiconductor substrate to obtain a layered stack with the desired number of silicon (channel) layers. The terms "epitaxially growing and / or depositing" and "epitaxially grown and / or deposited" refer to the growth of a semiconductor material on a deposition surface of the semiconductor material, where the growing semiconductor material has the same crystallinity as the semiconductor material on the deposition surface. In an epitaxial deposition process, chemical reactants provided by source gases are controlled and system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with enough energy to move around on the surface and are oriented to match the crystalline arrangement of the atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same crystallinity as the deposition surface on which it is formed.

[0061] The monolithic structure shown in Figures 1, 1A, and 1B is obtained by first growing alternating silicon and silicon germanium nanosheet layers on a substrate. The sacrificial silicon germanium layer 26, which will replace the metal gate and gate dielectric material later in the process, can have a thickness in the range of six to twenty nanometers (6-20 nm). The dimensional ranges of the channel layer and sacrificial silicon germanium layer should be considered typical rather than limiting. The sacrificial silicon germanium layer 26 is Si to allow selective etching relative to the silicon and underlying silicon germanium substrate layer 26'. 1-x Ge x (x is 0.2 to 0.3). In one exemplary embodiment, the sacrificial silicon germanium layer 26 may have a composition of Si 1-x Ge x (x is about 0.3), while the silicon germanium substrate layer 26' has a composition of Si 1-x Ge x (x is about 0.55). The thickness of the upper silicon germanium substrate layer 26' may or may not be the same as the thickness of the sacrificial silicon germanium layer 26 adjacent to the silicon channel layer 21. Using the patterned hard mask (e.g., silicon nitride), a first reactive ion etch (RIE) is performed to obtain a multi-layer fin-type semiconductor structure with a dielectric cap (not shown) formed from the hard mask. The multi-layer fin-type semiconductor structure (nanosheet stack 20) ​​extends vertically from the semiconductor substrates 24, 26. The remaining portions of the hard mask are removed.

[0062] 1B, a cavity is formed in the semiconductor substrate between the nanosheet stacks 20. The bottom of the cavity is above the top surface of the etch stop layer 28. Shallow trench isolation (STI) regions 34 are formed in the cavity in the substrate 24 to provide electrical isolation of active areas, including neighboring transistors or other devices, that may be formed on the substrate 24. Silicon dioxide or other suitable dielectric material may be deposited to form such regions.

[0063] A sacrificial gate layer is formed on the stack of nanosheet layers 20. The sacrificial gate layer may include, for example, thin layers of SiO2 and amorphous silicon (a-Si) or polycrystalline silicon (polysilicon). The sacrificial gate material used to form the sacrificial gate layer may be formed using, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof. A hard mask (e.g., SiNx or a combination of SiNx and SiO2) is deposited and patterned on the top surface of the sacrificial gate layer. The sacrificial gate layer is then subjected to reactive ion etching. The resulting structure includes a sacrificial gate 22 extending perpendicular to the parallel nanosheet stack 20. A patterned gate hard mask 32 is adjacent to the top surface of the sacrificial gate. As shown in FIG. 1, the sacrificial gate 22 extends through both the nFET and pFET regions of the typical structure.

[0064] Selective removal of the top substrate layer 26′ forms a space 36 between the top surface of the semiconductor layer 24 and the nanosheet stack 20. As discussed above, the top substrate layer 26′ has a higher germanium content than the sacrificial silicon germanium layer 26 in the nanosheet stack 20 and can therefore be etched selectively with respect to such layer. A selective etching process, such as dry HCl etching, can be employed to remove the top substrate layer 26′ selectively with respect to the silicon channel layer 21 and the sacrificial silicon germanium layer 26. Figures 2A and 2B provide cross-sectional views of the resulting structure in the x- and y-planes, respectively.

[0065] A dielectric layer is deposited on the resulting structure, filling the space 36 below the nanosheet stack 20. The dielectric gate spacer may comprise, for example, SiN, SiBCN, SiOCN, and / or SiCO, or other suitable dielectric materials. Such materials can be deposited using atomic layer deposition (ALD). In a typical embodiment, a silicon nitride liner is deposited on the monolithic structure. The silicon nitride liner is selectively etched back to remove its unprotected horizontal portions, forming vertical upper sidewall gate spacers 38 on the sidewalls of the nanosheet stack 20 and the sacrificial gate 22. The spacer material below the nanosheet stack is protected and remains in the space 36 after etchback, thereby forming a lower dielectric isolation layer. Figures 3A and 3B provide cross-sectional views of the resulting structure, including the vertical gate spacer 38 and the lower dielectric isolation layer (horizontal spacer 38A) below the nanosheet stack 20.

[0066] An interlevel dielectric (ILD) layer 40 is deposited on the structure using a deposition technique including, but not limited to, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), radio-frequency CVD (RFCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD), and / or liquid source misted chemical deposition (LSMCD), spin-on coating, sputtering, and / or plating. The ILD layer 40 may comprise, but is not necessarily limited to, a low-k material (e.g., k less than about 4.0), such as, for example, porous silicates, carbon-doped oxides, silicon dioxide, silicon oxynitride, carbon-doped silicon oxide (SiCOH) and its porous variants, silsesquioxanes, siloxanes, or other dielectric materials, e.g., having a dielectric constant in the range of about 2 to about 4. A SiCOH dielectric film having a dielectric constant (k) of about 2.7-2.8, for example, can be included in one or more ILD layers. Such a dielectric film can be deposited using PECVD. In some embodiments, the ILD layer can include an ultra-low-k (ULK) dielectric material having a dielectric constant of 2.5 or less. In some embodiments, the ILD layer includes multiple layers. The ILD layer 40 is recessed to the top surface of the nanosheet stack. As shown schematically in FIG. 4B, the ILD layer 40 fills the spaces between the gate spacers 38 and extends to the top surface of the STI region 34.

[0067] Referring to Figures 5A and 5B, the portion of the nanosheet stack 20 outside the area protected by the sacrificial gate 22, hard mask 32, and gate spacer 38 is subjected to reactive ion etching down to the horizontal spacer 38A, which forms the bottom dielectric isolation (BDI) layer. The resulting structure is subjected to a timed wet etching process to selectively recess the silicon germanium layer 26 within the nanosheet stack 20. In some embodiments, hydrogen chloride gas is employed to selectively remove the silicon germanium, leaving the silicon nanosheet (channel) layer 21 substantially intact. Alternatively, a wet etching process containing an aqueous ammonia-hydrogen peroxide solution can be used to etch SiGe selectively relative to other materials. Each exposed edge of the silicon germanium layer 26 may be recessed, for example, by three to seven nanometers (3-7 nm). After the timed etching, the width of the silicon germanium layer 26 is smaller than the width of the silicon (channel) layer 21. Thus, the stack of semiconductor nanosheet layers has a recess between each pair of ends of the silicon (channel) layer 21.

[0068] A dielectric spacer material is deposited in the trenches resulting from reactive ion etching of the stack of semiconductor layers. The dielectric spacer material is etched back to form interior spacers 44 within each of the recesses in the stack of nanosheet semiconductor layers. Selective wet etching may be employed to remove the dielectric interior spacer material outside the recesses between the silicon layers. A structure 50 is obtained, as shown schematically in Figures 5A and 5B. The interior spacers 44 of this structure may comprise, for example, a low-k dielectric material. In some embodiments, silicon oxynitride, silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), and / or silicon oxycarbide (SiOC) interior spacers may be formed. When a silicon nitride-based material with a relatively low dielectric constant is used to form the interior spacers, the silicon nitride-based material can be selectively etched using, for example, phosphoric acid. Various techniques for forming interior spacers for nanosheet transistors have been discussed in the literature and are continuing to be developed. Therefore, the specific materials and steps discussed for forming the interior spacers should be considered exemplary rather than limiting.

[0069] An organic planarization layer (OPL) 46 is deposited and then patterned to obtain structure 60 as shown in FIGS. 6A and 6B. A lithographically patterned hard mask (not shown) can be employed to form vertical placeholder trenches 48 that extend through OPL 46 and down to etch stop layer 28 in the substrate. As shown in FIG. 6B, each trench 48 extends between a pair of STI regions 34. A placeholder material layer is deposited in placeholder trenches 48. The placeholder material layer is recessed to form structure 70 as shown schematically in FIGS. 7A and 7B. The placeholder material layer includes sacrificial placeholders 52 in the substrate, which will later be replaced with metal backside contacts, as described below. The sidewalls of the sacrificial placeholders 52 are substantially vertical. The bottom surfaces of the sacrificial placeholders are adjacent to etch stop layer 28. The top surface of the sacrificial placeholder may extend above the bottom surface of BDI layer 38A but below the level of the bottom of nanosheet stack 20. Materials that may comprise sacrificial placeholder 52 include silicon carbide, aluminum oxide, and titanium oxide.

[0070] The OPL 46 is removed to expose additional edges of the channel nanosheet layer 21 of the nanosheet stack 20. Ashing or other suitable processes can be employed to remove the OPL. Source / drain regions 56-1, 56-2 are epitaxially grown on the exposed edges of the silicon nanosheet channel layer 21. Selected source / drain regions 56-1 are grown directly on the sacrificial placeholder 52. Other source / drain regions 56-2 are grown on the BDI layer 38A, as shown in the exemplary structure 80 shown in Figures 8A and 8B. The timing of the epitaxial growth of the source / drain regions 56-1, 56-2 is adjusted to control their height and width dimensions. As known in the art, dopants may be incorporated in situ using appropriate precursors. By "in situ," we mean that the dopants that determine the conductivity type of the doped layer are introduced during the process step that forms the doped layer, e.g., epitaxial deposition. As used herein, the term "conductivity type" refers to the addition of an impurity to an intrinsic semiconductor that results in a deficiency of valence electrons. For silicon-containing substrates, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. As used herein, "n-type" refers to the addition of an impurity that provides free electrons to an intrinsic semiconductor. For silicon-containing substrates, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus.Typical epitaxial growth processes suitable for use in forming silicon and / or silicon germanium epitaxy include rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Referring to FIG. 1, the nFET region includes transistors with n-type source / drain regions, while the pFET region includes p-type source / drain regions. The source / drain regions of nanosheet devices are typically grown before the RMG (replacement metal gate) process.

[0071] 9A and 9B, a dielectric liner 54, such as a silicon nitride liner, is conformally deposited on the source / drain regions 56-1, 56-2, the ILD layer 40, and the spacers 38. A dielectric fill layer 58 is then deposited on the dielectric liner 54 and planarized to the top surface of the hard mask 32. The planarization may be performed using a chemical mechanical planarization (CMP) process. The dielectric fill layer 58 may be, for example, a silicon dioxide layer. A monolithic structure 90, as shown in FIGS. 9A and 9B, is obtained.

[0072] The hard mask 32 and sacrificial gate layer 22 are removed from the structure 90. The silicon germanium layer 26 is then selectively removed, leaving behind a stack of silicon (channel) layers 21 separated by spaces (not shown). In some embodiments, hydrogen chloride gas is employed to selectively remove the silicon germanium, leaving the silicon nanosheets substantially intact. Alternatively, a wet etching process containing an aqueous ammonia-hydrogen peroxide solution can be used to etch SiGe selectively relative to other materials. A gate stack 62 is formed adjacent to the nanosheet (channel) layer 21. A gate dielectric layer forms the portion of the gate stack that replaces the sacrificial silicon germanium layer. The gate stack is adjacent to the silicon nanosheet channel layer 21. Non-limiting examples of suitable materials for the gate dielectric layer include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, or any combination thereof. Examples of high-k gate dielectric materials (dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k material may further include dopants such as lanthanum and aluminum. The gate dielectric layer may be formed by a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other similar processes. The thickness of the gate dielectric material may vary depending on the deposition process and the composition and number of high-k dielectric materials used. In one exemplary embodiment, a 2.5 nm thick high-k dielectric layer is employed. In some embodiments, the gate dielectric layer comprises multiple dielectric layers.

[0073] A conductive gate material is deposited in the space originally filled by the sacrificial gate 22 and the silicon germanium nanosheet layer 26. The deposited metal gate material forms the metal gate of the resulting nanosheet field effect transistor of the structure 100. In some embodiments, the conductive gate comprises a work function metal (WFM) layer. The WFM serves the dual purpose of Vt setting and gate conductor. Non-limiting examples of suitable work function metals include p-type work function metal materials and n-type work function metal materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, titanium nitride, or any combination thereof. N-type metal materials include, for example, hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The work function metal can be deposited by a suitable deposition process, for example, a conformal ALD process.

[0074] In one exemplary embodiment, a three nanometer (3 nm) thick n-type WFM layer may be formed on the gate dielectric layer. The WFM layer thickness may be, for example, in the range of two to ten nanometers (2-10 nm), with thinner layers being used as device scaling decreases. The n-type WFM layer is intended for use in conjunction with n-type transistors. Therefore, it may replace portions of the n-type WFM layer that may also be deposited in the pFET region later in the process. The n-type WFM layer and gate dielectric may fill the space between the silicon channel layer 21 and the region originally occupied by the sacrificial gate 22.

[0075] The n-type WFM layer in the nFET region may be protected by a patterned OPL (not shown). The exposed portions of the n-type WFM layer in the pFET region are removed, leaving open spaces between the silicon channel layer 21 in the pFET region. Thus, the gate metal is removed from the pFET region while leaving the protected nFET region intact. An SC1 etch or other suitable etching process can be employed to selectively remove the gate metal while leaving the gate dielectric layer substantially intact. The duration of the etch is sufficient to remove all of the gate metal from the pFET region without affecting the gate metal in the nFET region. After the initially deposited n-type WFM layer is removed from the pFET region, a new gate metal, determined to be appropriate for the pFET transistor, is deposited. In embodiments where the initially deposited metal is n-type, a p-type WFM layer is deposited. It will be understood that in some alternative embodiments, the process can be reversed, with the n-type metal being deposited after the p-type metal. Chemical mechanical planarization can be used to remove the metallization. Thus, a FEOL layer is provided that includes FETs and possibly other electronic devices (not shown) within the ILD layer 40. Figures 10A and 10B provide cross-sectional views of an exemplary structure 100.

[0076] The gate stack 62 is recessed and a self-aligned contact dielectric gate cap (SAC cap) layer 64 is formed on the structure. The dielectric gate cap layer is planarized to the top surface of the dielectric fill layer 58. The composition of the dielectric gate cap layer 64 is different from the composition of the gate spacers 38. For example, in some exemplary embodiments, a silicon carbide (SiC) gate cap layer 64 is formed. Figures 11A and 11B show an exemplary structure 110 obtained after recessing the gate stack and forming the gate cap layer.

[0077] The dielectric fill layer 58 is recessed and rests on the dielectric liner 54. As shown in FIG. 12A, a recess 66 is formed between portions of the gate cap layer 64. A structure 120 may be obtained, as shown in FIGS. 12A and 12B. The horizontal portions of the dielectric liner 54 are removed selectively to the gate cap layer 64 and the source / drain regions 56-1, 56-2. Vertical portions of the dielectric liner 54 remain, as shown in the x-section in FIG. 13A. Reactive ion etching may be employed to remove the horizontal portions of the dielectric liner, thereby exposing the top surfaces of the source / drain regions 56-1, 56-2. The unprotected portions of the gate spacer 38 are also removed selectively down to the STI regions 34, thereby exposing the sidewall surfaces of the source / drain regions, as shown in FIG. 13B. The top portions of the source / drain regions may also be removed at this point because the spacer pull-down process may not be completely selective to source / drain epitaxy. The resulting structure 130 includes a vertical space between the sidewalls of the source / drain regions and the sidewalls of the adjacent portions of the ILD layer 40. A vertical space extends through device layer 65 and is open at its upper end and adjacent to STI region 34 at its lower end.

[0078] Metal sidewall source / drain contacts 68-1 are formed in the vertical spaces between the source / drain regions 56-1, 56-2 and the ILD layer 40. In some embodiments, titanium (Ti) is deposited using an atomic layer deposition (ALD) process to fill the vertical spaces. Alternatively, other metals or conductive compositions, such as nickel (Ni), nickel platinum (NiPt), or Ti / TiN, or combinations thereof, may be deposited during sidewall metallization. An isotropic etch-back process may be employed to obtain a structure 140 as shown in FIGS. 14A and 14B. This structure may be annealed to form a metal silicide layer between the contact metal and source / drain epitaxy. The source / drain sidewall contacts 68-1 are embedded in the device layer 65 and extend between the upper surface of the ILD layer 40 and its lower surface. As further shown in FIG. 14B, the source / drain sidewall contacts extend through openings in the BDI layer 38A, with their lower ends adjacent to the STI regions 34. Each sidewall source / drain contact 68-1 forms an electrical connection to one of the source / drain regions 56-1, 56-2. As shown in FIG. 14B, the opposite sidewall surfaces of the source / drain regions 56-1, 56-2 are in direct contact with the sidewall contact metal when viewed in the y-section. The sidewall contact 68-1 on each source / drain region is electrically isolated from the sidewall contact of an adjacent source / drain region by the STI regions 34 and a portion of the ILD layer 40.

[0079] Referring to Figures 15A and 15B, front-side contacts are formed in middle-of-line (MOL) processing. Silicon-based devices typically include multiple interconnect metallization layers above a device (front-end-of-line) layer 65 containing field-effect transistors (FETs) and / or other electronic structures. Front-end-of-line (FEOL) processing includes high-temperature steps to manipulate the conductivity of semiconductors. Middle-end (MOL) processing includes steps typically used to fabricate metal contacts for logic circuit components such as field-effect transistors (FETs), resistors, diodes, and capacitors. MOL processing may include intermediate-temperature steps to form semiconductor-metal compounds (e.g., silicides, germanosilicides) for electrical contacts. Back-end (BEOL) processing involves creating metal interconnect lines that connect devices formed in FEOL processing to form electrical circuits and may include silicidation as discussed above with respect to MOL processing.

[0080] A MOL ILD layer 40' is deposited and patterned on the device layer. Openings in the MOL ILD layer extend to the top surfaces of selected source / drain regions 56-2 and their associated sidewall contacts 68-1. The top (front-side) source / drain contacts 68-F and gate contact (not shown) can comprise conductive materials, including, but not limited to, silicide layers such as Ti, Ni, NiPt, and the like; metal adhesion layers such as TiN, TaN, and conductive metal fillers such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), or any other suitable conductive material, and combinations thereof. The metal silicide layer can be formed on the source / drain regions 56-2 by depositing a metal liner, such as a titanium liner, prior to depositing the metal fill layer. Such a titanium liner can be deposited using physical vapor deposition (PVD) and then annealed at temperatures between approximately 200 and 800 degrees Celsius to form a metal silicide. As shown in the y-cross-section of FIG. 15B, the sidewall contact 68-1 and the frontside contact 68-F together form a frontside wrap-around contact (WAC) that contacts the top (front surface) and sidewall of selected source / drain regions 56-2. The electrical connection between such a WAC and the source / drain regions 56-2 is enhanced by the relatively large contact area therebetween. At this stage in the fabrication process, recesses 66 in the gate cap layer 64 above the other source / drain regions 56-1 of the structure 150 remain filled with ILD material.

[0081] After MOL processing, metal interconnect lines are formed in one or more BEOL layers 75 that connect devices in the FEOL (device) layer 65 to form electrical circuits. BEOL layers are formed on the front side of the device layer 65. Metal lines, including the interconnect lines, are deposited sequentially (e.g., M1, M2, M3, etc.) on the FEOL layers and include dielectric layers. The interconnect lines within each metal line are electrically connected to the interconnect lines within other metal lines and to the devices in the FEOL (device) layer 65. BEOL processing typically includes low-temperature steps to form the metal lines and maintain temperature-sensitive FEOL and MOL structures. BEOL processing involves the formation of interconnect layers above the MOL layers. A chip may have multiple BEOL interconnect layers. Each interconnect layer has a wiring scheme and is connected to other interconnect layers by vias. These lines and vias are in dielectric layers, one or more of which may include low-k materials.

[0082] A carrier wafer 72 is bonded to the resulting structure and adjacent to the BEOL layers 75. A typical monolithic semiconductor structure 150 shown in Figures 15A and 15B includes a FEOL (device) layer 65 containing nFET and pFET transistors, their source / drain regions 56-1, sidewall contacts 68-1 adjacent to the sidewalls of 56-2, and optionally other electronic devices; a MOL layer including a frontside contact 68-F; and a BEOL layer 75 electrically connected to the devices in the device layer. The structure 150 further includes the carrier wafer 72. The frontside contact 68-F and the sidewall contact 68-1 form integral wrap-around contacts that extend around and over the source / drain regions 56-2 in the device layer 65, forming a relatively large contact area therebetween. The wrap-around contacts electrically connect selected source / drain regions 56-2 to the BEOL layers 75.

[0083] Monolithic structure 150 is inverted, and the portion of silicon substrate layer 24 underlying etch stop layer 28 is removed therefrom. Because of their high selectivity to silicon germanium, ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) may be employed for such removal. (As noted above, the etch stop layer may include silicon germanium.) Monolithic structure 160 may be obtained as shown schematically in FIGS. 16A and 16B (front-side up). The remaining portions of etch stop layer 28 and silicon substrate layer 24 are then selectively removed to obtain structure 170 as shown in FIGS. 17A and 17B (also front-side up). After such removal, sacrificial placeholder 52 is exposed on the backside of the structure.

[0084] A backside ILD layer 40" is deposited on the inverted structure 170 and planarized to the backside surface of the sacrificial placeholder 52. During such processing, the backside surface of the sacrificial placeholder faces upward. Although not required, the backside ILD layer 40" may have the same composition as the previously formed ILD layers 40, 40', discussed above. As shown in Figures 18A and 18B, the backside surface of the sacrificial placeholder 52 is exposed in the resulting structure 180.

[0085] A conventional dry or wet etching process is used to selectively remove the sacrificial placeholder 52. A cavity 76 is formed in the backside ILD layer 40″ in place of the sacrificial placeholder 52, as shown in FIGS. 19A and 19B. The backside of the source / drain region 56-1 of the resulting structure 190 is exposed at the upper edge of the cavity 76. The cavity 76 is then laterally expanded to form a structure 200, as shown in FIGS. 20A and 20B. As shown in FIG. 20B, the lateral expansion of the cavity 76 exposes the underside of the sidewall contact 68-1 adjacent to the source / drain region 56-1. An isotropic dry or wet etch may be employed to laterally expand the cavity 76. The etch selectively removes the STI region 34 and a portion of the backside ILD layer 40″ while leaving the source / drain region 56-1 and the sidewall contact 68-1 on the source / drain region 56-1 substantially intact.

[0086] After backside contact metallization, excess metal is removed to form backside source / drain contacts 68-B. The source / drain sidewall contacts 68-1 and the source / drain backside contacts 68-B form an integral, wraparound contact structure that contacts the backside (underside) and sidewall surfaces of the source / drain regions 56-1. The backside source / drain contacts 68-B may or may not comprise the same metal / metal silicide used to form the frontside source / drain contacts 68-F and the sidewall source / drain contacts 68-1. The presence of the BEOL layer 75 at this stage of the process may prevent high-temperature thermal annealing. The relatively large contact area between the source / drain regions 56-1 and the WAC formed by the backside and sidewall source / drain contacts 68-B, 68-1 helps mitigate contact resistance issues that can arise from not performing a high-temperature thermal anneal during the backside metallization process. Because the sidewall source / drain contacts 68-1 are formed on the sidewalls of the source / drain regions 56-1 before forming the BEOL interconnect layer 75, only the portions of the backside wraparound contact structures that contact the backside surfaces of the source / drain regions 56-1 need to consider possible temperature limitations due to the backside metallization and the BEOL layers 75 during annealing.

[0087] The width of each backside source / drain contact 68-B is greater than the width of the backside surface of the corresponding source / drain region 56-1, and the "backside" surface is on top of this structure during backside metallization after wafer flip, as discussed above. The backside source / drain contacts 68-B extend into the backside ILD layer 40''. As shown schematically in FIG. 21B, a portion of the backside source / drain contacts 68-B may contact the lower sidewall surface of the sidewall source / drain contact 68-1 and its backside surface (lower surface). As shown in FIG. 21A, the upper portions of the backside source / drain contacts 68-B may also extend partially into the BDI layer 38A.

[0088] A backside interconnect structure is formed on the backside ILD layer 40''. In some embodiments, the backside interconnect structure includes a backside power rail (BPR) and a backside power delivery network (BSPDN). A backside interconnect structure 78 is shown schematically in Figures 21A and 21B. The backside source / drain contacts 68-B are electrically connected to the backside interconnect structure 78.

[0089] Using the fabrication techniques discussed above, a monolithic semiconductor structure 210, as shown in FIGS. 21A and 21B, can be obtained. The structure 210 includes a device layer 65 formed by FEOL processing and having a front side and a back side. Field-effect transistors and possibly other electronic devices (not shown) are incorporated within the device layer. The device layer 65 includes a FET, including a channel region (in a typical structure, a stacked silicon nanosheet channel layer 21), source / drain regions 56-1 and 56-2 extending laterally from the channel region, and a gate stack 62, all of which are embedded within the ILD layer 40. A BEOL interconnect layer 75 is positioned on the front side of the device layer 65 and electrically connects to the field-effect transistor. Sidewall source / drain contacts 68-1 are adjacent to the sidewalls of the source / drain regions 56-1 and 56-2. The frontside source / drain contacts 68-F are adjacent to the upper surfaces of selected source / drain regions 56-2 and the sidewall source / drain contacts 68-1 associated with such source / drain regions. The frontside source / drain contacts 68-F and the sidewall source / drain contacts 68-1 form an integral wrap-around contact structure employed to electrically connect the source / drain regions 56-2 to the BEOL interconnect layer 75. The backside source / drain contacts 68-B are adjacent to the backside surfaces of selected other source / drain regions 56-1 and the sidewall source / drain contacts 68-1 associated with such source / drain regions. The backside source / drain contacts 68-B and the sidewall source / drain contacts 68-1 form an integral wrap-around contact structure employed to electrically connect the source / drain regions 56-1 to the backside interconnect layer 78. As shown in FIG. 21A , the lower dielectric isolation layer 38A below the gate stack 62 also extends over a portion of the upper surface of the backside source / drain contacts 68-B.

[0090] In some embodiments, a field-effect transistor (or FETs) in device layer 65 includes one source / drain region 56-2 electrically connected to BEOL layer 75 by a frontside contact 68-F and another source / drain region 56-1 electrically connected to backside interconnect layer 78 by a backside contact 68-B. Some FETs in device layer 65 may have their source / drain regions electrically connected only to BEOL interconnect layer 75 by a frontside contact, while the source / drain regions of other FETs may be electrically connected only to backside interconnect layer 78 by a backside contact. In embodiments in which backside interconnect layer 78 includes signal and power lines rather than just power lines, an integrated circuit including FETs may have both the source / drain regions of the FETs electrically connected to the backside interconnect layer by a backside contact. A wraparound contact structure, which provides contact with the top or bottom source / drain surfaces and the source / drain sidewall surfaces, allows for larger silicide areas on both the frontside and backside contacts. By providing source / drain sidewall contacts 68-1 that extend completely through the device layer 65 before forming the frontside and backside contacts, it is easier to provide wraparound source / drain contacts on both sides of the device layer.

[0091] The diagrams discussed above depict typical processing steps / stages in the fabrication of exemplary structures. While the overall fabrication method and the structures formed thereby are entirely novel, certain individual processing steps required to implement this method may utilize conventional semiconductor fabrication techniques and tools. These techniques and tools will already be familiar to those of ordinary skill in the relevant art in light of the teachings herein. Furthermore, one or more of the processing steps and tools used in the fabrication of semiconductor devices are also described in several readily available publications (including, for example, James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001), which are hereby incorporated by reference. While several individual processing steps are described herein, it is emphasized that these steps are exemplary only, and that those skilled in the art may be familiar with several equally suitable alternatives that may be applicable.

[0092] It should be understood that the various layers and / or regions illustrated in the accompanying figures may not be drawn to scale. Furthermore, for ease of illustration, one or more semiconductor or other layers of the type typically used in such integrated circuit devices may not be explicitly shown in a given figure. This is not to imply that the semiconductor or other layers not explicitly shown are omitted in the actual integrated circuit device.

[0093] At least a portion of the techniques described above can be implemented in an integrated circuit. In forming an integrated circuit, identical dies are typically manufactured in a repeating pattern on the surface of a semiconductor wafer. Each die includes the devices described herein and may include other structures and / or circuits. Individual dies are cut or diced from the wafer and then packaged as integrated circuits. Those skilled in the art will know how to dice wafers and package dies to create integrated circuits.

[0094] Those skilled in the art will understand that the exemplary structures discussed above may be distributed in raw form (i.e., a single wafer with multiple unpackaged chips), as bare die, in packaged form, or may be incorporated as part of an intermediate or final product that would benefit from having, for example, FET devices and contacts formed in accordance with one or more of the exemplary embodiments.

[0095] Numerous techniques are used by those skilled in the art to remove material at various stages in the fabrication of semiconductor structures. As used herein, these processes are collectively referred to as "etching." For example, etching includes wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE), all of which are known techniques for removing selective materials when forming semiconductor structures. Standard Clean 1 (SC1) contains a strong base, usually ammonium hydroxide, and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid and hydrogen peroxide. Etching techniques and applications are well understood by those skilled in the art, and therefore, a detailed description of such processes will not be presented herein.

[0096] The illustrations of the embodiments described herein are intended to provide a general understanding of various embodiments and are not intended to serve as a complete description of all elements and features of apparatus and systems that may employ the circuits and techniques described herein. Many other embodiments will be apparent to those skilled in the art in light of the teachings herein; other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of the present invention. It should also be noted that in some alternative implementations, some of the steps of a typical method may occur in an order other than that shown in the figures. For example, two steps shown in succession may, in fact, be executed substantially concurrently, or certain steps may, in some cases, be executed in the reverse order, depending on the functionality involved. The drawings are also merely representational and not drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative and not a restrictive sense.

[0097] For convenience only, embodiments may be individually and / or collectively referred to herein as "embodiments," but this is not intended to limit the scope of the present application to any single embodiment or inventive concept when, in fact, more than one embodiment or inventive concept is disclosed. Thus, while specific embodiments have been shown and described herein, it should be understood that other mechanisms which achieve the same purpose can be substituted for the specific embodiment shown. Combinations of the above embodiments, as well as other embodiments not specifically described herein, will be apparent to those skilled in the art in light of the teachings herein.

[0098] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used herein, specify the presence of stated features, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, actions, elements, components, and / or groups thereof. Terms such as "above," "below," and "vertical" are used to indicate the relative positioning of elements or structures with respect to one another, rather than relative height. When a layer of a structure is described herein as being "on" another layer, it will be understood that there may or may not be intermediate elements or layers between the two specified layers. When a layer is described herein as being "directly on" another layer, it indicates direct contact between the two layers.

[0099] When a means or step-plus-function element appears within the scope of the following claims, the corresponding structure, material, acts, and equivalents of that element are intended to include any structure, material, or acts for performing the function in combination with other specifically claimed claim elements. The description of various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art without departing from the scope thereof. The embodiments were chosen and described to best explain the principles and practical applications and to enable others skilled in the art to understand various embodiments with various modifications suited to the particular uses contemplated.

[0100] The Abstract is provided to comply with 37 C.F.R. §1.72(b). It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing Detailed Description, various features may be found grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, claimed subject matter may reside in fewer than all features of a single embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

[0101] In light of the teachings provided herein, those skilled in the art will be able to contemplate other implementations and applications of these techniques and the disclosed embodiments. Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the exemplary embodiments are not limited to those precise embodiments, and that various other changes and modifications can be made thereto by those skilled in the art without departing from the scope of the appended claims.

[0102] In accordance with the preferred embodiment of the present invention described above, a monolithic semiconductor structure is provided. The monolithic semiconductor structure has a device layer including a frontside and a backside, the device layer including an interlayer dielectric layer; and field effect transistors positioned within the interlayer dielectric layer. Each field effect transistor includes a channel region and first and second source / drain regions extending laterally from the channel region, each of the first and second source / drain regions having an upper surface, a lower surface, and sidewall surfaces extending between the upper and lower surfaces. The structure also includes source / drain sidewall contacts, each comprising a metal and adjacent to the sidewall surfaces of the first and second source / drain regions of each field effect transistor, where each source / drain sidewall contact has an upper end and a lower end. The structure also includes a backside source / drain contact, the backside source / drain contact extending from the backside of the device layer. Each backside source / drain contact comprises a metal and directly contacts a lower surface of a first source / drain region of one of the field effect transistors and a lower end of one of the source / drain sidewall contacts on a sidewall surface of the first source / drain region of one of the field effect transistors. Preferably, the device layer comprises an integrated circuit, and second source / drain regions of the plurality of field effect transistors are electrically connected to frontside source / drain contacts extending from a front side of the device layer. The structure further comprises a lower dielectric isolation layer adjacent the lower end of the second source / drain regions and an upper surface of each of the backside source / drain contacts. The structure further comprises frontside source / drain contacts extending from the front side of the device layer, each frontside source / drain contact comprising a metal and directly contacting a top surface of one of the second source / drain regions and an upper end of one of the source / drain sidewall contacts on a sidewall surface of one of the second source / drain regions. The structure further includes a BEOL interconnect layer on the front side of the device layer, the front side source / drain contacts being electrically connected to the BEOL interconnect layer.The structure further includes a backside interconnect layer on the backside of the device layer, and the backside source / drain contacts are electrically connected to the backside interconnect layer. The structure further includes a MOL dielectric layer between the device layer and the BEOL interconnect layer, and the frontside source / drain contacts extend through the MOL dielectric layer. The structure further includes a backside dielectric layer between the device layer and the backside interconnect layer, and the backside source / drain contacts extend through the backside dielectric layer. Preferably, the channel region of each field effect transistor includes a stack of nanosheet semiconductor layers. The structure further includes a gate stack between the nanosheet semiconductor layers of each field effect transistor; and a lower dielectric isolation layer, the lower dielectric isolation layer adjacent to the gate stack, a lower end of each second source / drain region, and an upper surface of each backside source / drain contact. The structure may further include a carrier wafer bonded to the upper surface of the BEOL interconnect layer.

Claims

1. 1. A monolithic semiconductor structure comprising: a device layer having a front side and a back side, the device layer having an interlevel dielectric layer; a field effect transistor in the interlevel dielectric layer, the field effect transistor having a channel region and first and second source / drain regions extending laterally from the channel region, each of the first and second source / drain regions including an upper surface, a lower surface, and a sidewall surface extending between the upper surface and the lower surface; a first metal source / drain sidewall contact directly contacting the sidewall surface of the first source / drain region, the first metal source / drain sidewall contact having a top edge and a bottom edge; a second metal source / drain sidewall contact directly contacting the sidewall surface of the second source / drain region, the second metal source / drain sidewall contact having a top end and a bottom end; a backside source / drain contact comprising metal and directly contacting the lower surface of the first source / drain region and the lower edge of the first metal source / drain sidewall contact; and a front-side source / drain contact comprising metal and directly contacting the top surface of the second source / drain region and the top edge of the second metal source / drain sidewall contact; 1. A monolithic semiconductor structure comprising:

2. a BEOL interconnect layer on the front side of the device layer, the front side source / drain contacts being electrically connected to the BEOL interconnect layer; and a backside interconnect layer on the backside of the device layer, the backside source / drain contacts being electrically connected to the backside interconnect layer; 10. The monolithic semiconductor structure of claim 1 further comprising:

3. 3. The monolithic semiconductor structure of claim 2 further comprising a lower dielectric isolation layer adjacent said lower end of said second source / drain region and adjacent an upper surface of said backside source / drain contact.

4. a MOL dielectric layer between the device layer and the BEOL interconnect layer, the front-side source / drain contacts extending through the MOL dielectric layer; and a backside dielectric layer between the device layer and the backside interconnect layer, the backside source / drain contacts extending through the backside dielectric layer; 3. The monolithic semiconductor structure of claim 2 further comprising:

5. 5. The monolithic semiconductor structure of claim 4 wherein said channel region comprises a stack of nanosheet semiconductor layers.

6. a gate stack between the nanosheet semiconductor layers; and a lower dielectric isolation layer adjacent the gate stack, the lower edge of the second source / drain region, and an upper surface of the backside source / drain contact; 6. The monolithic semiconductor structure of claim 5 further comprising:

7. 6. The monolithic semiconductor structure of claim 5 further comprising a carrier wafer bonded to a top surface of said BEOL interconnect layer.

8. 6. The monolithic semiconductor structure of claim 5, wherein said first metal source / drain sidewall contact and said second metal source / drain sidewall contact comprise a metal suicide layer.

9. 1. A method for fabricating a monolithic semiconductor structure including a backside contact and a frontside contact, comprising: obtaining a device layer having a front side and a back side, wherein the device layer comprises: an interlevel dielectric layer; and a field effect transistor in the interlevel dielectric layer, the field effect transistor having a channel region and first and second source / drain regions extending laterally from the channel region, each of the first and second source / drain regions including an upper surface, a lower surface, and a sidewall surface extending between the upper surface and the lower surface; Includes; forming a first metal source / drain sidewall contact directly on the sidewall surface of the first source / drain region and a second metal source / drain sidewall contact directly on the sidewall surface of the second source / drain region, wherein the first metal source / drain sidewall contact and the second metal source / drain sidewall contact each have an upper end and a lower end; forming front-side source / drain contacts comprising metal directly on the top surfaces of the second source / drain regions and the top edges of the second metal source / drain sidewall contacts; and forming backside source / drain contacts comprising a metal directly on the lower surface of the first source / drain region and the lower end of the first metal source / drain sidewall contact; A method comprising:

10. the monolithic semiconductor structure further includes a substrate on the backside of the device layer and a sacrificial placeholder extending into the substrate, the sacrificial placeholder directly beneath the first source / drain region; The method further comprises: removing the substrate; forming a backside interlayer dielectric layer on the backside of the device layer; and removing the sacrificial placeholder to form a cavity in the backside interlayer dielectric layer to expose the lower surface of the first source / drain region; Including, forming the backside source / drain contacts further comprises filling the cavities with a contact metal; 10. The method of claim 9.

11. 11. The method of claim 10, wherein the device layer further comprises a lower dielectric isolation layer extending beneath the second source / drain region, and wherein the backside interlayer dielectric layer is formed partially over the lower dielectric isolation layer.

12. forming a BEOL interconnect layer over the device layer; bonding a carrier wafer to the BEOL interconnect layer; and forming a backside interconnect layer over the backside interlayer dielectric layer; The method of claim 10 further comprising:

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