Method for forming semiconductor devices using a metal hard mask

Abstract

A method for forming a semiconductor device is disclosed. The method includes forming a first metal layer on an amorphous mask layer disposed over a substrate. The method includes forming a second metal layer extending along vertical sidewalls of an opening in the amorphous mask layer. The method includes forming a first recess partially extending into the substrate using the first metal layer and the second metal layer as a first etching mask. The method includes forming a third metal layer extending along the vertical sidewalls of the first recess. The method includes forming a second recess below the first recess using the first, second, and third metal layers as a second etching mask.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Non-Provisional Patent Application No. 17 / 901,727, filed September 1, 2022, and entitled "METHODS FOR FORMING SEMICONDUCTOR DEVICES USING METAL HARDMASKS," the entire disclosure of which is incorporated herein by reference for all purposes.

[0002] The present disclosure relates generally to hard masks for semiconductor processing, and more particularly to metal hard masks for fabricating high aspect ratio geometries. [Background technology]

[0003] Semiconductor circuits continue to shrink to smaller and smaller areas. To increase the number of transistors and other semiconductor devices per unit area, manufacturers are now utilizing another dimension, i.e., the vertical third dimension (3D). For example, in 3D NAND memory arrays, charge-trapping flash transistors are stacked vertically on the sidewalls of high-aspect-ratio openings. In DRAM memory arrays, high-aspect-ratio DRAM trench capacitor openings are etched deeper and deeper into the semiconductor substrate to increase capacitance. Through-silicon vias (TSVs) for stacking integrated circuit chips are fabricated by etching high-aspect-ratio holes completely through the substrate.

[0004] Etch masks used to etch high aspect ratio openings such as trenches and holes require high mask-to-substrate etch selectivity to maintain pattern integrity throughout the extended high aspect ratio opening etch. Because photoresist etch selectivity can be poor, the photoresist pattern is etched into a hard mask, and the hard mask pattern is used as the etch mask when etching the high aspect ratio features. Summary of the Invention [Means for solving the problem]

[0005] At least one aspect of the present disclosure is directed to a method for forming a semiconductor device. The method includes forming a first metal layer on an amorphous mask layer disposed over a substrate. The method includes forming a second metal layer extending along vertical sidewalls of an opening in the amorphous mask layer. The method includes forming a first recess partially extending into the substrate using the first metal layer and the second metal layer as a first etching mask. The method includes forming a third metal layer extending along the vertical sidewalls of the first recess. The method includes forming a second recess below the first recess using the first, second, and third metal layers as a second etching mask.

[0006] The first to third metal layers may each include a refractory metal.

[0007] The second and third metal layers may each comprise a metallic material selected from the group consisting of tungsten, titanium, tantalum, molybdenum, chromium, hafnium, ruthenium, and combinations thereof, hi one implementation, the second and third metal layers each comprise titanium and tungsten.

[0008] The first to third metal layers may each contain tungsten or tungsten nitride.

[0009] In some implementations, the first to third metal layers may be made of the same metal material.

[0010] The amorphous mask layer may include amorphous carbon or amorphous silicon.

[0011] According to the present technology, the first recess has a first aspect ratio of its depth to its width, and the second recess has a second aspect ratio of its depth to its width, the second aspect ratio being substantially greater than the first aspect ratio.

[0012] The substrate may consist of a single dielectric layer comprising silicon oxide.

[0013] Additionally or alternatively, the substrate may be comprised of a plurality of alternating first and second dielectric layers, each of the first dielectric layers comprising silicon dioxide and each of the second dielectric layers comprising silicon nitride or silicon oxynitride.

[0014] The method further includes filling the first recess and the second recess with a semiconductor material or a metallic material.

[0015] At least another aspect of the present disclosure is directed to a method for forming a semiconductor device. The method includes forming a low-stress mask layer over a substrate. The method includes forming a first metal layer over the low-stress mask layer, the first metal layer comprising a first metal. The method includes forming an opening in the first metal layer and the low-stress mask layer. The method includes forming a first portion of a metal spacer comprising a second metal along a sidewall of the opening. The method includes etching the substrate using the first metal layer and the first portion of the metal spacer as a first etch mask to form a first recess. The method includes forming a second portion of a metal spacer comprising a third metal along a sidewall of the first recess. The method includes etching the substrate again using both the first metal layer and the first and second portions of the metal spacer as a second etch mask to form a second recess below the first recess.

[0016] The method further includes depositing a second metal layer and etching the horizontally extending portion of the second metal layer to form a first portion of a metal spacer.

[0017] The method further includes depositing a third metal layer and etching the horizontally extending portion of the third metal layer to form a second portion of the metal spacer.

[0018] In some implementations, each of the first, second, and third metals comprises a refractory metal.

[0019] The method further includes filling the first recess and the second recess with a semiconductor material or a metallic material. The method further includes forming features of a three-dimensional (3D) memory cell based on the semiconductor material or the metallic material filling the first recess and the second recess.

[0020] The first recess has a first aspect ratio of its depth to its width, and the second recess has a second aspect ratio of its depth to its width, the second aspect ratio being substantially greater than the first aspect ratio.

[0021] Yet another aspect of the present disclosure is directed to an apparatus for forming a semiconductor device, the apparatus including: a first chamber configured to accommodate a substrate having a mask layer thereon and to deposit a first metal layer on the mask layer, a second chamber configured to form an opening through the first metal layer and the mask layer, a third chamber configured to deposit a second metal layer extending along vertical sidewalls of the opening, a fourth chamber configured to etch a horizontal portion of the second metal layer, a fifth chamber configured to form a first recess extending into the substrate based on at least a remaining vertical portion of the second metal layer, a sixth chamber configured to deposit a third metal layer extending along the vertical sidewall of the first recess, a seventh chamber configured to etch the horizontal portion of the third metal layer, and an eighth chamber configured to form a second recess further extending into the substrate based on at least a remaining vertical portion of the third metal layer.

[0022] The first chamber, the third chamber, and the sixth chamber may be the same chamber.

[0023] These and other aspects and implementations are described in detail below. The foregoing information and the following detailed description, including illustrative examples of various aspects and implementations, provide an overview or framework for understanding the nature and characteristics of the claimed aspects and implementations. The drawings illustrate various aspects and implementations to provide a further understanding and are incorporated into and constitute a part of this specification. It will be readily understood that multiple aspects can be combined, and that features described in the context of one aspect of the invention can be combined with any number of other aspects. Multiple aspects can be implemented in any convenient manner. As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

[0024] Non-limiting embodiments of the present disclosure will now be described, by way of example, with reference to the accompanying drawings, which are schematic and are not intended to be drawn to scale. Unless otherwise indicated as representing background art, the drawings represent aspects of the present disclosure. For clarity, not every component is necessarily labeled in every drawing. [Brief explanation of the drawings]

[0025] [Figure 1] 1 illustrates a flowchart of a method for forming a semiconductor device using a metal shell hard mask, according to various embodiments. [Figure 2] 2A-2D illustrate cross-sectional views of a semiconductor device fabricated by the method shown in FIG. 1 at various stages of fabrication, according to various embodiments. [Figure 3] 2A-2D illustrate cross-sectional views of a semiconductor device fabricated by the method shown in FIG. 1 at various stages of fabrication, according to various embodiments. [Figure 4] 2A-2D illustrate cross-sectional views of a semiconductor device fabricated by the method shown in FIG. 1 at various stages of fabrication, according to various embodiments. [Figure 5] 2A-2D illustrate cross-sectional views of a semiconductor device fabricated by the method shown in FIG. 1 at various stages of fabrication, according to various embodiments. [Figure 6]2A-2D illustrate cross-sectional views of a semiconductor device fabricated by the method shown in FIG. 1 at various stages of fabrication, according to various embodiments. [Figure 7] 2A-2D illustrate cross-sectional views of a semiconductor device fabricated by the method shown in FIG. 1 at various stages of fabrication, according to various embodiments. [Figure 8] 2A-2D illustrate cross-sectional views of a semiconductor device fabricated by the method shown in FIG. 1 at various stages of fabrication, according to various embodiments. [Figure 9] 2A-2D illustrate cross-sectional views of a semiconductor device fabricated by the method shown in FIG. 1 at various stages of fabrication, according to various embodiments. [Figure 10] 2A-2D illustrate cross-sectional views of a semiconductor device fabricated by the method shown in FIG. 1 at various stages of fabrication, according to various embodiments. [Figure 11] 2A-2D illustrate cross-sectional views of a semiconductor device fabricated by the method shown in FIG. 1 at various stages of fabrication, according to various embodiments. [Figure 12] 2A-2D illustrate cross-sectional views of a semiconductor device fabricated by the method shown in FIG. 1 at various stages of fabrication, according to various embodiments. [Figure 13] 2A-2D illustrate cross-sectional views of a semiconductor device fabricated by the method shown in FIG. 1 at various stages of fabrication, according to various embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0026] Reference will now be made to the exemplary embodiments illustrated in the drawings, and specific language will be used to describe the embodiments herein. It will be understood, however, that no limitation on the scope of the claims or the present disclosure is intended in any way. Alterations and further modifications to the inventive features illustrated herein, and further applications of the principles of the subject matter illustrated herein that may occur to one skilled in the art in possession of this disclosure, are intended to be within the scope of the subject matter disclosed herein. Other embodiments may be used and / or other changes may be made without departing from the spirit or scope of the disclosure. The exemplary embodiments described in the detailed description do not limit the presented subject matter.

[0027] Hard masks utilized for etching high-aspect ratio trenches and holes can be relatively thick to allow only vertically oriented atoms and ions from the etching gas to impact the surface of the substrate. Hard masks made of metals such as tungsten (W), titanium tungsten (TiW), or titanium nitride (TiN) can provide the necessary selectivity, but stress from the thick metal layer can be excessive. Hard masks fabricated from thick, low-stress materials such as amorphous carbon and amorphous silicon can provide acceptable stress, but offer lower selectivity when etching deep, high-aspect ratio trenches and holes. Lower selectivity requires the deposition of very thick layers of amorphous material, which may still not be sufficient to protect the underlying material.

[0028] Gas mixtures such as Ar and O2 along with fluorinated hydrocarbons such as CF8, CF6, and CF8 are commonly used to etch high-aspect ratio features in dielectrics such as silicon dioxide. Fluorinated hydrocarbons such as CHF3, CH3F, and CH2F2 are commonly used to etch high-aspect ratio features in dielectrics such as silicon nitride (SiN). Features such as openings with a depth-to-width ratio greater than 20 are generally considered high-aspect ratio features. Because the selectivity of hard masks to the substrate is low, higher carbon-containing fluorocarbons can be added to the etching chemistry to improve the selectivity between the mask material, e.g., the amorphous hard mask, and the material being etched. Fluorocarbon gases with high carbon content increase hard mask selectivity by increasing polymer deposition on the surface of the amorphous hard mask. Unfortunately, during etching of high-aspect ratio features, polymer can deposit on the sidewalls of these high-aspect ratio features, causing the sidewalls to taper, resulting in a smaller size and distortion of the bottom of the feature. For example, the critical dimension (CD) of the bottom of the formed opening may be much smaller than the CD of the top of the opening.

[0029] The present disclosure provides various embodiments of methods for geometrically shaping (e.g., etching) high-aspect ratio features using a metal shell hard mask. In various embodiments, the metal shell hard mask does not induce significant stress and can provide high selectivity of the hard mask to the substrate using low-polymer-forming fluorocarbon gases. A metal shell hard mask as disclosed herein is formed by first covering the surface of a low-stress mask material with a first thin metal shell. A first recess can be formed in an underlying dielectric layer based on the first thin metal shell (forming a first portion of a metal spacer). The disclosed metal shell hard mask can then be formed by forming a second portion of the metal spacer. The first and second portions of the metal spacer can be used together to form a second recess having a high aspect ratio (its depth to width) in the dielectric layer below the first recess.

[0030] FIG. 1 shows a flowchart of an exemplary method 100 for forming a metal shell hard mask and fabricating a semiconductor device, according to various embodiments. FIGS. 2-13 are cross-sectional views of such a semiconductor device 200, illustrating some of the key operations described in the method 100 of FIG. 1. For example, features (e.g., openings) having a high aspect ratio are formed (e.g., etched) in one or more dielectric layers disposed over a semiconductor substrate. Such high aspect ratio openings can be rectangular, square, circular (in the case of contacts), or any other regular or irregular shape. In various embodiments, the high aspect ratio openings can be trenches or holes.

[0031] 1 and the cross-sectional view of FIG. 2, several metal shell hard mask layers 202 are deposited on a substrate 200. The substrate 200 may include a semiconductor substrate 206 having an overlying dielectric layer 208. While the dielectric layer 208 is shown as a single layer, it should be understood that the dielectric layer 208 may include multiple layers stacked on top of each other.

[0032] In various embodiments, the semiconductor substrate 206 may be a single crystal semiconductor substrate, such as a single crystal silicon wafer or a silicon-on-insulator substrate. As described above, in some embodiments, the dielectric layer 208 may be a single dielectric layer comprising silicon oxide. In other embodiments, the dielectric layer 208 may include multiple alternating first and second dielectric layers, each comprising silicon dioxide and each comprising silicon nitride or silicon oxynitride. In such embodiments, the nitride-based second dielectric layer may be later replaced with a metal layer, while the oxide-based first dielectric layer may serve as a separation layer between the metal layers.

[0033] In various embodiments, the metal shell hard mask layer 202 includes an amorphous mask layer 210, such as amorphous carbon or amorphous silicon, covered with a thin first metal shell layer 212. The amorphous mask layer 210 can be deposited using a spin-on process and can include, for example, spin-on carbon. In various embodiments, the amorphous mask layer 210 can be formed as a low-stress mask material having a relatively low intrinsic stress due to relaxation of the amorphous material. For example, the intrinsic stress of the low-stress mask material, as measured in wafer bow experiments, can be less than ±20 MPa, preferably close to zero. The first metal shell layer 212 can include refractory metals such as tungsten, molybdenum, niobium, tantalum, titanium, chromium, hafnium, ruthenium, and zirconium, including oxides, nitrides, and oxynitrides of the refractory metals. In one embodiment, the first metal shell layer 212 may include tungsten (W), tungsten nitride (WN), titanium tungsten (TiW), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum, and carbides such as tungsten carbide. In various embodiments, the first metal shell layer 212 may be deposited using various thin film deposition techniques, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and other techniques, such as sputtering, evaporation, etc.

[0034] The thickness of the amorphous mask layer 210 is generally determined based on the depth of the high aspect ratio opening, e.g., trench or hole, to be etched in the dielectric layer 208. The thickness of the first metal shell layer 212 can range from approximately 2 nanometers (nm) to 500 nm or more. In general, the thickness of the first metal shell layer 212 can depend on the stress of the amorphous mask layer 210 and the dimensions of the opening to be formed.

[0035] 1 and the cross-sectional view of FIG. 3, a metal etch hard mask layer 214 is deposited on the first metal shell layer 212. The metal etch hard mask layer 214 is a hard mask layer that is primarily used as an etch mask during etching of the first metal shell layer 212. The metal etch hard mask layer 214 may be a dielectric layer such as SiO, SiON, or SiN, and may be deposited by known deposition techniques, including deposition techniques such as physical vapor deposition, chemical vapor deposition, plasma-enhanced vapor deposition, and atomic layer deposition.

[0036] 1 and the cross-sectional view of FIG. 4, a photomask layer 204 is deposited on the metal etch hard mask layer 214. The photomask layer 204 may be a three-layer photomask (shown in the example of FIG. 4) having a bottom organic layer (ODL) 216, a middle anti-reflective coat layer 218, and a top photoresist layer 220. However, it should be understood that the photomask layer 204 may include any suitable single layer or any number of stacked layers while remaining within the scope of the present disclosure. Upon forming the top layer of the photomask layer 204 (e.g., photoresist layer 220), an opening 222 is formed in the photoresist layer 220 using suitable photolithography techniques.

[0037] 1 and the cross-sectional view of FIG. 5, an opening 222 is etched through the anti-reflective coat layer 218, through the bottom organic layer 216, and through the metal etch hard mask layer 214. In some embodiments, the opening 222 may stop on the first metal shell layer 212. The opening 222 may be etched using any suitable anisotropic etching process, such as reactive ion etching.

[0038] 1 and the cross-sectional view of FIG. 6, after transferring the pattern to the metal etch hard mask layer 214 (e.g., by extending the openings 222 in operation 108), the photomask layer 204 may be removed from the metal etch hard mask layer 214. Then, as shown in FIG. 6, an anisotropic etching process using the metal etch hard mask layer 214 as an etch mask may extend the openings 222 further through the metal shell hard mask layer 202, including the first metal shell layer 212 and the amorphous mask layer 210. In some embodiments, the openings 222 may stop on the dielectric layer 208.

[0039] 1 and the cross-sectional view of FIG. 7, once the pattern is transferred to the metal shell hard mask layer 202 (e.g., by extending the openings 222 in operation 110), the metal etch hard mask layer 214 may be removed using either a dry plasma etch or a wet etch. In some embodiments, a wet etch with high selectivity may be used to remove the metal etch hard mask layer 214 relative to the dielectric layer 208. For example, if the dielectric layer 208 is SiO2 and the metal etch hard mask layer 214 is SiN, hot phosphoric acid may be used to remove the SiN with little or no damage to the underlying SiO2 layer.

[0040] Next, referring to operation 114 of FIG. 1 and the cross-sectional view of FIG. 8 , a second metal shell layer 230 is conformally deposited on the horizontal and vertical surfaces of the metal shell hard mask layer 202. The second metal shell layer 230 may include a refractory metal such as tungsten, molybdenum, niobium, tantalum, titanium, chromium, hafnium, ruthenium, and zirconium. In one embodiment, the second metal shell layer 230 may be a material such as tungsten (W), tungsten nitride (WN), titanium tungsten (TiW), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), molybdenum, and a carbide such as tungsten carbide. In various embodiments, the second metal shell layer 230 may be deposited using various thin film deposition techniques, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and other techniques, such as sputtering, evaporation, etc. The thickness of the second metal shell layer 230 may be about 2 nm or more, for example, in one embodiment, between 1 nm and 10 nm.

[0041] Next, referring to operation 116 of FIG. 1 and the cross-sectional view of FIG. 9 , the second metal shell layer 230 is removed from the horizontal surfaces by anisotropic etching to form first portions of metal spacers 232 in the openings 222. Specifically, the second metal shell layer 230 is removed from the top surface of the substrate 200 to expose the dielectric layer 208, and from the top surface of the first metal shell layer 212 to expose its top surface. In anisotropic etching, a bias is applied to accelerate ions in the etching gas plasma toward the substrate. Due to the vertical trajectories of the ions, the horizontal surfaces are etched much faster than the vertical surfaces.

[0042] In various embodiments, the second metal shell layer 230 can be the same material as the first metal shell layer 212. Using the same metal shell material for the first metal shell layer 212 and the second metal shell layer 230 can advantageously lower production costs by using the same metal deposition tool, thereby reducing both cycle time and capital costs. In these embodiments, the anisotropic etching process must be carefully controlled to prevent complete removal of the first metal shell layer 212 from horizontal surfaces. In other embodiments, the materials for the first metal shell layer 212 and the second metal shell layer 230 can be different. These embodiments may increase equipment costs by requiring the deposition of two different metals, but provide relaxed process control. The first metal shell layer 212 can be selected to have high selectivity so that it is not removed during the etching of the second metal shell layer 230, significantly expanding the anisotropic etch process window. This can ensure that no portion of the dielectric layer 208 is covered by any remaining second metal shell layer 230.

[0043] Next, referring to operation 118 of FIG. 1 and the cross-sectional view of FIG. 10 , when forming the first portion of the metal spacer 232, a first recess 238 extending partially into the dielectric layer 208 may be formed based on the amorphous mask layer 210, the first metal shell layer 212, and the metal shell hard mask layer 202, including the first portion of the metal spacer 232. For example, using the metal shell hard mask layer 202 as an etching mask, an anisotropic etch removes the upper portion of the dielectric layer 208 through the opening 222, thereby forming the first recess 238 below the opening 222. In anisotropic etching, a bias is applied to accelerate ions in the etching gas plasma toward the substrate. Due to the vertical trajectory of the ions, horizontal surfaces are etched much faster than vertical surfaces. As a non-limiting example, the first recess 238 may have a depth D1 ranging from about 1 μm to about 2 μm.

[0044] Next, referring to operation 120 of FIG. 1 and the cross-sectional view of FIG. 11 , a third metal shell layer 240 is conformally deposited on the workpiece, for example, on the horizontal and vertical surfaces of the metal shell hard mask layer 202, as well as on the sidewalls and bottom of the first recess 238. The third metal shell layer 240 and the second metal shell layer 230 may have the same metal material. The third metal shell layer 240 may include a refractory metal such as tungsten, molybdenum, niobium, tantalum, titanium, chromium, hafnium, ruthenium, and zirconium. In one embodiment, the third metal shell layer 240 may be a material such as tungsten (W), tungsten nitride (WN), titanium tungsten nitride (TiW), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), molybdenum, and a carbide such as tungsten carbide. In various embodiments, the third metal shell layer 240 can be deposited using a variety of thin film deposition techniques, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, as well as other techniques such as sputtering, evaporation, etc. The thickness of the third metal shell layer 240 can be about 2 nm or greater, for example, in one embodiment, between 1 nm and 10 nm.

[0045] Next, referring to operation 122 of FIG. 1 and the cross-sectional view of FIG. 12 , the third metal shell layer 240 is removed from the horizontal surfaces by anisotropic etching, forming second portions of the metal spacers 242 in the openings 222 and the first recesses 238. Specifically, as shown in FIG. 12 , the third metal shell layer 240 is removed from the horizontal surfaces of the first recesses 238, re-exposing the dielectric layer 208. In other words, the second portions of the metal spacers 242 may be formed to extend at least along the sidewalls of the first recesses 238. In anisotropic etching, a bias is applied to accelerate ions in the etching gas plasma toward the substrate. Due to the vertical trajectories of the ions, the horizontal surfaces are etched much faster than the vertical surfaces.

[0046] In some embodiments, forming the second portion of the metal spacer 242 completes the fabrication of the metal shell hard mask 250. Such a metal shell hard mask 250 includes an amorphous mask layer 210, a first metal shell layer 212, a first portion of the metal spacer 232, and a second portion of the metal spacer 242. As shown, the first portion of the metal spacer 232 may extend along the sidewalls of both the amorphous mask layer 210 and the first metal shell layer 212, and the second portion of the metal spacer 242 may extend along the (inner) sidewall of the first portion of the metal spacer 232 and further along the sidewall of the first recess 238. The amorphous mask layer 210 enables the formation of a thick hard mask with low stress. The thin first metal shell layer 212 and metal spacers 232 and 242 provide high selectivity with little additional stress. The steps described for forming the metal shell hard mask 250 are for illustrative purposes and not limiting. Those skilled in the art can use different but similar processes to fabricate the metal shell hard mask 250 of the embodiment.

[0047] Referring now to operation 124 of FIG. 1 and the cross-sectional view of FIG. 13 , metal shell hard mask 250 is used as an etch mask to etch high-aspect ratio second recesses 258 that extend through dielectric layer 208 and stop on semiconductor substrate 206. Such high-aspect ratio recesses can be rectangular, square, circular (in the case of contacts), or any other regular or irregular shape, and in various embodiments, can be formed like trenches or holes. As a non-limiting example, second recesses 258 can have a depth D2 that is substantially larger than the depth (D1) of first recesses 238, e.g., in the range of about 5 μm to about 100 μm. Thus, second recesses 258 can have a substantially larger aspect ratio (depth to width) than first recesses 238, given that the first and second recesses can share a substantially similar width.

[0048] In some embodiments, operations 120-124 may be performed repeatedly until a desired depth and / or shape is reached. For example, after forming second recess 258, a fourth metal shell layer may be formed (operation 120), followed by etching a horizontal portion of the fourth metal shell layer (operation 122). A third recess may then be formed (operation 124) to further extend second recess 258.

[0049] In various embodiments, operations 102, 108, 114, 116, 118, 120, 122, and 124 may be performed in first, second, third, fourth, fifth, sixth, seventh, and eighth chambers, respectively. Each of the first through eighth chambers may house a workpiece (e.g., a semiconductor device 200 formed at any of the above-described manufacturing stages) in a particular environment (e.g., a particular pressure, a particular temperature, a particular gas flow rate, etc.), thereby enabling a particular process to be performed on the semiconductor device 200. For example, the first, third, and sixth chambers may each be configured to perform a deposition process (e.g., atomic layer deposition, chemical vapor deposition, physical vapor deposition, metalorganic chemical vapor deposition, molecular beam epitaxy, electron beam physical vapor deposition, etc.), and the second, fourth, fifth, seventh, and eighth chambers may each be configured to perform an etching process (e.g., a plasma etch, a wet etch, an anisotropic wet etch, etc.). Additionally, in some embodiments, the first, third, and sixth chambers may be the same chamber, and the second, fourth, fifth, seventh, and eighth chambers may be the same chamber.

[0050] Advantageously, because the etching process does not significantly remove the metal shell hard mask 250, specifically the first metal shell layer 212, it is not necessary to increase the thickness of the amorphous mask layer to compensate for mask erosion during etching. Furthermore, the metal spacers 232 and 242 on the sidewalls of the mask prevent lateral erosion during long etching times, which can result in bowing of the sidewalls of the etched high-aspect ratio openings. With a metal shell hard mask (e.g., 250), the depth of the etched high-aspect ratio features is not limited by the mask. For example, high-aspect ratio features (e.g., 258) can be etched deeper and with greater fidelity using a metal shell hard mask than using an amorphous material hard mask. In one or more embodiments, the depth (D1 and D2) etched into the dielectric layer 208, i.e., the depth of the high-aspect ratio feature, can be between 2 and 100 times the combined thickness of the amorphous mask layer 210 and the first metal shell layer 212.

[0051] After forming such high aspect ratio features (e.g., 238 and 258, hereafter "feature 260") in dielectric layer 208, in various embodiments, a semiconductor or metallic material may be deposited to partially or completely fill feature 260 (along with opening 222). In one example, the semiconductor material may be selected from the group consisting of silicon, silicon germanium, a conductive oxide material, a two-dimensional (2D) semiconductor material, and combinations thereof, and may form channels for each of several vertically spaced-apart memory cells of a three-dimensional (3D) memory array. In another example, the metallic material may be selected from the group consisting of copper, aluminum, tungsten, gold, and combinations thereof, and may form control lines (e.g., word lines, source lines, bit lines) shared by several vertically spaced-apart memory cells of a three-dimensional (3D) memory array.

[0052] After filling the features 260 with an appropriate material, a substantial portion of the metal shell hard mask 250 may be removed by a polishing process (e.g., a chemical-mechanical polishing (CMP) process) and / or one or more (e.g., dry and / or wet) etching processes. For example, the polishing process may remove the amorphous mask layer 210 and the first metal shell layer 212 (along with respective portions of other components above the top surface of the dielectric layer 208). Thus, a lower portion of the second portion of the metal spacer 242 (disposed below the top surface of the dielectric layer 208) may remain. In another example, the polishing process may remove the amorphous mask layer 210 and the first metal shell layer 212 (along with the first and second portions of the metal spacers 242 and 242) until a lower portion of the second portion of the metal spacer 232 extending into the dielectric layer 208 is also removed. In yet another example, the first metal shell layer 212 may be removed by a wet etching process, and the amorphous mask layer 210 may be removed by a dry etching process using oxygen plasma.

[0053] In the preceding description, specific details have been set forth, such as the particular geometry of the processing system and descriptions of the various components and processes used therein. However, it should be understood that the techniques described herein may be practiced in other embodiments that deviate from these specific details, and that such details are for purposes of explanation and not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numerical values, materials, and configurations have been set forth to provide a thorough understanding. However, embodiments may be practiced without such specific details. Components having substantially the same functional structure are designated by similar reference numerals, and redundant description may be omitted.

[0054] To facilitate understanding of various embodiments, various techniques have been described as multiple discrete operations. The order of description should not be construed as to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The described operations may also be performed in a different order than in the described embodiments. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0055] As used herein, "substrate" or "target substrate" generally refers to an object to be processed in accordance with the present invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may include, for example, a base substrate structure such as a semiconductor wafer or a reticle, or a layer on or superimposed on a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or not, but is intended to include such layers or base structures, as well as any combination of layers and / or base structures. While this specification may refer to particular types of substrates, this is for illustrative purposes only.

[0056] Those skilled in the art will also appreciate that many variations in the operation of the above-described techniques are possible while still achieving the same objectives of the present invention. Such variations are intended to be within the scope of the present disclosure. Accordingly, the above description of embodiments of the present invention is not intended to be limiting. Rather, any limitations to embodiments of the present invention are set forth in the following claims.

Claims

1. 1. A method of forming a semiconductor device, comprising: forming a first metal layer on an amorphous mask layer disposed on a substrate; forming a second metal layer extending along vertical sidewalls of the opening in the amorphous mask layer; forming a first recess extending partially into the substrate using the first metal layer and the second metal layer as a first etch mask; forming a third metal layer extending along vertical sidewalls of the first recess; forming a second recess below the first recess using the first to third metal layers as a second etching mask; A method comprising:

2. The method of claim 1 , wherein the first through third metal layers each comprise a refractory metal.

3. 10. The method of claim 1, wherein the second and third metal layers each comprise a metallic material selected from the group consisting of tungsten, titanium, tantalum, molybdenum, chromium, hafnium, ruthenium, and combinations thereof.

4. 4. The method of claim 3, wherein the second and third metal layers each comprise titanium and tungsten.

5. 2. The method of claim 1, wherein the first, second, and third metal layers each comprise tungsten or tungsten nitride.

6. The method of claim 1 , wherein the first, second, third and third metal layers are composed of the same metal material.

7. The method of claim 1 , wherein the amorphous mask layer comprises amorphous carbon, spin-on carbon, or amorphous silicon.

8. moreover, forming a fourth metal layer extending along at least vertical sidewalls of the second recess; forming a third recess below the second recess using the first to fourth metal layers as a third etching mask; 2. The method of claim 1, comprising:

9. The method of claim 1 , wherein the substrate is comprised of a single dielectric layer comprising silicon oxide.

10. 10. The method of claim 1, wherein the substrate is comprised of a plurality of alternating first and second dielectric layers, each of the first dielectric layers comprising silicon dioxide and each of the second dielectric layers comprising silicon nitride or silicon oxynitride.

11. The method of claim 1 , further comprising filling the first recess and the second recess with a semiconductor material or a metallic material.

12. 1. A method of forming a semiconductor device, comprising: forming a mask layer over a substrate; forming a first metal layer comprising a first metal over the mask layer; forming an opening in the first metal layer and the mask layer; forming a first portion of a metal spacer comprising a second metal along a sidewall of the opening; etching the substrate using the first metal layer and the first portion of the metal spacer as a first etch mask to form a first recess; forming a second portion of the metal spacer comprising a third metal along a sidewall of the first recess; etching the substrate using both the first metal layer and the first and second portions of the metal spacer as a second etch mask to form a second recess below the first recess; A method comprising:

13. The step of forming the first portion of the metal spacer further comprises: depositing a second metal layer; etching the horizontally extending portions of the second metal layer to form the first portions of the metal spacers; 13. The method of claim 12, comprising:

14. The step of forming the second portion of the metal spacer further comprises: depositing a third metal layer; etching the horizontally extending portions of the third metal layer to form the second portions of the metal spacers; 13. The method of claim 12, comprising:

15. The method of claim 12 , wherein the first, second, third and third metals each comprise a refractory metal.

16. 13. The method of claim 12, further comprising filling the first recess and the second recess with a semiconductor material or a metallic material.

17. 17. The method of claim 16, further comprising forming a feature of a three-dimensional (3D) memory cell based on the semiconductor material or the metallic material filling the first recess and the second recess.

18. the first recess has a first aspect ratio of its depth to its width; the second recess has a second aspect ratio of its depth to its width; The method of claim 12 , wherein the second aspect ratio is substantially greater than the first aspect ratio.

19. a first chamber configured to accommodate a substrate covered by a mask layer and to perform deposition of a first metal layer on the mask layer; a second chamber configured to form an opening through the first metal layer and the mask layer; a third chamber configured to perform deposition of a second metal layer extending along the vertical sidewalls of the opening; a fourth chamber configured to etch horizontal portions of the second metal layer; a fifth chamber configured to form a first recess extending into the substrate based on at least a remaining vertical portion of the second metal layer; a sixth chamber configured to perform deposition of a third metal layer extending along vertical sidewalls of the first recess; a seventh chamber configured to etch horizontal portions of the third metal layer; an eighth chamber configured to form a second recess further extending into the substrate based on at least a remaining vertical portion of the third metal layer; An apparatus having:

20. 20. The apparatus of claim 19, wherein the first chamber, the third chamber, and the sixth chamber are the same chamber.

Images