Systems and methods for reducing die stress and improving surface adhesion - Patents.com

Abstract

Provided are a die, an integrated circuit (IC) device including two or more stacked dies, and a process for forming the die. The die includes a circuit, a passivation layer disposed over the circuit and including a top surface and a bottom surface, and a polyimide layer disposed on the top surface of the passivation layer. The top surface of the passivation layer includes portions of different heights that extend vertically away from the circuit. Opposite the top surface of the passivation layer, the top surface of the polyimide layer includes portions of different heights that extend vertically away from the circuit, such that the surface area of ​​the top surface of the polyimide layer is increased compared to a flat top surface.

Description

[Technical Field]

[0001] The present disclosure relates to dies in integrated circuit (IC) devices having two or more stacked dies, and more particularly to die improvements to reduce stress and improve surface adhesion in IC devices having two or more stacked dies. Summary of the Invention

[0002] In accordance with the present disclosure, a die suitable for a three-dimensional (3D) IC device is provided for correcting wafer bow and die-level warpage and / or improving die surface adhesion between stacked dies. The die includes a circuit, a top surface, and a bottom surface, and includes a passivation layer disposed on the circuit, and a polyimide layer disposed on the top surface of the passivation layer. The top surface of the passivation layer includes portions of different heights extending vertically away from the circuit.

[0003] In some embodiments, the top surface of the passivation layer may include a plurality of protrusions extending away from a base of the top surface.

[0004] In some embodiments, each of the plurality of protrusions may include individual sides, each of which is tapered to become thinner as the protrusion extends away from the base.

[0005] In some embodiments, the sides of some of the protrusions may each be tapered at an angle.

[0006] In some embodiments, the protrusions may include protrusions of different heights extending away from the base of the top surface.

[0007] In some embodiments, each of the plurality of protrusions may be one of a trapezoidal prism, a pyramidal shape, or a triangular prism.

[0008] In some embodiments, the arrangement and shape of the protrusions may be based on the silicon lattice orientation and circuit size in the die.

[0009] In some embodiments, the top surface of the polyimide layer opposite the top surface of the passivation layer may include portions of different individual heights that extend vertically away from the circuitry, increasing the surface area of ​​the top surface of the polyimide layer compared to a flat top surface.

[0010] In some embodiments, an IC device is provided. The IC device includes a substrate and a first die disposed on the substrate, the first die including a first circuit; a first passivation layer including a top surface and a bottom surface and disposed on the first circuit; and a first polyimide layer disposed on the top surface of the first passivation layer. Opposite the top surface of the passivation layer, the top surface of the polyimide layer includes portions of different heights extending away from the first passivation layer. The IC further includes a die attach film (DAF) disposed on the top surface of the first polyimide layer, and a second die including a second circuit; a second passivation layer including a top surface and a bottom surface and disposed on the second circuit; and a second polyimide layer disposed on the top surface of the second passivation layer. The second die is vertically stacked on top of the first die and attached to the first die by the DAF. The DAF bonds the top surface of the first polyimide layer to the bottom surface of the second circuit, opposite the second passivation layer.

[0011] In some embodiments, the IC device is a three-dimensional floating gate NAND memory.

[0012] In some embodiments, a method of disposing a passivation layer is provided, the method including disposing a passivation layer over a circuit layer, the passivation layer including a top surface and a bottom surface, and modifying a thickness of a portion of the passivation layer such that the top surface is non-planar.

[0013] In some embodiments, modifying the thickness of the portion may include etching away the thickness from the top surface of the passivation layer.

[0014] In some embodiments, the step of modifying the thickness of the portion may include applying a photolithographic process to an upper surface of the passivation layer to modify the thickness of the portion.

[0015] In some embodiments, the photolithography process may include using a reticle mask having portions that allow different individual percentages of leaky chrome to reach the top surface of the passivation layer, thereby varying the thickness of the passivation. [Brief explanation of the drawings]

[0016] The following description includes a description of figures illustrating exemplary implementations of embodiments of the present disclosure. These figures are to be understood as examples, not as limitations. References herein to one or more "embodiments" should be understood as describing particular features, structures, and / or characteristics present in at least one implementation. Thus, phrases such as "in one embodiment" or "in an alternative embodiment" appearing herein describe various embodiments and implementations, and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0017] [Figure 1] 1 shows a simplified side view of a 3D IC device.

[0018] [Figure 2] 1 illustrates an exemplary side view of an IC device according to some embodiments of the present disclosure.

[0019] [Figure 3A] 3 illustrates an exemplary sequence of steps in a process for fabricating the passivation layer of FIG. 2, for example, according to some embodiments of the present disclosure. [Figure 3B] 3 illustrates an exemplary sequence of steps in a process for fabricating the passivation layer of FIG. 2, for example, according to some embodiments of the present disclosure. [Figure 3C] 3 illustrates an exemplary sequence of steps in a process for fabricating the passivation layer of FIG. 2, for example, according to some embodiments of the present disclosure.

[0020] [Figure 4A] 3 illustrates an exemplary sequence of steps in a process for fabricating the polyimide layer of FIG. 2, for example, according to some embodiments of the present disclosure. [Figure 4B] 3 illustrates an exemplary sequence of steps in a process for fabricating the polyimide layer of FIG. 2, for example, according to some embodiments of the present disclosure.

[0021] [Figure 5] 1 illustrates an exemplary side view of a die according to some embodiments of the present disclosure.

[0022] [Figure 6] 1 illustrates an exemplary side view of another die, according to some embodiments of the present disclosure.

[0023] [Figure 7A] 1 illustrates an exemplary plan view of geometric elements on the top surface of a protective layer, according to some embodiments of the present disclosure. [Figure 7B] 1 illustrates an exemplary plan view of geometric elements on the top surface of a protective layer, according to some embodiments of the present disclosure. [Figure 7C]1 illustrates an exemplary plan view of geometric elements on the top surface of a protective layer, according to some embodiments of the present disclosure. [Figure 7D] 1 illustrates an exemplary plan view of geometric elements on the top surface of a protective layer, according to some embodiments of the present disclosure.

[0024] [Figure 8] 1 illustrates a flowchart of an exemplary process for manufacturing a die according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0025] To increase the chip density of an IC device (e.g., flash memory), multiple dies may be stacked vertically on a substrate (e.g., a 3D IC device). FIG. 1 shows a simplified side view of a 3D IC device 100. As shown, the IC device 100 includes multiple stacked dies 103a, 103b, 103n (collectively referred to as dies 103) stacked vertically (e.g., in the y-direction) on a substrate 101. Each of the dies 103 includes a circuit layer 102 housing one or more ICs, a passivation layer 104 disposed on the circuit layer 102, and a polyimide layer 106 disposed on the circuit layer. As shown, die 103a is bonded to substrate 101 by adhesive layer 108a (e.g., DAF), die 103b is bonded to polyimide layer 106 of die 103a by another adhesive layer 108b, and die 103n is bonded to polyimide layer 106 of IC die 103b by another adhesive layer 108c. In this manner, multiple dies 103 can be stacked vertically to increase the chip density of IC device 100 without substantially increasing the footprint of IC device 100.

[0026] In some approaches, to further increase the chip density of IC device 100, the wafer thickness (e.g., of circuit layer 102) may be reduced, allowing for an increase in the number of vertically stacked dies 103. However, as wafer thickness decreases and the number of vertically stacked dies 103 increases (e.g., with each new silicon (Si) produced), the likelihood of wafer-level bow and die-level warpage increases. This can result in microcracks in the passivation layer, reduced adhesion between stacked dies (e.g., delamination), and wafer cracks.

[0027] According to the present disclosure, a die for a 3D IC device is provided for correcting wafer bow and die-level warpage and / or for improving die surface adhesion between stacked dies.

[0028] The subject matter of the present disclosure may be better understood with reference to FIGS.

[0029] 2 illustrates an exemplary side view of an IC device 200 according to some embodiments of the present disclosure. In some embodiments, IC device 200 may be a solid-state storage memory including one or more packages of non-volatile memory dies. For example, IC device 200 may be a 3D NAND-based flash memory (e.g., using floating gate technology). However, this is merely one example, and IC device 200 may be any IC memory device (e.g., volatile memory) or non-memory device using ICs.

[0030] As shown, IC device 200 may include multiple dies 203 a, 203 b, 203 n (collectively referred to as dies 203) stacked vertically on substrate 201 (e.g., a mounting substrate). Although only three dies 203 are shown, it should be understood that any suitable number of dies 203 can be stacked vertically (e.g., in the y direction of the illustrated xy plane) on substrate 201. In one example, 16 dies 203 are stacked vertically on substrate 201. However, this is merely one example. The multiple stacked dies 203 may include more or less than 16 (e.g., 2, 4, 8, 32, 64, 128, etc.) stacked dies 203, and the number need not be an even number. In some embodiments, as shown, multiple dies 203 may be stacked with a lateral offset (e.g., in the x direction of the illustrated xy plane) to expose wire bond pad areas (220a, 220b, 220n) on each of the dies 203 for interconnection by wire bond connections (e.g., in a shingle-stacked or stair-stepped configuration). However, it should be understood that the dies 203 may be arranged in other vertical stacking configurations, in which case other suitable wire bonding configurations may be used. For example, the dies 203 may be flush edged (e.g., in this case, film-over-wire bonding may be used).

[0031] As shown, each of the dies 203 may include a circuit layer 202 housing one or more ICs (collectively referred to as circuits), a passivation layer 204 disposed on the circuit layer 202, and a polyimide layer 206 disposed on the passivation layer 204. It should be understood that the dies 203 may include other suitable layers, contact pads, and elements (not shown). For example, a metal layer (e.g., an aluminum layer) may be disposed between the circuit layer 202 and the passivation layer 204. However, these components, along with other well-known components, are not shown because these components are known to those skilled in the art. This is for ease of illustration and description and to avoid obscuring the present disclosure.

[0032] Substrate 201 may be a mounting substrate or a carrier substrate. As shown, substrate 201 includes a top surface 211 upon which multiple dies 203 may be stacked. Substrate 201 may include silicon, glass, epoxy, any other suitable material, or any combination thereof. In some embodiments, substrate 201 may include one or more conductive pads configured to connect to circuit layer 202 (e.g., via solder bumps).

[0033] The circuit layer 202 may include one or more ICs formed on a silicon (Si) wafer. In some embodiments, the thickness of the Si wafer may be less than or equal to 55 microns (μm). However, this is merely one example, and the thickness of the Si wafer may be any suitable thickness (e.g., greater than 55 μm). In some embodiments, the Si wafer may include 100-oriented or 110-oriented lattice Si (e.g., an arrangement of lattice structures in silicon). As shown, the circuit layer 202 includes a top surface 212a and a bottom surface 212b. Although a Si wafer is described, it should be understood that one or more ICs may be formed on other suitable wafer materials (e.g., gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC)). Furthermore, the circuitry formed on the wafer may include components that match the material of the wafer or may include components formed from different materials (e.g., GaAs components on a Si wafer).

[0034] The passivation layer 204 is disposed above the circuit layer 202 (e.g., in the y-direction) and can protect the circuit layer 202 from (e.g., electrical and / or mechanical) damage and contamination (e.g., a first protective layer). In some embodiments, the passivation layer 204 can be a hard-coat protective layer fabricated using a modified wafer (hard-coat) passivation process, as described in more detail below. While the passivation layer 204 is shown as a single layer, it should be understood that the passivation layer 204 can include multiple layers (e.g., according to a modified passivation process). In some embodiments, the passivation layer 204 includes a combination of at least one silicon dioxide (SiO2) layer and / or an oxynitride (ONON) layer.

[0035] As shown, passivation layer 204 includes a top surface 214a and a bottom surface 214b. In some embodiments, bottom surface 214b may be a planar surface disposed above and opposite top surface 212a of circuit layer 202, while top surface 214a may be a non-planar surface including portions of different individual heights (e.g., multiple protrusions) extending vertically (in the y-direction) away from circuit layer 202. As described in more detail below, the geometric elements of top surface 214a of passivation layer 204 may be configured to correct for wafer bow (of circuit layer 202) and die 203 warpage (e.g., die-level warpage) in IC device 200.

[0036] The polyimide layer 206 is disposed on the top surface 214a of the passivation layer 204. The polyimide layer 206 can be an insulating layer (e.g., a second protective layer) that further protects the die 203. In some embodiments, as described in more detail below, the polyimide layer 206 can be fabricated using a modified polyimide (soft coat) protective coating process. For example, the polyimide layer 206 can be fabricated using a modified polyimide reticle layout design to enable a defined photoexposure pattern to increase surface area and reduce wafer bow / die warpage, as described in more detail below. As shown, the polyimide layer 206 includes a top surface 216a and a bottom surface 216b. The bottom surface 216b of the polyimide layer 206 can conform to the geometric elements of the top surface 214a of the passivation layer 204 (e.g., as a result of being disposed on the top surface 214a of the passivation layer 204), and the top surface 216a of the polyimide layer 206 can be a non-planar surface including portions of different individual heights (e.g., multiple protrusions) that extend vertically (in the y-direction) away from the passivation layer 204. As described in more detail below, the added geometric elements of the top surface 216a of the polyimide layer 206 can improve die surface adhesion between stacked dies (e.g., compared to the flat top surface shown in FIG. 1 ) by increasing the surface area of ​​the top surface 216a of the polyimide layer 206 to which the adhesive layer 208b bonds.

[0037] As shown, the first die 203a may be bonded to the substrate 201 by an adhesive layer 208a, which bonds the bottom surface 212b of the circuit layer 202 of the first die 203a to the top surface 211 of the substrate 201. The second die 203b may be bonded to the top surface 216a of the polyimide layer 206 of the first die 203a by an adhesive layer 208b, which bonds the top surface 216a of the polyimide layer 206 of the first die 203a (by the bottom surface 218b of the adhesive layer 208b) to the bottom surface 212b of the circuit layer 202 of the second die 203b (by the top surface 218a of the adhesive layer 208b). Similarly, the third die 203 n may be bonded to the top surface 216 a of the polyimide layer 206 of the second die 203 b by an adhesive layer 208 c, which bonds the top surface 216 a of the polyimide layer 206 of the second die 203 b to the bottom surface 212 b of the circuit layer 202 of the third die 203 n. In some embodiments, each of the adhesive layers 208 a, 208 b, 208 c (collectively referred to as adhesive layers 208) may include a die attach film (DAF). In some embodiments, the DAF may include a thermosetting resin or a thermoplastic resin.

[0038] 3A-3C illustrate an exemplary sequence of steps in a process for fabricating, for example, passivation layer 204 of FIG. 2, according to some embodiments of the present disclosure. In some embodiments, the process is a modified wafer passivation process.

[0039] 3A illustrates a passivation layer 204 disposed on the circuit layer 202. In some embodiments, as illustrated, the passivation layer 204 (as disposed) may have a substantially flat upper surface. Additionally, while the passivation layer 204 is illustrated as a single layer, it should be understood that the passivation layer 204 may be comprised of multiple layers disposed on top of each other, as discussed above. For example, the passivation layer 204 may include at least one SiO2 layer and / or a combination of an ONON layer. However, these are merely examples, and the passivation layer 204 may include any suitable layers.

[0040] 3B illustrates a photolithography process applied to the top surface 214a of the passivation layer 204 of FIG. 3A. The photolithography process may include selectively leaking light (from the light source 302) around the chrome of the reticle 304 to allow a different percentage of light (the "leaky chrome") to reach the top surface 214a of the passivation layer 204, thereby varying the thickness of the passivation layer 204 (e.g., in a subsequent etching step). As will be described in more detail with reference to FIGS. 7A-7D, the reticle 304 may be configured with a pattern corresponding to the desired geometric elements of the top surface 214a of the passivation layer 204.

[0041] FIG. 3C illustrates the geometry of the top surface 214a of the passivation layer 204 immediately after the etching process via the photolithography process of FIG. 3B. As illustrated, the top surface 214a of the passivation layer 204 includes a plurality of protrusions 310 extending away from the base 312 (e.g., at a lower height). As illustrated, each individual side surface 314 of the protrusions 310 tapers to become thinner as the protrusion extends away from the base 312. In some embodiments, the angle of the taper of the side surfaces 314 may be varied between 30 and 45 degrees based on the geometry required to correct for wafer bow and die-level warpage. In some embodiments, the angle of the taper of the side surfaces 314 may be varied to other suitable angles.

[0042] In some embodiments, the wafer bow and die-level warpage may be determined experimentally (e.g., by measuring the wafer bow and die-level warpage of a die of an IC device (e.g., the IC device illustrated in FIG. 1 ). In some embodiments, the wafer bow and die-level warpage may be determined based on the design and configuration of the IC device. Based on the determined wafer bow and die-level warpage, the shape and thickness of passivation layer 204 may be modified to compensate for the determined wafer bow and die-level warpage. For example, the shape and thickness of passivation layer 204 may be modified to provide geometric elements (shape, pattern, features, feature spacing, etc.) that provide the strength and stability required for a desired application and to compensate for the determined wafer bow and die-level warpage. In the field of mechanical engineering, it is understood that various geometric elements produce desired results. Thus, the shape and thickness of passivation layer 204 may be modified according to mechanical engineering principles to compensate for the determined wafer bow and die-level warpage. For example, FIG. 5 shows a passivation layer 204 having geometric elements that provide the strength and stability required for another IC device.

[0043] Although each of the plurality of protrusions 310 is shown as a trapezoidal prism, it should be understood that the protrusions 310 may be formed with other geometric elements, such as pyramidal shapes, triangular prisms, spheres, or any other suitable geometric elements based on known principles of mechanical engineering. Furthermore, although the plurality of protrusions 310 are shown as being regularly spaced (e.g., along the x-direction), it should be understood that the protrusions 310 may be irregularly spaced and still provide the strength and stability required for a desired application. In some embodiments, the arrangement and shape of the protrusions 310 are based on the lattice orientation of the silicon (e.g., with respect to IC placement) within the circuit layer 202 and the size of the circuit layer 202. For example, the placement of the ICs on a die relative to the lattice orientation of the silicon (e.g., wafer) may affect the wafer bow and die-level warpage of stacked dies. Therefore, the arrangement and shape of the protrusions 310 may compensate for this wafer bow and die-level warpage.

[0044] 4A and 4B illustrate an exemplary sequence of steps in a process for fabricating, for example, polyimide layer 206 of FIG. 2, according to some embodiments of the present disclosure. In some embodiments, the process is a modified polyimide protective coating process.

[0045] 4A illustrates a polyimide layer 206 disposed on an upper surface 214a of a passivation layer 204 (e.g., of FIG. 3B). In some embodiments, as illustrated, the upper surface 216a of the polyimide layer 206 (as disposed) may be substantially flat. However, this is by way of example only, and the upper surface 216a of the polyimide layer 206 may retain some geometric features from the upper surface 214a of the passivation layer 204 as a result of being disposed on the upper surface 214a of the passivation layer 204.

[0046] FIG. 4B illustrates the resulting geometry of the top surface 216a of the polyimide layer 206 immediately after the modification process. In some embodiments, the modification process may be the photolithography (and etching) process described above with reference to FIG. 3B. In some embodiments, the modification process may be a pad etching process. As shown, the top surface 216a of the polyimide layer 206 includes a plurality of protrusions 410 extending away from a base 412 (e.g., at a lower height). As shown, each individual side 414 of the protrusions 410 tapers to become narrower as the protrusion extends away from the base 412. In some embodiments, the angle of taper of the side 414 may vary between 30 and 45 degrees. However, this is merely one example, and each individual side 414 of the protrusions 410 may not be tapered, as illustrated in FIG. 5. In some embodiments, the angle of taper of the side 414 may be varied to any other suitable angle. In some embodiments, the thickness of the polyimide layer 206 may vary between 1.7 μm and 3.5 μm, however, this is by way of example only and the thickness of the polyimide layer 206 may be any suitable thickness.

[0047] In some embodiments, the non-planar surface of top surface 216a of polyimide layer 206 increases the surface area of ​​top surface 216a of polyimide layer 206 (e.g., compared to a flat surface), thus potentially improving adhesion with adhesive layer 208 and, consequently, improving die surface adhesion between stacked dies 203 of FIG.

[0048] 5 illustrates an exemplary side view of a die 500 according to some embodiments of the present disclosure. The die 500 may correspond to the die 203 of FIG. 2, except that the geometries of the top surface 505 of the passivation layer 504 and the top surface 507 of the polyimide layer 506 may be configured differently to provide the strength and stability required for different applications. For example, as shown, the top surface 505 of the passivation layer 504 may be stepped down toward the center of the die 500, and the top surface 507 of the polyimide layer 506 may include multiple protrusions 508 extending away from the passivation layer 504 and formed by removing pyramidal portions 510 from the top surface.

[0049] 6 illustrates an exemplary side view of a die 600 in accordance with some embodiments of the present disclosure. In some embodiments, even when the passivation layer 604 does not need to be modified to correct wafer bow (of the circuit layer 202) and die 203 warpage (e.g., die-level warpage) (e.g., for circuit layer 202 with a large wafer thickness), it may be desirable to improve adhesion between stacked dies. For example, as shown, the passivation layer 604 may include a flat top surface 605, and the top surface 607 of the polyimide layer 606 may include a plurality of rectangular protrusions (e.g., formed by a pad etching process) to increase the surface area of ​​the top surface 607 of the polyimide layer 606. However, this is merely one example, and the top surface 607 of the polyimide layer 606 may be modified in any suitable manner.

[0050] 7A-7D illustrate exemplary plan views of top surface geometric elements of a protective layer according to some embodiments of the present disclosure. The top surfaces (700a, 700b, 700c, 700d) may correspond to the top surfaces of either the passivation layer (204 or 504) or the polyimide layer (206, 506, or 606) described above. In some embodiments, the patterns illustrated in FIGS. 7A-7D may correspond to the pattern of a reticle (e.g., reticle 304 in FIG. 3) used in a photolithography process to form the individual top surface geometric elements, as described above. While the illustrated patterns may represent the base shape of the features, it should be understood that the side shapes of the features may be altered to the angles described above (e.g., by a 45-degree angle alteration process or any other suitable angle). While four patterns are shown, these are merely examples, and the top surface geometric elements of the protective layer may be any suitable pattern based on the strength and stability required for the desired application.

[0051] 7A illustrates an example plan view of a top surface 700a of a protective layer. The top surface 700a may include a plurality of square portions 701a of decreasing thickness of the protective layer. As shown, the plurality of square portions 701a may be arranged in a checkered pattern.

[0052] 7B illustrates an example plan view of a top surface 700b of the protective layer. The top surface 700b may include multiple circular portions 701b of decreasing thickness of the protective layer. As shown, the multiple circular portions 701b may be arranged in a checkered pattern.

[0053] 7C illustrates an exemplary plan view of a top surface 700c of the protective layer. The top surface 700c may include multiple rectangular portions 701c of decreasing thickness of the protective layer. As shown, the multiple rectangular portions 701c may be regularly spaced apart from one another, but may vary in size.

[0054] 7D illustrates an example plan view of a top surface 700d of the protective layer. The top surface 700d may include a plurality of rectangular portions 701d where the thickness of the protective layer decreases. As shown, the density of the rectangular portions 701d may increase along the x-direction. Furthermore, the size of the rectangular portions 701d may vary based on the strength and stability required for a desired application.

[0055] FIG. 8 illustrates a flowchart of an exemplary process 800 for manufacturing a die according to some embodiments of the present disclosure.

[0056] In step 802, circuitry is provided, which may be circuit layer 202, as described above in FIG.

[0057] In step 804, a passivation layer (e.g., a first protective layer) is placed over the circuitry. The passivation layer may be passivation layer 204 (or 504), as described above in Figures 2 and 5.

[0058] In step 806, the thickness of portions of the top surface of the passivation layer is modified to form portions of different individual heights that extend vertically away from the circuitry. For example, as described above in Figures 3B and 3C, a photolithography (and etching) process may be applied to top surface 214a of passivation layer 204. The passivation layer may also be passivation layer 504, as described in Figure 5. The resulting geometry of the top surface of the passivation layer can compensate for the determined wafer bow and die-level warpage of die 203, as described above.

[0059] In step 808, a polyimide layer may be placed on top of the passivation layer. The polyimide layer may be polyimide layer 206, as described above in Figure 4A.

[0060] In step 810, the thickness of portions of the top surface of the polyimide layer may be modified to form portions of different individual heights that extend vertically away from the passivation layer. For example, as described above in FIG. 4B, photolithography and / or etching processes may be applied to top surface 216a of polyimide layer 206. The polyimide layer may also be polyimide layer 506 or 606, as described above in FIGS. 5 and 6. The resulting top surface geometry of the polyimide layer may improve die surface adhesion between stacked dies by increasing the surface area of ​​the top surface (e.g., compared to a flat surface), as described above.

[0061] The foregoing is merely illustrative of the principles of the present disclosure, and various modifications may be made by those skilled in the art without departing from the scope of the present disclosure. The above-described embodiments are presented for purposes of illustration and not limitation. The present disclosure may take many forms other than those expressly described herein. It is therefore emphasized that the present disclosure is not limited to the expressly disclosed methods, systems, and apparatus, but is intended to include changes and modifications thereto, and such changes and modifications are within the spirit of the following claims.

Claims

1. circuit; a passivation layer having a top surface and a bottom surface, the passivation layer disposed over the circuitry, wherein the top surface of the passivation layer includes portions of different individual heights extending vertically away from the circuitry; and a polyimide layer disposed on the top surface of the passivation layer; A die comprising:

2. The die of claim 1 , wherein the top surface of the passivation layer includes a plurality of protrusions extending away from a base of the top surface.

3. 3. The die of claim 2, wherein each of the plurality of protrusions has an individual side surface, the individual side surface of each of the plurality of protrusions tapering to become narrower as the protrusion extends away from the base.

4. The die of claim 3 , wherein the side surfaces of certain of the plurality of protrusions are each tapered at an angle.

5. The die of claim 2 , wherein the plurality of protrusions includes protrusions of different heights that extend away from the base of the top surface.

6. The die of claim 2 , wherein each of the plurality of protrusions is one of a trapezoidal prism, a pyramidal shape, or a triangular prism.

7. The die of claim 2 , wherein the arrangement and shape of the plurality of protrusions are based on a lattice orientation of silicon in the die and a size of the circuitry.

8. 2. The die of claim 1, wherein a top surface of the polyimide layer opposite the top surface of the passivation layer includes portions of different individual heights that extend vertically away from the circuitry such that a surface area of ​​the top surface of the polyimide layer is increased compared to a flat top surface.

9. 1. An integrated circuit (IC) device comprising: substrate; a first die disposed on the substrate; a first circuit; a first passivation layer having a top surface and a bottom surface, the first passivation layer disposed over the first circuit; and a first polyimide layer disposed on the top surface of the first passivation layer, wherein a top surface of the first polyimide layer opposite the top surface of the first passivation layer includes portions of different individual heights extending away from the first passivation layer; a die attach film (DAF) disposed on the top surface of the first polyimide layer; and Second circuit; a second passivation layer having a top surface and a bottom surface, the second passivation layer disposed over the second circuit; and a second polyimide layer disposed on the top surface of the second passivation layer; A second die having Equipped with wherein the second die is vertically stacked on top of the first die and attached to the first die by the DAF, which bonds the top surface of the first polyimide layer to a bottom surface of the second circuit, opposite the second passivation layer.

10. the top surface of the first passivation layer includes portions of different heights extending vertically away from the first circuitry; and 10. The IC device of claim 9, wherein the top surface of the second passivation layer includes portions of different individual heights that extend vertically away from the second circuitry.

11. 11. The IC device according to claim 9, wherein the IC device is a three-dimensional floating gate NAND memory.

12. 1. A method of depositing a passivation layer, comprising: disposing the passivation layer over the circuit layer, the passivation layer having a top surface and a bottom surface; and Varying the thickness of a portion of the passivation layer so that the top surface is non-planar. A method for providing the above.

13. The method of claim 12 , wherein modifying the thickness of the portion comprises etching away the thickness of the portion from the top surface of the passivation layer.

14. 14. The method of claim 12 or 13, wherein modifying the thickness of the portion comprises applying a photolithographic process to the top surface of the passivation layer to modify the thickness of the portion.

15. 15. The method of claim 14, wherein the photolithography process includes using a reticle mask that includes portions that allow different respective percentages of leaky chrome to reach the top surface of the passivation layer, thereby varying the thickness of the passivation.

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