Stacked random access memory with complementary adjacent cells

Abstract

A field effect transistor (FET) cell structure for an integrated circuit (IC) is provided. The FET cell structure includes first and second adjacent cells. Each of the first and second adjacent cells straddles a first layer and a second layer. The second layer is vertically stacked on the first layer. The first cell includes an n-doped FET (NFET) on one of the first and second layers and a p-doped FET (PFET) on the other of the first and second layers. The second cell includes at least one of a number of NFETs on one of the first and second layers that is different from the number of NFETs in the first cell and a number of PFETs on the other of the first and second layers that is different from the number of PFETs in the first cell.

Description

[Technical Field]

[0001] The present invention relates generally to manufacturing methods and resulting structures for semiconductor devices, and more particularly to stacked random-access-memory (RAM) cells having complementary adjacent cells. [Background technology]

[0002] Semiconductors and integrated circuit (IC) chips have become widely used in many products, especially as they continue to shrink in cost and size. Recently, there has been a desire to reduce the size of structural features and / or provide a larger number of structural features for a given chip size. This is because miniaturization generally enables improved performance at lower power levels and lower cost. Current technology has reached the scaling of certain microdevices, such as logic gates, field-effect transistors (FETs), and capacitors, at or near atomic levels.

[0003] For example, an array of FETs within a given cell structure may have one word line and two bit lines and may include first and second transistors each operably connected to the word line, one of which is operably connected to one of the bit lines and the other of which is operably connected to the other bit line. The first and second transistors may be provided as n-doped access transistors or NFETs. The array within a given cell may further include first and second pull-up transistors operably interposed between the access transistors and connected to a voltage terminal. The first and second pull-up transistors may be provided as p-doped pull-up transistors or PFETs. The array within a given cell may also include first and second pull-down transistors operably interposed between the access transistors and connected to a ground terminal. The first and second pull-down transistors may be provided as NFETs.

[0004] The cell structure described above may be provided as a static RAM cell structure or SRAM.

[0005] Using the cell structure described above, it is clear that there are four total NFETs and two total PFETs. In previous designs, the placement of these four total NFETs and two total PFETs was not optimized for space considerations, among other issues. This presents a problem in achieving the desired level of miniaturization. Summary of the Invention

[0006] Embodiments of the present invention are directed to a field effect transistor (FET) cell structure for an integrated circuit (IC). A non-limiting example of the FET cell structure includes first and second adjacent cells. Each of the first and second adjacent cells straddles a first layer and a second layer. The second layer is vertically stacked on the first layer. The first cell includes an n-doped FET (NFET) on one of the first and second layers and a p-doped FET (PFET) on the other of the first and second layers. The second cell includes at least one of a number of NFETs on one of the first and second layers that is different from the number of NFETs in the first cell and a number of PFETs on the other of the first and second layers that is different from the number of PFETs in the first cell.

[0007] The first and second cells are vertically complementary to one another, which allows the first and second cells to fit adjacently in an optimized manner, which allows for a desired level of miniaturization for the IC.

[0008] According to one or more additional or alternative embodiments of the invention, the first and second cells are vertically complementary.

[0009] According to one or more additional or alternative embodiments of the present invention, the first cell may have four NFETs and the second cell may have two NFETs, or more specifically, the first cell may have four NFETs and two PFETs and the second cell may have two NFETs and four PFETs.

[0010] According to one or more additional or alternative embodiments of the present invention, the first and second cells may be of the same functional type or may be separately operable.

[0011] According to one or more additional or alternative embodiments of the present invention, the IC further comprises first and second bit lines having different bit line voltage precharge capabilities, the first bit line being coupled to the first cell and the second bit line being coupled to the second cell.

[0012] According to one or more additional or alternative embodiments of the present invention, the IC further comprises first and second bit lines, the first bit line coupled to the front or back surface of the first cell and the second bit line coupled to the back or front surface of the second cell.

[0013] According to one or more additional or alternative embodiments of the present invention, the IC further comprises first and second different word lines having different word line voltages, the first word line being coupled to the first cell and the second word line being coupled to the second cell.

[0014] According to one or more additional or alternative embodiments of the present invention, each of the first and second adjacent cells includes one or more additional layers, and each of the first and second cells further includes complementary NFETs and PFETs on the one or more additional layers.

[0015] Embodiments of the present invention are directed to a field effect transistor (FET) cell structure for an integrated circuit (IC). A non-limiting example of the FET cell structure includes first and second cells, each spanning a first layer and a second layer vertically stacked on the first layer. The first cell includes an n-doped FET (NFET) on one of the first and second layers and a p-doped FET (PFET) on the other of the first and second layers. The second cell includes at least one of a number of NFETs on one of the first and second layers that is different from the number of NFETs in the first cell and a number of PFETs on the other of the first and second layers that is different from the number of PFETs in the first cell. The FET cell structure further includes an additional electronic device on the first and second layers and interposed between the first and second cells. The first and second cells and the additional electronic device are vertically complementary.

[0016] The first and second cells and the additional electronic device are vertically complementary to one another, and the first and second cells and the additional electronic device may fit adjacently in an optimized manner, which optimally allows for a desired level of miniaturization for the IC.

[0017] According to one or more additional or alternative embodiments of the present invention, the additional electronic device is shared between the first and second cells.

[0018] Embodiments of the present invention are directed to an integrated circuit (IC) cell structure. A non-limiting example of the cell structure includes first and second vertically complementary and adjacent cells, each spanning a first layer and a second layer vertically stacked on the first layer. The first cell includes a first electronic device on one of the first and second layers and a second electronic device on the other of the first and second layers. The second cell includes at least one of: a number of first electronic devices on one of the first and second layers that is different from the number of first electronic devices in the first cell; and a number of second electronic devices on the other of the first and second layers that is different from the number of second electronic devices in the first cell.

[0019] The first and second cells are vertically complementary to one another, allowing the first and second cells to fit adjacently in an optimized manner, which allows for a desired level of miniaturization for the IC.

[0020] According to one or more additional or alternative embodiments of the present invention, the first electronic device comprises an n-doped field effect transistor (NFET) and the second electronic device comprises a p-doped field effect transistor (PFET).

[0021] According to one or more additional or alternative embodiments of the invention, the cell structure is a static random access memory (SRAM) cell, the first electronic device includes a transistor, and the second electronic device includes a resistor.

[0022] According to one or more additional or alternative embodiments of the invention, the cell structure is a ternary content addressable memory (TCAM) cell, the first electronic device includes a transistor, and the second electronic device includes a capacitor.

[0023] According to one or more additional or alternative embodiments of the present invention, the first and second cells may be of the same functional type or may be separately operable.

[0024] According to one or more additional or alternative embodiments of the present invention, the cell structure further comprises first and second bit lines having different bit line voltage precharge capabilities, the first bit line being coupled to the first cell and the second bit line being coupled to the second cell.

[0025] According to one or more additional or alternative embodiments of the present invention, the cell structure further comprises first and second bit lines, the first bit line coupled to the front or back surface of the first cell and the second bit line coupled to the back or front surface of the second cell.

[0026] According to one or more additional or alternative embodiments of the present invention, the cell structure further comprises first and second different word lines having different word line voltages, the first word line being coupled to the first cell and the second word line being coupled to the second cell.

[0027] Additional technical features and advantages are realized through the techniques of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, reference is made to the detailed description and drawings. [Brief explanation of the drawings]

[0028] The particulars of the exclusive rights set forth herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0029] [Figure 1] 1 is a schematic circuit diagram of a memory cell in accordance with one or more embodiments of the present invention.

[0030] [Figure 2] 1 is a schematic diagram of a FET cell structure in accordance with one or more embodiments of the present invention.

[0031] [Figure 3] 3 is a detailed schematic diagram of the FET cell structure of FIG. 2 in accordance with one or more embodiments of the present invention.

[0032] [Figure 4] FIG. 1 is a schematic diagram of a FET cell structure having an additional electronic device in accordance with one or more embodiments of the present invention.

[0033] [Figure 5] 1 is a schematic diagram of a first type of static random-access-memory (SRAM) cell structure in accordance with one or more embodiments of the present invention;

[0034] [Figure 6] 2 is a schematic diagram of a second type of static random access memory (SRAM) cell structure in accordance with one or more embodiments of the present invention.

[0035] [Figure 7] 1 is a schematic diagram of a ternary content addressable memory (TCAM) cell structure in accordance with one or more embodiments of the present invention.

[0036] The drawings depicted herein are exemplary. There may be many variations to the drawings or the operations described therein without departing from the scope of the invention. For example, operations may be performed in a different order, or operations may be added, deleted, or modified. Also, the term "coupled" and variations thereof describe having a communication path between two elements and do not imply a direct connection between them without an intervening element / connection between them. All of these variations are considered part of this specification.

[0037] In the accompanying figures and the following detailed description of the illustrated embodiments, various elements illustrated in the figures are given two- or three-digit reference numbers. With some exceptions, the left-most digit(s) of each reference number corresponds to the figure in which the element is first shown. DETAILED DESCRIPTION OF THE INVENTION

[0038] For the sake of brevity, conventional techniques related to the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Moreover, various tasks and process steps described herein may have additional steps or functionality not described in detail herein, or may be incorporated into more comprehensive procedures or processes. In particular, because the various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps may only be briefly described herein or may be omitted entirely without providing well-known process details.

[0039] Referring now to a summary of aspects of the present invention, one or more embodiments of the present invention address the above-mentioned shortcomings and problems of the prior art by providing a stacked cell structure, e.g., an SRAM, having complementary adjacent cells, which allows the placement of the number of NFETs and PFETs within the cell structure to be optimized for space considerations, facilitating the achievement of a desired level of miniaturization.

[0040] The above-described aspects of the present invention address the shortcomings of the prior art by providing a FET cell structure for an IC. The FET cell structure includes first and second adjacent cells, each spanning a first layer and a second layer vertically stacked on the first layer. The first cell includes an n-doped FET (NFET) on one of the first and second layers and a p-doped FET (PFET) on the other of the first and second layers. The second cell includes a PFET on one of the first and second layers and an NFET on the other of the first and second layers.

[0041] As used herein, the terms FET, NFET, and PFET may be used interchangeably with VTFET, FINFET, nanosheet FET, etc., or combinations thereof. However, for clarity and brevity, the terms FET, NFET, and PFET will be used.

[0042] Referring now to a more detailed description of embodiments of the present invention, FIG. 1 depicts a memory cell structure 101 having an array of transistors. The memory cell structure 101 has a word line 102 and two bit lines 103, and includes first and second transistors 104 and 105, each operably connected to the word line 102. One of the first and second transistors 104 and 105 is operably connected to one of the bit lines 103, and the other is operably connected to the other of the bit lines 103. The first and second transistors 104 and 105 may be provided as n-doped access transistors or NFETs. The array of transistors in the memory cell structure 101 may further include first and second pull-up transistors 106 and 107, operably interposed between the first and second transistors 104 and 105 and connected to voltage terminals 108 and 109. The first and second pull-up transistors 106 and 107 may be provided as p-doped pull-up transistors or PFETs. The array of transistors in memory cell structure 101 may also include first and second pull-down transistors 110 and 111, which are operatively interposed between first and second transistors 104 and 105 and connected to ground terminals 112 and 113. First and second pull-down transistors 110 and 111 may be provided as NFETs.

[0043] Referring to FIG. 2, the array of transistors in memory cell structure 101 of FIG. 1 may be arranged in a FET cell structure 201, along with additional arrays of transistors in additional memory cell structures (other types of cell structures) in an IC.

[0044] The FET cell structure 201 includes a first cell 210 having a transistor array and a second cell 220 having a transistor array. The first cell 210 and the second cell 220 are adjacent to each other, and each of the first cell 210 and the second cell 220 straddles a first layer 230 and a second layer 231. The second layer 231 is vertically stacked on top of the first layer 230 within the IC. The first cell 210 includes an NFET 211 on one of the first layer 230 and the second layer 231 (e.g., the first layer 230) and a PFET 212 on the other of the first layer 230 and the second layer 231 (e.g., the second layer 231). The second cell 220 includes NFETs 211 on one of the first layer 230 and the second layer 231 (e.g., the first layer 230) and PFETs 212 on the other of the first layer 230 and the second layer 231 (e.g., the second layer 231). In the second cell 220, the number of NFETs 211 on one of the first layer 230 and the second layer 231 (e.g., the first layer 230) is different from the number of NFETs 211 in the first cell 210. Similarly, in the second cell 220, the number of PFETs 212 on the other of the first layer 230 and the second layer 231 (e.g., the second layer 231) is different from the number of PFETs 212 in the first cell 210.

[0045] As shown in FIG. 2, the first cell 210 and the second cell 220 of the FET cell structure 201 are, by their respective configurations, vertically complementary at least along their respective interior sides.

[0046] 2, it should be understood that FET cell structure 201 may have one or more additional layers and one or more additional cells. First and second cells 210 and 220 and the one or more additional cells may span first and second layers 230 and 231 and one or more additional layers. The configuration of the one or more additional cells may be vertically complementary to first and second cells 210 and 220 and to the other additional cells, at least along their respective interiors.

[0047] Referring to Figure 3, the FET cell structure 201 of Figure 2 is shown in more detail. As shown in Figure 3, a first cell of the FET cell structure 201 may be provided as an NFET passgate cell 301, and a second cell of the FET cell structure 201 may be provided as a PFET passgate cell 302. The NFET passgate cell 301 and the PFET passgate cell 302 may be of the same functional type, or they may be separately operable.

[0048] The NFET passgate cell 301 and the PFET passgate cell 302 are vertically complementary, at least along their respective interior sides 301 a and 302 a. The FET cell structure 201 includes a first layer 303 and a second layer 304. The NFET passgate cell 301 spans both the first layer 303 and the second layer 304. The PFET passgate cell 302 also spans both the first layer 303 and the second layer 304. The FET cell structure 201 also includes a first bitline 310, a second bitline 320, and a wordline 330. The first bitline 310 may be provided in multiple portions, including a first bitline area 311 in the NFET passgate cell 301, a second bitline area 312, and a bitline bar 313 in the NFET passgate cell 301. The second bit line 320 may similarly be provided in multiple portions, including a first bit line area 321 and a bit line bar 322 in the PFET pass gate cell 302. The FET cell structure 201 may be fabricated on the backside metal ground plane of the IC, with ground terminal 340 and ground terminal 341 formed in the NFET pass gate cell 301 and the PFET pass gate cell 302, respectively, and the FET cell structure 201 may further include voltage terminal 342 and voltage terminal 343 in the NFET pass gate cell 301 and the PFET pass gate cell 302, respectively.

[0049] According to one or more embodiments of the present invention, the first bit line 310 and the second bit line 320 may have different bit line voltage precharge capabilities. Furthermore, the first bit line 310 may be coupled to the front or back side of the NFET pass gate cell 301, and the second bit line 320 may be coupled to the back or front side of the PFET pass gate cell 302, or vice versa. Similarly, the word line 330 may be provided as multiple or first and second different word lines having different word line voltages.

[0050] According to one or more embodiments of the present invention, NFET passgate cell 301 may include two NFET passgate or access transistors 350 and 351 sandwiching two NFET pulldown transistors 352 and 353 on a first layer 303 (four NFETs total on first layer 303), and two PFET or pullup transistors 354 and 355 on a second layer 304 (two PFETs total on second layer 304). The two NFET passgate or access transistors 350 and 351 are communicative with a first bitline area 311 and a bitline bar 313, respectively, and the two NFET pulldown transistors 352 and 353 each communicate with a ground terminal 340. The two PFET or pullup transistors 354 and 355 communicate with the four NFETs on first layer 303 and a voltage terminal 342. According to one or more further embodiments of the present invention, PFET passgate cell 302 may include two NFET pulldown transistors 360 and 361 on first layer 303 (two NFETs total on first layer 303) and two PFET passgate or access transistors 362 and 363 (four PFETs total on second layer 304) sandwiching two PFET pullup transistors 364 and 365 on second layer 304. The two NFET pulldown transistors 360 and 361 communicate with the four PFETs on second layer 304 and with ground terminal 341. The two PFET passgate or access transistors 362 and 363 communicate with second bitline area 312 and wordline 330, and the two PFET pullup transistors 364 and 365 communicate with voltage terminal 343.

[0051] Thus, a set of NFETs in NFET passgate cell 301 are NFET passgates and another set of NFETs are NFET pulldown gates, while a set of PFETs in NFET passgate cell 301 are pullup gates. Similarly, a set of PFETs in PFET passgate cell 302 are PFET passgates and another set of PFETs are pullup gates, while a set of NFETs in PFET passgate cell 302 are pulldown gates.

[0052] 3, NFET passgate cell 301 has a total of four NFETs on first layer 303 (and two PFETs on second layer 304), and PFET passgate cell 302 has two NFETs on first layer 303 (and a total of four PFETs on second layer 304), it should be understood that this is not required and other embodiments are possible. For example, the number of NFETs and PFETs in NFET passgate cell 301 and PFET passgate cell 302 may be increased or decreased as long as NFET passgate cell 301 and PFET passgate cell 302 remain vertically complementary (i.e., NFET passgate cell 301 and PFET passgate cell 302 may have a 4 / 2:2 / 4 configuration, a 5 / 2:2 / 5 configuration, a 6 / 2:2 / 6 configuration, etc.). As another example, as described above, there may be one or more additional layers within FET cell structure 201, and NFET passgate cell 301 and PFET passgate cell 302 may include additional NFETs and PFETs on one or more additional layers (i.e., NFET passgate cell 301 and PFET passgate cell 302 may have a 6 / 4 / 2:2 / 4 / 6 configuration, an 8 / 5 / 2:2 / 5 / 8 configuration, a 10 / 6 / 2:2 / 6 / 10 configuration, etc.). Furthermore, FET cell structure 201 may include one or more additional cell structures that may be configured with a vertically complementary configuration, similar to NFET passgate cell 301 and PFET passgate cell 302 (i.e., NFET passgate cell 301, PFET passgate cell 302, and the additional cell structures may have a 4 / 2:2 / 4:4 / 2 configuration, a 5 / 2:2 / 5:5 / 2 configuration, a 6 / 2:2 / 6:6 / 2 configuration, etc.).

[0053] 4 , according to one or more embodiments of the present invention, the FET cell structure 201 may further include additional electronic devices 401 on the first layer 303 and the second layer 304, interposed between the NFET passgate cells 301 and the PFET passgate cells 302, which need not be adjacent. Such additional electronic devices 401 may be dummy electronic devices or functional electronic devices shared between the NFET passgate cells 301 and the PFET passgate cells 302. As shown in FIG. 4 , the number or size of the additional electronic devices 401 on the first layer 303 and on the second layer 304 may be provided such that the vertically complementary nature of the NFET passgate cells 301 and the PFET passgate cells 302 continues even in the presence of the additional electronic devices 401. That is, the NFET passgate cells 301, the PFET passgate cells 302, and the additional electronic devices 401 are vertically complementary.

[0054] 2-4 and further with reference to Figures 5-7, it will be appreciated that the cell structures described above need not be limited to FET cell structures, and other options and configurations are possible. That is, an integrated circuit (IC) cell structure is provided that may be configured as one or more of a first type SRAM cell 501 (see Figure 5), a second type SRAM cell 601 (see Figure 6), and a ternary content addressable memory (TCAM) cell 701 (see Figure 7).

[0055] 5 , a first type SRAM cell 501 includes first and second vertically complementary and adjacent cells 502 and 503, each spanning a first layer 504 and a second layer 505 vertically stacked on the first layer 504. The first cell 502 includes a first electronic device 510 on one of the first layer 504 and the second layer 505 and a second electronic device 520 on the other of the first layer 504 and the second layer 505. The second cell 503 includes at least one of a number of first electronic devices 510 on one of the first layer 504 and the second layer 505 that differs from the number of first electronic devices 510 in the first cell 502 and a number of second electronic devices 520 on the other of the first layer 504 and the second layer 505 that differs from the number of second electronic devices 520 in the first cell 502. According to an embodiment, the first electronic device 510 may include or be provided as an NFET, and the second electronic device 520 may include or be provided as a PFET.

[0056] 6 , a second type SRAM cell 601 includes first and second vertically complementary and adjacent cells 602 and 603, each spanning a first layer 604 and a second layer 605 vertically stacked on the first layer 604. The first cell 602 includes a first electronic device 610 on one of the first layer 604 and the second layer 605 and a second electronic device 620 on the other of the first layer 604 and the second layer 605. The second cell 603 includes at least one of a number of first electronic devices 610 on one of the first layer 604 and the second layer 605 that differs from the number of first electronic devices 610 in the first cell 602 and a number of second electronic devices 620 on the other of the first layer 604 and the second layer 605 that differs from the number of second electronic devices 620 in the first cell 602. According to an embodiment, the first electronic device 610 may include or be provided as a transistor, and the second electronic device 620 may include or be provided as a resistor or resistive element.

[0057] 7 , a second type TCAM cell 701 includes first and second vertically complementary and adjacent cells 702 and 703, each spanning a first layer 704 and a second layer 705 vertically stacked on the first layer 704. The first cell 702 includes a first electronic device 710 on one of the first layer 704 and the second layer 705 and a second electronic device 720 on the other of the first layer 704 and the second layer 705. The second cell 703 includes at least one of a number of first electronic devices 710 on one of the first layer 704 and the second layer 705 that differs from the number of first electronic devices 710 in the first cell 702 and a number of second electronic devices 720 on the other of the first layer 704 and the second layer 705 that differs from the number of second electronic devices 720 in the first cell 702. According to an embodiment, the first electronic device 710 may include or be provided as a transistor, and the second electronic device 720 may include or be provided as a capacitor or capacitive element.

[0058] The technical advantages of one or more embodiments of the present invention described above provide for optimizing the placement of a number of electronic devices within an IC, such as the number of NFETs and PFETs within a cell structure of an SRAM cell, for spatial considerations to facilitate achieving a desired level of miniaturization.

[0059] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternative embodiments may be devised without departing from the scope of the present invention. While the following description and drawings describe various connections and relationships between elements (e.g., above, below, adjacent, etc.), those skilled in the art will recognize that many of the relationships described herein are independent of orientation, provided that the described functionality is maintained even when the orientation is changed. These connections and / or relationships may be direct or indirect, unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, a connection between entities may refer to either a direct or indirect connection, and a relationship between entities may be a direct or indirect relationship. As an example of an indirect relationship, references herein to layer "A" being formed on layer "B" include situations in which one or more intermediate layers (e.g., layer "C") exist between layer "A" and layer "B," so long as the relevant properties and functionality of layer "A" and layer "B" are not substantially altered by the intermediate layers.

[0060] The following definitions and abbreviations will be used in interpreting the claims and the specification. As used herein, the words "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements and may include other elements not expressly listed or inherent in such composition, mixture, process, method, article, or device.

[0061] Additionally, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "plurality" may be understood to include any integer greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connection" may include an indirect "connection" and a direct "connection."

[0062] References herein to "one embodiment," "an embodiment," "an example embodiment," or the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but that all embodiments may or may not include the particular feature, structure, or characteristic. Also, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in the context of one embodiment, it is believed to be within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in the context of other embodiments, whether or not explicitly described.

[0063] For purposes of the following description, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," and "bottom," as well as derivatives thereof, refer to the structures and methods being described in terms of their orientation within the drawings. Terms such as "overlying," "atop," "on top of," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is on a second element, such as a second structure, where an intervening element, such as an interfacial structure, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0064] Spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," and the like, may be used herein for ease of description to describe the relationship of one element or feature to another, as shown in the figures. It will be understood that spatially relative terms are intended to encompass multiple different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in a figure is rotated, elements described as "below" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein will be interpreted accordingly.

[0065] For example, the phrase "selective to," such as "a first element selective to a second element," means that the first element can be etched and the second element can act as an etch stop.

[0066] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on the equipment available at the time of filing. For example, "about" can include a range of ±8%, or 5%, or 2% of a given value.

[0067] The term "conformal" (e.g., conformal layer) means that the thickness of the layer is substantially the same on all surfaces or that the thickness varies by less than 15% of the nominal thickness of the layer.

[0068] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" refer to the growth of one semiconductor material (crystalline substance) on the deposition surface of another semiconductor material (crystalline substance), where the growing semiconductor material (crystalline overlayer) has substantially the same crystallinity as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, chemical reactants provided by source gases can be controlled, and system parameters can be set so that the depositing atoms arrive at the deposition surface of a semiconductor substrate with sufficient energy to travel across the surface, resulting in the depositing atoms orienting themselves to the crystalline arrangement of atoms on the deposition surface. Epitaxially grown semiconductor material can have substantially the same crystallinity as the deposition surface on which it is formed. For example, epitaxially grown semiconductor material deposited on a crystalline surface with a {100} orientation can have a {100} orientation. In some embodiments of the present invention, the epitaxial growth and / or deposition process may be selective to formation on semiconductor surfaces and not allow material to be deposited on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0069] As noted earlier herein, for the sake of brevity, conventional techniques associated with the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. However, by way of background, a more general description of semiconductor device manufacturing processes that may be utilized in implementing one or more embodiments of the present invention is now provided. While the particular manufacturing operations used in implementing one or more embodiments of the present invention may be individually known, the combination of operations described and / or resulting structures of the present invention are unique. Thus, the unique combination of operations described in connection with the manufacture of semiconductor devices in accordance with the present invention utilizes various individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the following paragraphs.

[0070] Generally, the various processes used to form microchips that are packaged into ICs fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. Removal / etching is any process that removes material from a wafer. Examples include etching processes (either wet or dry) and chemical mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping the source and drain of a transistor, for example, typically by diffusion and / or ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). The annealing serves to activate the implanted dopants. Films, both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.), are used to connect and separate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be altered by applying a voltage. By creating structures of these various components, millions of transistors can be constructed and wired together to form the complex circuitry of modern microelectronic devices. Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate and the subsequent transfer of the pattern into the substrate. In semiconductor lithography, the pattern is formed with a light-sensitive polymer called a photoresist. The lithography and etching pattern transfer steps are repeated multiple times to build the intricate structures that make up the transistors and the many wires that connect the circuit's millions of transistors.Each pattern printed on the wafer is aligned to a previously formed pattern, slowly building up conductors, insulators, and selectively doped regions to form the final device.

[0071] The flowcharts and block diagrams in the figures illustrate possible implementations of methods of manufacture and / or operation according to various embodiments of the present invention. In the flow diagrams, various functions / acts of the method are represented by blocks. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved.

[0072] The description of various embodiments of the present invention is presented for purposes of illustration and is not intended to be comprehensive or limited to the described embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications of, or technical improvements to, the technology found in the market, or to enable others skilled in the art to understand the embodiments described herein.

Claims

1. 1. A field effect transistor (FET) cell structure for an integrated circuit (IC), the FET cell structure comprising: a first cell and a second cell disposed adjacent to the first cell, each spanning a first layer and a second layer vertically stacked on the first layer; the first cell having an n-doped FET (NFET) on one of the first and second layers and a p-doped FET (PFET) on the other of the first and second layers; The second cell comprises: a number of NFETs on the one of the first and second layers that is different from the number of NFETs in the first cell; and a number of PFETs on the other of the first and second layers that is different from the number of PFETs in the first cell; having at least one of: FET cell structure.

2. The FET cell structure of claim 1 , wherein the first and second cells are vertically complementary.

3. 2. The FET cell structure of claim 1, wherein the set of NFETs of the first cell are NFET passgates and the set of PFETs of the second cell are PFET passgates.

4. 2. The FET cell structure of claim 1, wherein the first cell has four NFETs and the second cell has two NFETs.

5. 5. The FET cell structure of claim 4, wherein said first cell has said four NFETs and two PFETs, and said second cell has said two NFETs and four PFETs.

6. 10. The FET cell structure of claim 1, wherein the first and second cells are of the same functional type or are separately operable.

7. 2. The FET cell structure of claim 1, further comprising first and second bit lines having different bit line voltage precharge capabilities, the first bit line coupled to the first cell and the second bit line coupled to the second cell.

8. 2. The FET cell structure of claim 1, further comprising first and second bit lines, the first bit line coupled to a front or back surface of the first cell, and the second bit line coupled to the back or front surface of the second cell.

9. 2. The FET cell structure of claim 1, further comprising first and second different word lines having different word line voltages, the first word line coupled to the first cell and the second word line coupled to the second cell.

10. each of the first and second adjacent cells having one or more additional layers; the first and second cells each further comprising a complementary number of NFETs and PFETs on the one or more additional layers; The FET cell structure of claim 1 .

11. 1. A field effect transistor (FET) cell structure for an integrated circuit (IC), the FET cell structure comprising: first and second cells, each spanning a first layer and a second layer vertically stacked on the first layer; the first cell having an n-doped FET (NFET) on one of the first and second layers and a p-doped FET (PFET) on the other of the first and second layers; The second cell comprises: a number of NFETs on the one of the first and second layers that is different from the number of NFETs in the first cell; and a number of PFETs on the other of the first and second layers that is different from the number of PFETs in the first cell; and an additional electronic device overlying the first and second layers and interposed between the first and second cells; Including, the first and second cells and the additional electronic device are vertically complementary. FET cell structure.

12. The FET cell structure of claim 11 , wherein the additional electronic device is shared between the first and second cells.

13. 1. An integrated circuit (IC) cell structure, the cell structure comprising: comprising first and second vertically complementary and adjacent cells, each spanning a first layer and a second layer vertically stacked on the first layer; the first cell having a first electronic device on one of the first and second layers and a second electronic device on the other of the first and second layers; The second cell comprises: a number of first electronic devices on the one of the first and second layers that is different from the number of first electronic devices in the first cells; and a number of second electronic devices on the other of the first and second layers that is different from the number of second electronic devices in the first cells; having at least one of: Cell structure.

14. 14. The cell structure of claim 13, wherein the cell structure is a static random access memory (SRAM) cell, the first electronic device comprises an n-doped field effect transistor (NFET) and the second electronic device comprises a p-doped field effect transistor (PFET).

15. 14. The cell structure of claim 13, wherein the cell structure is a static random access memory (SRAM) cell, the first electronic device comprises a transistor, and the second electronic device comprises a resistor.

16. 14. The cell structure of claim 13, wherein the cell structure is a ternary content addressable memory (TCAM) cell, the first electronic device includes a transistor, and the second electronic device includes a capacitor.

17. 14. The cell structure of claim 13, wherein the first and second cells are of the same functional type or are separately operable.

18. 14. The cell structure of claim 13, further comprising first and second bit lines having different bit line voltage precharge capabilities, the first bit line coupled to the first cell and the second bit line coupled to the second cell.

19. 14. The cell structure of claim 13, further comprising first and second bit lines, the first bit line coupled to a front or back surface of the first cell, and the second bit line coupled to the back or front surface of the second cell.

20. 14. The cell structure of claim 13, further comprising first and second different word lines having different word line voltages, the first word line coupled to the first cell and the second word line coupled to the second cell.

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