Pseudo-Monolithic Die Architecture

Abstract

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, the microelectronic assembly may include a first die and through-dielectric vias (TDVs) surrounded by a dielectric material in a first layer, where the TDVs have a larger width at a first surface and a smaller width at a second surface opposite the first layer; a second die surrounded by a dielectric material in a second layer on the first layer, where the first die is bonded to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from the second surface of the second layer toward the first surface opposite the second layer and having an angle of less than 90 degrees with respect to the second surface; and a substrate on and bonded to the second layer.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of U.S. Non-Provisional Application No. 17 / 821,001, filed August 19, 2022, and entitled "QUASI-MONOLITHIC DIE ARCHITECTURES," and hereby incorporates by reference the entire contents of that U.S. Non-Provisional Application for all purposes.

[0002] The present disclosure relates to techniques, methods, and apparatus directed to pseudo-monolithic die architectures in semiconductor integrated circuit (IC) packaging. [Background technology]

[0003] Electronic circuits are generally called ICs when they are fabricated on wafers of semiconductor material, such as silicon. Wafers with such ICs are typically cut into many individual dies. The dies may be packaged into IC packages containing one or more dies, along with other electronic components such as resistors, capacitors, and inductors. The IC packages may be integrated onto electronic systems, such as consumer electronics systems. [Brief explanation of the drawings]

[0004] Embodiments will be readily understood by the following detailed description taken in conjunction with the accompanying drawings, in which: To facilitate this description, like reference numerals designate like structural elements; and Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:

[0005] [Figure 1A] 1 is a schematic cross-sectional view of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0006] [Figure 1B] 1B is a schematic cross-sectional view of a portion of the example microelectronic assembly of FIG. 1A.

[0007] [Figure 1C] 1B is a schematic cross-sectional view of a portion of the example microelectronic assembly of FIG. 1A.

[0008] [Figure 2] 1 is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0009] [Figure 3] 1 is a schematic cross-sectional view of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0010] [Figure 4] 1 is a schematic cross-sectional view of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0011] [Figure 5] 1 is a schematic cross-sectional view of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0012] [Figure 6A] 1B-1D are schematic cross-sectional views of different stages of an exemplary process for manufacturing the microelectronic assembly of FIG. 1A, according to some embodiments of the present disclosure. [Figure 6B] 1B-1D are schematic cross-sectional views of different stages of an exemplary process for manufacturing the microelectronic assembly of FIG. 1A, according to some embodiments of the present disclosure. [Figure 6C] 1B-1D are schematic cross-sectional views of different stages of an exemplary process for manufacturing the microelectronic assembly of FIG. 1A, according to some embodiments of the present disclosure. [Figure 6D] 1B-1D are schematic cross-sectional views of different stages of an exemplary process for manufacturing the microelectronic assembly of FIG. 1A, according to some embodiments of the present disclosure. [Figure 6E] 1B-1D are schematic cross-sectional views of different stages of an exemplary process for manufacturing the microelectronic assembly of FIG. 1A, according to some embodiments of the present disclosure. [Figure 6F] 1B-1D are schematic cross-sectional views of different stages of an exemplary process for manufacturing the microelectronic assembly of FIG. 1A, according to some embodiments of the present disclosure. [Figure 6G] 1B-1D are schematic cross-sectional views of different stages of an exemplary process for manufacturing the microelectronic assembly of FIG. 1A, according to some embodiments of the present disclosure. [Figure 6H] 1B-1D are schematic cross-sectional views of different stages of an exemplary process for manufacturing the microelectronic assembly of FIG. 1A, according to some embodiments of the present disclosure.

[0013] [Figure 7] FIG. 1 is a schematic flow diagram listing example operations that may be associated with manufacturing a microelectronic assembly, according to some embodiments of the present disclosure.

[0014] [Figure 8] FIG. 1 is a cross-sectional view of a device package including one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0015] [Figure 9] FIG. 1 is a cross-sectional side view of a device assembly including one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0016] [Figure 10] FIG. 1 is a block diagram of an example computing device including one or more microelectronic assemblies according to any of the embodiments disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0017] For purposes of illustrating the IC packages described herein, it is important to understand the phenomena that may be at play during the assembly and packaging of ICs. The following underlying information may be considered a basis upon which the present disclosure may be adequately explained. Such information is provided solely for illustrative purposes and, therefore, should not be construed in any way as limiting the broad scope of the present disclosure and its potential applications.

[0018] Advances in semiconductor processing and logic design have enabled an increase in the amount of logic that can be included in processors and other IC devices. As a result, many processors now have multiple cores monolithically integrated on a single die. These types of monolithic ICs are also generally described as planar because they take the form of a flat surface and are typically constructed on a single silicon wafer made from a single-crystal silicon boule. The typical manufacturing process for such monolithic ICs is called a planar process, which allows photolithography, etching, thermal diffusion, oxidation, and other such processes to be performed on the surface of the wafer so that active circuit elements (e.g., transistors and diodes) are formed on the planar surface of the silicon wafer.

[0019] Current technology allows hundreds and thousands of such active circuit elements to be formed on a single die, allowing a large number of logic circuits to be enabled thereon. In such monolithic dies, the manufacturing process must be optimized equally for all circuits, resulting in trade-offs between different circuits. Additionally, due to the constraints of placing circuits on a planar surface, some circuits are farther apart from others, resulting in performance degradation such as longer delays. Manufacturing yields can also be severely affected, as the entire die may have to be scrapped if even one circuit is malfunctioning.

[0020] One solution to overcome such negative effects of monolithic dies is to subdivide circuits into smaller dies (e.g., chiplets, tiles) electrically coupled by interconnect bridges. The smaller dies are part of an assembly of interconnected dies that together form a complete IC in terms of application and / or function, such as memory chips, microprocessors, microcontrollers, commodity ICs (e.g., chips used for repetitive processing routines, simple tasks, application-specific ICs, etc.), and systems-on-a-chip (SoCs). In other words, the individual dies are connected to create the functionality of the monolithic IC. By using separate dies, each individual die can be optimally designed and manufactured for a specific function. For example, a processor core containing logic circuits may be targeted for performance and therefore may require a highly speed-optimized layout. This has different manufacturing requirements compared to a USB controller built to meet a specific universal serial bus (USB) standard rather than processing speed. Therefore, by separating different parts of the overall design onto different dies, each optimized from a design and manufacturing perspective, the overall yield and cost of the combined die solution can be improved.

[0021] Connectivity between these dies can be achieved in many ways. For example, in 2.5D packaging solutions, silicon interposers and through-silicon vias (TSVs) connect dies together at silicon interconnect speeds with minimal footprints. In another example, silicon bridges embedded under the edges of two interconnecting dies facilitate electrical coupling between them. In three-dimensional (3D) architectures, dies are stacked on top of each other to create a smaller overall footprint. Typically, electrical connectivity and mechanical coupling in such 3D architectures are achieved using TSVs and high-pitch solder-based bumps (e.g., C2 interconnects). Bridge and 3D stack architectures may be combined to allow the top-packaged chip to communicate with other chips horizontally using bridges and vertically using through-mold vias (TMVs), which are typically larger than TSVs. However, these current interconnect technologies use solder or its equivalent for connectivity and therefore have low vertical and horizontal interconnect densities.

[0022] One way to mitigate low vertical interconnect density is to use an interposer, which improves vertical interconnect density but suffers from low lateral interconnect density if the interposer's base wafer is passive. In a general sense, "interposer" is commonly used to refer to a base piece of silicon that interconnects two dies. Including active circuit elements within the interposer can improve lateral speed, but it requires more expensive manufacturing processes, especially when a large base die is used to interconnect smaller dies. Additionally, not all interfaces require fine-pitch connections, which can result in additional manufacturing and processing overhead without the benefits of fine pitch.

[0023] In one aspect of the present disclosure, an example of a pseudo-monolithic die architecture includes recursively combining multiple IC dies to form a microelectronic assembly of a processing system. The multiple IC dies may include active and / or passive dies, and at least a portion of the multiple dies are combined using a high-density interconnect. As used herein, a "high-density interconnect" includes a die-to-die (DTD) interconnect having a pitch of less than 10 microns. As used herein, pitch is measured center-to-center (e.g., from the center of one interconnect to the center of an adjacent interconnect). In some embodiments, two interconnects may form a single interconnect (e.g., a dual interconnect).

[0024] Thus, microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, the microelectronic assembly may include a first die and through-dielectric vias (TDVs) surrounded by a dielectric material in a first layer, where the TDVs have a larger width at a first surface and a smaller width at a second surface opposite the first layer; a second die surrounded by a dielectric material in a second layer on the first layer, where the first die is bonded to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from the second surface of the second layer toward the first surface opposite the second layer and having an angle of less than 90 degrees with respect to the second surface; and a substrate on and bonded to the second layer.

[0025] The structures, assemblies, packages, methods, devices, and systems of the present disclosure may each have several innovative aspects, no single aspect of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described herein are set forth in the following description and accompanying drawings.

[0026] In the following detailed description, various aspects of exemplary implementations may be described using terms commonly adopted by those skilled in the art to convey the substance of their work to others skilled in the art.

[0027] The terms "circuit" and "circuitry" mean one or more passive and / or active electrical and / or electronic components arranged to cooperate with each other to provide a desired function. These terms also refer to analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, microcontroller circuitry, and / or any other type of physical hardware electrical and / or electronic component.

[0028] The term "integrated circuit" means a circuit integrated into a monolithic semiconductor or similar material.

[0029] In some embodiments, the IC die disclosed herein may comprise a substantially single-crystalline semiconductor, such as silicon or germanium, as a base material (e.g., substrate, body) on which an integrated circuit is fabricated using conventional semiconductor processing methods. The semiconductor base material may comprise, for example, an N-type or P-type material. The die may comprise, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure. In other embodiments, the base material of one or more of the IC dies may comprise an alternative material, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV materials, which may or may not be combined with silicon. In still other embodiments, the substrate may comprise a compound semiconductor, for example, having a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In still other embodiments, the substrate may comprise an intrinsic IV or III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in alternative embodiments, nominal impurity dopant levels may be present. In still other embodiments, the die may comprise an amorphous material such as a polymer; for example, the substrate may comprise a silica-filled epoxy. In other embodiments, the substrate may comprise a high-mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.Generally, the substrate may comprise one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may optionally be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, magnesium, and the like. Although a few examples of materials for the die are described herein, any material or structure that can serve as a foundation (e.g., substrate) upon which IC circuits and structures as described herein can be built falls within the spirit and scope of the present disclosure.

[0030] Unless otherwise described, an IC die described herein includes one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) a particular function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., ICs that implement one or more of: memory devices, memory arrays, control logic configured to control these memory devices and arrays, etc.). In another such example, the term "computational die" may be used to describe a die that includes one or more ICs that implement logic / computational circuitry (e.g., ICs that implement one or more of: I / O functions, arithmetic operations, data pipelining, etc.).

[0031] As another example, the terms "package" and "IC package" are synonymous, as are the terms "die" and "IC die." Note that the terms "chip," "die," and "IC die" are used interchangeably herein.

[0032] Unless otherwise specified, the term "insulating" means "electrically insulating" and the term "conducting" means "electrically conducting." In reference to optical signals and / or devices, components, and elements that operate on or using optical signals, the term "conducting" can also mean "optically conducting."

[0033] The terms "oxide," "carbide," "nitride," and the like refer to compounds containing oxygen, carbon, nitrogen, and the like, respectively.

[0034] The term "high-k dielectric" refers to a material that has a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material that has a lower dielectric constant than silicon oxide.

[0035] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to solid materials (and / or liquid materials that solidify after processing as described herein) that are substantially electrically non-conductive. They may include, by way of example and not limitation, organic polymers and plastics, and inorganic materials such as ionic crystals, porcelain, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and alumina, or combinations thereof. They may include dielectric materials, high-polarizability materials, and / or piezoelectric materials. Dielectric materials may include silicon and one or more of oxygen, nitrogen, hydrogen, and carbon (e.g., in the form of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbon nitride); polyimide materials; or any suitable dielectric material commonly used in semiconductor manufacturing, such as low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photosensitive dielectrics, and / or benzocyclobutene-based polymers). They may be transparent or opaque without departing from the scope of this disclosure. Further examples of insulating materials are underfills and mold or mold-like materials used in packaging applications, including, for example, materials used in organic interposers, package supports, and other such components.

[0036] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those monolithically integrated within the IC, those mounted on the IC, or those connected to the IC. The ICs described herein may be either analog or digital and, depending on the components associated with the IC, may be used in many applications such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc. The ICs described herein may be employed in a single IC die or as part of a chipset to perform one or more related functions in a computer.

[0037] In various embodiments of the present disclosure, the transistors described herein may be field-effect transistors (FETs), such as MOSFETs. In many embodiments, the FET is a four-terminal device. In silicon-on-insulator, nanoribbon, or gate-all-around (GAA) FETs, the FET is a three-terminal device including source, drain, and gate terminals, and uses an electric field to control the current flowing through the device. A FET typically includes a gate stack including a channel material, source and drain regions provided in and / or above the channel material, and a gate electrode material, alternatively referred to as a "work function" material, provided above a portion of the channel material between the source and drain regions (the "channel portion"), and optionally a gate dielectric material between the gate electrode material and the channel material.

[0038] In a general sense, an “interconnect” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, facilitating the communication of electrical signals therebetween; an optical interconnect provides optical connectivity between two optical components, facilitating the communication of optical signals therebetween. As used herein, both electrical and optical interconnects are included in the term “interconnect.” The nature of the interconnect being described herein should be understood with reference to its associated signal medium. Thus, when used with reference to an electronic device, such as an IC, that operates using electrical signals, the term “interconnect” describes any element formed from a conductive material for providing electrical connectivity to one or more elements associated with the IC and / or between various such elements. In such cases, the term “interconnect” can refer to both conductive traces (sometimes also referred to as “lines,” “wires,” “metal lines,” or “trenches”) and conductive vias (sometimes also referred to as “vias” or “metal vias”). Sometimes, conductive traces and vias may be referred to as "conductive traces" and "conductive vias," respectively, to emphasize that these elements comprise a conductive material such as a metal. Similarly, when used in reference to a device that similarly operates with optical signals, such as a photonic integrated circuit (PIC), "interconnect" may also describe any element formed from an optically conductive material to provide optical connectivity to one or more elements associated with a PCI. In such cases, the term "interconnect" may refer to optical waveguides, including optical fiber, optical splitters, optical combiners, optical couplers, and optical vias.

[0039] The term "waveguide" refers to any structure that functions to guide the propagation of light from one location to another, typically through a substrate material such as silicon or glass. In various examples, waveguides can be formed from silicon, doped silicon, silicon nitride, glass, such as silica (e.g., silicon dioxide or SiO), borosilicate (e.g., 70-80 wt% SiO, 7-13 wt% B2O3, 4-8 wt% Na2O or KO, and 2-8 wt% Al2O3), etc. Waveguides can be formed using various techniques, including, but not limited to, forming the waveguide in situ. For example, in some embodiments, waveguides can be formed in situ in glass using low-temperature glass-to-glass bonding or by laser direct writing. Waveguides formed in situ can have lower loss characteristics.

[0040] The term "conductive trace" may be used to describe conductive elements separated by insulating material. Within an IC die, such insulating material includes interlayer low-k dielectrics provided within the IC die. Within package substrates and printed circuit boards (PCBs), such insulating material includes organic materials such as Ajinomoto Buildup Film (ABF), polyimide, or epoxy resin. Such conductive lines are typically arranged in several levels, or layers, of a metallization stack.

[0041] The term "conductive via" may be used to describe a conductive element that interconnects two or more conductive lines on different levels of a metallization stack. To this end, the via may be provided substantially perpendicular to the plane of the support structure above which the IC die / chip or IC structure is provided, and may interconnect two conductive lines on adjacent levels or two conductive lines on non-adjacent levels.

[0042] The term "package substrate" may be used to describe any substrate material that facilitates co-packaging with any collection of other electrical components, such as a semiconductor die and / or passive electrical components. As used herein, a package substrate may be formed from any material, including, but not limited to, insulating materials, such as resin-impregnated glass fiber (e.g., PCB or Printed Wiring Board (PWB)), glass, ceramic, silicon, silicon carbide, etc. Additionally, as used herein, a package substrate may refer to a substrate that includes build-up layers (e.g., ABF layers).

[0043] The term "metallization stack" may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC die / chip and / or package substrate.

[0044] As used herein, the term "pitch" of an interconnect refers to the center-to-center distance between adjacent interconnects.

[0045] In the context of a stack of dies bonded together or a die bonded to a package substrate, the term "interconnect" can also refer to die-to-die (DTD) interconnects and die-to-package substrate (DTPS) interconnects, respectively. DTD interconnects can also be referred to as first-level interconnects (FLI). DTPS interconnects can also be referred to as second-level interconnects (SLI).

[0046] Although not specifically shown in all of the present examples to avoid cluttering the drawings, when a DTD or DTPS interconnect is described, a surface of a first die may include a first set of conductive contacts and a surface of a second die or package substrate may include a second set of conductive contacts, and one or more conductive contacts of the first set may then be electrically and mechanically coupled to some of the conductive contacts of the second set by the DTD or DTPS interconnect.

[0047] In some embodiments, the pitch of the DTD interconnects may be different from the pitch of the DTPS interconnects, while in other embodiments, the pitches may be substantially the same.

[0048] The DTPS interconnects disclosed herein may take any suitable form. In some embodiments, the set of DTPS interconnects may include solder (e.g., solder bumps or balls that are thermally reflowed to form the DTPS interconnect). DTPS interconnects including solder may include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, the set of DTPS interconnects may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. The anisotropic conductive material may include a conductive material dispersed in a non-conductive material. In some embodiments, the anisotropic conductive material may include fine conductive particles embedded in a binder or a thermosetting adhesive film (e.g., a thermosetting biphenyl-type epoxy resin or an acrylic-based material). In some embodiments, the conductive particles may include a polymer and / or one or more metals (e.g., nickel or gold). For example, the conductive particles may include nickel-coated gold or silver-coated copper, which may be further coated with a polymer. In another example, the conductive particles may include nickel. When the anisotropic conductive material is uncompressed, there may be no conductive path from one side of the material to the other. On the other hand, when the anisotropic conductive material is sufficiently compressed (e.g., by conductive contacts on both sides of the anisotropic conductive material), conductive material near the compressed region may contact each other to form a conductive path from one side of the film to the other in the compressed region.

[0049] The DTD interconnects disclosed herein may take any suitable form. In some embodiments, some or all of the DTD interconnects in a microelectronic assembly or IC package as described herein may be metal-to-metal interconnects (e.g., copper-to-copper interconnects or plated interconnects). In such embodiments, the conductive contacts on either side of the DTD interconnect may be joined together (e.g., under elevated pressure and / or temperature) without the use of an intervening solder or anisotropic conductive material. In some metal-to-metal interconnects, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide) may be present between the metals joined together (e.g., between copper pads or posts that provide the associated conductive contacts). In some embodiments, one side of the DTD interconnect may be a metal-to-metal interconnect (e.g., a copper-to-copper interconnect or a plated interconnect). One side of the DTD interconnect may include a metal pillar (e.g., a copper pillar), and the other side of the DTD interconnect may include a metal contact (e.g., a copper contact) recessed in the dielectric. In some embodiments, the inter-metal interconnect (e.g., a copper-to-copper interconnect) may include a noble metal (e.g., gold) or a metal whose oxide is conductive (e.g., silver). In some embodiments, the inter-metal interconnect may include metal nanostructures (e.g., nanorods) that may have a low melting point. Inter-metal interconnects may be capable of reliably conducting higher currents than other types of interconnects; for example, some solder interconnects may form brittle intermetallic compounds when current is passed through them, and the maximum current provided through such interconnects may be limited to mitigate mechanical failure.

[0050] In some embodiments, the die on either side of a set of DTD interconnects may be bare (eg, unpackaged) die.

[0051] In some embodiments, the DTD interconnects may include solder. For example, the DTD interconnects may include conductive bumps or pillars (e.g., copper bumps or pillars) attached to their respective conductive contacts by solder. In some embodiments, a thin cap of solder may be used in the intermetallic interconnects to accommodate planarity, and this solder may become intermetallic during processing. In some embodiments, the solder used in some or all of the DTD interconnects may have a higher melting point than the solder included in some or all of the DTPS interconnects. For example, if the DTD interconnects in the IC package are formed before the DTPS interconnects are formed, the solder-based DTD interconnects may use a higher temperature solder (e.g., having a melting point above 200 degrees Celsius), while the DTPS interconnects may use a lower temperature solder (e.g., having a melting point below 200 degrees Celsius). In some embodiments, the higher temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (e.g., eutectic tin bismuth), tin, silver, bismuth, indium, indium and tin, or gallium.

[0052] In some embodiments, the set of DTD interconnects may include anisotropic conductive materials, such as any of the materials discussed above for DTPS interconnects. In some embodiments, the DTD interconnects may be used as data transfer lanes, while the DTPS interconnects may be used for power and ground lines, among other things.

[0053] In a microelectronic assembly or IC package as described herein, some or all of the DTD interconnects may have a finer pitch than the DTPS interconnects. In some embodiments, the DTPS interconnects disclosed herein may have a pitch between about 80 microns and 300 microns, while the DTD interconnects disclosed herein may have a pitch between about 0.5 microns and 100 microns, depending on the type of DTD interconnect. An example of silicon-level interconnect density is provided by the density of some DTD interconnects. In some embodiments, the DTD interconnects may have a pitch that is too fine to bond directly to a package substrate (e.g., too fine to function as a DTPS interconnect). The DTD interconnects may have a smaller pitch than the DTPS interconnects due to the similarity of the materials between the different dies on either side of a set of DTD interconnects, which is higher than the similarity between the dies on either side of the set of DTD interconnects and the package substrate. In particular, differences in the material composition of the die and the package substrate can result in differential expansion and contraction of the die and the package substrate due to heat generated during operation (and heat applied during various manufacturing operations). To mitigate damage (e.g., cracks, solder bridges, etc.) caused by this differential expansion and contraction, the DTPS interconnects in any of the microelectronic assemblies or IC packages described herein may be formed larger and farther apart than the DTD interconnects, which may experience less thermal stress due to the greater material similarity of the die pair on either side of the DTD interconnect.

[0054] It will be appreciated that one or more levels of underfill (e.g., organic polymer materials such as benzotriazole, imidazole, polyimide, or epoxy) may be provided in the IC packages described herein and may not be labeled to avoid cluttering the drawings. In various embodiments, the levels of underfill may comprise the same or different insulating materials. In some embodiments, the levels of underfill may comprise a thermally cured epoxy with silicon oxide particles, while in some embodiments, the levels of underfill may comprise any suitable material capable of performing underfill functions such as supporting the die and reducing thermal stress on the interconnect. In some embodiments, the selection of the underfill material may be based on design considerations such as form factor, size, stress, operating conditions, etc.; in other embodiments, the selection of the underfill material may be based on material properties and processing conditions such as cure temperature, glass transition temperature, viscosity, and chemical resistance, among other factors; in some embodiments, the selection of the underfill material may be based on both design and processing considerations.

[0055] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photopolymer, dry film photopolymer, acrylic resin, solvent) may be provided in the IC packages described herein and may not be labeled or shown to avoid cluttering the drawings. The solder resist may be a liquid or dry film material including a photopolymer. In some embodiments, the solder resist may be non-photosensitive.

[0056] The terms "substantially," "close," "approximately," "near," and "about" generally refer to being within + / - 20% of a target value (e.g., within + / - 5% or 10% of a target value) based on the context of a particular value as described herein or as known in the art.

[0057] Terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, generally refer to within + / - 5% to 20% of a target value based on the context of the particular value as described herein or as known in the art.

[0058] The term "connected" means a direct connection (which may be one or more of a mechanical, electrical, and / or thermal connection) between the things being connected without any intermediate devices, while the term "coupled" means either a direct connection between the things being connected, or an indirect connection through one or more passive or active intermediate devices.

[0059] This specification uses the phrases "in an embodiment" or "in embodiments," which can each refer to one or more of the same or different embodiments.

[0060] Furthermore, the terms "comprising," "including," "having," and the like are synonymous when used in connection with embodiments of the present disclosure.

[0061] Although the present disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side," such descriptions are used for ease of discussion and are not intended to limit the application of the disclosed embodiments.

[0062] The terms "over," "under," "between," and "on," as used herein, refer to the relative location of one layer of material or component with respect to another layer or component. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Moreover, a layer disposed between two layers may be in direct contact with one or both of the two layers or may have one or more intervening layers. In contrast, a first layer described as being "on" a second layer refers to a layer that is in direct contact with the second layer. Similarly, unless explicitly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature or may have one or more intervening layers.

[0063] The term "dispose," as used herein, refers to a position, location, arrangement, and / or configuration, rather than any particular method of formation.

[0064] The term "between," when used in reference to measurement ranges, includes both ends of those measurement ranges.

[0065] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). As used herein, the designation "A / B / C" means (A), (B), and / or (C).

[0066] Although certain elements may be referred to in the singular herein, such elements may include multiple subelements. For example, a "conductive material" may include one or more conductive materials. As another example, a "dielectric material" may include one or more dielectric materials.

[0067] Unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third" to describe a common object indicates only that different instances of a similar object are being referred to and is not intended to imply that the objects so described must be in a given order, either temporally, spatially, in ranking, or in any other manner.

[0068] In the following detailed description, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0069] The accompanying drawings are not necessarily drawn to scale.

[0070] In the drawings, the same reference number refers to the same or similar elements / materials shown, so that, unless otherwise stated, a description of an element / material with a given reference number provided in the context of one of the drawings is applicable to other drawings in which the element / material with the same reference number may be shown. Furthermore, the singular and plural forms of a label may be used in conjunction with a reference number to indicate a single and a plurality, respectively, of elements of the same or similar type, species, or class.

[0071] Additionally, while in the drawings, schematic depictions of some of the example structures of the various devices and assemblies described herein may be shown with strict right angles and straight lines, it should be understood that such schematic depictions may not reflect the limitations of real-world processes, such that when any of the structures described herein are examined using images from a suitable characterization tool, such as, for example, a scanning electron microscopy (SEM) image, a transmission electron microscope (TEM) image, or a non-contact profilometer, features may appear less than “ideal.” In such images of actual structures, possible processing and / or surface imperfections, such as surface roughness, curvature or profile deviations, pits or scratches, less-than-perfectly straight edges of material, tapered vias or other openings, unintentional rounding of corners or variations in thickness of different material layers, accidental kinks, edges, or complex dislocations within crystalline regions, and / or accidental dislocation defects of single atoms or clusters of atoms, may also be visible. There may be other defects not listed here but which are common within the field of device manufacturing and / or packaging.

[0072] It should be noted that in the figures, various components (e.g., interconnects) are shown as aligned (e.g., at their respective interfaces) solely for ease of illustration; in reality, some or all of them may be misaligned. Additionally, there may be other components, such as bond pads, landing pads, metallization, etc., present in the assembly that are not shown in the figures to avoid complication. Furthermore, the figures are intended to show the relative placement of components within their assemblies; generally, such assemblies may include other components not shown (e.g., various interface layers or various other components related to optical functionality, electrical connectivity, or thermal mitigation). For example, in some further embodiments, assemblies such as those shown in the figures may include more dies along with other electrical components. Additionally, while some components of the assemblies are shown in the figures as being planar rectangular or formed from rectangular prisms, this is solely for ease of illustration, and these assembly embodiments may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes unavoidable due to, the manufacturing processes used to fabricate the various components.

[0073] In the drawings, specific numbers and arrangements of structures and components are presented for illustrative purposes; any desired number or arrangement of such structures and components may be presented in various embodiments.

[0074] Furthermore, unless otherwise specified, structures shown in the figures may take any suitable form or shape according to material properties, manufacturing processes, and operating conditions.

[0075] For convenience, where there is a collection of drawings designated with different letters (e.g., Figures 1A-1C), such collection may be referred to herein without the letter (e.g., as "Figure 1"). Similarly, where there is a collection of reference numbers designated with different numbers or letters (e.g., 104-1, 104-2, 104-3), such collection may be referred to herein without the number or letter (e.g., as "104").

[0076] Various operations may be described as multiple separate actions or operations, sequentially, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations need not be performed in the order presented. The operations described may be performed in a different order than in the described embodiment. Various additional operations may be performed and / or the operations described may be omitted in additional embodiments.

[0077] 1A is a schematic cross-sectional view of an exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The microelectronic assembly 100 includes multiple layers 102 (e.g., 102-1 and 102-2) of IC dies 104 (e.g., 104-1, 104-2, 104-3), with each layer 102 coupled to an adjacent layer 102 by an interconnect 106. In various embodiments, the interconnects 106 may be FLI with a pitch of less than 10 micrometers between adjacent interconnects. An example of an interconnect 106 in some embodiments is a hybrid bond including a metal-to-metal and a dielectric-to-dielectric bond. In the example shown in this figure, the number of layers 102 is two, i.e., a first layer 102-1 and a second layer 102-2. In various other embodiments, the microelectronic assembly 100 may include two or more layers 102. In some embodiments, each layer 102 may include an interface layer on either side (not shown for ease of illustration and to avoid cluttering the drawing), which interface layer includes the metallic and dielectric materials of the interconnect 106. The layers 102 may have a first surface 170-1 (e.g., a bottom surface) and an opposing second surface 170-2 (e.g., a top surface).

[0078] In various embodiments, one or more of the multiple layers 102 may include a dielectric material 108 around (e.g., between, around, etc.) the IC die 104. In the example shown, the layer 102-1 includes a first dielectric material 108-1 around the die 104-1, and the second layer 102-2 has a second dielectric material 108-2 around the IC dies 104-2, 104-3. The dielectric material 108-2 around the die 104-2 may include an interface seam 125 that extends from the second die 104-2 at the second surface 172-2 of the layer 102-2 toward the first surface 172-1 of the layer 102-2 and has an angle (θ) of less than 90 degrees with respect to the second surface of the layer 102-2. In some embodiments, the interface seam 125 may have an angle between 25 degrees and 65 degrees (e.g., between 35 degrees and 55 degrees) with respect to the second surface of the layer. As shown in FIG. 1A , the dielectric material 108-2 may include more than one interface seam 125 extending from the die 104-2, 104-3 at the second surface 172-2 of the layer 102-2 toward the first surface 172-1 of the layer 102-2 and forming an angle of less than 90 degrees with respect to the second surface of the layer 102-2. In other embodiments where a greater number of layers 102 are present, the dielectric material 108 in other layers may include an interface seam 125 extending from the IC die 104 at the second surface of the layer 102 toward the first surface of the layer 102 and forming an angle of less than 90 degrees with respect to the second surface of the respective layer. The interface seams 125 may be formed as described below with reference to FIGS. 6A-6H . In other embodiments where a greater number of layers 102 are present, the dielectric material 108 may not be present around the IC die 104 in one or more such layers 102. One or more through-dielectric vias (TDVs) 110 may be present in the dielectric material 108 in the layer 102. In various embodiments, the dielectric material 108 comprises an inorganic material, such as silicon and one or more of oxygen, nitrogen, hydrogen, and carbon (e.g., in the form of silicon oxide, silicon nitride, or silicon carbide), and / or other forms of inorganic dielectric materials typically used as interlayer dielectrics (ILDs) in semiconductor devices.

[0079] A substrate 112 may be coupled to the second surface 170-2 of the plurality of layers 102. In some embodiments, the substrate 112 may comprise a structurally rigid and thermally conductive base, such as silicon, that may provide mechanical support and stability to the plurality of layers 102. In various embodiments, the substrate 112 may comprise a wafer of silicon cut to a suitable size to fit above the layer 102. The substrate 112 may be coupled to the second surface 170-2 of the layer 102-2 by a fusion bond (i.e., a dielectric-to-dielectric bond without a metal-to-metal bond at the interface). In some embodiments, as shown in FIG. 1A, the substrate 112 may not include devices and / or metal traces. In other embodiments (e.g., as shown in FIG. 3), the substrate 112 may include devices and / or metal traces such that the substrate 112 is electrically coupled to the second surface 170-2 of the second layer 102-2 by an interconnect (e.g., interconnect 106).

[0080] In some embodiments (as shown), one or more IC dies 104 (e.g., 104-1) in some layers 102 (e.g., 102-1) may include through-substrate vias (TSVs) 122. The TSVs 122 may be configured to maintain power, signal, and / or ground connections between the package substrate 118 and the IC dies 104 in the layers 102. In various embodiments, one or more IC dies 104 in the microelectronic assembly 100 may include different types of conductive traces, such as conductive traces configured to carry power and conductive traces configured to carry signals, having different dimensions (e.g., conductive traces configured to carry power may generally be larger (e.g., thicker, wider) than conductive traces configured to carry signals). The conductive traces may reside in a metallization stack 116 having multiple metal layers through insulators fabricated using known semiconductor manufacturing processes. In some embodiments, the insulator material in the metallization stack may be the same as that of the dielectric material 108 around the IC die 104; in other embodiments, the insulator material in the metallization stack may be different from that of the dielectric material 108 around the IC die 104.

[0081] In the exemplary embodiment shown in this figure, the metallization stacks 116 of the IC die 104 are face-to-face (e.g., the metallization stacks 116 of the IC die 104-1 face toward and are coupled to the metallization stacks 116 of the IC die 104-2, 104-3). In other embodiments, the metallization stacks 116 of the IC die 104 are face-to-back (not shown) (e.g., the metallization stacks 116 of the IC die 104-1 may face away from the metallization stacks 116 of the IC die 104-2, 104-3 such that the IC die 104-2, 104-3 are coupled to the TSVs 122 of the IC die 104-1).

[0082] 1B is a schematic cross-sectional view of details of one particular one of the interconnects 106 in the microelectronic assembly 100. Note that while only the interconnect 106 is shown, the same structure and description may apply, where applicable, to any other such interconnect, including hybrid bonds, in the microelectronic assembly 100. In a general sense, the interconnect 106 may include a metal-to-metal bond between a bond pad 132 of the layer 102-1 and a bond pad 134 of the layer 102-2 at the interface 130 between the layers 102-1 and 102-2, and a dielectric-to-dielectric bond (e.g., an oxide-to-oxide bond) in the dielectric material 109 of the layers 102-1 and 102-2. In some embodiments, a structure such as that shown in this figure may be present in an interface layer between the layers 102-1 and 102-2 (e.g., bonding layer 124 in FIGS. 6A-6H). In other embodiments, structures such as those shown in this figure may be present in the IC die 104 of each layer. In still other embodiments, some structures such as those shown in this figure may be present in the IC die 104 of one of the layers, and other structures may be present on the outside / around the IC die 104 of another of the layers. Bond pad 132 of layer 102-1 may bond with bond pad 134 of layer 102-2. Dielectric materials 109 (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.) in layers 102-1 and 102-2 may bond to each other. In some embodiments, dielectric material 109 may be the same material as dielectric material 108. The bonded metal and dielectric materials form interconnect 106, including hybrid bonds, providing electrical and mechanical coupling between layers 102-1 and 102-2. In various embodiments, the interconnects 106 may have linear dimensions of less than 5 micrometers and a pitch between adjacent interconnects of less than 10 micrometers.

[0083] FIG. 1C is a schematic cross-sectional view of a particular detail of one of the TDVs 110 in the microelectronic assembly 100. As shown in FIG. 1A, the TDV 110 may be included in the layer 102-1 adjacent to the IC die 104-1. The layer 102-1 may include a first surface 171-1 and an opposite second surface 171-2. The TDV 110 may extend from the first surface 171-1 to the second surface 171-2 of the layer 102-1 through the dielectric material 108. The TDV 110 may have a tapered or conical shape. The TDV 110 may have a larger width 191-1 (e.g., in the y dimension) at the first surface 171-1 of the layer 102-1 and a smaller width 191-2 at the second surface. Although FIG. 1A shows TDV 110 included only in layer 102-1, any layer 102 (e.g., layer 102-2) may include TDV 110 having a width 191-1 toward first surface 171-1 that is greater than width 191-2 toward second surface 171-2.

[0084] Referring back to FIG. 1A , the package substrate 118 may include conductive paths (not shown) through the organic dielectric material. The conductive paths may include conductive traces connected by conductive vias. The package substrate 118 may further include bond pads, redistribution layers, substrate cores, passive components, and other elements, which are not shown by way of limitation and solely for ease of illustration. The package substrate 118 may be coupled to the first surface 170-1 of the plurality of layers 102 by SLIs 142 (e.g., DTPS interconnects such as flip-chip solder bonds). In various embodiments, the SLIs 142 may have a pitch greater than 10 micrometers between adjacent interconnects. An underfill material 127 may be disposed around the SLIs 142. The underfill process may include dispensing the underfill material in liquid form, allowing the material to flow and fill the interstitial gaps around the SLIs 142, and subjecting the assembly to a curing process, such as baking, to solidify the material.

[0085] FIG. 2 is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of FIG. 1A, except for differences as will be further described. The configuration of the microelectronic assembly 100 as described herein is a quasi-monolithic package architecture. The substrate 112 in a conventional quasi-monolithic package architecture typically includes a silicon substrate with no devices or metal traces, and the interface to this structural silicon is a fusion bond (i.e., a dielectric-to-dielectric bond without a metal-to-metal bond at the interface, as shown in FIG. 1A). In contrast, in the embodiment as described herein, the substrate 112 may be electrically coupled to the second surface 170-2 of the plurality of layers 102 by the interconnect 107. The interface 130 between the substrate 112 and the second surface 170-2 of the plurality of layers 102 may include metal-to-metal and dielectric-to-dielectric bonds as described in FIG. 1B. In some embodiments, conductive traces (not shown) may be disposed on the substrate 112 proximate the second surfaces 170-2 of the layers 102 and electrically coupled to the second surfaces 170-2 of the layers 102 by the interconnects 107. The interconnects 107 may improve the thermal performance of the microelectronic assembly 100 by dissipating heat therethrough. In some embodiments, the interconnects 107 may be the same type and pitch as the interconnects 106. In other embodiments, the interconnects 107 may have different dimensions and pitch than the interconnects 106. In other embodiments, the top substrate 112 may include active devices such as memory or processing logic.

[0086] FIG. 3 is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of FIG. 2, except for differences as will be further described. The substrate 112 may further include a metallization stack 116 having multiple metal layers (e.g., conductive paths formed by conductive vias and conductive traces) through an insulator electrically coupled to the second surfaces 170-2 of the multiple layers 102 by interconnects 107. The interface 130 between the substrate 112 and the second surfaces 170-2 of the multiple layers 102 may include metal-to-metal and dielectric-to-dielectric bonds as described in FIG. 1B. In some embodiments, the substrate 112 may further include a device such as a capacitor. In some embodiments, IC dies 104-2, 104-3 may be double-sided dies (e.g., having metallization stacks on opposite sides or having TSVs 122 similar to IC die 104-1), and substrate 112 may be electrically coupled to transmit signals between IC dies 104-2, 104-3.

[0087] FIG. 4 is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of FIG. 1A , except for differences as will be further described. The IC dies 104 in layer 102-2 may include multiple IC dies 104 stacked vertically and electrically coupled by interconnects 106. As shown in FIG. 4 , IC dies 104-4 and 104-5 may include TSVs 122 and may be electrically coupled to IC die 104-1 on their bottom surfaces by interconnects 106-1 and to IC dies 104-6 and 104-7 on their top surfaces by interconnects 106-2, respectively. The stacked IC dies (e.g., IC dies 104-4 and 104-6 and IC dies 104-5 and 104-7) may be pre-assembled before being integrated into microelectronic assembly 100.

[0088] 5 is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of FIG. 1A, except for differences as will be further described. The microelectronic assembly 100 includes multiple layers 102 (e.g., 102-1, 102-2, 102-3) of IC dies 104 (e.g., 104-1, 104-2, 104-3, 104-8, 104-9), each layer 102 coupled to an adjacent layer 102 by an interconnect 106. In the example shown in this figure, the number of layers 102 is three: a first layer 102-1 having a first surface 171-1 and an opposing second layer 171-2; a second layer 102-2 at the second surface 171-2 of the first layer 102-1; and a third layer 102-3 at the first surface 171-1 of the first layer 102-1. In some embodiments, each layer 102 may include an interface layer on either side, which includes the metallic and dielectric materials of the interconnects 106. In various embodiments, one or more of the layers 102 may include a dielectric material 108 around (e.g., between, around, etc.) the IC die 104. In the example shown, layer 102-1 includes dielectric material 108 around die 104-1, layer 102-2 has dielectric material 108 around IC dies 104-2 and 104-3, and layer 102-3 has dielectric material 108 around IC dies 104-8 and 104-9. The dielectric material 108 around the dies 104-8, 104-9 may include an interface seam 125 extending from the die 104-2 at the second surface 173-2 of the layer 102-3 toward the first surface 173-1 of the layer 102-3 and having an angle of less than 90 degrees with respect to the second surface of the layer 102-3. The interface seam 125 may have an angle of between 25 degrees and 65 degrees (e.g., between 35 degrees and 55 degrees) with respect to the second surface of the layer. As shown in FIG. 5, the dielectric material 108 may include more than one interface seam 125 extending from the dies 104-8, 104-9 at the second surface 173-2 of the layer 102-3 toward the first surface 173-1 of the layer 102-3 and having an angle of less than 90 degrees with respect to the second surface of the layer 102-3. The interface seam 125 may be formed as described below with reference to FIGS. 6A-6H.In some embodiments, all layers 102 of the IC die 104 may include an interfacial seam 125. In some embodiments, only one layer 102 of the IC die 104 may include an interfacial seam 125.

[0089] Any suitable technique may be used to fabricate the microelectronic assembly 100 disclosed herein. For example, FIGS. 6A-6H are side cross-sectional views of various stages in an example process for fabricating the microelectronic assembly 100 of FIG. 1A, according to various embodiments. Although the operations discussed below with reference to FIGS. 6A-6H (and other accompanying figures depicting the fabrication process) are shown in a particular order, these operations may be performed in any suitable order. Moreover, additional operations not shown may be performed without departing from the scope of the present disclosure. Also, various of the operations discussed herein with respect to FIGS. 6A-6H may be modified in accordance with the present disclosure to fabricate the other microelectronic assemblies 100 disclosed herein.

[0090] 6A shows the assembly after mounting the IC dies 104-2, 104-3 on the substrate 112 with the metallization stack 116 facing away from the substrate 112. Any suitable method, such as automated pick-and-place, may be used to position the IC dies 104-2, 104-3. The substrate 112 may comprise any suitable material to provide mechanical stability during manufacturing operations and use, and in some embodiments, may comprise silicon. In some embodiments, the IC dies 104-2, 104-3 may be coupled to the substrate 112 by fusion bonding. In some embodiments, the IC dies 104-2, 104-3 may be electrically coupled to the substrate 112 by interconnects, such as interconnect 107 in FIG. 2.

[0091] 6B shows the assembly during deposition of dielectric material 108 on the top surfaces of the assembly (e.g., on the top and side surfaces of IC dies 104-2, 104-3 and on the top surface of substrate 112). Interfacial seam 125 may be formed by depositing dielectric material 108 on the surfaces of dies 104-2, 104-3 and on the surface of substrate 112. Dielectric material 108 may be deposited using any suitable technique, such as chemical vapor deposition, physical vapor deposition, or plasma-enhanced chemical vapor deposition, among others. In some embodiments, dielectric material 108 may be dispensed in liquid form to flow through and conform to various shapes of components and metallizations, and then may be subjected to a process, e.g., curing, that solidifies dielectric material 108. In other embodiments, the dielectric may be deposited and then reflowed to improve its planarity for subsequent processing.

[0092] 6C shows the assembly after depositing dielectric material 108 throughout and between IC dies 104-2, 104-3 and on substrate 112, and planarizing the top surface of the assembly to remove the dielectric material above the IC dies. The top surface of the assembly may be planarized to remove dielectric 108 using any suitable technique, such as grinding or etching, followed by chemical mechanical polishing (CMP).

[0093] Figure 6D shows the assembly of Figure 6C after forming a bonding layer 124 on the top surface thereof. The bonding layer 124 may include bond pads 134 in the dielectric material 109 that correspond to the bond pads 132 as described above with reference to Figure 1B for forming a hybrid direct bond (e.g., the interconnect 106 as shown in Figure 6E).

[0094] FIG. 6E shows the assembly after attaching the IC die 104-1, which may include TSVs 122, to the bonding layer 124 to form the interconnects 106. The assembly of FIG. 6E may be subjected to a suitable bonding process to form the interconnects 106. For example, the bonding process may include applying suitable pressure and heating to a suitable temperature (e.g., to a moderately high temperature, e.g., between about 50 and 400 degrees Celsius) for a duration of time. In some embodiments, a bonding material may be applied at the interface between the IC die 104-1 and the bonding layer 124. In some embodiments, the bonding material may be an adhesive that ensures attachment of the IC die 104-1 to the bonding layer 124. In other embodiments, the bonding material may be an etch-stop material. In yet other embodiments, the bonding material may be an etch-stop material and have suitable adhesive properties to ensure attachment of the IC die 104-1 to the bonding layer 124. In still other embodiments, no bonding material may be used.

[0095] 6F illustrates the assembly of FIG. 6E after disposing dielectric material 108 on the top surface thereof (e.g., on and around the top surfaces of IC die 104-1 and bonding layer 124). In some embodiments, dielectric material 108 around IC die 104-1 may be the same material as dielectric material 108 around IC dies 104-2, 104-3. In some embodiments, dielectric material 108 around IC die 104-1 may be a different material than dielectric material 108 around IC dies 104-2, 104-3. Any suitable technique may be used to deposit dielectric material 108, such as the operations described above with reference to FIGS. 6B and 6C, including forming interfacial seam 125.

[0096] FIG. 6G shows the assembly after forming via openings through the dielectric material 108, depositing a conductive material, such as a metal, in the openings to form TDVs 110, and planarizing the top surface of the assembly to remove the dielectric material 108 and expose the top surfaces of the TDVs 110 and TSVs 122 in IC die 104-1 to form layer 102-1. The TDVs 110 may be electrically coupled to bond pads 134 in bonding layer 124. The top surface of the assembly may be planarized using any suitable technique, such as grinding or chemical-mechanical polishing (CMP). The via openings may be formed using any suitable technique, such as laser drilling, where the via openings have a tapered or conical shape. The processes described in FIGS. 6A-6F, or portions thereof, may be repeated any number of times as desired to fabricate a microelectronic assembly 100 including any number of layers 102 and any number of IC dies 104 within individual layers 102.

[0097] FIG. 6H shows the assembly of FIG. 6G after inverting it and performing finishing operations on the bottom surface of the assembly, such as forming conductive contacts 144, depositing solder resist (not shown), and depositing solder 145 on the bottom surface of the conductive contacts 144. When multiple assemblies are fabricated together, the assemblies may be singulated. The assembly of FIG. 6H may itself be the microelectronic assembly 100, as shown. Further fabrication operations may be performed on the microelectronic assembly 100 of FIG. 6H to form other microelectronic assemblies 100; for example, solder 145 may be used to bond the microelectronic assembly 100 of FIG. 6H to a package substrate 118, similar to the microelectronic assembly 100 of FIG. 1A.

[0098] 7 is a flow diagram of an example method of manufacturing an example microelectronic assembly, according to various embodiments. At 702, second layer IC dies 104-2, 104-3 may be attached to substrate 112. IC dies 104-2, 104-3 may include metallization stacks 116 facing away from substrate 112. IC dies 104-2, 104-3 may be bonded to substrate 112 using any suitable technique, including forming fusion bonds or hybrid direct bonds.

[0099] At 704, dielectric material 108 is deposited on and around the IC second layer dies 104-2, 104-3 and substrate 112. The dielectric material 108 may be deposited using any technique and may be formed with an interfacial seam 125. The top surface of the dielectric material 108 may be planarized using CMP or any other suitable process to expose the bond pads 134 on the IC dies 104-2, 104-3.

[0100] At 706, a bonding layer 124 may be formed on the top surfaces of the IC dies 104-2, 104-3 and the dielectric layer 108. The bonding layer 124 may include bond pads 134 surrounded by a dielectric material 109.

[0101] At 708, the first layer IC die 104-1 may be attached to the top surface of the bonding layer 124. Interconnects 106 are formed to electrically couple the IC die 104-1 to the IC dies 104-2, 104-3. Any suitable bonding process may be used to form the interconnects 106, such as applying a suitable pressure and heating to a suitable temperature for a duration.

[0102] At 710, dielectric material 108 may be disposed over and around the top surfaces of IC die 104-1 and bonding layer 124 to form TDV 110. Dielectric material 108 may be deposited using any technique and may be formed with an interfacial seam 125. The top surfaces of dielectric material 108 and / or TDV 110 may be planarized using CMP or any other suitable process.

[0103] At 712, the assembly may be singulated, inverted, and surface finishing operations may be performed. In some embodiments, surface finishing operations may be performed prior to singulation. Surface finishing operations may include, for example, forming conductive contacts 144, dispensing solder resist, and attaching solder balls 145 on the bottom surface.

[0104] Any of the packages disclosed herein, such as microelectronic assembly 100, or any further embodiments described herein, may be included in any suitable electronic component. Figures 8-10 show various examples of packages, assemblies, and devices that may be used with or include any of the IC packages as disclosed herein.

[0105] 8 is a cross-sectional side view of an example IC package 2200, which may include an IC package according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a SiP.

[0106] As shown in this figure, package substrate 2252 may be formed from an insulator (e.g., ceramic, build-up film, epoxy film with filler particles therein, etc.) and may have conductive paths extending through the insulator between first surface 2272 and second surface 2274, or between different locations on first surface 2272 and / or different locations on second surface 2274. These conductive paths may take the form of any of an interconnect structure including lines and / or vias.

[0107] Package substrate 2252 may include conductive contacts 2263 coupled to conductive paths 2262 through package substrate 2252, allowing circuitry within die 2256 and / or interposer 2257 to be electrically coupled to various of the conductive contacts 2264 (or to other devices (not shown) included in package substrate 2252).

[0108] IC package 2200 may include an interposer 2257 coupled to a package substrate 2252 via conductive contacts 2261 of the interposer 2257, first level interconnects 2265, and conductive contacts 2263 of the package substrate 2252. The first level interconnects 2265 shown in this figure are solder bumps, although any suitable first level interconnects 2265 may be used, such as solder bumps, solder posts, or bond wires.

[0109] IC package 2200 may include one or more dies 2256 coupled to an interposer 2257 via conductive contacts 2254 of die 2256, first level interconnects 2258, and conductive contacts 2260 of interposer 2257. Conductive contacts 2260 may be coupled to conductive paths (not shown) through interposer 2257, allowing circuitry within die 2256 to be electrically coupled to various of the conductive contacts 2261 (or to other devices (not shown) included in interposer 2257). The first level interconnects 2258 shown in this figure are solder bumps, although any suitable first level interconnects 2258 may be used, such as solder bumps, solder posts, or bond wires. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., a metal) that serves as an interface between different components; a conductive contact may be recessed in, flush with, or extend away from the surface of a component and may take any suitable form (e.g., a conductive pad or socket).

[0110] In some embodiments, underfill material 2266 may be disposed between package substrate 2252 and interposer 2257 around first level interconnect 2265, and molding 2268 may be disposed around die 2256 and interposer 2257 and in contact with package substrate 2252. In some embodiments, underfill material 2266 may be the same as molding 2268. An exemplary material that may be used as suitable for underfill material 2266 and molding 2268 is epoxy. Second level interconnect 2270 may be coupled to conductive contacts 2264. The second level interconnect 2270 shown in this figure is a solder ball (e.g., for a ball grid array (BGA) arrangement), although any suitable second level interconnect 2270 (e.g., a pin in a pin grid array arrangement or a land in a land grid array arrangement) may be used. Second level interconnect 2270 may be used to couple IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and discussed below with reference to FIG. 9.

[0111] In various embodiments, any of the dies 2256 may be a microelectronic assembly 100 as described herein. In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry for performing any desired function. For example, in addition to one or more of the dies 2256 being a microelectronic assembly 100 as described herein, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), one or more of the dies 2256 may be memory dies (e.g., HBM), etc. In some embodiments, any of the dies 2256 may be implemented as discussed with reference to any of the preceding figures. In some embodiments, at least some of the dies 2256 may not include an implementation as described herein.

[0112] Although the IC package 2200 shown in this figure is a flip-chip package, other package architectures may be used. For example, the IC package 2200 may be a BGA package such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200, the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors, disposed above the first side 2272 or the second side 2274 of the package substrate 2252, or on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0113] In some embodiments, interposer 2257 may not be included in IC package 2200; instead, die 2256 may be directly coupled to conductive contacts 2263 on first surface 2272 by first level interconnect 2265.

[0114] 9 is a cross-sectional side view of an IC device assembly 2300 that may include components having one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein. The IC device assembly 2300 includes multiple components disposed above a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed above a first side 2340 of the circuit board 2302 and on an opposite second side 2342 of the circuit board 2302; generally, components may be disposed above one or both sides 2340 and 2342. In particular, any suitable ones of the components of the IC device assembly 2300 may include any of one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein; for example, any of the IC packages discussed below with reference to the IC device assembly 2300 may take the form of any of the embodiments of the IC package 2200 discussed above with reference to FIG. 8.

[0115] In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from each other by layers of insulation and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between components coupled to circuit board 2302. In other embodiments, circuit board 2302 may be a non-PCB package substrate.

[0116] As shown in this figure, in some embodiments, IC device assembly 2300 may include a package-on-interposer structure 2336 coupled to a first surface 2340 of circuit board 2302 by coupling components 2316. Coupling components 2316 may electrically and mechanically couple package-on-interposer structure 2336 to circuit board 2302 and may include solder balls (as shown), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0117] Package-on-interposer structure 2336 may include an IC package 2320 coupled to interposer 2304 by a coupling component 2318. Coupling component 2318 may take any suitable form depending on the desired functionality, such as those discussed above with reference to coupling component 2316. In some embodiments, IC package 2320 may be or include IC package 2200, for example, as described above with reference to FIG. 8. In some embodiments, IC package 2320 may include at least one microelectronic assembly 100 as described herein. Microelectronic assembly 100 is not specifically shown in this figure to avoid overcomplicating the drawing.

[0118] Although a single IC package 2320 is shown in this figure, multiple IC packages may be coupled to the interposer 2304; in fact, additional interposers may be coupled to the interposer 2304. The interposer 2304 may provide an intermediate package substrate used to bridge the circuit board 2302 and the IC package 2320. In general, the interposer 2304 may rewire connections to a wider pitch or reroute certain connections to different connections. For example, the interposer 2304 may couple the IC package 2320 to a BGA of the mating component 2316 for coupling to the circuit board 2302.

[0119] In the embodiment shown in this figure, IC package 2320 and circuit board 2302 are mounted on opposite sides of interposer 2304. In other embodiments, IC package 2320 and circuit board 2302 may be mounted on the same side of interposer 2304. In some embodiments, three or more components may be interconnected by interposer 2304.

[0120] The interposer 2304 may be formed from a polymeric material such as epoxy, fiberglass-reinforced epoxy, ceramic material, or polyimide. In some implementations, the interposer 2304 may be formed from alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including, but not limited to, TSVs 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.

[0121] In some embodiments, IC device assembly 2300 may include an IC package 2324 coupled to a first surface 2340 of circuit board 2302 by a coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0122] In some embodiments, IC device assembly 2300 may include a package-on-package structure 2334 coupled to second surface 2342 of circuit board 2302 by coupling component 2328. Package-on-package structure 2334 may include IC package 2326 and IC package 2332 coupled together by coupling component 2330 such that IC package 2326 is disposed between circuit board 2302 and IC package 2332. Coupling components 2328 and 2330 may take the form of any of the embodiments of coupling component 2316 discussed above, and IC package 2326 and / or 2332 may take the form of any of the embodiments of IC package 2320 discussed above. Package-on-package structure 2334 may be configured according to any of the package-on-package structures known in the art.

[0123] 10 is a block diagram of an example computing device 2400 that may include one or more components having one or more IC packages according to any of the embodiments disclosed herein. For example, any suitable ones of the components of computing device 2400 may include a microelectronic assembly (e.g., 100) according to any of the embodiments disclosed herein. In another example, any one or more of the components of computing device 2400 may include any embodiment of IC package 2200 (e.g., as shown in FIG. 8). In yet another example, any one or more of the components of computing device 2400 may include IC device assembly 2300 (e.g., as shown in FIG. 9).

[0124] While many components are shown in this figure as being included in computing device 2400, any one or more of these components may be omitted or duplicated as appropriate for the present application. In some embodiments, some or all of the components included in computing device 2400 may be mounted on one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SoC die.

[0125] Additionally, in various embodiments, computing device 2400 may not include one or more of the components shown in this figure, but may include interface circuitry for coupling to one or more components. For example, computing device 2400 may not include display device 2406, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 2406 may be coupled. In another set of examples, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which audio input device 2418 or audio output device 2408 may be coupled.

[0126] Computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the terms “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory. Processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptoprocessors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. Computing device 2400 may include memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, memory 2404 may include memory that shares a die with processing device 2402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0127] In some embodiments, computing device 2400 may include a communications chip 2412 (e.g., one or more communications chips). For example, communications chip 2412 may be configured to manage wireless communications for the transfer of data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. This term does not imply that the associated device does not include any wires, although in some embodiments this may not be the case.

[0128] The communications chip 2412 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), the IEEE 802.16 standard (e.g., the IEEE 802.16-2005 amendment), any amendments, updates, and / or revisions (e.g., the LTE project with the Advanced LTE project, the Ultramobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed IEEE 802.16 standard compliance and interoperability testing. The communications chip 2412 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.The communications chip 2412 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications chip 2412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. The communications chip 2412 may operate according to other wireless protocols in other embodiments. Computing device 2400 may include an antenna 2422 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmissions).

[0129] In some embodiments, the communications chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (e.g., Ethernet). As noted above, the communications chip 2412 may include multiple communications chips. For example, a first communications chip 2412 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications chip 2412 may be dedicated to longer-range wireless communications, such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communications chip 2412 may be dedicated to wireless communications and the second communications chip 2412 may be dedicated to wired communications.

[0130] Computing device 2400 may include battery / power circuitry 2414. Battery / power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 2400 to an energy source (e.g., AC line power) separate from computing device 2400.

[0131] Computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above), which may include any visual indicator, such as, for example, a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0132] The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry as discussed above), which may include any device that produces an audible indicator, such as, for example, a speaker, a headset, or earbuds.

[0133] The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry as discussed above), which may include any device that generates signals representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a musical instrument digital interface (MIDI) output).

[0134] The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry as discussed above), which may communicate with a satellite-based system, as known in the art, and may receive the location of the computing device 2400.

[0135] The computing device 2400 may include other output devices 2410 (or corresponding interface circuitry as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0136] The computing device 2400 may include other input devices 2420 (or corresponding interface circuitry as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an imaging device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0137] Computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), desktop computing device, server or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, computing device 2400 may be any other electronic device that processes data.

[0138] The above description of illustrated implementations of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. While specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the art will recognize.

[0139] Example 1 includes a first die in a first layer, the first layer having a first surface and an opposite second surface, the first die being surrounded by a dielectric material; a through-dielectric via (TDV) in the first layer, the TDV having a greater width toward the first surface of the first layer and a smaller width toward the second surface of the first layer; a second die in a second layer, the second layer having a first surface and an opposite second surface, the first surface of the second layer being at the second surface of the first layer, , the first die is electrically coupled to the second die by interconnects having a pitch of less than 10 microns between adjacent interconnects, wherein the second die is surrounded by the dielectric material and includes an interface seam at the second surface of the second layer extending from the second die toward the first surface of the second layer, the interface seam having an angle of less than 90 degrees with respect to the second surface of the second layer; and a substrate coupled to the second surface of the second layer.

[0140] Example 2 may include the subject matter of Example 1 and may further specify that the dielectric material includes silicon and one or more of nitrogen, oxygen, hydrogen, and carbon; a polyimide material; or a low-k or ultra-low-k dielectric.

[0141] Example 3 may include the subject matter of Examples 1 or 2, and may further specify that the dielectric material in the first layer is a first dielectric material and the dielectric in the second layer is a second dielectric material different from the first dielectric material.

[0142] Example 4 may include the subject matter of any of Examples 1-3, and may further specify that the angle of the interface seam is between 35 degrees and 55 degrees relative to the second surface of the second layer.

[0143] Example 5 may include the subject matter of any of Examples 1-4, and may further specify that the interfacial seam is a first interfacial seam, and the dielectric material in the second layer further includes a second interfacial seam extending from the second die at the second surface of the second layer toward the first surface of the second layer, and the second interfacial seam has an angle of less than 90 degrees with respect to the second surface of the second layer.

[0144] Example 6 may include the subject matter of Example 5, and may further specify that the angle of the second interface seam is between 35 degrees and 55 degrees relative to the second surface of the second layer.

[0145] Example 7A may include the subject matter of any of Examples 1-6, and may further specify that the TDV is electrically coupled to the second die.

[0146] Example 7B may include the subject matter of any of Examples 1-6 and may further specify that the TDV is one of a plurality of TDVs.

[0147] Example 8 may include the subject matter of any of Examples 1-7, and may further include a package substrate electrically coupled to the first surface of the first layer by a solder interconnect.

[0148] Example 9 may include the subject matter of Example 8 and may further specify that the TDV is electrically coupled to the package substrate at a first end and electrically coupled to the second die at an opposite second end.

[0149] Example 10 may include the subject matter of any of Examples 1-9 and may further specify that the substrate material includes silicon.

[0150] Example 11 includes a first layer having a first surface and an opposite second surface, the first layer having a first die, a dielectric material around the first die, and a through-dielectric via (TDV), wherein the TDV has a greater width toward the first surface of the first layer and a smaller width toward the second surface of the first layer; and a second layer having a first surface and an opposite second surface, the first surface of the second layer being at the second surface of the first layer, the second layer having a second die, a third die, and the dielectric material around and between the second and third dies, wherein the first die is electrically coupled to the second and third dies by interconnects having a pitch of less than 10 microns between adjacent interconnects, wherein the TDV is electrically coupled to the second die, and wherein the dielectric material between the second and third dies includes an interfacial seam extending from the second die at the second surface of the second layer to the third die at the first surface of the second layer, the interfacial seam having an angle of less than 90 degrees with respect to the second surface of the second layer.

[0151] Example 12 may include the subject matter of Example 11, and may further specify that the dielectric material includes silicon and one or more of nitrogen, oxygen, hydrogen, and carbon; a polyimide material; or a low-k or ultra-low-k dielectric.

[0152] Example 13 may include the subject matter of Examples 11 or 12, and may further specify that the dielectric material in the first layer is a first dielectric material and the dielectric in the second layer is a second dielectric material different from the first dielectric material.

[0153] Example 14 may include the subject matter of any of Examples 11-13, and may further specify that the angle of the interface seam is between 35 degrees and 55 degrees relative to the second surface of the second layer.

[0154] Example 15 may include the subject matter of any of Examples 11-14, and may further specify that the interfacial seam is a first interfacial seam, and the dielectric material between the second and third die further includes a second interfacial seam extending from the third die at the second surface of the second layer toward the second die at the first surface of the second layer, and the second interfacial seam has an angle of less than 90 degrees with respect to the second surface of the second layer.

[0155] Example 16 may include the subject matter of Example 15, and may further specify that the angle of the second interface seam is between 35 degrees and 55 degrees relative to the second surface of the second layer.

[0156] Example 17 may include the subject matter of any of Examples 11-16, and may further specify that the TDV is one of a plurality of TDVs.

[0157] Example 18 can include the subject matter of any of Examples 11-17, and can further include a package substrate electrically coupled to the first surface of the first layer by a solder interconnect.

[0158] Example 19 can include the subject matter of any of Examples 11-18, and can further include a substrate coupled to the second surface of the second layer.

[0159] Example 20 may include the subject matter of Example 19, and may further specify that the substrate material includes silicon.

[0160] Example 21 may include the subject matter of Example 19, and may further specify that the substrate is bonded to the second surface of the second layer.

[0161] Example 22 may include the subject matter of Example 19, and may further specify that the substrate is coupled to the second die by second interconnects having a pitch of less than 10 microns between adjacent second interconnects.

[0162] Example 23 may include the subject matter of Example 22, and may further specify that the substrate further comprises a conductive path, the conductive path being electrically coupled to the second die by the second interconnect.

[0163] Example 24 may include the subject matter of Example 23 and may further specify that the conductive paths in the substrate are further electrically coupled to the third die by third interconnects having a pitch of less than 10 microns between adjacent third interconnects.

[0164] Example 25 includes a first die in a first layer, the first layer having a first surface and an opposite second surface, the first die being surrounded by a dielectric material; a through-dielectric via (TDV) in the first layer, wherein the TDV has a greater width toward the first surface of the first layer and a smaller width toward the second surface of the first layer; a second die in a second layer, the second layer having a first surface and an opposite second surface, wherein the first surface of the second layer is at the second surface of the first layer, and wherein the first die is between adjacent first interconnects. a substrate coupled to the second surface of the second layer; and a packaging substrate electrically coupled to the first surface of the first layer by a first interconnect having a pitch of less than 10 microns at 1000 .mu.m, wherein the second die is surrounded by the dielectric material and includes an interfacial seam extending from the second die at the second surface of the second layer toward the first surface of the second layer, the interfacial seam oriented at an angle of less than 90 degrees relative to the second surface of the second layer; a substrate coupled to the second surface of the second layer; and a packaging substrate electrically coupled to the first surface of the first layer by the second interconnect.

[0165] Example 26 may include the subject matter of Example 25, and may further specify that the substrate material includes silicon.

[0166] Example 27 may include the subject matter of Example 25 or 26, and may further specify that the substrate is bonded to the second surface of the second layer.

[0167] Example 28 may include the subject matter of Examples 25 or 26, and may further specify that the substrate is coupled to the second die by second interconnects having a pitch of less than 10 microns between adjacent second interconnects.

[0168] Example 29 may include the subject matter of Example 28, and may further specify that the substrate further comprises a conductive path, the conductive path being electrically coupled to the second die by the second interconnect.

[0169] Example 30 includes bonding a second die and a third die to a substrate, wherein the second die and the third die have first surfaces and opposing second surfaces having conductive contacts, wherein the first surfaces of the second and third dies face away from the substrate; depositing a dielectric material around and between the second and third dies to expose the conductive contacts, wherein depositing the dielectric material around and between the second and third dies includes forming an interfacial seam between the second and third dies, wherein the interfacial seam is formed by bonding the second and third dies to the substrate. a first die extending from a second surface of the first die toward the first surface of the third die, wherein the interfacial seam has an angle of less than 90 degrees with respect to the substrate; attaching the first die to the second and third dies by forming interconnects to electrically couple conductive contacts of the first die to the conductive contacts of the second and third dies, wherein the interconnects have a pitch of less than 10 microns between adjacent interconnects; and depositing the dielectric material around the first die.

[0170] Example 31 may include the subject matter of Example 30, and may further specify that forming the interconnect further comprises forming an interface layer having bond pads and a dielectric material on the second and third dies, and forming metal-to-metal bonds and dielectric-to-dielectric bonds with the interface layer.

[0171] Example 32 may include the subject matter of Examples 30 or 31, and may further specify that depositing the dielectric material around and between the second and third die further includes forming a second interfacial seam between the second and third die, the second interfacial seam extending from the second surface of the third die toward the first surface of the second die, and the second interfacial seam having an angle of less than 90 degrees with respect to the substrate.

[0172] Example 33 may include the subject matter of any of Examples 30-32, and may further include forming a through-dielectric via (TDV) in the dielectric material adjacent to the first die, the TDV electrically coupled to the first surface of the second die, and the TDV having a smaller width toward the first surface of the second die.

[0173] Example 34 may include the subject matter of any of Examples 30-33, and may further specify that the dielectric material includes silicon and one or more of nitrogen, oxygen, hydrogen, and carbon; a polyimide material; or a low-k or ultra-low-k dielectric.

[0174] Example 35 may include the subject matter of Example 33, and may further comprise electrically coupling a package substrate to the first die and the TDV.

Claims

1. a first die in a first layer, the first layer having a first surface and an opposite second surface, the first die being surrounded by a dielectric material; a through-dielectric via (TDV) in the first layer, wherein the TDV has a greater width toward the first surface of the first layer and a smaller width toward the second surface of the first layer; a second die in a second layer, the second layer having a first surface and an opposite second surface, wherein the first surface of the second layer is at the second surface of the first layer, wherein the first die is electrically coupled to the second die by interconnects having a pitch of less than 10 microns between adjacent interconnects, wherein the second die is surrounded by the dielectric material and includes an interface seam extending from the second die at the second surface of the second layer toward the first surface of the second layer, the interface seam having an angle of less than 90 degrees with respect to the second surface of the second layer; and a substrate bonded to the second surface of the second layer A microelectronic assembly comprising:

2. 10. The microelectronic assembly of claim 1, wherein the dielectric material comprises silicon and one or more of nitrogen, oxygen, hydrogen, and carbon; a polyimide material; or a low-k or ultra-low-k dielectric.

3. 10. The microelectronic assembly of claim 1, wherein the dielectric material in the first layer is a first dielectric material and the dielectric material in the second layer is a second dielectric material different from the first dielectric material.

4. The microelectronic assembly of claim 1 , wherein the angle of the interface seam is between 35 and 55 degrees relative to the second surface of the second layer.

5. 2. The microelectronic assembly of claim 1, wherein the interface seam is a first interface seam, and the dielectric material in the second layer further includes a second interface seam extending from the second die at the second surface of the second layer toward the first surface of the second layer, the second interface seam having an angle of less than 90 degrees with respect to the second surface of the second layer.

6. 6. The microelectronic assembly of claim 5, wherein the angle of the second interface seam is between 35 and 55 degrees relative to the second surface of the second layer.

7. a package substrate electrically coupled to the first surface of the first layer by a solder interconnect; The microelectronic assembly of any one of claims 1 to 6, further comprising:

8. 8. The microelectronic assembly of claim 7, wherein the TDV is electrically coupled at a first end to the package substrate and at an opposite second end to the second die.

9. a first layer having a first surface and an opposite second surface, the first layer having a first die, a dielectric material around the first die, and a through-dielectric via (TDV), wherein the TDV has a greater width toward the first surface of the first layer and a smaller width toward the second surface of the first layer; and a second layer having a first surface and an opposite second surface, the first surface of the second layer being on the second surface of the first layer, the second layer having a second die, a third die, and the dielectric material around and between the second die and the third die, wherein the first die is electrically coupled to the second die and the third die by interconnects having a pitch of less than 10 microns between adjacent interconnects, wherein the TDV is electrically coupled to the second die, and wherein the dielectric material between the second die and the third die includes an interface seam extending from the second die at the second surface of the second layer to the third die at the first surface of the second layer, the interface seam having an angle of less than 90 degrees with respect to the second surface of the second layer; 1. An integrated circuit (IC) package comprising:

10. 10. The IC package of claim 9, wherein the dielectric material comprises silicon and one or more of nitrogen, oxygen, hydrogen, and carbon; a polyimide material; or a low-k or ultra-low-k dielectric.

11. 10. The IC package of claim 9, wherein the dielectric material in the first layer is a first dielectric material and the dielectric material in the second layer is a second dielectric material different from the first dielectric material.

12. 10. The IC package of claim 9, wherein the angle of the interfacial seam is between 35 degrees and 55 degrees relative to the second surface of the second layer.

13. 10. The IC package of claim 9, wherein the interfacial seam is a first interfacial seam, and the dielectric material between the second die and the third die further includes a second interfacial seam extending from the third die at the second surface of the second layer toward the second die at the first surface of the second layer, the second interfacial seam having an angle of less than 90 degrees with respect to the second surface of the second layer.

14. 14. The IC package of claim 13, wherein the angle of the second interfacial seam is between 35 and 55 degrees relative to the second surface of the second layer.

15. a substrate bonded to the second surface of the second layer 15. The IC package according to claim 9, further comprising: a substrate material including silicon.

16. 16. The IC package of claim 15, wherein the substrate is bonded to the second surface of the second layer.

17. a first die in a first layer, the first layer having a first surface and an opposite second surface, the first die being surrounded by a dielectric material; a through-dielectric via (TDV) in the first layer, wherein the TDV has a greater width toward the first surface of the first layer and a smaller width toward the second surface of the first layer; a second die in a second layer, the second layer having a first surface and an opposite second surface, wherein the first surface of the second layer is at the second surface of the first layer, wherein the first die is electrically coupled to the second die by first interconnects having a pitch of less than 10 microns between adjacent first interconnects, wherein the second die is surrounded by the dielectric material and includes an interface seam extending from the second die at the second surface of the second layer toward the first surface of the second layer, the interface seam having an angle of less than 90 degrees with respect to the second surface of the second layer; a substrate bonded to the second surface of the second layer; and a package substrate electrically coupled to the first surface of the first layer by a second interconnect; A computing device comprising:

18. The computing device of claim 17 , wherein the substrate material comprises silicon.

19. 19. The computing device of claim 17 or 18, wherein the substrate is coupled to the second die by second interconnects having a pitch of less than 10 microns between adjacent second interconnects.

20. 20. The computing device of claim 19, wherein the substrate further comprises a conductive path, the conductive path electrically coupled to the second die by the second interconnect.

21. bonding a second die and a third die to a substrate, wherein the second die and the third die have first surfaces with conductive contacts and opposing second surfaces, wherein the first surfaces of the second die and the third die face away from the substrate; depositing a dielectric material around and between the second die and the third die and exposing the conductive contacts, wherein depositing a dielectric material around and between the second die and the third die comprises forming an interfacial seam between the second die and the third die, wherein the interfacial seam extends from a second surface of the second die toward the first surface of the third die, and wherein the interfacial seam has an angle of less than 90 degrees with respect to the substrate; attaching the first die to the second die and the third die by forming interconnects to electrically couple conductive contacts of the first die to the conductive contacts of the second die and the third die, wherein the interconnects have a pitch of less than 10 microns between adjacent interconnects; and depositing the dielectric material around the first die A method for manufacturing a microelectronic assembly, comprising:

22. 22. The method of claim 21 , wherein forming the interconnect further comprises forming an interface layer having bond pads and a dielectric material on the second die and the third die, and forming metal-to-metal and dielectric-to-dielectric bonds with the interface layer.

23. 22. The method of claim 21 , wherein depositing the dielectric material around and between the second die and the third die further comprises forming a second interface seam between the second die and the third die, the second interface seam extending from the second surface of the third die toward the first surface of the second die, and the second interface seam having an angle of less than 90 degrees with respect to the substrate.

24. 22. The method of claim 21, further comprising forming a through-dielectric via (TDV) in the dielectric material adjacent to the first die, the TDV electrically coupled to the first surface of the second die, the TDV having a smaller width toward the first surface of the second die.

25. 25. The method of any one of claims 21 to 24, wherein the dielectric material comprises silicon and one or more of nitrogen, oxygen, hydrogen, and carbon; a polyimide material; or a low-k or ultra-low-k dielectric.

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