Lanthanum nitride as a molybdenum liner for DRAM

Abstract

A method for a DRAM device with buried word lines is described, which includes forming a metal nitride layer including lanthanum nitride (LaN) and a molybdenum conductor layer in a feature of a substrate, and depositing the molybdenum conductor layer on the metal nitride layer by atomic layer deposition (ALD).

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure relate to the field of semiconductor devices and semiconductor device manufacturing. More particularly, embodiments of the present disclosure are directed to methods of utilizing lanthanum nitride as a liner for DRAM molybdenum applications. [Background technology]

[0002]

[0002] Electronic devices (e.g., personal computers, workstations, computer servers, mainframes, and other computer-related equipment such as printers, scanners, and hard disk drives) use memory devices that consume low power while providing substantial data storage capacity. There are two main types of random access memory cells suitable for use in electronic devices: dynamic and static. Dynamic random access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but must be periodically reprogrammed or "refreshed" to maintain this voltage for more than a very short period of time. Static random access memory (SRAM) is so named because it does not require periodic refreshing.

[0003] DRAM memory circuits are fabricated by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field-effect transistor (FET) and a capacitor.

[0004]

[0004] The fabrication of a DRAM cell includes a transistor, a capacitor, and three contacts (one each for the bit line, word line, and reference voltage). DRAM fabrication is a competitive business. There is a constant demand to shrink the size of individual cells and increase memory cell density, allowing more memory to be packed onto a single memory chip, especially to achieve densities beyond 256 megabits. Cell size reduction is limited by the routing of both active and passive word lines through the cell, the size of the cell capacitor, and compatibility with array and non-array devices. Forming low-resistance contacts between the active area and the bottom electrode of a three-dimensional DRAM is essential for device performance.

[0005] One of the primary goals in DRAM devices is to increase storage per unit space, which results in an increase in the vertical dimension, or stack height, of the DRAM device. Vertical cell DRAMs have the advantage of reducing chip area by approximately one-third compared to conventional cell DRAMs. Therefore, there is a need for a three-dimensional DRAM device and method for fabricating the same that does not have floating access transistor bodies and does not increase the area of ​​the cells. Summary of the Invention

[0006] One or more embodiments of the present disclosure are directed to a method of forming buried word lines, in one or more embodiments, the method including depositing a metal nitride layer on a substrate and depositing a molybdenum conductor layer on the metal nitride layer by an atomic layer deposition (ALD) process.

[0007]

[0007] In one or more embodiments, a method for forming a buried word line includes depositing a metal nitride layer including lanthanum nitride on a substrate and depositing a molybdenum conductor layer on the metal nitride layer by an atomic layer deposition (ALD) process.

[0008]

[0008] In order that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above will be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting the scope thereof, since the present disclosure may admit of other equally effective embodiments. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 shows a process flow diagram of a method according to one or more embodiments of the present disclosure. [Figure 2A-D] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 3A-C] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4A-D] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 5A-C] 1 illustrates a cross-sectional view of a device according to one or more embodiments.

[0010]

[0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further description.

[0011]

[0015] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0012]

[0016] The term "substrate," as used herein and in the appended claims, refers to a surface or a portion of a surface upon which a process acts. Those skilled in the art will also understand that when reference is made to a substrate, it may refer to only a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, when reference is made to deposition on a substrate, it may refer to both a bare substrate and a substrate upon which one or more films or features have been deposited or formed.

[0013]

[0017] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates.

[0014]

[0018] According to one or more embodiments, the use of the term "on" in reference to a film or layer of a film includes the presence of a film or layer directly on a surface (e.g., a substrate surface) and the presence of one or more underlying layers between the film or layer and the surface (e.g., a substrate surface). Thus, in one or more embodiments, the phrase "on the substrate surface" is intended to include one or more underlying layers. In other embodiments, the phrase "directly on" refers to a layer or film that is in contact with a surface (e.g., a substrate surface) but without any intervening layers. Thus, the phrase "a layer directly on the substrate surface" refers to a layer that is in direct contact with the substrate surface and without any intervening layers.

[0015]

[0019] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0016]

[0020] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit layers of material on a substrate surface. A substrate or a portion of a substrate is separately exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay, allowing each compound to adhere to and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, various portions of the substrate surface, or materials on the substrate surface, are simultaneously exposed to two or more reactive compounds such that any given point on the substrate is not substantially simultaneously exposed to multiple reactive compounds. As used herein and in the appended claims, the term "substantially" as used in this context means that, as will be understood by those skilled in the art, small portions of a substrate may be simultaneously exposed to multiple reactive gases due to diffusion, and simultaneous exposure is not intended.

[0017]

[0021] In one embodiment of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A, e.g., an aluminum precursor) is pulsed into the reaction zone, followed by a first time delay. Then, a second precursor or compound B (e.g., an oxidizer) is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas (e.g., argon) is introduced into the process chamber to purge the reaction zone or remove any residual reactive compounds or reaction by-products from the reaction zone. Alternatively, a purge gas can flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between pulses of reactive compounds. The reactive compounds are alternately pulsed until a desired film or film thickness is formed on the substrate surface. In either case, the ALD process of pulsing compound A, purge gas, compound B, and purge gas constitutes one cycle. A cycle can begin with either compound A or compound B, and each step of the cycle can be continued until a film having a predetermined thickness is achieved.

[0018]

[0022] In embodiments of spatial ALD processes, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are simultaneously supplied to a reaction zone but separated by an inert gas curtain and / or a vacuum curtain, and the substrate is moved relative to the gas supply system so that any given point on the substrate is exposed to the first reactive gas and the second reactive gas.

[0019]

[0023] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either co-flow or when there is overlap for the majority of the precursor exposure.

[0020]

[0024] As used throughout this specification, "substantially simultaneously" means that the majority of the duration of exposure of the first reactive compound overlaps with the exposure of the second reactive compound.

[0021]

[0025] As used herein, the term "purging" includes any suitable purge process that removes unreacted precursors, reaction products, and by-products from the processing region. A suitable purge process includes moving the substrate through a gas curtain to a portion or area of ​​the processing region that is free or substantially free of reactants. In one or more embodiments, purging the processing chamber includes applying a reduced pressure. In some embodiments, purging the processing chamber includes flowing a purge gas over the substrate. In some embodiments, the purge process includes flowing an inert gas. In one or more embodiments, the purge gas is selected from one or more of nitrogen (N), helium (He), and argon (Ar). In some embodiments, purging of the substrate surface or reaction chamber can occur for a duration ranging from 0.2 seconds to 30 seconds, 0.2 seconds to 10 seconds, 0.2 seconds to 5 seconds, 0.5 seconds to 30 seconds, 0.5 seconds to 10 seconds, 0.5 seconds to 5 seconds, 1 second to 30 seconds, 1 second to 10 seconds, 1 second to 5 seconds, 5 seconds to 30 seconds, 5 seconds to 10 seconds, or 10 seconds to 30 seconds.

[0022]

[0026] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores data bits by storing packets of charge (i.e., binary 1) or no charge (i.e., binary 0) in a capacitor. Charge is transferred to the capacitor via through an access transistor, and this charge is sensed by turning on the same transistor and observing the voltage perturbation caused by dumping the charge packet onto the interconnect line at the transistor's output. A single DRAM cell thus consists of one transistor and one capacitor. DRAM devices are formed from an array of DRAM cells. Rows of access transistors are linked by word lines, and the transistor inputs and outputs are linked by bit lines. Historically, DRAM capacitors have evolved from planar polysilicon-oxide-substrate plate capacitors to three-dimensional structures that have branched out into "stacked" capacitors, where both plates reside on top of the substrate, and "trench" capacitors, which use a cavity etched into the substrate as the shared plate.

[0023]

[0027] Traditionally, DRAM cells have recessed high work function metal structures into buried word line structures. In DRAM devices, bit lines are formed in a metal level above the substrate, while word lines are formed in a polysilicon gate level at the substrate surface. In buried word line (bWL) devices, word lines are buried below the surface of a semiconductor substrate, using the gate electrode as the metal. Current DRAM buried word line (bWL) processes use titanium nitride (TiN) as a liner and tungsten (W) or molybdenum (Mo) as a stack. The stack can have high resistivity, a high effective work function (eWF), and poor equivalent oxide thickness (EOT) / interface trap density (DiT). Therefore, embodiments of the present disclosure advantageously provide an alternative liner material, lanthanum nitride (LaN), for the molybdenum (Mo) stack in DRAM buried word lines (bWL) on a substrate, which reduces the resistance of DRAM devices.

[0024]

[0028] In one or more embodiments, the resistance (μΩ·cm) is measured for buried wordlines having a total thickness of 100 Å. In one or more embodiments, the buried wordlines have a resistance of 40 μΩ·cm or less, 30 μΩ·cm or less, 25 μΩ·cm or less, 20 μΩ·cm or less, or 15 μΩ·cm or less at a total thickness of 100 Å. In some embodiments, the buried wordlines have a resistance of 20 μΩ·cm or less at a total thickness of 100 Å. In one or more embodiments, the buried wordlines formed by method 100 have a resistance in the range of 50 μΩ·cm to 5 μΩ·cm, 40 μΩ·cm to 10 μΩ·cm, 30 μΩ·cm to 10 μΩ·cm, 25 μΩ·cm to 10 μΩ·cm, or 20 μΩ·cm to 10 μΩ·cm at a total thickness of 100 Å.

[0025]

[0029] Embodiments of the present disclosure are described with reference to figures illustrating devices (e.g., transistors, memory devices, etc.) and processes for forming the devices according to one or more embodiments of the present disclosure. The illustrated processes are merely examples of possible uses of the disclosed processes, and one of ordinary skill in the art will recognize that the disclosed processes are not limited to the applications shown.

[0026]

[0030] One or more embodiments of the present disclosure will be described with reference to the figures. Figure 1 shows a process flow diagram of a method according to one or more embodiments of the present disclosure. Figures 2A-3D are cross-sectional views illustrating a memory device 100 at various stages of processing to form buried word lines (bWLs) according to one or more embodiments.

[0027]

[0031] Referring to Figure 1, one or more embodiments of the present disclosure are directed to a method 10 of forming a memory device, e.g., a buried word line (bWL). In operation 12, a substrate is provided. In operation 14, a metal nitride layer including lanthanum nitride is formed on the substrate. In operation 16, a second metal nitride layer is optionally formed on the metal nitride layer. In operation 18, a molybdenum conductor layer is formed on the metal nitride layer.

[0028]

[0032] 2A-3C, a substrate 102 is provided for processing. As used in this context, the phrase "provided" means that the substrate is placed in a location or environment for further processing.

[0029]

[0033] In one or more embodiments, the substrate 102 may be any suitable substrate material. In one or more embodiments, the substrate 102 may be silicon oxynitride (SiON), silicon oxide (SiO x ), or high-dielectric-constant materials. The term "silicon oxide" may be used to describe the substrate 102, although those skilled in the art will recognize that the present disclosure is not limited to a particular stoichiometry. For example, "silicon oxide" and "silicon dioxide" may both be used to describe a material having silicon and oxygen atoms in any suitable stoichiometric ratio. The same applies to other materials listed in this disclosure, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, etc. Although several examples of materials from which the substrate 102 may be formed are described herein, any material that can serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) may be constructed falls within the spirit and scope of the present disclosure.

[0030]

[0034] In one or more embodiments, the substrate 102 may have any suitable thickness known to those skilled in the art, hi some embodiments, the substrate 102 has a thickness in the range of 20 Å to 100 Å, including the range of 30 Å to 75 Å, and including the range of 40 Å to 60 Å.

[0031]

[0035] 2B and 3B, a metal nitride layer 104 is formed on the surface of the substrate 102. The metal nitride layer 104 may include any suitable material known to those skilled in the art. In one or more embodiments, the metal nitride layer 104 includes lanthanum nitride (LaN).

[0032]

[0036] The metal nitride layer 104 can have any suitable thickness. In one or more embodiments, the metal nitride layer 104 has a thickness of less than 20 Å. In one or more embodiments, the metal nitride layer 104 has a thickness in the range of about 1 Å to less than about 20 Å, including the range of 5 Å to 20 Å, the range of 5 Å to 15 Å, the range of 10 Å to 20 Å, and the range of 10 Å to 15 Å. In one or more embodiments, the metal nitride layer 104 is formed to include lanthanum nitride (LaN) having a thickness in the range of about 10 Å to about 15 Å.

[0033]

[0037] In one or more embodiments, referring to FIG. 2C , a second metal nitride layer 106 is optionally formed on the surface of the metal nitride layer 104. The second metal nitride layer 106 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the second metal nitride layer 106 comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), yttrium nitride (YN), zirconium nitride (ZrN), hafnium nitride (HfN), and barium nitride (BaN). In one or more particular embodiments, the second metal nitride layer 106 comprises titanium nitride (TiN). Note that FIGS. 3A-3C illustrate an alternative embodiment in which the second metal nitride layer 106 is not present and only the first metal nitride layer 104 is present on the surface of the substrate 102.

[0034]

[0038] The second metal nitride layer 106 can have any suitable thickness. In one or more embodiments, the second metal nitride layer 106 has a thickness in the range of about 0.1 nm to about 10 nm (e.g., 5 nm to 8 nm, 1 nm to 3 nm, or 1 nm to 2 nm). In one or more embodiments, the second metal nitride layer 106 is formed to include titanium nitride (TiN) having a thickness in the range of about 1 nm to about 2 nm.

[0035]

[0039] In one or more embodiments, the first metal nitride layer 104 and the second metal nitride layer 106 have a combined thickness of about 30 Å, including in the range of 15 Å to about 30 Å.

[0036]

[0040] In one or more embodiments, the molybdenum conductor 108 is formed by atomic layer deposition. Atomic layer deposition can be a thermal process. Referring to Figure 2D, the device 100 is exposed to a molybdenum precursor, and a molybdenum conductor layer 108 is deposited on the second metal nitride layer 106. Referring to Figure 3C, the device 100 is exposed to a molybdenum precursor, and a molybdenum conductor layer 108 is deposited on the metal nitride layer 104. The molybdenum precursor can be any suitable molybdenum-containing compound that can react (i.e., adsorb or chemisorb) with the metal nitride layers 104, 106 to leave molybdenum-containing species on the surface.

[0037]

[0041] In one or more embodiments, the molybdenum precursor comprises any suitable precursor known to those skilled in the art. In one or more embodiments, the molybdenum precursor is volatile, thermally stable, and suitable for vapor deposition. In some embodiments, the molybdenum precursor comprises a molybdenum halide. As used herein, the term "halide" refers to a two-phase compound, one portion of which is a halogen atom and the other portion is an element or radical less electronegative than a halogen, forming a fluoride, chloride, bromide, iodide, or astatide compound. A halide ion is a negatively charged halogen atom. As known to those skilled in the art, halide anions include fluoride (F-), chloride (Cl-), bromide (Br-), iodide (I-), and astatide (At-). Thus, as used herein, the term "molybdenum halide" refers to a coordination compound of molybdenum with one or more halogens or halogen ligands. The term molybdenum halide includes mixed molybdenum halides having at least two different halide atoms.

[0038]

[0042] In one or more embodiments, the molybdenum halide is selected from one or more of molybdenum chloride, molybdenum pentachloride, molybdenum bromide, molybdenum iodide, molybdenum bromochloride, molybdenum bromoiodide, molybdenum chlorobromide, molybdenum chloroiodide, molybdenum iodobromide, and molybdenum iodochloride.

[0039]

[0043] In some embodiments, the molybdenum precursor comprises a molybdenum oxyhalide species, which may comprise one or more of molybdenum tetrachloride oxide (MoClO), molybdenum tetrabromide oxide (MoBrO), molybdenum tetraiodide oxide (MoIO), molybdenum dibromide dioxide (MoOBr), molybdenum dichloride dioxide (MoClO), and / or molybdenum diiodide dioxide (MoIO).

[0040]

[0044] In one or more embodiments, the molybdenum precursor includes one or more of molybdenum chloride (MoCl5), molybdenum fluoride (MoF6), molybdenum iodide (MoI6), molybdenum bromide (MoBr3), molybdenum hexacarbonyl (Mo(CO)6), molybdenum dioxide dichloride (MoOCl2), molybdenum oxytetrachloride (MoOCl4), tetrakis(dimethylamino)molybdenum(IV), and bis(tert-butylimido)-bis(dimethylamido)molybdenum.

[0041]

[0045] In some embodiments, the metal nitride layers 104, 106 are exposed to a molybdenum precursor at a temperature in the range of 350°C to 550°C, 400°C to 550°C, 450°C to 550°C, 500°C to 550°C, 350°C to 500°C, 400°C to 500°C, 450°C to 500°C, 350°C to 450°C, 400°C to 450°C, or 350°C to 400°C.

[0042]

[0046] In some embodiments, the metal nitride layers 104, 106 are exposed to the molybdenum precursor for a duration in the range of 0.25 seconds to 20 minutes, 10 seconds to 20 minutes, 1 minute to 20 minutes, 5 minutes to 20 minutes, 10 minutes to 20 minutes, 0.25 seconds to 10 minutes, 10 seconds to 10 minutes, 1 minute to 10 minutes, 5 minutes to 10 minutes, 0.25 seconds to 5 minutes, 10 seconds to 5 minutes, 1 minute to 5 minutes, 0.25 seconds to 1 minute, or 10 seconds to 1 minute.

[0043]

[0047] In some embodiments, the metal nitride layers 104, 106 are exposed to a molybdenum precursor at a dosage in the range of 50 sccm to 700 sccm, 100 sccm to 700 sccm, 300 sccm to 700 sccm, 500 sccm to 700 sccm, 50 sccm to 500 sccm, 100 sccm to 500 sccm, 300 sccm to 500 sccm, 50 sccm to 300 sccm, 100 sccm to 300 sccm, or 50 sccm to 100 sccm.

[0044]

[0048] In some embodiments, the metal nitride layers 104, 106 are exposed to the molybdenum precursor at a pressure in the range of 5 Torr to 50 Torr, 10 Torr to 50 Torr, 25 Torr to 50 Torr, 5 Torr to 25 Torr, 10 Torr to 25 Torr, or 5 Torr to 10 Torr.

[0045]

[0049] In some embodiments, the formed molybdenum conductor layer 108 comprises elemental molybdenum. In some embodiments, the molybdenum conductor layer 108 consists essentially of molybdenum. As used in this manner, the phrase "consisting essentially of molybdenum" means that the molybdenum content in the film is greater than or equal to about 80%, 85%, 90%, 95%, 98%, 99%, or 99.5% molybdenum on an atomic basis. Measurements of the composition of the molybdenum conductor layer 108 refer to the bulk of the molybdenum conductor layer 108, excluding interface regions where diffusion of elements from adjacent films may occur.

[0046]

[0050] 2D and 3C, in some embodiments, the thickness of the molybdenum conductor layer 108 may be any suitable thickness. In some embodiments, the molybdenum conductor layer 108 has a thickness in the range of 1 nm to 50 nm, 5 nm to 50 nm, 10 nm to 50 nm, 25 nm to 50 nm, 1 nm to 25 nm, 5 nm to 25 nm, 10 nm to 25 nm, 1 nm to 10 nm, 5 nm to 10 nm, or 1 nm to 5 nm.

[0047]

[0051] 1 and 4A-5C, one or more embodiments of the present disclosure are directed to a method 10 of forming a memory device 200 (eg, a buried word line (bWL)).

[0048]

[0052] 3A-5C, in one or more embodiments, a substrate 202 is provided having a plurality of trenches 210. The trenches 210 form recessed channels. The trenches have a bottom 203 and at least one sidewall 207. The plurality of trenches 210 can be formed to have a width within a range of about 10 to about 100 nm (including, but not limited to, a range of about 10 nm to about 80 nm, about 10 nm to about 70 nm, about 10 nm to about 60 nm, about 10 nm to about 50 nm, or about 10 nm to about 40 nm). As will be appreciated by those skilled in the art, the width of the plurality of trenches 210 is defined by the distance W1 from one sidewall 207 to the other sidewall 207. The plurality of trenches 210 may be formed to have a depth within a range of about 120 nm to about 250 nm (including, but not limited to, about 120 nm to about 150 nm, about 150 nm to about 200 nm, about 200 nm to about 250 nm, about 120 nm to about 200 nm, or about 150 nm to about 250 nm). As will be appreciated by those skilled in the art, the depth of the plurality of trenches 210 is defined by the distance D1 from the substrate surface 205 to the bottom 203 of the plurality of trenches 210.

[0049]

[0053] One or more embodiments of the present disclosure are directed to methods of depositing films in high aspect ratio features. High aspect ratio features are trenches, vias, or pillars with height-to-width ratios of about 10, 20, or 50 or more. In some embodiments, films are conformally deposited on or within the high aspect ratio features. When used in this manner, conformal films have a thickness near the top of the feature that is in the range of about 80-120% of the thickness at the bottom of the feature.

[0050]

[0054] A buffer insulating layer (e.g., a silicon oxide layer, not shown) may be formed on the substrate surface 205 and / or a hard mask layer (e.g., a nitride layer, not shown) may be formed to form the plurality of trenches 210. Such techniques are not shown as they are well known to those skilled in the art.

[0051]

[0055] 4B and 5B, in some embodiments, a metal nitride layer 204 is formed on the substrate 202. In one or more embodiments, the metal nitride layer 204 comprises any suitable metal nitride. In one or more embodiments, the metal nitride layer 204 comprises lanthanum nitride (LaN).

[0052]

[0056] The metal nitride layer 204 can have any suitable thickness. In one or more embodiments, the metal nitride layer 204 has a thickness of less than 20 Å. In one or more embodiments, the metal nitride layer 204 has a thickness in the range of about 1 Å to less than about 20 Å, including the range of 5 Å to 20 Å, the range of 5 Å to 15 Å, the range of 10 Å to 20 Å, and the range of 10 Å to 15 Å. In one or more embodiments, the metal nitride layer 204 is formed to include lanthanum nitride (LaN) having a thickness in the range of about 10 Å to about 15 Å.

[0053]

[0057] In one or more embodiments, referring to FIG. 4C , a second metal nitride layer 206 is optionally formed on the surface of the metal nitride layer 204. The second metal nitride layer 206 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the second metal nitride layer 206 comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), yttrium nitride (YN), zirconium nitride (ZrN), hafnium nitride (HfN), and barium nitride (BaN). In one or more particular embodiments, the second metal nitride layer 206 comprises titanium nitride (TiN). Note that FIGS. 5A-5C illustrate an alternative embodiment in which the second metal nitride layer 206 is not present and only the first metal nitride layer 204 is present on the surface of the substrate 202.

[0054]

[0058] The second metal nitride layer 206 can have any suitable thickness. In one or more embodiments, the second metal nitride layer 206 has a thickness in the range of about 0.1 nm to about 5 nm, including a range of 1 nm to 3 nm, and including a range of 1 nm to 2 nm. In one or more embodiments, the second metal nitride layer 206 is formed to include titanium nitride (TiN) having a thickness in the range of about 1 nm to about 2 nm.

[0055]

[0059] In one or more embodiments, the molybdenum conductor 208 is formed by atomic layer deposition. Atomic layer deposition may be a thermal process. Referring to FIG. 4D , a process is performed to deposit a molybdenum conductor layer 204 on the substrate 202 (substrate surface). The deposition process may include one or more operations to form the molybdenum conductor layer 204 on the substrate 202. In some embodiments, the deposition process is selective for deposition onto the metal nitride layer 204. Referring to FIG. 5C , a process is performed to deposit a molybdenum conductor layer 204 on the substrate 202 (substrate surface). The deposition process may include one or more operations to form the molybdenum conductor layer 204 on the substrate 202. In some embodiments, the deposition process is selective for deposition onto the second metal nitride layer 206.

[0056]

[0060] The molybdenum precursor can be any suitable molybdenum-containing compound capable of reacting (i.e., adsorbing or chemisorbing) with the metal nitride layers 204, 206 to leave behind molybdenum-containing species on the surface. The atomic layer deposition process of some embodiments includes sequential exposure to a precursor and a reactant. The substrate 202 (or substrate surface) is optionally exposed to the reactant. In some embodiments, the reactant includes a reducing agent. The reducing agent can be any suitable compound known to those skilled in the art. In some embodiments, the reducing agent includes hydrogen (H).

[0057]

[0061] In one or more embodiments, the molybdenum precursor comprises any suitable precursor known to those skilled in the art. The molybdenum precursor of one or more embodiments is volatile and thermally stable, making it suitable for vapor deposition. In some embodiments, the molybdenum precursor comprises a molybdenum halide. As used herein, the term "halide" refers to a two-phase compound, one portion of which is a halogen atom and the other portion is an element or radical less electronegative than a halogen, creating a fluoride, chloride, bromide, iodide, or astatide compound. A halide ion is a negatively charged halogen atom. As known to those skilled in the art, halide anions include fluoride (F-), chloride (Cl-), bromide (Br-), iodide (I-), and astatide (At-). Thus, as used herein, the term "molybdenum halide" refers to a coordination compound of molybdenum with one or more halogens or halogen ligands. The term molybdenum halide includes mixed molybdenum halides having at least two different halide atoms.

[0058]

[0062] In one or more embodiments, the molybdenum halide is selected from one or more of molybdenum chloride, molybdenum pentachloride, molybdenum bromide, molybdenum iodide, molybdenum bromochloride, molybdenum bromoiodide, molybdenum chlorobromide, molybdenum chloroiodide, molybdenum iodobromide, and molybdenum iodochloride.

[0059]

[0063] In some embodiments, the molybdenum precursor comprises a molybdenum oxyhalide species, which may comprise one or more of molybdenum tetrachloride oxide (MoClO), molybdenum tetrabromide oxide (MoBrO), molybdenum tetraiodide oxide (MoIO), molybdenum dibromide dioxide (MoOBr), molybdenum dichloride dioxide (MoClO), and / or molybdenum diiodide dioxide (MoIO).

[0060]

[0064] In one or more embodiments, the molybdenum precursor includes one or more of molybdenum chloride (MoCl5), molybdenum fluoride (MoF6), molybdenum iodide (MoI6), molybdenum bromide (MoBr3), molybdenum hexacarbonyl (Mo(CO)6), molybdenum dioxide dichloride (MoOCl2), molybdenum oxytetrachloride (MoOCl4), tetrakis(dimethylamino)molybdenum(IV), and bis(tert-butylimido)-bis(dimethylamido)molybdenum.

[0061]

[0065] In some embodiments, the metal nitride layers 204, 206 are exposed to a molybdenum precursor at a temperature in the range of 350°C to 550°C, 400°C to 550°C, 450°C to 550°C, 500°C to 550°C, 350°C to 500°C, 400°C to 500°C, 450°C to 500°C, 350°C to 450°C, 400°C to 450°C, or 350°C to 400°C.

[0062]

[0066] In some embodiments, the metal nitride layers 204, 206 are exposed to the molybdenum precursor for a duration in the range of 0.25 seconds to 20 minutes, 10 seconds to 20 minutes, 1 minute to 20 minutes, 5 minutes to 20 minutes, 10 minutes to 20 minutes, 0.25 seconds to 10 minutes, 10 seconds to 10 minutes, 1 minute to 10 minutes, 5 minutes to 10 minutes, 0.25 seconds to 5 minutes, 10 seconds to 5 minutes, 1 minute to 5 minutes, 0.25 seconds to 1 minute, or 10 seconds to 1 minute.

[0063]

[0067] In some embodiments, the metal nitride layers 204, 206 are exposed to a molybdenum precursor at a dosage in the range of 50 sccm to 700 sccm, 100 sccm to 700 sccm, 300 sccm to 700 sccm, 500 sccm to 700 sccm, 50 sccm to 500 sccm, 100 sccm to 500 sccm, 300 sccm to 500 sccm, 50 sccm to 300 sccm, 100 sccm to 300 sccm, or 50 sccm to 100 sccm.

[0064]

[0068] In some embodiments, the metal nitride layers 204, 206 are exposed to the molybdenum precursor at a pressure in the range of 5 Torr to 50 Torr, 10 Torr to 50 Torr, 25 Torr to 50 Torr, 5 Torr to 25 Torr, 10 Torr to 25 Torr, or 5 Torr to 10 Torr.

[0065]

[0069] 4D and 5C , in one or more embodiments, the molybdenum conductor layer 208 may have any suitable thickness. For example, the molybdenum conductor layer 208 may have a thickness in the range of 10 Å to 200 Å, 20 Å to 200 Å, 50 Å to 200 Å, 100 Å to 200 Å, 150 Å to 200 Å, 10 Å to 150 Å, 50 Å to 150 Å, 100 Å to 150 Å, 10 Å to 100 Å, 50 Å to 100 Å, 10 Å to 50 Å, or 10 Å to 30 Å.

[0066]

[0070] 4D and 5C, in some embodiments, the molybdenum conductor layer 208 is formed within the feature 210. The molybdenum conductor layer 208 in some embodiments fills the gap formed by the feature in a bottom-up manner. As used in this manner, "bottom-up" means that deposition occurs substantially on the bottom of the feature relative to the sidewalls.

[0067]

[0071] In some embodiments, the formed molybdenum conductor layer 208 comprises elemental molybdenum. In some embodiments, the molybdenum conductor layer 108 consists essentially of molybdenum. As used in this manner, the phrase "consisting essentially of molybdenum" means that the molybdenum content in the film is greater than or equal to about 80%, 85%, 90%, 95%, 98%, 99%, or 99.5% molybdenum on an atomic basis. Measurements of the composition of the molybdenum conductor layer 108 refer to the bulk of the molybdenum conductor layer 208, excluding interface regions where diffusion of elements from adjacent films may occur.

[0068]

[0072] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures for ease of description. It will be understood that the spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being "below" or "beneath" another element or feature would then be oriented "above" the other element or feature. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be oriented other than as depicted (rotated 90 degrees or to other orientations), and the spatially relative descriptions used herein should be interpreted accordingly.

[0069]

[0073] In the context of describing the materials and methods discussed herein (particularly in the context of the claims that follow), the use of "a" and "an," "the," and similar referents should be construed to encompass both the singular and the plural unless otherwise indicated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of referring individually to each individual value falling within the range, unless otherwise stated herein, and each individual value is incorporated into the specification as if set forth individually herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better describe the materials and methods and does not impose a limitation on scope unless specifically claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the disclosed materials and methods.

[0070]

[0074] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0071]

[0075] Although the disclosure herein has been described with reference to particular embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, the present disclosure is intended to cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a buried word line, comprising: depositing a metal nitride layer comprising lanthanum nitride on a substrate; depositing a molybdenum conductor layer on the metal nitride layer by an atomic layer deposition (ALD) process; A method comprising:

2. The method of claim 1 , wherein the metal nitride layer has a thickness of less than 20 Å.

3. The method of claim 1 further comprising depositing a second metal nitride layer on the metal nitride layer.

4. 4. The method of claim 3, wherein the second metal nitride layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), yttrium nitride (YN), zirconium nitride (ZrN), hafnium nitride (HfN), and barium nitride (BaN).

5. The method of claim 4 , wherein the second metal nitride layer comprises titanium nitride.

6. The method of claim 1 , wherein the ALD process is a thermal process.

7. The method of claim 1 , wherein the molybdenum conductor layer is selectively deposited on the metal nitride layer.

8. The method of claim 1 , wherein the ALD process comprises sequentially exposing the substrate to a reactant and a molybdenum precursor.

9. The method of claim 1, wherein the molybdenum conductor layer is deposited to a thickness in the range of 10 Å to 200 Å.

10. The method of claim 1, wherein the ALD process is carried out at a temperature in the range of 350°C to 550°C.

11. 2. The method of claim 1, wherein said buried wordlines have a resistance of 20 [mu][Omega]-cm or less at a total thickness of 100 Å.

12. The method of claim 1 , wherein the substrate has at least one feature having at least one sidewall and a bottom.

13. The method of claim 12, wherein the at least one feature has a width in the range of 10 nm to 12 nm.

14. The method of claim 12 , wherein the at least one feature is filled with the molybdenum conductor layer in a bottom-up manner.

15. 1. A method of forming a buried word line, comprising: depositing a first metal nitride layer comprising lanthanum nitride on a substrate; depositing a second metal nitride layer on the substrate; depositing a molybdenum conductor layer on the first metal nitride layer by an atomic layer deposition (ALD) process; A method comprising:

16. 16. The method of claim 15, wherein the first metal nitride layer has a thickness of less than 20 Å.

17. 16. The method of claim 15, wherein the second metal nitride layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), yttrium nitride (YN), zirconium nitride (ZrN), hafnium nitride (HfN), and barium nitride (BaN).

18. 16. The method of claim 15, wherein the first metal nitride layer and the second metal nitride layer have a combined thickness in the range of 15 Å to 30 Å.

19. 16. The method of claim 15, wherein the ALD process is a thermal process.

20. The method of claim 15 , wherein the molybdenum conductor layer is selectively deposited on the second metal nitride layer.

Images