Integrated circuit chip with backside power supply and multiple types of backside-to-frontside vias - Patent Application 20070122997

Abstract

A semiconductor device including a first via connecting a back surface of the semiconductor device to a front surface of the semiconductor device and a second via connecting the back surface of the semiconductor device to a front surface of the semiconductor device, wherein the first via and the second via are directly connected to at least one different wiring level on the front surface or the back surface.

Description

[Technical Field]

[0001] The present disclosure relates to integrated circuit (IC) chips. More specifically, the present disclosure provides semiconductor structures having first and second frontside (FS) to backside (BS) vias, and related processes. [Background technology]

[0002] Semiconductor processing for the fabrication of IC chips continues to evolve towards increased device density, with active devices (mainly transistors) of ever decreasing device dimensions being placed in greater numbers on a given surface of semiconductor material, which imposes constraints on the design and fabrication of IC chips. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a semiconductor device is provided, the semiconductor device including a first via connecting a back surface of the semiconductor device to a front surface of the semiconductor device and a second via connecting the back surface of the semiconductor device to the front surface of the semiconductor device, the first via and the second via directly connecting to at least one different wiring level on the front surface or the back surface.

[0004] According to some embodiments of the present disclosure, there is provided a semiconductor device including a first set of vias connecting a back surface of the semiconductor device to a front surface of the semiconductor device and a second set of vias connecting the back surface of the semiconductor device to the front surface of the semiconductor device, wherein the at least one via of the first set of vias and at least one via of the second set of vias are directly connected to at least one different wiring level on the front surface or the back surface.

[0005] According to some embodiments of the present disclosure, there is provided a method for fabricating a semiconductor device, the method including: receiving a substrate having a front surface and a back surface, the substrate including a first substrate layer, a first semiconductor layer attached to the substrate layer, and a first dielectric layer embedded below the first semiconductor layer; forming a first via extending from the front surface of the substrate to the back surface of the substrate; inverting the substrate; bonding a second substrate layer to the front surface of the substrate; removing the first substrate layer and the first dielectric layer to expose a front end of line (FEOL) layer; forming a second dielectric layer on the back surface of the substrate, the second dielectric layer including a second set of wiring levels and including second vias extending from the back surface of the substrate to the front surface; and forming a back surface BEOL on the back surface of the substrate.

[0006] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure. [Brief explanation of the drawings]

[0007] The drawings contained herein are incorporated into and form a part of this specification. They illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. The drawings are merely illustrative of particular embodiments and are not intended to limit the disclosure.

[0008] [Figure 1] 1 is a schematic diagram of a cross-sectional view of a portion of a semiconductor device according to an embodiment of the present disclosure.

[0009] [Figure 2] 1 is a schematic diagram of a cross-sectional view of a portion of a semiconductor device according to an embodiment of the present disclosure.

[0010] [Figure 3A] 1A-1D illustrate cross-sectional views of a chip at successive steps in a process performed to form a semiconductor device according to an embodiment of the present disclosure. [Figure 3B]1A-1D illustrate cross-sectional views of a chip at successive steps in a process performed to form a semiconductor device according to an embodiment of the present disclosure. [Figure 3C] 1A-1D illustrate cross-sectional views of a chip at successive steps in a process performed to form a semiconductor device according to an embodiment of the present disclosure. [Figure 3D] 1A-1D illustrate cross-sectional views of a chip at successive steps in a process performed to form a semiconductor device according to an embodiment of the present disclosure. [Figure 3E] 1A-1D illustrate cross-sectional views of a chip at successive steps in a process performed to form a semiconductor device according to an embodiment of the present disclosure. [Figure 3F] 1A-1D illustrate cross-sectional views of a chip at successive steps in a process performed to form a semiconductor device according to an embodiment of the present disclosure.

[0011] [Figure 4] FIG. 2 is a schematic diagram of a top view of a via in a semiconductor device according to an embodiment of the present disclosure.

[0012] [Figure 5] 1 is a schematic diagram of a cross-sectional view of a via in a semiconductor device according to an embodiment of the present disclosure.

[0013] [Figure 6] FIG. 1 is a flow diagram of a process for forming a semiconductor device according to an embodiment of the present disclosure.

[0014] While the present disclosure is susceptible to various modifications and alternative forms, specific features thereof have been shown by way of example in the drawings and will be described in detail. It is to be understood, however, that the disclosure is not intended to be limited to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives within the spirit and scope of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015] Aspects of the present disclosure relate to integrated circuit chips, hereafter abbreviated as IC or IC chip. More specifically, the present disclosure provides semiconductor structures having first and second front-side (FS) to back-side (BS) vias, and related processes. While the present disclosure is not necessarily limited to such applications, aspects of the present disclosure may be understood through a discussion of various examples using this context.

[0016] Traditionally, interconnects between the front end of the line (FEOL) of an IC chip (which primarily consists of the IC chip's active devices and contact terminals) are integrated into the back end of the line (BEOL) (i.e., semiconductor structure) of the IC chip. Such interconnects include a stack of metallization layers above the FS, including layers of circuitry connected by vertical via connections. For example, to provide power to individual active devices in the FS, a power delivery network (PDN) can be formed by conductors and vias connected to the drain supply / source supply (VDD / VSS) terminals of the IC chip. However, integrating PDNs into the BEOL has become particularly challenging with the evolution toward increased device density.

[0017] Embodiments of the present disclosure relate to an IC chip having a BS power supply and multiple types of BS-to-FS vias. Such an IC chip includes at least two different types of vias extending from the BS to the FS. The at least two different types of vias may differ in size, such as width, material, etc., and may connect different wiring levels. Embodiments of the present disclosure also relate to a process for forming an IC chip including multiple types of BS-to-FS vias.

[0018] One feature and advantage of the disclosed structures and processes is that they can include and provide multiple types of via configurations for products utilizing BS power distribution. Another feature and advantage of the disclosed structures and processes is that BS interconnects for signal routing in the disclosed semiconductor structures can address the challenge of FS congestion in such semiconductor structures. Yet another feature and advantage of the disclosed structures and processes is that the inclusion of high-performance vias can be formed later in the process and can bridge different metallization levels in the semiconductor structure. Such high-performance vias can provide significantly improved power delivery compared to nanovias intended to supply power or signals to a single transistor in a device layer within the FS of the semiconductor structure. A further feature and advantage of the disclosed processes for forming IC chips with multiple BS-to-FS vias is that they do not have the relatively high cost or complexity compared to processes for forming IC chips that do not have multiple BS-to-FS vias.

[0019] For the sake of brevity, conventional techniques related to semiconductor device and IC manufacturing may or may not be described in detail herein, and various tasks and process steps or operations described herein may be combined into a more comprehensive procedure or process having additional operations or functionality not described in detail herein.

[0020] FIG. 1 is a schematic diagram of a cross-sectional view of a portion of a semiconductor structure 100 according to an embodiment of the present disclosure. The semiconductor structure 100 includes a stack 102 having a FS 104 and a BS 106. The stack 102 includes a front-side back-end-of-line (FS BEOL) portion 108, which further includes device layers 110, and a back-side back-end-of-line (BS BEOL) portion 112. The devices (not shown) may include, for example, transistors, resistors, capacitors, diodes, etc. The FS BEOL portion 108 may include a FS interconnect structure, which may include multiple FS metallization layers (not shown) disposed within and surrounded by a FS dielectric layer 114. The FS metallization layers (not shown) may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines (not shown). The BS BEOL portion 112 may also include a BS interconnect structure, which may further include, for example, metallization layers (not shown) and vias. The BS BEOL portion 112 may also include a BS dielectric layer 116.

[0021] 1 , vias may extend between the FS BEOL portion 108 and the BS BEOL portion 112. In particular, consistent with some embodiments, a first set of vias 118 extends between the FS BEOL portion 108 and the BS BEOL portion 112, and a second set of vias 120 extends between the FS BEOL portion 108 and the BS BEOL portion 112. The first set of vias 118 and the second set of vias 120 are different types of vias. The different types of vias may differ based on, for example, size (e.g., width), cross-sectional shape, material, etc. The first set of vias 118 includes a first FS wiring level 122 and a first BS wiring level 124 in the FS BEOL portion 108 and the BS BEOL portion 112, respectively. A second set of vias 120 connects a second FS wiring level 126 and a second BS wiring level 128 in the FS BEOL portion 108 and the BS BEOL 112, respectively. As shown, the first FS wiring level 122 is different from the second FS wiring level 126, and the first BS wiring level 124 is different from the second BS wiring level 128. The first and second BS wiring levels 124, 128 may be included in an area generally referred to as a BS power delivery network (PDN).

[0022] FIG. 2 is a schematic diagram of a cross-sectional view of a portion of a semiconductor structure 200 according to an embodiment of the present disclosure. The semiconductor structure 200 includes a stack 202 having a FS 204 and a BS 206. The stack 202 includes a FS BEOL portion 208, which further includes device layers 210, and a BS BEOL portion 212. The devices (not shown) may include, for example, transistors, resistors, capacitors, diodes, etc. The FS BEOL portion 208 may include a FS interconnect structure, which may include multiple FS metallization layers (not shown) disposed within and surrounded by a FS dielectric layer 214. The FS metallization layers (not shown) may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines (not shown). The BS BEOL portion 212 may also include a BS interconnect structure, which may further include, for example, metallization layers (not shown) and vias. The BS BEOL portion 212 may also include a BS dielectric layer 216.

[0023] 2 , vias may extend between FS BEOL portion 208 and BS BEOL portion 212. In particular, consistent with some embodiments, a first set of vias 218 extends between device layer 210 and BS BEOL portion 212, and a second set of vias 220 extends between FS BEOL portion 208 and BS BEOL portion 212. First set of vias 218 and second set of vias 220 are different types of vias. The different types of vias may differ based on, for example, size (e.g., width), cross-sectional shape, material, etc.

[0024] The first set of vias 218 includes a first FS wiring level 222 and a first BS wiring level 224 in the device layer 210 and the BS BEOL 212, respectively. The second set of vias 220 includes a second FS wiring level 226 and a second BS wiring level 228 in the FS BEOL portion 208 and the BS BEOL 212, respectively. The first and second BS wiring levels 224, 228 may be included in a structure generally referred to as a BS PDN.

[0025] For purposes of this disclosure, reference will be made to exemplary process flows. Various exemplary embodiments of the processes and structures disclosed herein will be described in more detail with reference to the accompanying figures.

[0026] 3A-3F include schematic illustrations of cross-sectional views of a portion of a chip 300 through steps in an example process, according to an embodiment of the present disclosure. The accompanying drawings provide various views of one exemplary embodiment of a process or method for forming a chip 300 having first and second FS-to-BS vias 318, 320 (or first and second sets of vias). While only two different types of vias are shown, it is contemplated by the present disclosure that multiple sets of vias, more than two, may be included.

[0027] FIG. 3A shows a portion of a chip 300 in an early stage of fabrication. The chip 300 includes a substrate 305 including a first substrate layer 301, a dielectric layer 303, and a semiconductor or device layer 310 including a plurality of devices 311, according to an embodiment of the present disclosure. The portion of the chip 300 in FIG. 3A may be a "semiconductor-on-insulator substrate," such as, for example, a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In embodiments, the device layer 310 may include, for example, silicon, silicon germanium, germanium, or other suitable semiconductor. The first substrate layer 310 may be, for example, a portion of a silicon wafer. The dielectric layer 303 may be, for example, silicon oxide. Other suitable materials for layers 301, 303, and 310 are also contemplated. The semiconductor-on-insulator substrate may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0028] 3B illustrates the next step in fabricating chip 300 according to an embodiment of the present disclosure. As shown, a first set of FS-to-BS vias 318 extend from device layer 310 to dielectric layer 303. Vias 318 may be formed using known lithography and etching techniques, such as by a single or double damascene process. A dual damascene process may be characterized by patterning vias and trenches in such a way that they are simultaneously filled with metal deposition.

[0029] FIG. 3C illustrates another step in the formation of a chip 300 according to an embodiment of the present disclosure. FS BEOL portion 308 or layer may be added adjacent to device layers 310. BEOL layers, such as FS BEOL layer 308, may be formed by dielectric stack deposition, masking and etching to form line and via openings, metallization, and polishing. FS BEOL portion 308 may include one or more FS metallization (or wiring) layers 326, 330 disposed within and surrounded by FS dielectric layer 314. FS metallization layers 326, 330 may be oriented perpendicular to FS-to-BS via 318, as shown. One or more FS vias 327 may be formed and extend between two of the FS metallization layers 326, 330, as shown. One embodiment for forming a configuration of FS metallization layers 326, 330 and FS vias 327 is shown, and other configurations are contemplated by the present disclosure. Wires can be used to electrically connect devices to form circuits, which can then be routed to power and additional circuitry. The goal of BEOL is to interconnect all the devices to form complex chips with logic, memory, I / O, etc.

[0030] 3D shows the chip portion 300 after being flipped and bonded to a second substrate layer 307. The second substrate layer 307 may be bonded using a thin oxide layer, which may be formed on both surfaces of the wafer, and then the two wafers may be brought together and subjected to heat and pressure to bond the oxide layers. Oxide-to-oxide bonding is a standard industry bonding technique. The first substrate layer 301 and dielectric layer 303 are shown removed from the chip 300. The first substrate layer 301 and dielectric layer 303 may be removed, for example, by polishing to thin the first substrate layer 301, and then reactive ion etching (RIE) or chemical etching techniques.

[0031] 3E illustrates another step in the formation of a chip 300 according to an embodiment of the present disclosure. A BS BEOL portion 312 including a BS dielectric layer 316 is shown added adjacent to the device layer 310 or front-end-of-line (FEOL). The BS dielectric layer 316 may be formed by dielectric deposition followed by masking to form lines and vias. A second set (plurality) of vias 320 may be formed between the FS BEOL portion 308 and the BS BEOL portion 312 (i.e., the BS and FS). The vias 320 may be formed using lithography and etching techniques, such as by single or double damascene processing.

[0032] The first set of vias 318 and the second set of vias 320 may be different types of vias. The different types of vias may differ based on, for example, size (e.g., width), cross-sectional shape, material, etc. The first set of vias 318 includes a first FS wiring level 322 and a first BS wiring level 324 in the FS BEOL portion 308 and the BS dielectric layer 316, respectively. In some embodiments, the first set of vias 318, 320 may be directly connected to at least one different wiring level.

[0033] 3F illustrates another step in the formation of a chip 300 according to an embodiment of the present disclosure. A BS BEOL 312 is formed, including a second BS wiring level 328. BEOL layers, such as BS BEOL layer 312, may be formed by dielectric stack deposition, masking and etching to form line and via openings, metallization, and polishing. A second set of vias 320 includes a second FS wiring level 326 and a second BS wiring level 328 in FS BEOL portion 308 and BS BEOL 312, respectively.

[0034] In chip 300, in some embodiments, first and second sets of vias 318, 320 may terminate on different metallization layers / lines (or planes) in chip 300. First set of vias 318 may be located adjacent to source / drain (S / D) regions (not shown), for example, and second set of vias 320 may be located adjacent to shallow trench isolation (STI) regions (not shown), or vice versa. Vias 318 or 320 may have a dielectric barrier protection (see FIG. 5 ), for example, in STI / silicon regions, which may optionally be removed, for example, in oxide / ultra-low K (ULK) regions.

[0035] The first and second sets of vias 318, 320 may be made of different metals. For example, one set of vias may be made of copper, while another set of vias may be made of another metal, such as ruthenium, tungsten, etc. The width of each via in the first set of vias 318 may be, for example, more than 1.5 times the width of each via in the second set of vias 320.

[0036] 4 is a schematic diagram of a top view of vias 420A-D of a semiconductor device (or chip) according to an embodiment of the present disclosure. The vias (118, 120, 218, 220, 318, 320) described herein above have a variety of different cross-sectional shapes when viewed from top to bottom. Some examples include a circular shape as in via 420A, an oval shape as in via 420B, an elongated oval shape as in via 420C, and a "long rod" shape (i.e., an elongated oval shape) as in via 420D. Other suitable shapes are also contemplated by the present disclosure.

[0037] 5 is a schematic diagram of a cross-sectional view of a via 520 in a semiconductor device (or chip) according to an embodiment of the present disclosure. One exemplary embodiment of a via that may be included in a semiconductor device disclosed herein is via 520. Via 520 includes a layer of dielectric material 521 (i.e., a dielectric barrier) that surrounds via 520 within the semiconductor device. An advantage of dielectric material layer 521 is that it provides additional electrical short isolation between via 520 and adjacent structures.

[0038] 6 is a flow diagram of a process 600 for forming or making a chip 300 (using FIGS. 3A-3F as an example) according to an embodiment of the present disclosure. In step 610, the process 600 includes receiving a substrate 305 having a FS 304 and a BS 306, where the substrate 305 includes a first substrate layer 301 and a first semiconductor layer 310 attached to the substrate layer 301, with a first dielectric layer 303 embedded beneath the first semiconductor layer 310. In step 620, the process 600 further includes forming a first via 318 extending from the FS 304 of the substrate 305 toward the BS 306 of the substrate 305. The process 600 also includes step 630 of forming a back-end layer 308 on the FS 304 of the substrate 305, where the back-end layer 308 includes a first set of wiring levels 336, 330. The process 600 further includes step 640 of inverting the substrate 305. Also, in step 650, process 600 includes bonding a second substrate layer to the FS of the substrate. Process 600 also includes step 660 of removing first substrate layer 301 and first dielectric layer 303 to expose device layer 310 or FEOL. In addition, process 600 includes step 670 of forming second dielectric layer 316 on BS 306 of substrate 305 (or BS BEOL 312), where second dielectric layer 316 includes a second set of wiring levels 324 and includes second vias 320 extending from BS 306 to FS 304 of substrate 305. Further, process 600 includes step 680 of forming BS BEOL 312 on BS 306 of substrate 305. In the process, first vias 318 may include a first plurality of vias, and second vias 320 may include a second plurality of vias.

[0039] For purposes of explanation herein, the terms "upper," "lower," "top," "bottom," "left," "right," "rear," "front," "vertical," "horizontal," "front," "back," and derivatives thereof, refer to the device in the orientation shown in the figures. However, it is understood that the device may assume various alternative orientations and step sequences, unless expressly specified to the contrary. It is also understood that the specific devices and processes illustrated in the accompanying drawings and described in the following disclosure are merely exemplary embodiments of the inventive concepts defined in the appended claims. Accordingly, other physical characteristics associated with the embodiments disclosed herein are not to be considered limiting, unless the claims expressly state otherwise.

[0040] For purposes of description, certain aspects, advantages, and novel features of the disclosed embodiments are described herein. The disclosed processes and systems should not be construed as limiting in any way. Instead, the present disclosure is directed to all novel and unstated features and aspects of the various disclosed embodiments, alone or in various combinations and subcombinations with one another. The processes and systems are not limited to any specific aspect or feature or combination thereof, nor do the disclosed embodiments require that any one or more specific advantages be present or problems be solved.

[0041] Although some steps of the disclosed embodiments have been described in a particular sequential order for convenient presentation, it should be understood that this description scheme encompasses rearrangement unless a particular order is required by the language set forth below. For example, steps described sequentially may in some cases be rearranged and / or performed simultaneously. Also, for simplicity, the accompanying figures may not show the various ways in which the disclosed processes may be used in conjunction with other processes. Also, the description sometimes uses the terms "providing" or "implementing" to describe the disclosed processes. These terms are high-level abstractions of the actual steps that are performed. The actual steps that correspond to these terms may vary depending on the particular implementation and are readily discernible by those skilled in the art.

[0042] As used in this application and in the claims, the singular forms "a," "an," and "the" include the plural forms unless the context clearly dictates otherwise. Also, the word "includes" means "comprises."

[0043] While the description of various embodiments of the present disclosure has been presented for illustrative purposes, it is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to explain the principles of the embodiments, practical applications, or technical improvements over technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A semiconductor device comprising: a first via connecting a back surface of the semiconductor device to a front surface of the semiconductor device; and a second via connecting the back surface of the semiconductor device to the front surface of the semiconductor device; The first via and the second via are directly connected to at least one different wiring level on the front side or the back side. Semiconductor devices.

2. The semiconductor device of claim 1 , wherein at least one of the first via and the second via is dual damascene.

3. 2. The semiconductor device of claim 1, wherein the first via and the second via are directly connected to at least one same wiring level on the front side or the back side.

4. 10. The semiconductor device of claim 1, wherein the first via and the second via are made of different metals.

5. 10. The semiconductor device of claim 1, wherein the first via is made of copper.

6. 2. The semiconductor device of claim 1, wherein the first via has a first width and the second via has a second width, the first width being greater than 1.5 times the second width.

7. further comprising one or more source / drain regions; 2. The semiconductor device of claim 1, wherein the second via is adjacent to at least one of the source / drain regions.

8. 2. The semiconductor device of claim 1, wherein the first via is adjacent to a shallow trench isolation region of the semiconductor device.

9. 10. A semiconductor device according to any preceding claim, wherein the first and second vias are long bar-shaped vias.

10. 2. A semiconductor device according to any preceding claim, wherein the first and second vias terminate on different planes within the semiconductor device.

11. 1. A semiconductor device comprising: a first set of vias connecting a back surface of the semiconductor device to a front surface of the semiconductor device; and a second set of vias connecting the back surface of the semiconductor device to the front surface of the semiconductor device; wherein at least one via of the first set of vias and at least one via of the second set of vias are directly connected to at least one different wiring level on the front side or the back side. Semiconductor devices.

12. 12. The semiconductor device of claim 11, wherein at least one of the first set of vias and the second set of vias is dual damascene.

13. 13. The semiconductor device of claim 11, wherein at least one via of the first set of vias and at least one via of the second set of vias are directly connected to at least one same wiring level on the front side or the back side.

14. 14. A semiconductor device according to any preceding claim 11 to 13, wherein the first set of vias and the second set of vias are made of different metals.

15. 15. The semiconductor device of any of the preceding claims 11 to 14, wherein at least one first via of the first set of vias has a first width and at least one second via of the second set of vias has a second width, the first width being greater than 1.5 times the second width.

16. 16. The semiconductor device of any of the previous claims 11 to 15, wherein the first set of vias and the second set of vias are long bar vias.

17. 17. The semiconductor device of any of the preceding claims 11 to 16, wherein the at least one of the first set of vias and at least one of the second set of vias terminate on different planes within the semiconductor device.

18. further comprising one or more source / drain regions; The second set of vias is adjacent to at least one of the source / drain regions.

18. A semiconductor device according to any one of the preceding claims 11 to 17.

19. 1. A method of making a semiconductor device, the method comprising: receiving a substrate having a front surface and a back surface, wherein the substrate includes a first substrate layer, a first semiconductor layer attached to the substrate layer, and a first dielectric layer embedded beneath the first semiconductor layer; forming a first via extending from the front surface of the substrate toward the back surface of the substrate; forming back end of line (BEOL) layers on the front side of the substrate, including a first set of wiring levels in the BEOL layers; inverting the substrate; bonding a second substrate layer to the front surface of the substrate; removing the first substrate layer and the first dielectric layer to expose a front end of line (FEOL) layer; forming a second dielectric layer on the back surface of the substrate, the second dielectric layer including a second set of wiring levels and second vias extending from the back surface to the front surface of the substrate; and forming a backside backend layer (BEOL) on the backside of the substrate; A method comprising:

20. 20. The method of claim 19, wherein the first vias comprise a first plurality of vias and the second vias comprise a second plurality of vias.

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