Patterning semiconductor workpieces

Abstract

In certain embodiments, a method includes depositing a photoresist layer on a semiconductor wafer to be patterned by photolithography, the photoresist layer having a first height, and exposing the photoresist layer to an actinic radiation pattern to form exposed and unexposed regions in the photoresist layer. The method further includes depositing a chemical agent-containing layer on the photoresist layer and performing a post-exposure bake of the semiconductor wafer. The post-exposure bake modifies portions of the photoresist layer to form soluble portions of the photoresist layer for development. The soluble portions of the photoresist layer include the exposed regions and upper portions of the unexposed regions. The method further includes developing the photoresist layer to selectively remove the soluble portions, the remaining portions of the unexposed regions forming a patterned structure on the semiconductor wafer and having a second height less than the first height.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Non-Provisional Patent Application No. 17 / 943,926, filed September 13, 2022, which is incorporated herein by reference in its entirety.

[0002] FIELD OF THE DISCLOSURE The present disclosure relates generally to semiconductor manufacturing, and in particular embodiments, to patterning semiconductor workpieces. [Background technology]

[0003] Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and other material layers on a semiconductor substrate and patterning the layers using lithography to form circuit components and elements on the substrate. The semiconductor industry continues to increase the density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually shrinking minimum feature sizes, allowing more components to be packed into a given area. Summary of the Invention [Means for solving the problem]

[0004] In certain embodiments, a method includes depositing a photoresist layer on a semiconductor wafer to be patterned by photolithography, the photoresist layer having a first height, and exposing the photoresist layer to an actinic radiation pattern to form exposed and unexposed regions in the photoresist layer. The method further includes depositing a chemical agent-containing layer on the photoresist layer and performing a post-exposure bake of the semiconductor wafer. The post-exposure bake modifies portions of the photoresist layer to form soluble portions of the photoresist layer for development. The soluble portions of the photoresist layer include the exposed regions and upper portions of the unexposed regions. The method further includes developing the photoresist layer to selectively remove the soluble portions, the remaining portions of the unexposed regions forming a patterned structure on the semiconductor wafer and having a second height less than the first height.

[0005] In certain embodiments, a method includes depositing a photoresist layer on a semiconductor wafer to be patterned by photolithography, the photoresist layer having a first height. The method further includes depositing a chemical agent-containing layer on the photoresist layer and performing a pre-exposure bake of the semiconductor wafer. The pre-exposure bake diffuses a first solubility-modifying agent from the chemical agent-containing layer into a first portion of the photoresist layer, such that the first portion of the photoresist layer is disposed between the chemical agent-containing layer and a second portion of the photoresist layer. The method further includes selectively removing the chemical agent-containing layer and exposing the second portion of the photoresist layer to a pattern of actinic radiation through the first portion of the photoresist layer to form exposed and unexposed regions in the second portion of the photoresist layer. The method further includes performing a post-exposure bake of the semiconductor wafer, where the post-exposure bake modifies exposed areas of the second portion of the photoresist layer so that they are soluble in development, and developing the photoresist layer to selectively remove the first portion of the photoresist layer and the exposed areas of the second portion of the photoresist layer modified by the post-exposure bake, wherein the remaining portions of the unexposed areas of the photoresist layer form a patterned structure of the semiconductor wafer and have a second height that is less than the first height of the photoresist layer.

[0006] In certain embodiments, a method includes forming a first patterned structure on a semiconductor wafer, the first patterned structure defining a first recess and having a first height. Forming the first patterned structure includes depositing a photoresist layer on the photolithographically patterned semiconductor wafer, the photoresist layer having a second height greater than the first height, depositing a trimming layer on the photoresist layer, reducing the second height of the photoresist layer to the first height using a first solubility modifier diffused into the photoresist layer from the trimming layer before developing the photoresist layer, exposing the photoresist layer to an actinic radiation pattern, and developing the photoresist layer, wherein remaining portions of the photoresist layer form micro-fabricated structures defining the recess. The method further includes depositing a first overcoat film on the semiconductor wafer, where the first overcoat film fills the first recess and covers the first patterned structure, diffusing a second solubility modifier of the first overcoat film into an outer periphery of the first patterned structure, and selectively removing the first overcoat film. The method further includes depositing a second overcoat film on the semiconductor wafer, where the second overcoat film fills the first recess and covers the first patterned structure, and performing a development process that removes a first portion of the second overcoat film to expose the outer periphery of the first patterned structure and removes the outer periphery of the first patterned structure to define a second patterned structure. The second patterned structure includes remaining portions of the first patterned structure and second portions of the second overcoat film interspersed among the remaining portions of the first patterned structure, and the second patterned structure defines a second recess.

[0007] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following descriptions which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1A] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 1B] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 1C] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 1D] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 1E] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 1F] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 1G] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 2A] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 2B] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 2C] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 2D] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 2E] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 3A] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 3B]1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 3C] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 3D] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 3E] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 3F] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 3G] 1A-1C illustrate cross-sectional views of an exemplary semiconductor workpiece during an exemplary patterning process in accordance with certain embodiments. [Figure 4] 1 illustrates an exemplary method for patterning a semiconductor workpiece, according to certain embodiments. [Figure 5] 1 illustrates an exemplary method for patterning a semiconductor workpiece, according to certain embodiments. [Figure 6] 1 illustrates an exemplary method for patterning a semiconductor workpiece, according to certain embodiments. [Figure 7] FIG. 1 illustrates a block diagram of an exemplary lithography system, in accordance with certain embodiments. [Figure 8] FIG. 1 illustrates a block diagram of an exemplary lithography system, in accordance with certain embodiments. [Figure 9] 1 illustrates an exemplary liquid-based spin-on deposition system, in accordance with certain embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0009] Throughout the deposition, patterning, and removal processes associated with forming semiconductor devices, certain structures fabricated may include recesses with high aspect ratios. The aspect ratio of a feature (e.g., a trench) generally refers to the ratio of two dimensions of the feature (e.g., height (or depth / thickness) to width). A high aspect ratio may describe a structure in which one dimension is significantly larger than the other. As a specific example, features are often formed in layers of semiconductor devices with heights that are significantly larger than their widths. Generally, the higher the aspect ratio, the greater the risk that certain patterning defects, such as pattern wiggling and pattern collapse, may occur. Pattern wiggling may refer to a scenario in which patterned lines are not straight. Pattern collapse may include any number of symptoms, but ultimately results in the pattern not matching the target pattern.

[0010] As an example, the circuit element / feature may be a contact, and the recesses formed in one or more layers in one or more etching processes may have a high aspect ratio, with the depth of the recess significantly greater than the width of the recess. As a particular example, an organic layer (e.g., a spin-on carbon anti-reflective coating) may be used as an etch mask in forming recesses (e.g., contact holes). Before the organic layer is used as an etch mask, an overlying photoresist layer may be used as an etch mask to pattern recesses in the organic layer, and the depth of these recesses may be greater, sometimes significantly greater, than the width of the recesses. A linear critical dimension profile in high aspect ratio features (e.g., contact holes, metal lines, fins, gate lines, vias, or other elements) may be important in certain devices. For example, maintaining linear critical dimensions in high aspect ratio etches may be difficult, especially at technology nodes of 10 nanometers and below.

[0011] Another challenge posed by high aspect ratio narrow recesses in patterned layers is the perpendicularity of the recesses to the underlying layer: if the recess sidewalls are sloped, accurately transferring the target pattern into the underlying layer (e.g., using an anisotropic etching process such as reactive ion etching (RIE)) can be more difficult due to shadow effects that prevent reactive etching species from penetrating the full depth of the recess.

[0012] One exemplary area where high aspect ratio processing can be encountered is during photolithography. Forming features in semiconductor devices typically involves a photolithography process, which generally involves photolithographically forming a pattern in a photoresist layer and then transferring the pattern to one or more underlying layers for further manufacturing steps. In the lithography process, a patterned mask formed from the photoresist layer is used to form the features. However, defects in the patterned mask can propagate to the formed features. Problems associated with such defects in the formed features can be amplified at smaller technology nodes.

[0013] The wavelength of the radiation, which may be determined according to the photolithography technique used, may affect the minimum feature size achievable in semiconductor manufacturing. Some newer techniques, such as extreme ultraviolet (EUV) lithography, can directly achieve relatively small feature sizes approaching a 13 nm half pitch using EUV at a wavelength of 13.5 nanometers with a numerical aperture (NA) of 0.33. However, these newer techniques may have certain drawbacks, including cost.

[0014] Some older lithography techniques, such as 193 nanometer immersion and i-line technologies, are still commonly used and can be used in combination with other processes to achieve smaller feature sizes than can be achieved directly using the older lithography techniques. For example, 193 nanometer immersion lithography can be used in combination with anti-spacer patterning processes to achieve sub-resolution feature sizes of less than 15 nanometers, and potentially even 10 nanometers or less. Anti-spacers can also be formed through the lateral diffusion of solubility modifiers (e.g., acids) in organic films such as photoresists and polymer overcoats.

[0015] In some cases, the primary photoresist pattern for the anti-spacer is generated using older lithography techniques, such as 193 nanometer immersion and / or i-line technologies, to reduce the cost of high-volume manufacturing (HVM). With these lithography techniques, the photoresist film thickness can range from 100 nanometers to 1 micrometer. This photoresist thickness can present challenges to the anti-spacer patterning process. For example, for a 10 nanometer anti-spacer trench, the trench aspect ratio can be 10:1 with 193 nanometer immersion lithography and up to 100:1 with i-line lithography, both of which can experience loss of pattern fidelity. As a specific example, applying sub-10 nanometer anti-spacer techniques to older lithography techniques (e.g., 193 nanometer immersion) using relatively thick photoresists (e.g., 50 nanometers or thicker) can result in feature aspect ratio concerns that affect pattern fidelity and the ability to properly transfer the pattern to the underlying hard mask.

[0016] Certain embodiments of the present disclosure provide techniques for reducing aspect ratios that may be encountered during semiconductor manufacturing, such as during a patterning process. For example, certain embodiments provide techniques for reducing the thickness of a photoresist layer before a development process for developing the exposed photoresist. In certain embodiments, the thickness of the photoresist is reduced after an exposure lithography step for processing the photoresist. In certain embodiments, the thickness of the photoresist is reduced before the exposure lithography step. In certain embodiments, the thickness of the photoresist is reduced with little or no effect on the integrity of the lithography process for patterning the photoresist. For example, the thickness of the photoresist may be reduced with little or no effect on the critical dimensions (e.g., width) of patterned structures (e.g., lines) in the photoresist.

[0017] 1A-1G illustrate cross-sectional views of an exemplary semiconductor workpiece 100 during an exemplary patterning process 102, according to certain embodiments. In certain embodiments, some or all of the patterning process 102 may be referred to as an anti-spacer patterning process, or simply an anti-spacer process. In certain embodiments, the patterning process 102 may be used to achieve sub-resolution features in an underlying layer of a semiconductor wafer. Sub-resolution features may refer to features that are smaller than can be achieved directly depending on the wavelength of the lithography technique being used (e.g., without the use of some additional patterning process, such as an anti-spacer process).

[0018] Semiconductor workpiece 100 generally refers to any suitable semiconductor element that may be processed according to embodiments of the present disclosure. Semiconductor workpiece 100, or a portion thereof, may also be referred to as a semiconductor wafer, such as a silicon wafer. Semiconductor workpiece 100 includes a substrate 104, an intermediate layer 106 disposed on substrate 104, and a patterned structure 108 disposed on intermediate layer 106.

[0019] Substrate 104 may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer on or overlying a base substrate structure, such as a thin film. Thus, substrate 104 is not limited to any particular base structure, underlying layer, or overlying layer, patterned or not, but rather may include any such layer or base structure, and any combination of layers and / or base structures. Substrate 104 may be a bulk substrate, such as a bulk silicon wafer, a silicon-on-insulator (SOI) wafer, or various other semiconductor substrates.

[0020] The intermediate layer 106 and the patterned structure 108 may be a photolithographic stack. The intermediate layer 106 may also be referred to as an underlayer, particularly when described with reference to the patterned structure 108 or the layer on which the patterned structure 108 is formed. The present disclosure contemplates the substrate 104 and the intermediate layer 106 having any suitable thickness.

[0021] The intermediate layer 106 represents any suitable combination of one or more layers, one or more of which are patterned using the patterning structure 108. For example, the intermediate layer 106 may include a hard mask layer, an amorphous carbon layer, a silicon carbide layer, an underlayer anti-reflective coating, and / or any other layer, one or more of which may be useful in the patterning process. Additionally or alternatively, the intermediate layer 106 may include a stack of films. For example, the intermediate layer 106 may include films of dielectric and / or conductive materials, such as oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium nitride, tantalum nitride, alloys thereof, and combinations thereof. For example, the intermediate layer 106 may be a dielectric layer or alternating dielectric layers.

[0022] The semiconductor workpiece 100 may be formed in any suitable manner, including using any suitable combination of wet and / or dry deposition and etching techniques. For example, the semiconductor workpiece 100 may be deposited using any technique appropriate for the material being deposited and the semiconductor features being formed. Suitable deposition processes include spin-on coating processes, chemical vapor deposition (CVD) processes, atomic layer deposition (ALD) processes, plasma deposition processes (e.g., plasma-enhanced CVD (PECVD) processes), and / or other layer deposition processes or combinations of processes.

[0023] Patterned structures 108 may be formed of any suitable material and may be lines or other suitable types of semiconductor structures. In particular embodiments, patterned structures 108 are formed of a photoresist material. Additional details regarding patterned structures 108 and possible techniques for forming patterned structures 108 are described below with reference to Figures 2A-2E and 3A-3G. Furthermore, patterned structures 108 may be formed using any suitable type of lithographic technique.

[0024] The patterned structure 108 may be formed from a layer of photoresist material. To form the patterned structure 108, the photoresist layer may be processed in two main steps, an exposure step and a development step, to create a pattern for further processing of an underlying layer (e.g., the intermediate layer 106). In the exposure step, the photoresist material reacts with ultraviolet (UV) or other light to form a pattern on the photoresist material according to a pattern mask. Depending on the type of photoresist material used, portions of the photoresist exposed to UV light may be more or less soluble in a developer, making those exposed areas more or less removable when processed using a developer. For example, due to exposure to UV light, portions of the photoresist exposed to UV light may have different material properties than unexposed areas of the photoresist. Different material properties may include, for example, volatility, reactivity, and / or solubility. In the development step, the photoresist material is exposed to a developer to remove portions of the photoresist layer.

[0025] Patterned structure 108 may have any suitable thickness, referred to as height (labeled H2) throughout this disclosure. In particular embodiments, photoresist layer 110 has a thickness between 5 nm and 100 nm, e.g., between 10 nm and 30 nm. It should be understood that these thickness values ​​are provided by way of example only, and that photoresist layer 109 may have any suitable thickness. For reasons described in more detail below, it may be desirable to reduce the height of patterned structure 108 relative to conventional techniques.

[0026] A recess 110 may be defined by the patterned structure 108. While two patterned structures 108 are shown, it should be understood that additional patterned structures 108 may be formed laterally from the illustrated patterned structure 108. The recess 110 may have any suitable lateral dimension. While this disclosure primarily describes "recesses," other suitable features may be formed in or on a semiconductor substrate using embodiments of the present disclosure, including lines, holes, trenches, vias, and / or other suitable structures (whether or not considered "recesses").

[0027] As will be described in more detail below in accordance with FIG. 1G, the patterning process used to form the patterned structure 108 shown in FIG. 1A is carried out in accordance with the concepts described in this disclosure, such that the height (H2) of the patterned structure 108 is reduced before performing subsequent steps of the patterning process 102.

[0028] Additional processing may be performed to create features with critical dimensions smaller than the critical dimensions of patterned structure 108. In this particular example, an anti-spacer patterning process may be performed on semiconductor workpiece 100 of FIG.

[0029] As shown in FIG. 1B , an overcoat film 112 may be deposited on the semiconductor workpiece 100. The overcoat film 112 may fill the recess 110 and cover the patterned structure 108. The overcoat film 112 may be a multi-component material including a first component and a second component as deposited. The first component may be, for example, a polymer. The second component may be, for example, a solubility modifier such as an acid (e.g., a free acid). As another example, the second component may be a chemical agent-generating component that generates a solubility modifier (e.g., an acid) in response to an appropriate chemical agent activation trigger (e.g., heat or radiation). Exemplary chemical agent-generating components include a thermal acid generator (TAG) configured to generate an acid in response to heat or a photoacid generator (PAG) configured to generate an acid in response to actinic radiation.

[0030] The overcoat film 112 may be deposited on the semiconductor workpiece 100 in any suitable manner. For example, the overcoat film 112 may be deposited by spin coating, spray coating, dip coating, or roll coating. As a particular example, the overcoat film 112 may be deposited on the semiconductor workpiece 100 using a spin-on deposition technique 114, which may also be referred to as spin coating.

[0031] Spin-on deposition deposits a specific material (e.g., a material of the overcoat film 112) onto a substrate (e.g., the intermediate layer 106 formed on the substrate 104). The substrate is then spun at a relatively high speed (or, if not already spinning, at a relatively low speed) so that centrifugal force causes the deposited material to move toward the edge of the substrate, thereby coating the substrate. Excess material is typically shaken off the substrate. In certain embodiments, the spin-on deposition technique 114 includes dispensing liquid chemicals onto the semiconductor workpiece 100 (e.g., onto the upper surface of the intermediate layer 106 and onto the exposed surface of the patterned structure 108) using a coating module equipped with a liquid delivery system capable of dispensing one or more types of liquid chemicals. The dispensed volume can be between 0.2 ml and 10 ml, e.g., between 0.5 ml and 2 ml. The substrate (e.g., the workpiece 100) can be secured to a rotating chuck that supports the substrate. The rotation speed during liquid dispensing can be between 50 rpm and 3000 rpm, e.g., between 1000 rpm and 2000 rpm. The system may also include an anneal module that can bake or apply photon radiation to the substrate after the chemicals have been applied. It should be understood that this exemplary spin-on deposition technique 114 and associated values ​​are provided by way of example only.

[0032] Additionally or alternatively, the overcoat film 112 may be deposited using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable processes.

[0033] In certain embodiments, the overcoat film 112 may be deposited in a deposition module (e.g., a spin-coating module) of a larger track system for the lithography process. An exemplary lithography system including a track system is described in more detail below with reference to Figures 7-8.

[0034] 1C, a bake 116 of the semiconductor workpiece 100 may be performed. Baking the semiconductor workpiece 100 may cause a solubility modifier 117 (e.g., an acid) to diffuse into portions of the patterned structure 108, causing those portions of the patterned structure 108 to dissolve in a developer solution.

[0035] For example, in the case of an overcoat film 112 that includes free acid, the solubility modifier 117 may be the free acid, and baking the semiconductor workpiece 100 may cause the free acid to diffuse into portions of the patterned structure 108, causing those portions of the patterned structure 108 to dissolve in the developer.

[0036] As another example, in the case of an overcoat film 112 that includes TAG as a chemical agent-generating component, baking the semiconductor workpiece 100 may cause the TAG to generate a solubility modifier 117 (e.g., an acid) (this may be referred to as activating the acid), causing the generated solubility modifier 117 to diffuse into portions of the patterned structure 108 and cause those portions of the patterned structure 108 to dissolve in a developer solution.

[0037] As another example, for an overcoat film 112 that includes a PAG as a chemical agent-generating component, an exposure step that includes exposing the overcoat film 112 to radiation can be performed before baking the semiconductor workpiece 100. The exposure step can generate a solubility modifier 117 (e.g., an acid) in the PAG, which can be referred to as activating the acid. Baking the semiconductor workpiece 100 can cause the generated solubility modifier 117 to diffuse into portions of the patterned structure 108, causing those portions of the patterned structure 108 to dissolve in a developer solution.

[0038] Baking the semiconductor workpiece 100 generally causes the solubility modifier 117 to diffuse into the peripheral region of the patterned structure 108 to a target depth, modifying the peripheral region to be soluble in a developer, forming modified portion 118. For example, the modified peripheral region (modified portion 118) may form a deprotected shell-like structure around the patterned structure 108, consuming a portion of the periphery of the patterned structure 108 and thereby reducing both the vertical and lateral dimensions of the patterned structure 108. Among other factors, the baking time and / or temperature may be optimized to control the depth of diffusion of the solubility modifier to achieve the target depth. The target depth, particularly the target depth on the sidewall surface of the patterned structure 108, may generally correspond to a target critical dimension of a recess in a structure formed using process 102 as described in more detail below in connection with FIG. 1G.

[0039] 1A, the difference between H2 and H3 represents the depth of diffusion of the solubility modifier in at least the vertical dimension. In certain embodiments, the depth of diffusion, and the resulting modification of the solubility of the patterned structure 108, is approximately equal on all sides of the patterned structure 108.

[0040] In certain embodiments, bake 116 may be performed by heating semiconductor workpiece 100 in a process chamber under vacuum or gas flow at a temperature between 50°C and 250°C, for example, in certain embodiments, at a temperature between 60°C and 140°C. In certain examples, semiconductor workpiece 100 is baked for 1 to 3 minutes. Bake conditions for bake 116 may be selected to promote diffusion of the solubility modifier (and optionally, generation of the solubility modifier from chemical-generating components of overcoat film 112, if appropriate) and solubility modification to a target depth at the periphery of the associated patterned structure 108. The present disclosure contemplates performing bake 116 in any suitable manner.

[0041] 1D , the overcoat film 112 may be selectively removed from the semiconductor workpiece 100 with minimal or no removal of the modified portions 118 of the patterned structure 108. The present disclosure contemplates selectively removing the overcoat film 112 in any suitable manner. In certain embodiments, the overcoat film 112 may be selectively removed from the semiconductor workpiece 100 using a suitable solvent or other developer.

[0042] 1E, an overcoat film 120 may be deposited on the semiconductor workpiece 100. The overcoat film 120 may fill the recess 110 and cover the patterned structure 108, including over the modified portions 118 of the patterned structure 108.

[0043] The overcoat film 120 may include a polymer capable of filling the recess 110. The material of the overcoat film 120 may have a low dissolution rate in a developer selected to expose the recess 124, as described in more detail below with reference to FIG. 1E. The material of the overcoat film 120 may also be resistant to etching at a later stage to transfer the pattern to the interlayer 106 (e.g., the pattern defined by the remaining portions of the overcoat film 120 and the patterned structure 123, including the recess 124, and the associated patterned transfer, are described in more detail below with reference to FIGS. 1F-1G). In certain embodiments, the material (e.g., polymer) and formulation additives of the overcoat film 120 are soluble in one or more solvents that exhibit little or no intermixing with the underlying resist mandrel (e.g., the patterned structure 108). Such polymer compositions may include a combination of monomer units containing moderately polar structures, such as hydroxystyrene, methyl methacrylate, and methyl acrylic acid. Low (e.g., minimal) concentrations of additional formulation components may include quenchers and / or photodecomposable bases. Although the overcoat film 120 is described as comprising particular materials, the present disclosure contemplates an overcoat film 120 comprising any suitable material.

[0044] The overcoat film 120 may be deposited on the semiconductor workpiece 100 in any suitable manner. For example, the overcoat film 120 may be deposited by spin coating, spray coating, dip coating, or roll coating. As a particular example, the overcoat film 120 may be deposited on the semiconductor workpiece 100 using a spin-on deposition technique 114, similar to that described above with reference to FIG. 1B. Additionally or alternatively, the overcoat film 120 may be deposited using CVD, PECVD, ALD, or other suitable processes.

[0045] In certain embodiments, the overcoat film 120 may be deposited in a deposition module (e.g., a spin-coating module) of a larger track system for the lithography process. An exemplary lithography system including a track system is described in more detail below with reference to Figures 7-8.

[0046] 1F, modified portions 118 of patterned structure 108 and portions of overcoat film 120 may be selectively removed to expose unmodified portions 119 of patterned structure 108 and remaining portions 122 of overcoat film 120. The present disclosure contemplates removing modified portions 118 of patterned structure 108 and portions of overcoat film 120 in any suitable manner.

[0047] In particular embodiments, portions of the overcoat film 120 and the modified portions 118 of the patterned structure 108 are selectively removed using a developer. For example, the developer may remove a sufficient portion of the overcoat film 120 to expose the modified portions 118 of the patterned structure 108, and then remove those modified portions 118 of the patterned structure 108 at a faster removal rate (e.g., dissolution rate). As a particular example, the developer may remove a sufficient portion of the overcoat film 120 at a first removal rate to expose the modified portions 118 of the patterned structure 108, and then remove the modified portions 118 of the patterned structure 108 at a second, faster removal rate. In certain embodiments, the second removal rate is significantly greater than the first removal rate (for example, 1000:1, as a non-limiting example) so that when the modified portions 118 of the patterned structure 108 are exposed, the modified portions 118 of the patterned structure 108 are removed much faster than the additional removal of portions of the overcoat film 120.

[0048] Removal of modified portions 118 of patterned structure 108 results in patterned structure 123 formed from unmodified portions 119 of patterned structure 108. Removal of modified portions 118 of patterned structure 108 exposes remaining portions 122 of overcoat film 120 and recesses 124 defined by patterned structure 123.

[0049] In the state shown in FIG. 1F , the combination of the remaining portion 122 of the overcoat film 120, the patterned structure 123, and the recess 124 defines a pattern that can be transferred to an underlying layer (e.g., the interlayer 106). The difference between the width (critical dimension, or CD) of the recess 124 and the adjacent structures (e.g., the remaining portion 122 of the overcoat film 120 and the patterned structure 123) defines the aspect ratio. As discussed above, larger aspect ratios generally create problems when the recess 124 is formed or when the patterning defined by the recess 124 and the adjacent structures is transferred to an underlying layer. These problems can lead to pattern collapse, surface roughness, lack of fidelity to the target critical dimension, and / or other issues. Thus, it may be desirable to minimize the aspect ratio defined by the remaining portion 122 of the overcoat film 120, the patterned structure 123, and the recess 124.

[0050] Certain embodiments of the present disclosure provide techniques for forming semiconductor workpiece 100 in the state shown in FIG. 1A . Thus, in certain embodiments, the techniques described herein can be incorporated into a larger patterning process (e.g., process 102) to form sub-resolution features. The present disclosure provides an exemplary process for reducing the height of a patterned structure (e.g., patterned structure 108) from photoresist to height H2 as part of forming semiconductor workpiece 100 in the state shown in FIG. 1A . That is, the patterning process used to form patterned structure 108 shown in FIG. 1A is performed according to concepts described in the present disclosure, resulting in a reduction in the height (H2) of patterned structure 108 before performing subsequent steps of patterning process 102. Performing the height reduction at this stage can reduce the aspect ratio of a pattern defined using further steps of process 102 to create recess 124. Furthermore, height reduction of a structure patterned from photoresist (e.g., patterned structure 108) can be achieved with little or no impact on the ability to accurately pattern the structure (e.g., patterned structure 108) from photoresist.

[0051] As shown in FIG. 1F, patterned structure 123 has a reduced height H3 that is less than the height (H2) of patterned structure 108 (see FIG. 1A) and less than the height (H1) of the photoresist layer (see FIGS. 2A and 3A, described below) in which the semiconductor structure is formed. This reduced height H3 may be due, at least in part, to the manner in which semiconductor workpiece 100 is formed in the state shown in FIG. 1A (e.g., using patterning process 202 of FIGS. 2A-2E or patterning process 302 of FIGS. 3A-3G). Recess 124 has a lateral width that may be referred to as a critical dimension (labeled CD). This critical dimension (the lateral width of recess 124) may be the target critical dimension of process 102. In certain embodiments, reduced height H3 results in an improved ability to achieve the desired critical dimension of recess 124.

[0052] Although the height of the patterned structure 123 is shown to vary (e.g., the height of the remaining portion 122 of the overcoat film 120 is shown to be greater than the height of the unmodified portion 119 of the patterned structure 108), the present disclosure contemplates that the remaining portion 122 of the overcoat film 120 and the unmodified portion 119 of the patterned structure 108 have the same or different heights. In certain embodiments, processing conditions and formulation chemistries can be adjusted to planarize and / or minimize discrepancies in the height of the remaining portion 122 of the overcoat film 120 and the height of the unmodified portion 119 of the patterned structure 108.

[0053] 1G , the pattern defined by the combination of the remaining portions 122 of the overcoat film 120, the patterned structures 123, and the recesses 124 may be transferred to the interlayer 106. This pattern transfer may be performed using any suitable combination of etching processes, including any suitable wet and dry etching processes. For example, the etching process may include one or more of liquid etching, chemical wet etching, chemical dry etching, plasma etching, atomic layer etching, or other suitable etching processes. In the illustrated example, transferring the pattern defined by the combination of the remaining portions 122 of the overcoat film 120, the patterned structures 123, and the recesses 124 to the interlayer 106 includes extending the recesses 124 into the interlayer 106. Due at least in part to the improved CD and / or reduced height H3 of the recesses 124, certain embodiments improve pattern transfer fidelity when transferring the pattern to an underlying layer (e.g., the interlayer 106).

[0054] 2A-2E and 3A-3G, certain embodiments provide techniques for reducing the height of a photoresist layer, including reducing the height of the photoresist layer after exposing a semiconductor workpiece (e.g., including the photoresist layer) to an actinic radiation pattern as part of a process for patterning the photoresist layer (e.g., into one or more semiconductor structures). Examples of such are illustrated and described with reference to FIGS. 2A-2E. Certain embodiments provide techniques for reducing the height of a photoresist layer, including reducing the height of the photoresist layer before exposing a semiconductor workpiece (e.g., including the photoresist layer) to an actinic radiation pattern as part of a process for patterning the photoresist layer (e.g., into one or more semiconductor structures). Examples of such are illustrated and described with reference to FIGS. 3A-3G.

[0055] For the sake of brevity and clarity, this specification adopts the convention that elements patterned [x02] may be related implementations of processes and / or semiconductor workpieces in particular embodiments. For example, unless otherwise stated or readily apparent, semiconductor workpiece 200 may be similar to semiconductor workpiece 100, substrate 204 may be similar to substrate 104, and so on. A similar convention is adopted for other elements, as evidenced by the use of similar terminology in combination with the three-digit numbering system described above. By this convention, where appropriate, previously described features are incorporated by reference and not repeated.

[0056] 2A-2E illustrate cross-sectional views of an exemplary semiconductor workpiece 200 during an exemplary patterning process 202, in accordance with certain embodiments. In the example illustrated in Figures 2A-2E, the height of a photoresist layer is reduced after exposing the semiconductor workpiece 200 (e.g., including the photoresist layer) to an actinic radiation pattern, but before developing the photoresist layer.

[0057] 2A, a semiconductor workpiece 200 may be formed that includes an intermediate layer 206 formed on a substrate 204 and a photoresist layer 209 formed on the intermediate layer 206. For example, the intermediate layer 206 may be disposed on the substrate 204, and the photoresist layer 209 may be disposed on the intermediate layer 206.

[0058] The photoresist layer 209 may be used to form a masking layer for patterning the intermediate layer 206 and may include any suitable type of layer made of a suitable material to function as a photoresist. The photoresist layer 209 is a layer that is patterned by exposure, such as using an exposure module, which may be called a scanner or stepper, followed by a development step to form patterned features. For example, the photoresist layer 209 may include a light-sensitive material made of a polymer, a solvent, and a sensitizer. The polymer is designed to change its structure when exposed to actinic radiation. The solvent allows the material of the photoresist layer 209 to spin and form a thin layer on the underlying layer (e.g., the intermediate layer 206). The sensitizer (or inhibitor) controls the photoreaction in the polymer phase.

[0059] For example, the photoresist layer 209 can be a chemically amplified resist (CAR). As another example, the photoresist layer 209 can be a metal-based resist material, such as an organometallic material, such as a metal oxide (MOx) photoresist. The lithography technique used to pattern the photoresist layer to form the patterned structure 108 can have an associated resolution that matches the wavelength of the radiation implemented using the lithography technique. Such photolithography techniques include immersion lithography (e.g., using 193 nanometer immersion lithography), i-line lithography (e.g., using 365 nanometer wavelength UV radiation for exposure), h-line lithography (e.g., using 405 nanometer wavelength UV radiation for exposure), EUV lithography, deep ultraviolet (DUV) lithography, or any suitable photolithography. In addition, the lithography technique may be mask-based (eg, projection lithography), maskless (eg, electron beam (e-beam) lithography), or another suitable type of lithography.

[0060] The photoresist material of the photoresist layer 209 can be appropriate for the type of photolithography technique used to pattern the photoresist layer 209. The photoresist material of the photoresist layer 209 can be a positive photoresist or a negative photoresist. In the case of a positive photoresist, areas of the photoresist layer 209 that the semiconductor manufacturer intends to remove (and generally correspond to areas of the underlying layer that will be removed using the patterned structure from the photoresist layer 209 as an etch mask) are exposed to UV light. The UV light changes the chemical structure of the exposed areas of the photoresist so that they become more soluble in a developer that can be used to remove the exposed areas in a development process, while the unexposed areas of the photoresist remain. In the case of a negative photoresist, the portions of the photoresist layer 209 that are exposed to UV polymerize, crosslink, network, or otherwise change their chemical composition, making the exposed areas less soluble in the developer, while the unexposed areas can be removed using the developer.

[0061] In certain embodiments, photoresist layer 209 may include a chemical agent-generating component (e.g., a PAG) that releases a solubility-modifying agent (acid or photoacid) in response to exposure to UV light. The generated acid may induce further chemical reactions in photoresist layer 209, which may improve gradation in a patterned version of photoresist layer 209.

[0062] The photoresist layer 209 may be deposited in any suitable manner. For example, the photoresist layer 209 may be deposited by spin coating, spray coating, dip coating, or roll coating. As a particular example, the photoresist layer 209 may be deposited on the semiconductor workpiece 100 using a spin-on deposition technique 214, which may also be referred to as spin coating. Exemplary details of an exemplary technique for spin-on deposition are described above in connection with the spin-on deposition technique 114, and that description is incorporated by reference.

[0063] In certain embodiments, the photoresist layer 209 is deposited on the intermediate layer 206 in a deposition module (e.g., a spin coating module) of a larger track system for the lithography process. An exemplary lithography system including a track system is described in more detail below with reference to Figures 7-8. However, it should be understood that the photoresist layer 209 may be deposited using any suitable dry or wet process.

[0064] In certain embodiments, a topcoat 226 is formed on the upper surface of photoresist layer 209. Topcoat 226 can serve any suitable purpose. By way of example, if immersion lithography techniques are used to pattern photoresist layer 209, topcoat 226 may function as a diffusion barrier to inhibit diffusion into photoresist layer 209 of a liquid that functions as a high refractive index liquid (lensing agent) during immersion lithography. In certain embodiments, topcoat 226 may have the ability to be coated on top of a photoresist material with little or no effect on the original function of the photoresist, and to be stripped prior to or removed during photoresist development with little or no effect on the functionality of the photoresist. By way of example only, topcoat 226 may include a fluorinated polymer.

[0065] The topcoat 226 may be deposited on the semiconductor workpiece 200 in any suitable manner.

[0066] For example, the topcoat 226 may be deposited in a separate deposition step after the deposition of the photoresist layer 209. As a particular example, the topcoat 226 may be deposited in a separate spin-coating process and may be deposited in a separate on-track spin-coating module.

[0067] As another example, the photoresist layer 209 and the topcoat 226 may be deposited as part of a single deposition step. As a particular example, the photoresist component that forms the photoresist layer 209 and the topcoat component that forms the topcoat 226 may be combined into a single formulation (e.g., dissolved together in solution) in appropriate relative amounts. The formulation may be designed so that the photoresist component and the topcoat component self-segregate when deposited on the surface of the semiconductor workpiece 200 (e.g., on the surface of the intermediate layer 206). For example, a spin-coating technique (e.g., similar to the spin-on deposition technique 214) may deposit the photoresist component on the intermediate layer 206 to form the photoresist layer 209, while the spin-coating technique causes the topcoat component to rise to the top and form the topcoat 226 on the photoresist layer 209. During the spin-coating process (including associated process conditions such as temperature and spin speed), the photoresist component may be attracted to the surface material of the intermediate layer 206, while the topcoat component may be attracted to the environment (e.g., air) above the semiconductor workpiece 200, resulting in the photoresist component and the topcoat component separating into the photoresist layer 209 and the topcoat 226. Thus, in certain embodiments, the topcoat 226 may be formed on the photoresist layer 209 in a single deposition.

[0068] Furthermore, because the topcoat 226 is formed on the photoresist layer 209 before exposing (irradiating) the photoresist layer 209, the topcoat 226 may be relatively transparent to the actinic radiation used to irradiate portions of the photoresist layer 209. This additional consideration may also influence the selection of the material for the topcoat 226.

[0069] Initially, the photoresist layer 209 may have any suitable thickness, which will be referred to as height (labeled H1) throughout this disclosure. Height H1 may refer to the thickness of the photoresist layer 209 as deposited or after any suitable pre-patterning treatment, such as any planarization or other smoothing treatment. Height H1 may be optimized to take advantage of the full aerial image and photons to which the photoresist layer 209 is exposed during the exposure step. In other words, in certain embodiments, simply depositing a thinner photoresist layer 209 may not be optimal or practical to provide thinner patterned structures (e.g., patterned structure 108) because this may adversely affect lithographic performance. Depositing a thinner photoresist layer 209 (or otherwise thinning the photoresist layer 209) before exposure may result in the photoresist layer 209 having a non-optimized height during exposure, which may cause loss of patterning of the photoresist layer 209, including suboptimal profile, surface roughness, etc.

[0070] In particular embodiments, photoresist layer 209 has a thickness of 5 nm to 5 μm, for example, 20 nm to 1 μm. Suitable thickness values ​​may be determined, in part, by the photolithography technique used to pattern photoresist layer 209. It should be understood that these thickness values ​​are provided by way of example only, and that photoresist layer 209 may have any suitable thickness.

[0071] As shown in FIG. 2B , photoresist layer 209 is exposed (irradiated) with actinic radiation pattern 228 to form a pattern in photoresist layer 209. This may be referred to as the exposure phase of a photolithography process. For example, actinic radiation 228 may be directed toward the surface of semiconductor workpiece 200, particularly photoresist layer 209, through a patterned mask 230 to form a target pattern in photoresist layer 209. The target pattern may include exposed regions 232 and unexposed regions 234. Depending on whether a positive or negative photoresist is used, exposed regions 232 of photoresist layer 209 may be designed to be removed or remain when photoresist layer 209 is developed in a later step. In the illustrated example, as shown in connection with FIGS. 2D-2F , exposed regions 232 are designed to be removed such that the pattern in patterned mask 230 corresponds to the target pattern to be formed in photoresist layer 209.

[0072] As described above, the photoresist layer 209 can include a chemical agent-generating component configured to generate a solubility-modifying agent in response to appropriate energy (e.g., actinic radiation 228). For example, the chemical agent-generating component in the photoresist layer 209 can be a PAG. In response to exposure to actinic radiation 228, the chemical agent-generating component (e.g., a PAG) in the exposed regions 232 of the photoresist layer 209 can generate a solubility-modifying agent 236 (e.g., an acid) in the exposed regions 232.

[0073] The lithography techniques used in the exposure phase of patterning process 202 may include any of the lithography techniques described above, or any other suitable lithography technique. In certain embodiments, semiconductor workpiece 200 is transferred from the track system described above to an exposure module (which may also be referred to as a stepper module or a scanner module) for exposing photoresist layer 209 to actinic radiation pattern 228. An exemplary lithography system including a projection scanner is described in more detail below with reference to FIG. 7.

[0074] 2C, chemical agent-containing layer 238 may be deposited on semiconductor workpiece 200 (e.g., on photoresist layer 209) using a variety of deposition techniques, including any suitable dry or wet deposition process. For example, chemical agent-containing layer 238 may be deposited by spin coating, spray coating, dip coating, or roll coating. As a specific example, chemical agent-containing layer 238 may be deposited on semiconductor workpiece 200 (e.g., on photoresist layer 209) using a spin-on deposition technique 214 similar to that described above with respect to FIG. 2A, the details of which are incorporated by reference.

[0075] The chemical agent-containing layer 238 may be deposited to facilitate reducing the thickness (e.g., height) of the photoresist layer 209 and the semiconductor structure (e.g., similar to the patterned structure 108) that will ultimately be formed from the photoresist layer 209. The chemical agent-containing layer 238 may also be referred to as a trimming layer, given the role of the chemical agent-containing layer 238 in trimming the thickness / height of the photoresist layer 209 and the semiconductor structure (e.g., similar to the patterned structure 108) that will ultimately be formed from the photoresist layer 209.

[0076] The chemical agent of the chemical agent-containing layer may be the chemical agent itself or a chemical agent-generating component configured to generate the chemical agent in response to an appropriate chemical agent activation trigger (e.g., heat or radiation). The chemical agent may be a substance configured to modify the solubility of the material into which the chemical agent is disposed in response to an appropriate trigger (e.g., heat) and thus may be referred to as a solubility modifier. For example, the solubility modifier may be configured to modify the solubility of the chemical agent-containing layer 238 with a portion of the photoresist layer 209, as described in more detail below with reference to FIG. 2D.

[0077] The chemical agent-containing layer 238 may be a multi-component material that includes a first component and a second component as deposited. The first component may be, for example, a polymer. The second component may be, for example, a solubility modifier such as an acid (e.g., a free acid). As another example, the second component may be a chemical agent-generating component that generates a solubility modifier (e.g., an acid) in response to an appropriate chemical agent activation trigger (e.g., heat or radiation). Exemplary chemical agent-generating components include TAG or PAG.

[0078] 2A-2E , chemical agent-containing layer 238 is deposited after exposing semiconductor workpiece 200 (e.g., including photoresist layer 209) to actinic radiation pattern 228 and before performing a post-exposure bake (PEB), as described below with reference to FIG. 2D . In certain embodiments, chemical agent-containing layer 238 can remain on semiconductor workpiece 200 (e.g., on photoresist layer 209) through the PEB with little or no effect on lithographic performance, other than possibly reducing the thickness of unexposed regions 234 of photoresist layer 209, before removing chemical agent-containing layer 238 during a later phase (e.g., before or during a development phase).

[0079] In certain embodiments, depending on the configuration and capabilities of the equipment involved, and if the semiconductor workpiece 200 has not yet been transferred back to the track system, depositing the chemical agent-containing layer 238 may be performed in the exposure system or by a separate deposition system separate from the exposure system and the track system, or may be performed after transferring the semiconductor workpiece 200 from the exposure system back to the track system so that depositing the chemical agent-containing layer 238 (e.g., using spin-on deposition technique 214) is performed by an appropriate deposition module in the track system.

[0080] Chemical agent-containing layer 238 can have any suitable thickness. In certain embodiments, chemical agent-containing layer 238 has a thickness between 1 nm and 100 nm, such as between 20 nm and 70 nm. It should be understood that these thickness values ​​are provided by way of example only, and that chemical agent-containing layer 238 can have any suitable thickness.

[0081] 2D , PEB 240 may be performed to modify portions of photoresist layer 209 to be soluble in development. For example, PEB 240 may modify portions of photoresist layer 209 to be soluble in one or more developers to remove those portions of photoresist layer 209 from semiconductor workpiece 200. The portions of photoresist layer 209 that PEB 240 modifies to be soluble in development may include exposed regions 232 of photoresist layer 209 and upper portions 242 of unexposed regions 234 of photoresist layer 209 (upper portions 242 are shown in ghost mode using dashed lines). PEB 240 may achieve this solubility modification in several ways.

[0082] 2B , a solubility modifier 236 (e.g., an acid) is activated or otherwise generated in the exposed regions 232 of the photoresist layer 209. The PEB 240 may cause the solubility modifier 236 to react with another substance (e.g., a polymer) in the exposed regions 232, causing the exposed regions 232 to dissolve upon development. For example, the PEB 240 may cause the solubility modifier 236 to convert one or more of the pendant groups of another substance (e.g., a polymer) in the exposed regions 232, causing the exposed regions 232 to dissolve upon development. This process may also be referred to as a deprotection reaction, which renders the exposed regions 232 deprotected (e.g., dissolvable / removable) in a given developer.

[0083] As another example, PEB 240 may cause solubility modifier 244 to diffuse from chemical agent-containing layer 238 to upper portion 242 of unexposed region 234 of photoresist layer 209. Heat associated with PEB 240 may cause solubility modifier 244 to react with another substance (e.g., a polymer) in upper portion 242 of unexposed region 234, causing upper portion 242 of unexposed region 234 to dissolve in development. For example, in a similar type of deprotection reaction, PEB 240 may cause solubility modifier 244 to convert one or more of the pendant groups of another substance (e.g., a polymer) in upper portion 242 of unexposed region 234, causing upper portion 242 of unexposed region 234 to dissolve in a given developer.

[0084] In certain embodiments, the chemical agent-containing layer 238, as deposited, includes a solubility modifier 244. For example, in implementations in which the solubility modifier 244 is an acid, the solubility modifier 244 can be a free acid included in the chemical agent-containing layer 238 as deposited.

[0085] In certain embodiments, chemical agent-containing layer 238 includes a chemical agent-generating component that, in response to an appropriate chemical agent activation trigger (e.g., heat or radiation), generates solubility modifier 244. For example, in implementations in which solubility modifier 244 is an acid, the chemical agent-generating component can include a TAG or PAG, which can be included in chemical agent-containing layer 238 as deposited.

[0086] In the case of TAG, the TAG may generate a solubility modifier 244 (e.g., an acid) in response to heat. For example, heat associated with PEB 240 may cause TAG to generate a solubility modifier 244 within chemical agent-containing layer 238. Thus, in certain embodiments, heat associated with PEB 240 causes a chemical agent-generating component (e.g., TAG) of chemical agent-containing layer 238 to generate a solubility modifier 244 within chemical agent-containing layer 238, and causes the generated solubility modifier 244 to diffuse to appropriate portions of photoresist layer 209 (e.g., upper portions 242 of unexposed regions 234 of photoresist layer 209) to modify its solubility. Of course, the present disclosure contemplates heat to generate solubility modifier 244 in TAG (or other appropriate chemical agent-generating component) in a step separate from PEB 240, where appropriate.

[0087] In the case of a PAG, the PAG may generate a solubility modifier 244 (e.g., an acid) in response to radiation. For example, chemical agent-containing layer 238 may be exposed to radiation to cause the PAG to generate the solubility modifier 244 within chemical agent-containing layer 238. In certain embodiments, a separate irradiation step is introduced into the track-based process to irradiate chemical agent-containing layer 238 and cause the PAG to generate the solubility modifier 244 within chemical agent-containing layer 238. Semiconductor workpiece 200 is then moved to a module for performing PEB 240, which may diffuse the generated solubility modifier 244 into an appropriate portion of photoresist layer 209 (e.g., upper portion 242 of unexposed region 234 of photoresist layer 209) to modify its solubility.

[0088] Of course, the present disclosure contemplates including, where appropriate, other suitable types of chemical agent-generating components that generate solubility-modifying agent 244 in response to a suitable activation trigger (e.g., heat, radiation, or another suitable trigger).

[0089] In certain embodiments, diffusion of solubility modifier 244 from chemical agent-containing layer 238 into upper portion 242 of photoresist layer 209 moves primarily in a downward direction (as indicated by the downward arrow into upper portion 242 in FIG. 2D ) due to a concentration gradient of solubility modifier 244 between chemical agent-containing layer 238 and unexposed region 234 of photoresist layer 209. In other words, at PEB 238, solubility modifier 244 in chemical agent-containing layer 240 advances toward areas of lower concentration of solubility modifier 244, including particularly upper portion 242 of unexposed region 234. Additionally, the exposed regions 232 of the photoresist layer 209 adjacent to the unexposed regions 234 already contain a solubility modifier 236 that may be similar or the same as the solubility modifier 244, meaning that the exposed regions 232 of the photoresist layer 209 may act as areas of higher concentration of the photoresist layer 209, which may further promote the diffusion of the solubility modifier 244 towards the lower concentration upper portions 242 of the unexposed regions 234, further resulting in a primarily vertical component of diffusion of the solubility modifier 244 into the upper portions 242.

[0090] In certain embodiments, one or more characteristics of chemical agent-containing layer 238 can be selected to achieve a desired level of diffusion of solubility modifier 244 (e.g., acid) into certain portions of photoresist layer 209 (e.g., unexposed regions 234 of photoresist layer 209) such that those portions of photoresist layer 209 dissolve during subsequent development. The desired level of diffusion can be, for example, a target depth of diffusion into unexposed regions 234 of photoresist layer 209 that ultimately results in a thinning or height reduction of unexposed regions 234 of photoresist layer 209 by the target depth amount. The one or more characteristics of chemical agent-containing layer 238 can include the material of chemical agent-containing layer 238 (e.g., including a polymer and a chemical agent or chemical agent-generating component), the concentration of solubility modifier 244 (e.g., acid) in chemical agent-containing layer 238, the thickness of chemical agent-containing layer 238, and / or other suitable parameters.

[0091] Additionally, while the temperature and / or bake time associated with PEB 240 may be adjusted to affect the depth of diffusion and associated solubility modification of solubility modifier 244 into unexposed regions 234, adjusting the temperature and / or bake time associated with PEB 240 may undesirably alter other aspects of the patterning of photoresist layer 209, such as the lateral critical dimension of unexposed regions 234. Thus, in certain embodiments, it may be desirable for the temperature and / or bake time associated with PEB 240 to remain optimized for patterning photoresist layer 209 (e.g., the lateral critical dimension of unexposed regions 234). Nonetheless, the present disclosure contemplates adjusting the temperature and / or bake time associated with PEB 240, where appropriate, to achieve the desired diffusion depth and solubility modification.

[0092] One or more of the acid composition (e.g., molecular weight and stericity), polymer composition (e.g., polarity) and film density, bake temperature (e.g., bake temperature for PEB240), bake time (e.g., bake time for PEB240), and the possible presence of a quencher in the reacted film can affect the diffusion depth and associated solubility modification of the solubility modifier 244. Acids of the composition, ranging from relatively high to relatively low diffusion rates, include triflic acid, nonafluorolic acid, and p-toluenesulfonic acid. These considerations may also apply to other diffusion depth determinations in other figures of this disclosure.

[0093] A lower portion 248 of the unexposed region 234 of the photoresist layer 209 may remain insoluble in development during the development phase of the patterning process 202. The lower portion 248 may also be referred to as the remaining portion of the photoresist layer 209 (e.g., remaining after development in a subsequent stage). The lower portion 248 may have a reduced thickness relative to the thickness of the photoresist layer 209 at an earlier stage of the process 202. For example, the height (H2) of the lower portion 248 may be less than the height (H1) of the photoresist layer 209 deposited at the stage shown in FIG. 2A .

[0094] The difference between H1 and H2 can be the depth (D) to which the solubility modifier 244 penetrates into the unexposed regions 234 of the photoresist layer 209 to cause solubility modification in those unexposed regions 234 (e.g., upper portion 242). The depth of diffusion of the solubility modifier 244 into the unexposed regions 234 can be intentionally designed and controlled to achieve a desired thickness reduction / height (H2). Thus, the use of the chemical agent-containing layer 238 can enable a high degree of control over the height reduction of the unexposed regions 234 of the photoresist layer 209, and ultimately, can enable a patterned structure (e.g., similar to patterned structure 208) formed from the photoresist layer 209. In certain embodiments, a process designer may seek to achieve a desired level of diffusion and associated solubility modification, and thereby the associated height reduction of the unexposed regions 234, such that sufficient mask volume for pattern transfer is present in the patterned structure being formed. In certain embodiments, the height reduction achieves an aspect ratio (structure height to recess width) of 5:1 or less, such as 2:1. However, it should be understood that the present disclosure contemplates reducing the height of patterned structure 208 by any suitable amount.

[0095] It should be understood that heights H1, H2, etc. in Figures 1A-1G, 2A-2E, 3A-3G, and / or other figures may or may not be the same. By way of example only, H2 in Figure 1C may or may not be the same as H2 in Figure 2D.

[0096] In certain embodiments, PEB 240 may be performed by heating semiconductor workpiece 200 in a process chamber under vacuum or gas flow at a temperature between 50°C and 250°C, for example, between 60°C and 140°C. In certain examples, semiconductor workpiece 200 is baked for 1 to 3 minutes. PEB bake conditions may be selected to promote a degree of crosslinking in the exposed resist to improve contrast and reduce line edge roughness (LER). The present disclosure contemplates performing PEB 240 in any suitable manner.

[0097] In certain embodiments, if the semiconductor workpiece 200 has not yet been transferred back to the track system as part of depositing the chemical agent-containing layer 238 (e.g., using spin-on deposition technique 214), the semiconductor workpiece 200 may be transferred back to the track system from the exposure system so that PEB 240 is performed by an appropriate module of the track system.

[0098] 2E, in a development phase, photoresist layer 209 may be developed using a suitable development process that removes the soluble portions of photoresist layer 209. In the development phase, and according to the illustrated example of a positive photolithography process, the soluble portions of photoresist layer 209 may be removed using a suitable dry or wet etching process, thereby masking photoresist layer 209 according to a pattern mask 230 that may then be used to perform further manufacturing processes, such as those that may be associated with patterning process 102 of FIGS.

[0099] The soluble portions of the photoresist layer 209 that are removed in the development phase may include the exposed regions 232 of the photoresist layer 209 and upper portions 242 of the unexposed regions 234 of the photoresist layer 209. After removal of the soluble portions of the photoresist layer 209, lower portions 248 of the unexposed regions 234 of the photoresist layer 209 remain, forming the semiconductor structure 208. Additionally, removal of the soluble portions of the photoresist layer 209, particularly the exposed regions 232, forms recesses 210 in the photoresist layer 209. The recesses 210 in the photoresist layer 209 may be used in an etching process (e.g., the patterning process 102 of FIGS. 1A-1G) to etch features in the intermediate layer 206. The recesses 210 may have a lateral width (W). The recesses 210 may have the same or different widths in any suitable combination.

[0100] The semiconductor structure 208 has a reduced height H2 relative to the initial height H1 of the photoresist layer 209. The height reduction (H1-H2) may correspond to the depth D of the upper portion 242 that is removed as part of the development process. This height reduction, which may also be referred to as a thickness reduction, may reduce the aspect ratio (height of the semiconductor structure 208:width of the adjacent recess 210) in the semiconductor workpiece 200. This reduction in aspect ratio may persist (although not necessarily by the same amount) as the pattern formed by the semiconductor structure 208 is used as part of a patterning process to pattern an underlying layer. For example, if the semiconductor workpiece 200 in the state shown in FIG. 2E is used as the semiconductor workpiece 100 at the stage shown in FIG. 1A in connection with the anti-spacer patterning process 102 shown in FIGS. 1A-1F (and the subsequent pattern transfer shown in FIG. 1G), the reduction in aspect ratio associated with the pattern defined by the semiconductor structure 208 may result in a reduction in the aspect ratio at a later stage of the process 102 (e.g., at the stage shown in FIG. 1F).

[0101] In certain embodiments, the soluble portions of the photoresist layer 209 may be removed in a wet process by treating the semiconductor workpiece 200 with a developer to dissolve the soluble portions of the photoresist layer 209. A suitable developer for removing the soluble portions of the photoresist layer 209 depends in part on the material of the photoresist layer 209. In certain embodiments, the developer may include an aqueous alkaline solution including a water-soluble organic base. As a particular example, the developer may include tetramethylammonium hydroxide (TMAH).

[0102] Alternatively, in other embodiments, a dry process may be used. The dry process may include, for example, a selective plasma etching process or a thermal process, which may eliminate the use of a developer solution. In certain embodiments, the dry process may be performed using RIE or atomic layer etching (ALE).

[0103] 2E, the developing phase also includes removing the chemical agent-containing layer 238 (and topcoat 226, if applicable) from the photoresist layer 209. In certain embodiments, the process / chemicals used to develop the photoresist layer 209 (e.g., to remove soluble portions of the photoresist layer 209) may also be capable of removing material from the chemical agent-containing layer 238 (and topcoat 226, if applicable). In another example, the chemical agent-containing layer 238 (and topcoat 226, if applicable) may be removed from the semiconductor workpiece 200 prior to developing the photoresist layer 209 using a removal process that selectively removes the chemical agent-containing layer 238 (and topcoat 226, if applicable). The present disclosure contemplates performing the developing phase using any suitable process / chemicals.

[0104] For example, development of the photoresist layer 209 (e.g., to remove soluble portions of the photoresist layer 209 and potentially the chemical agent-containing layer 238, as well as the topcoat 226, if appropriate) may be carried out using an organic solvent. Exemplary possible organic solvents include propylene glycol methyl ether acetate (PGMEA), 2-heptanone, isopropyl alcohol (IPA), 2-pentanone, or another suitable organic solvent. In one example, the solvent dispense volume may be 5 ml to 500 ml, e.g., 10 ml to 100 ml. The substrate (e.g., workpiece 200) may be secured to a rotating chuck that supports the substrate. The rotation speed during liquid dispense may be 50 rpm to 3000 rpm, e.g., 1000 rpm to 2000 rpm. While organic solvents are primarily described, the present disclosure contemplates the use of any suitable solvent.

[0105] As another example, development of photoresist layer 209 (e.g., to remove photoresist layer 209 and potentially soluble portions of chemical agent-containing layer 238, and, if appropriate, topcoat 226) can be carried out in the gas phase with or without a plasma using an organic solvent. Exemplary gases for such a gas phase include hydrobromic acid (HBr), boron trichloride (BCl3), or another suitable gas / gas combination.

[0106] 3A-3G illustrate cross-sectional views of an exemplary semiconductor workpiece 300 during an exemplary patterning process 302, according to certain embodiments. In the example illustrated in FIGS. 3A-3G, a chemical-containing layer is used to modify portions of a photoresist layer to dissolve in development before exposing the semiconductor workpiece 300 (e.g., including a photoresist layer) to an actinic radiation pattern to pattern the photoresist layer.

[0107] 3A , a semiconductor workpiece 300 may be formed that includes an intermediate layer 306 formed on a substrate 304 and a photoresist layer 309 formed on the intermediate layer 306. For example, the intermediate layer 306 may be disposed on the substrate 304, and the photoresist layer 309 may be disposed on the intermediate layer 306. In certain embodiments, a topcoat 326 is formed on the photoresist layer 309.

[0108] 3B, chemical agent-containing layer 338 may be deposited on semiconductor workpiece 300 (e.g., on photoresist layer 309) using a suitable deposition technique, including any suitable dry or wet deposition process. For example, chemical agent-containing layer 338 may be deposited by spin coating, spray coating, dip coating, or roll coating. As a particular example, chemical agent-containing layer 338 may be deposited on semiconductor workpiece 300 (e.g., on photoresist layer 309) using spin-on deposition technique 314. Spin-on deposition technique 314 may be similar to spin-on deposition technique 214, the description of which is incorporated by reference.

[0109] The chemical agent-containing layer 338, the manner in which the chemical agent-containing layer 338 is deposited, and other related considerations may be similar to those described above in connection with the chemical agent-containing layer 238 described above in connection with FIG. 2C, which description is incorporated by reference.

[0110] In certain embodiments, depending on the configuration and capabilities of the equipment involved, deposition of chemical agent-containing layer 338 may be performed in a deposition module (e.g., a spin-on deposition module) of the same track system used to deposit photoresist layer 309, or in a deposition module of a track system separate from that used to deposit photoresist layer 309. Alternatively, semiconductor workpiece 300 may be transferred from the track system to a separate deposition system for deposition of chemical agent-containing layer 338.

[0111] 3C, a pre-exposure bake 350 may be performed to diffuse the solubility modifier 344 into portions of the photoresist layer 309. The portions of the photoresist layer 309 into which the solubility modifier 344 diffuses may be at least a portion of the portions of the photoresist layer 309 that are removed in a subsequent development step, and may particularly include portions of the photoresist layer 309 that reduce the height of patterned structures formed from the photoresist layer 309.

[0112] For example, the pre-exposure bake 350 may cause the solubility modifier 344 to diffuse from the chemical agent-containing layer 338 into a first portion 352 of the photoresist layer 309 such that the photoresist layer 309 includes a first portion 352 into which the solubility modifier 344 has diffused and a second portion 354 beyond the diffusion area of ​​the photoresist layer 309. The first portion 352 may be disposed between the chemical agent-containing layer 338 and the second portion 354. For example, the first portion 352 may be an upper portion of the photoresist layer 309, and the second portion 354 may be a lower portion of the photoresist layer 309.

[0113] In certain embodiments, the chemical agent-containing layer 338, as deposited, includes a solubility modifier 344. For example, in implementations in which the solubility modifier 344 is an acid, the solubility modifier 344 can be a free acid included in the chemical agent-containing layer 338 as deposited.

[0114] In certain embodiments, the chemical agent-containing layer 338 includes a chemical agent-generating component that, in response to an appropriate activation trigger (e.g., heat or radiation), generates the solubility modifier 344. For example, in implementations in which the solubility modifier 344 is an acid, the chemical agent-generating component can include a TAG or PAG, which can be included in the chemical agent-containing layer 338 as deposited.

[0115] In the case of TAG, the TAG may generate a solubility modifier 344 (e.g., an acid) in response to heat. For example, heat associated with pre-exposure bake 350 may cause the TAG to generate the solubility modifier 344 within chemical agent-containing layer 338. Thus, in certain embodiments, heat associated with pre-exposure bake 350 causes the chemical agent-generating component (e.g., TAG) of chemical agent-containing layer 338 to generate the solubility modifier 344 within chemical agent-containing layer 338 and diffuses the generated solubility modifier 344 to the appropriate portion (e.g., first portion 352) of photoresist layer 309. Of course, the present disclosure contemplates heat to generate the solubility modifier 344 in TAG or other suitable chemical agent-generating component in a step separate from pre-exposure bake 350, where appropriate.

[0116] In the case of a PAG, the PAG may generate a solubility modifier 344 (e.g., an acid) in response to radiation. For example, chemical agent-containing layer 338 may be exposed to radiation to cause the PAG to generate solubility modifier 344 within chemical agent-containing layer 338. Thus, in certain embodiments, a separate irradiation step is introduced into the track-based process to irradiate chemical agent-containing layer 338 and cause the PAG to generate solubility modifier 344 within chemical agent-containing layer 338. Thereafter, semiconductor workpiece 300 may be moved to a module for performing a pre-exposure bake 350, which diffuses the generated solubility modifier 344 into the appropriate portion (e.g., first portion 352) of photoresist layer 309.

[0117] Of course, the present disclosure contemplates including, where appropriate, other suitable types of chemical agent-generating components that generate the solubility-modifying agent 344 in response to a suitable activation trigger (e.g., heat, radiation, or another suitable trigger).

[0118] In certain embodiments, diffusion of the solubility modifier 344 from the chemical agent-containing layer 338 into the first portion 352 of the photoresist layer 309 moves primarily in a downward direction (as shown by the downward arrow into the first portion 352 in FIG. 3C ) due to a concentration gradient of the solubility modifier 344 between the chemical agent-containing layer 338 and the first portion 352 of the photoresist layer 309. In other words, during the pre-exposure bake 350, the solubility modifier 344 in the chemical agent-containing layer 338 moves toward areas of a lower concentration of the solubility modifier 344, such as the first portion 352 of the photoresist layer 309.

[0119] In certain embodiments, one or more characteristics of the chemical agent-containing layer 338 can be selected to achieve a desired level of diffusion of the solubility modifier 344 (e.g., acid) into a particular portion (e.g., first portion 352) of the photoresist layer 309 such that a desired amount of the photoresist layer 309 dissolves during subsequent development when the solubility modifier 344 is exposed to an appropriate trigger (e.g., an appropriate amount of heat). The desired level of diffusion can be, for example, a target depth of diffusion into the photoresist layer 309 that ultimately thins or reduces the height of the photoresist layer 309 by the target depth amount. The one or more characteristics of the chemical agent-containing layer 338 can include the material of the chemical agent-containing layer 338 (e.g., including a polymer and a chemical agent or chemical agent-generating component), the concentration of the solubility modifier 344 (e.g., acid) in the chemical agent-containing layer 338, the thickness of the chemical agent-containing layer 338, and / or other suitable parameters. Additionally, if the temperature and / or bake time associated with the pre-exposure bake 350 is adjusted to affect the depth of diffusion of the solubility modifier 344 into the photoresist layer 309, it may be appropriate to consider how the temperature and time may affect the second portion 354 of the photoresist layer 309 to avoid or minimize modifications to the first portion 352 that may adversely affect the performance of subsequent exposure and development to pattern the second portion 354.

[0120] In certain embodiments, at this stage, the solubility modifier 344 has diffused into the first portion 352 of the photoresist layer 309, but both the first portion 352 and the second portion 354 of the photoresist layer 309 may remain insoluble in development because the solubility modifier 344 has not yet reacted with the first portion 352 to cause it to dissolve in development, assuming an appropriate temperature is used for the pre-exposure bake 350. In certain embodiments, deferring modifying the first portion 352 to be soluble in developer until after exposure (as described below with respect to FIGS. 3E-3F ) may help promote the same or similar volume of the photoresist layer 309 interacting with the impinging radiation (actinic radiation 328, described below with respect to FIG. 3E ), which may promote the desired imaging performance as designed and tailored by the manufacturer of the photoresist layer 309 material. Of course, other approaches are contemplated by the present disclosure.

[0121] Second portion 354 may have a reduced thickness relative to the thickness of photoresist layer 309 at an earlier stage of process 302. For example, second portion 354 may have a height (H2) that is less than the height (H1) of photoresist layer 309 as deposited at the stage shown in FIG. 3A . The difference between H1 and H2 may be the depth (D) to which solubility modifier 344 penetrates into photoresist layer 309 to cause solubility modification in first portion 352 of photoresist layer 309. The depth of diffusion of solubility modifier 344 into first portion 352 may be intentionally designed and controlled to achieve a desired thickness reduction / height (H2). Thus, the use of chemical agent-containing layer 338 may enable a high degree of control over the height reduction of photoresist layer 309, ultimately enabling a patterned structure (e.g., similar to patterned structure 108) formed from photoresist layer 309.

[0122] In certain embodiments, a process designer may seek to achieve a desired level of diffusion and associated solubility modification, and thereby an associated height reduction of the photoresist layer 309, such that sufficient mask volume for pattern transfer is present within the patterned structure being formed. In certain embodiments, the height reduction achieves an aspect ratio (structure height to recess width) of 5:1 or less, such as 2:1. However, it should be understood that the present disclosure contemplates reducing the height of the photoresist layer 309 by any suitable amount.

[0123] In certain embodiments, the temperature for pre-exposure bake 350 is selected to be high enough to promote diffusion of solubility modifier 344 to a desired depth within photoresist layer 309, such that first portion 352 has the desired depth and second portion 354 has the desired height / thickness, but not so high that solubility modifier 344 deprotects first portion 352 (and thereby modifying first portion 352 to be soluble in development). In applicable embodiments (e.g., when the chemical agent-generating component of chemical agent-containing layer 338 is TAG), the temperature for pre-exposure bake 350 may also be high enough to generate solubility modifier 344 in the chemical agent-generating component of chemical agent-containing layer 338.

[0124] In certain embodiments, pre-exposure bake 350 may be performed by heating semiconductor workpiece 300 in a process chamber under vacuum or gas flow at a temperature between 50°C and 250°C, for example, in certain embodiments, at a temperature between 60°C and 100°C. In certain examples, semiconductor workpiece 300 is baked for 1 to 3 minutes. In certain embodiments, the temperature for pre-exposure bake 350 may be lower than the temperature that triggers modification of the solubility of first portion 352 by solubility modifier 344. For example, the temperature for pre-exposure bake 350 may be about 20°C lower than the temperature that triggers modification of the solubility of first portion 352 by solubility modifier 344. In certain examples, if a moderately diffusible solubility modifier 344 (e.g., a moderately diffusible acid) is used and deprotection of first portion 352 occurs at a temperature of 80°C or higher, a temperature of 60°C may be used for pre-exposure bake 350. The present disclosure contemplates performing the pre-exposure bake 350 in any suitable manner.

[0125] 3D , chemical agent-containing layer 338 may be removed from semiconductor workpiece 300. For example, a solvent rinse 356 may be performed to remove chemical agent-containing layer 338, with the solvent being selective to removing chemical agent-containing layer 338. The present disclosure contemplates removing chemical agent-containing layer 338 from semiconductor workpiece 300 in any suitable manner. In certain embodiments, removing chemical agent-containing layer 338 before a subsequent exposure step to pattern photoresist layer 309 (and particularly to expose second portion 354 of photoresist layer 309) can reduce or eliminate any effect chemical agent-containing layer 338 may have on patterning performance.

[0126] In certain embodiments, a solvent wash 356 may be performed using a solvent such as 4-methyl-2-pentanol or diisoamyl ether to selectively remove the chemical agent-containing layer 338. Although this disclosure describes a particular solvent for the solvent wash 356, this disclosure contemplates the use of any suitable solvent for the solvent wash 356.

[0127] 3E, during an exposure phase, second portion 354 of photoresist layer 309 is exposed (irradiated) through first portion 352 with actinic radiation pattern 328 to form a pattern in second portion 354. For example, actinic radiation 328 may be directed toward the surface of semiconductor workpiece 300, and particularly photoresist layer 309, through a patterned mask 330 to form a target pattern in second portion 354. The target pattern may include exposed regions 332 and unexposed regions 334 in second portion 354, the characteristics of which may depend, as discussed above, on whether a positive or negative photoresist layer 309 is used.

[0128] 3A-3G , the first portion 352, into which the solubility modifier 344 has been diffused, is present on the second portion 354 prior to exposing the semiconductor workpiece 300 (e.g., including the second portion 354) to the actinic radiation pattern 328, in order to pattern the second portion 354 so that the first portion 352 is present on the second portion 354 during the exposure. In such a scenario, it may be appropriate for the material of the first portion 352 to be relatively transparent to the actinic radiation 328 associated with the lithography technique used to pattern the second portion 354, such that the second portion 354 can be patterned as desired. In certain embodiments, the first portion 352 that is relatively transparent to actinic radiation 328 comprises a first portion 352 that is sufficiently transparent to actinic radiation 328 such that an appropriate area of ​​the second portion 354 (e.g., exposed area 332) can be exposed to actinic radiation 328 through the first portion 352 (e.g., according to a pattern defined by pattern mask 330).

[0129] In certain embodiments, depending on the transparency of first portion 352 to actinic radiation 328, and possibly on the transparency of first portion 352 to actinic radiation 328, it may be appropriate to increase the dose by an appropriate amount during exposure (e.g., compared to instances where exposure is prior to depositing chemical agent-containing layer 338 and / or converting portions of photoresist layer 309 to dissolve upon development) to facilitate exposure of appropriate areas of second portion 354 (e.g., exposed areas 332) to actinic radiation 328 through first portion 352, while attempting to minimize any adverse effects on the intended patterning of second portion 354.

[0130] Photoresist layer 309 can include a chemical agent-generating component configured to generate a solubility-modifying agent in response to appropriate energy (e.g., actinic radiation 328). For example, the chemical agent-generating component in photoresist layer 309 can be a PAG. In response to exposure to actinic radiation 328, the chemical agent-generating component (e.g., PAG) in exposed regions 332 can generate a solubility-modifying agent 336 (e.g., an acid) in exposed regions 332.

[0131] 3F, PEB 340 may be performed to modify portions of photoresist layer 309 to be soluble in development. In particular, PEB 340 may modify exposed regions 332 of first portion 352 and second portion 354 of photoresist layer 309 to be soluble in development, while leaving unexposed regions 334 of second portion 354 of photoresist layer 309 insoluble in development. For example, PEB 340 may modify exposed regions 332 of first portion 352 and second portion 354 of photoresist layer 309 to be soluble in one or more developers to remove those portions of photoresist layer 309 from semiconductor workpiece 300, while leaving second portion 354 of photoresist layer 309 insoluble in development.

[0132] 2D , which description is incorporated by reference. The temperature and other conditions for PEB 340 can be adjusted such that PEB 340 modifies exposed regions 332 of first portion 352 and second portion 354 of photoresist layer 309 to be soluble upon development, while leaving unexposed regions 334 of second portion 354 of photoresist layer 309 insoluble upon development.

[0133] At this stage, the second portion 354 of the photoresist layer 309 may remain insoluble upon development. The second portion 354 may have a reduced thickness relative to the thickness of the photoresist layer 309 at an earlier stage of the process 302. For example, the height (H2) of the second portion 354 may be less than the height (H1) of the photoresist layer 309 deposited at the stage shown in FIG. 3A . The difference between H1 and H2 may be the depth (D) to which the solubility modifier 344 penetrates into the photoresist layer 309 to cause solubility modification in the first portion 352 of the photoresist layer 309. The depth of diffusion of the solubility modifier 344 into the first portion 352 may be intentionally designed and controlled to achieve a desired thickness reduction / height (H2). Thus, the use of the chemical agent-containing layer 338 may enable a high degree of control over the height reduction of the photoresist layer 309, and ultimately, may enable a patterned structure (e.g., similar to the patterned structure 108) formed from the photoresist layer 309.

[0134] 3G, in a development phase, photoresist layer 309 may be developed using a suitable development process that removes the soluble portions of photoresist layer 309. In the development phase, and according to the illustrated example of a positive photolithography process, the soluble portions of photoresist layer 309 may be removed using a suitable dry or wet etching process, thereby masking photoresist layer 309 according to a pattern mask 330 that may then be used to perform further manufacturing processes, such as those that may be associated with patterning process 102 of FIGS.

[0135] The soluble portions of the photoresist layer 309 that are removed during the development phase may include the first portion 352 of the photoresist layer 309 and the exposed areas 332 of the second portion 354 of the photoresist layer 309. After removal of the soluble portions of the photoresist layer 309, the unexposed areas 334 of the second portion 354 of the photoresist layer 309 remain, forming the patterned structure 308. Additionally, removal of the soluble portions of the photoresist layer 309 forms recesses 310 in the photoresist layer 309. The recesses 310 in the photoresist layer 309 may be used in an etching process (e.g., the patterning process 102 of FIGS. 1A-1F) to etch features in the intermediate layer 306. The recesses 310 may have a lateral width (W). The recesses 310 may have the same or different widths in any suitable combination.

[0136] Patterned structure 308 has a reduced height H2 relative to an initial height H1 of photoresist layer 309. The height reduction (H1-H2) may correspond to a depth D of first portion 352 of photoresist layer 309 that is removed as part of a development process. This height reduction, which may also be referred to as a thickness reduction, may reduce the aspect ratio (height of patterned structure 308 to width of adjacent recess 310) in semiconductor workpiece 300. This reduction in aspect ratio may persist (although not necessarily by the same amount) because the pattern formed by patterned structure 308 is used as part of the patterning process to pattern underlying layers. For example, in connection with the anti-spacer patterning process 102 shown in Figures 1A-1F (and subsequent pattern transfer shown in Figure 1G), if the semiconductor workpiece 300 in the state shown in Figure 3G is used as the semiconductor workpiece 100 at the stage shown in Figure 1A, the reduction in aspect ratio associated with the pattern defined by the patterning structure 308 may result in a reduction in aspect ratio at a later stage of the process 102 (e.g., at the stage shown in Figure 1F).

[0137] The development phase of FIG. 3G may be similar to the development phase of FIG. 2E, the details of which are incorporated by reference.

[0138] 3C , in addition to diffusing the solubility-modifying agent 344 into portions of the photoresist layer 309 (e.g., first portions 352), the pre-exposure bake 350 may also modify those portions of the photoresist layer 309 (e.g., first portions 352) to be soluble in development. In particular, the pre-exposure bake 350 may modify those portions of the photoresist layer 309 to be soluble in one or more developers to remove those portions of the photoresist layer 309 from the semiconductor workpiece 300. For example, the pre-exposure bake 350 may modify the first portions 352 of the photoresist layer 309 to be soluble in development, while leaving the second portions 354 of the photoresist layer 309 insoluble in development.

[0139] For example, the pre-exposure bake 350 may cause the solubility modifier 344 to diffuse from the chemical agent-containing layer 338 into the first portion 352 of the photoresist layer 309. The heat associated with the pre-exposure bake 350 may cause the solubility modifier 344 to react with another substance (e.g., a polymer) in the first portion 352, causing the first portion 352 to dissolve upon development. For example, in a deprotection reaction of a type similar to that described above, the pre-exposure bake 350 may cause the solubility modifier 344 to convert one or more of the pendant groups of another substance (e.g., a polymer) in the first portion 352 of the photoresist layer 309, causing the first portion 352 to dissolve upon development in a predetermined developer.

[0140] In certain embodiments, the pre-exposure bake 350 may be performed at a temperature higher than the temperature described above for the pre-exposure bake 350 to achieve both diffusion of the solubility-modifying agent 344 from the chemical agent-containing layer 338 into the first portions 352 of the photoresist layer 309 and modifying those portions of the photoresist layer 309 (e.g., first portions 352) to dissolve upon development. In certain embodiments, the temperature of the pre-exposure bake 350 may be about 20°C higher than the above-described temperature for the pre-exposure bake 350. For example, in this variation, the pre-exposure bake 350 may be performed by heating the semiconductor workpiece 300 in a process chamber under vacuum or gas flow at a temperature between 50°C and 250°C, e.g., between 80°C and 160°C in certain embodiments. In certain examples, the semiconductor workpiece 300 is baked for 1 to 3 minutes. The pre-exposure bake conditions may be selected to promote a degree of crosslinking in the exposed resist to improve contrast and reduce LER. The present disclosure contemplates performing the pre-exposure bake 350 in any suitable manner.

[0141] In certain embodiments, the chemical agent-containing layer 338 includes a chemical agent-generating component that generates the solubility modifier 344 in response to an appropriate activation trigger (e.g., heat or radiation). For example, in implementations in which the solubility modifier 344 is an acid, the chemical agent-generating component may include a TAG or a PAG, which may be included in the chemical agent-containing layer 338 as deposited. In the case of a TAG, a pre-exposure bake 350 or a separate heating step may be performed to generate the solubility modifier 344. In the case of a PAG, a separate irradiation step may be performed before the pre-exposure bake 350 to generate the solubility modifier 344.

[0142] In certain embodiments, solubility modification of first portion 352 of photoresist layer 309 can occur when the pendant groups of the polymer (of photoresist layer 309) are solubility modified. In some cases, the total volume of modified groups, sufficient to modify the solubility of first portion 352 for subsequent removal, can be less than 50% (and potentially much less) of that available in first portion 352. After exposure (e.g., after FIG. 3E ), the PAG present in first portion 352 of photoresist layer 309 can decompose and react with the remaining protected pendant groups. In some scenarios, the deprotection reaction associated with solubility-modifying agent 344 within first portion 352 can consume most of the deprotected pendant groups, and any acid resulting from exposure of the PAG in first portion 352 (e.g., FIG. 3E ) can diffuse farther during the bake time (e.g., the bake time of PEB 340), but remains reactive. Even in this example where first portion 352 of photoresist layer 309 is deprotected (modified to dissolve) prior to exposure (FIG. 3E), then the transparency of first portion 352 to impinging photons associated with actinic radiation 328 can be maintained because these groups can constitute a small percentage of the total volume of first portion 352.

[0143] Figure 4 illustrates an exemplary method 400 for patterning a semiconductor workpiece, according to certain embodiments. Method 400 may be similar to some or all of patterning process 202, and for purposes of describing exemplary method 400, reference will be made primarily to the reference numerals used in connection with Figures 2A-2E. Additionally, at least aspects of Figures 2A-2E not described in connection with Figure 4 are incorporated by reference. However, method 400 may implement any suitable patterning process.

[0144] In step 402, a photoresist layer 209 may be deposited on a semiconductor wafer (semiconductor workpiece 200) to be photolithographically patterned. The photoresist layer 209 has a first height (H1). In step 404, the photoresist layer 209 is exposed to an actinic radiation pattern 228 to form exposed regions 232 and unexposed regions 234 of the photoresist layer 209. In certain embodiments, the lithography technique for exposing the photoresist layer 209 to the actinic radiation pattern 228 includes one or more of an immersion lithography technique or i-line lithography. The present disclosure contemplates using any suitable type of lithography technique.

[0145] In step 406, a chemical agent-containing layer 238 is deposited on the photoresist layer 209. In certain embodiments, depositing the chemical agent-containing layer 238 on the photoresist layer 209 includes depositing the chemical agent-containing material by spin-coating the chemical agent-containing material on the photoresist layer 209 (e.g., using a spin-on deposition technique 214). The semiconductor wafer (semiconductor workpiece 200) may include a topcoat 226 formed on the photoresist layer 209 before depositing the chemical agent-containing layer 238, the topcoat 226 being between the photoresist layer 209 and the chemical agent-containing layer 238. The topcoat 226 may be configured to function as a diffusion barrier.

[0146] In step 408, a PEB 240 of the semiconductor wafer (semiconductor workpiece 200) is performed. The PEB 240 may modify portions of the photoresist layer 209 to form soluble portions of the photoresist layer 209 upon development. The soluble portions of the photoresist layer 209 may include the exposed regions 232 and upper portions 242 of the unexposed regions 234.

[0147] In certain embodiments, the PEB 240 diffuses the solubility modifier 244 from the chemical agent-containing layer 238 into the upper portion 242 of the unexposed region 234 to modify portions of the photoresist layer 209 and form soluble portions of the photoresist layer 209 upon development. The solubility modifier 244 causes the upper portion 242 of the unexposed region 234 to dissolve upon development. The PEB 240 may diffuse the solubility modifier 244 from the chemical agent-containing layer 238 into the upper portion 242 of the unexposed region 234 to a target depth (D). The target depth (D) may correspond to the difference between a first height (H1) of the photoresist layer 209 and a second height (H2) of the lower portion 248 of the photoresist layer 209. In certain embodiments, one or more of the type of solubility modifier 244, the concentration of the solubility modifier 244, and the thickness of the chemical agent-containing layer 238 may be selected such that the PEB 240 diffuses the solubility modifier 244 from the chemical agent-containing layer 238 to the upper portion 242 of the unexposed region 234 of the photoresist layer 209 a target depth.

[0148] Additionally, in certain embodiments, PEB 240 causes solubility modifier 236 activated by actinic radiation 228 in exposed regions 232 to dissolve exposed regions 232 upon development, to modify portions of photoresist layer 209 to form soluble portions of photoresist layer 209 upon development. In certain embodiments, prior to PEB 240, exposed regions 232 include solubility modifier 236, which is generated in response to actinic radiation 228. In certain embodiments, solubility modifier 236 and solubility modifier 244 include an acid, and photoresist layer 209 includes an acid-reactive material.

[0149] In certain embodiments, the chemical agent-containing layer 238, upon deposition, includes a polymer and a solubility modifier 244 (e.g., a free acid) or a chemical agent-generating component (e.g., a TAG or a PAG) for generating the solubility modifier 244 (e.g., an acid).

[0150] In step 410, the photoresist layer 209 may be developed to selectively remove soluble portions of the photoresist layer 209. The remaining portions (e.g., lower portions 248) of the unexposed areas 234 of the photoresist layer 209 form the patterned structure 208 of the semiconductor wafer (semiconductor workpiece 200) and have a second height (H2) that is less than the first height (H1) of the photoresist layer 209.

[0151] Subsequent processing may be performed in step 412. For example, the patterned structure 208 of the semiconductor wafer (semiconductor workpiece 200) having the second height (H2) may be used to form sub-resolution features in an underlying layer (e.g., intermediate layer 206) of the semiconductor wafer (semiconductor workpiece 200).

[0152] Figure 5 illustrates an exemplary method 500 for patterning a semiconductor workpiece, according to certain embodiments. Method 500 may be similar to some or all of patterning process 302, and for purposes of describing exemplary method 500, reference will be made primarily to the reference numerals used in connection with Figures 3A-3G. Additionally, at least aspects of Figures 3A-3G not described in connection with Figure 5 are incorporated by reference. However, method 500 may implement any suitable patterning process.

[0153] In step 502, a photoresist layer 309 may be deposited on a semiconductor wafer (semiconductor workpiece 300) to be patterned by photolithography. The photoresist layer 309 has a first height (H1).

[0154] In step 504, a chemical agent-containing layer 338 is deposited on the photoresist layer 309. In certain embodiments, depositing the chemical agent-containing layer 338 on the photoresist layer 309 includes depositing the chemical agent-containing material by spin-coating the chemical agent-containing material on the photoresist layer 309 (e.g., using a spin-on deposition technique 314). The semiconductor wafer (semiconductor workpiece 300) may include a topcoat 326 formed on the photoresist layer 309 before depositing the chemical agent-containing layer 338, the topcoat 326 being between the photoresist layer 309 and the chemical agent-containing layer 338. The topcoat 326 may be configured to function as a diffusion barrier.

[0155] In step 506, a pre-exposure bake 350 of the semiconductor wafer (semiconductor workpiece 300) is performed. The pre-exposure bake 350 may cause the first solubility modifier 344 to diffuse from the chemical agent-containing layer 338 into a first portion 352 of the photoresist layer 309. The first portion 352 may be disposed between the chemical agent-containing layer 338 and a second portion 354 of the photoresist layer 309. For example, the first portion 352 and the second portion 354 may be upper and lower portions of the photoresist layer 309, respectively.

[0156] In certain embodiments, the pre-exposure bake 350 may modify the first portion 352 of the photoresist layer 309 to dissolve in development. In certain embodiments, the pre-exposure bake 350 may cause the solubility modifier 344 to diffuse from the chemical agent-containing layer 338 into the first portion 352 of the photoresist layer 309 to modify the first portion 352 to dissolve in development. Additionally, the pre-exposure bake 350 may cause the diffused solubility modifier 344 to react with the material (e.g., a polymer) of the first portion 352, causing the first portion 352 of the photoresist layer 309 to dissolve in development.

[0157] In certain other embodiments, the pre-exposure bake 350 causes the solubility modifier 344 to diffuse a target distance into the photoresist layer 309 (e.g., the first portion 352 of the photoresist layer 309), while the pre-exposure bake 350 is performed at a temperature low enough to prevent the diffused solubility modifier 344 from reacting with the material (e.g., a polymer) of the first portion 352 and causing the first portion 352 of the photoresist layer 309 to dissolve in development. In such embodiments, a later trigger (e.g., the PEB 340 in step 512) may cause the diffused solubility modifier 344 to react with the material (e.g., a polymer) of the first portion 352 and causing the first portion 352 of the photoresist layer 309 to dissolve in development.

[0158] The pre-exposure bake 350 may diffuse the solubility modifier 344 from the chemical agent-containing layer 338 into the first portion 352 to a target depth (D). The target depth (D) may correspond to the difference between the first height (H1) of the photoresist layer 309 and the second height (H2) of the second portion 354. In certain embodiments, one or more of the type of solubility modifier 344, the concentration of the solubility modifier 344, and the thickness of the chemical agent-containing layer 338 may be selected such that the pre-exposure bake 350 diffuses the solubility modifier 344 from the chemical agent-containing layer 338 into the first portion 352 by the target depth.

[0159] In certain embodiments, the chemical agent-containing layer 338, upon deposition, includes a polymer and a solubility modifier 344 (e.g., a free acid) or a chemical agent-generating component (e.g., a TAG or a PAG) for generating the solubility modifier 344 (e.g., an acid).

[0160] In step 508, the chemical agent-containing layer 338 may be selectively removed from the semiconductor wafer (semiconductor workpiece 300). For example, the chemical agent-containing layer 338 may be selectively removed from the surface of the photoresist layer 309 (or topcoat 326, if present).

[0161] In step 510, second portion 354 of photoresist layer 309 may be exposed to actinic radiation pattern 328 through first portion 352 to form exposed regions 332 and unexposed regions 334 in second portion 354. In certain embodiments, the lithography technique for exposing second portion 354 to actinic radiation pattern 328 includes one or more of an immersion lithography technique or i-line lithography. This disclosure contemplates using any suitable type of lithography technique. First portion 352 may be relatively transparent to the wavelengths of actinic radiation 328 in actinic radiation pattern 328.

[0162] In step 512, a PEB 340 of the semiconductor wafer (semiconductor workpiece 300) may be performed. The PEB 340 may modify the exposed regions 332 of the second portion 354 to be soluble in development. In certain embodiments, to modify the exposed regions 332 of the second portion 354 to be soluble in development, the PEB 340 causes a solubility modifier 336 activated by the actinic radiation 328 in the exposed regions 332 of the second portion 354 to react with the material (e.g., a polymer) of the exposed regions 332 of the second portion 354, causing the exposed regions 332 of the second portion 354 to be soluble in development. In certain embodiments, prior to the PEB 340, the exposed regions 332 of the second portion 354 include the solubility modifier 336, which is generated in response to the actinic radiation 328.

[0163] In certain embodiments, as described above in connection with step 506, PEB 340 may diffuse solubility modifier 344 into first portion 352 of photoresist layer 309, causing first portion 352 of photoresist layer 309 to dissolve upon development. For example, PEB 340 may cause solubility modifier 344 diffused into first portion 352 of photoresist layer 309 in step 506 to react with a material (e.g., a polymer) of first portion 352 of photoresist layer 309, causing first portion 352 to dissolve upon development.

[0164] In certain embodiments, solubility modifier 336 and solubility modifier 344 comprise an acid, and photoresist layer 309 comprises an acid-reactive material.

[0165] In step 514, the photoresist layer 309 may be developed to selectively remove the exposed areas 332 of the first portion 352 and second portion 354 that were modified by the PEB 340 in step 512. The remaining unexposed areas 334 of the second portion 354 form the patterned structure 308 of the semiconductor wafer (semiconductor workpiece) and may have a second height (H2) that is less than the first height (H1) of the photoresist layer 309.

[0166] Subsequent processing may be performed in step 516. For example, the patterned structure 308 of the semiconductor wafer (semiconductor workpiece 300) having the second height (H2) may be used to form sub-resolution features in an underlying layer (e.g., intermediate layer 306) of the semiconductor wafer (semiconductor workpiece 300).

[0167] FIG. 6 illustrates an exemplary method 600 for patterning a semiconductor workpiece, according to certain embodiments. Method 600 may be similar to some or all of patterning process 102, and for purposes of describing exemplary method 600, reference will be made primarily to the reference numerals used in connection with FIGS. 1A-1G. Additionally, at least aspects of FIGS. 1A-1G not described in connection with FIG. 6 are incorporated by reference. However, method 600 may implement any suitable patterning process. Method 600 may also incorporate aspects of patterning processes 202 and 302 and methods 400 and 500.

[0168] In step 602, patterned structure 108 may be formed on a semiconductor wafer (e.g., semiconductor workpiece 100). Patterned structure 108 may define recess 110 and have a height (H2). For example, semiconductor workpiece 100 at this stage of method 600 may correspond to semiconductor workpiece 200 at the stage shown in FIG. 2E, formed according to patterning process 202. In such an example, structure 108 may correspond to structure 208, and recess 110 may correspond to recess 210. As another example, semiconductor workpiece 100 at this stage of method 600 may correspond to semiconductor workpiece 300 at the stage shown in FIG. 3G, formed according to patterning process 302. In such an example, structure 108 may correspond to patterned structure 308, and recess 110 may correspond to recess 310.

[0169] Whether formed according to patterning process 202, patterning process 302, or otherwise, forming patterned structure 108 may include steps 602a-602e. In step 602a, a photoresist layer (e.g., photoresist layer 209 / 309) may be deposited on a semiconductor wafer (semiconductor workpiece 100) to be patterned by photolithography. The photoresist layer has a height (H1) that is greater than the height (H2) of patterned structure 108. In step 602b, a trimming layer (e.g., chemical agent-containing layer 238 / 338) may be deposited on the photoresist layer (e.g., photoresist layer 209 / 309) for subsequent trimming of the height / thickness of the photoresist layer.

[0170] In step 602c, prior to developing the photoresist layer, the height (H1) of the photoresist layer may be reduced to a height (H2) using a first solubility modifier (e.g., solubility modifier 244 / 344) diffused from a trimming layer (e.g., chemical agent-containing layer 238 / 338) into the photoresist layer (e.g., into the upper portion 242 of the unexposed area 234 after exposing photoresist layer 209 to actinic radiation 228 to pattern photoresist layer 209, or into the first portion 352 before exposing photoresist layer 309 to actinic radiation 328 to pattern photoresist layer 309). The solubility modifier 244 / 344 may include an acid.

[0171] In step 602d, the photoresist layer may be exposed to a pattern of actinic radiation. As described above, the photoresist layer may be exposed to a pattern of actinic radiation before step 602c (e.g., in patterning process 202) or after step 602c (e.g., in patterning process 302). In step 602e, the photoresist layer may be developed, and remaining portions of the photoresist layer may form micro-fabricated structures (e.g., patterned structures 108) that define recesses (e.g., recess 110).

[0172] With the semiconductor wafer (semiconductor workpiece 100) formed at the stage shown in FIG. 1A , an overcoat film 112 may be deposited on the semiconductor wafer in step 604. The overcoat film 112 may fill the recesses 110 and cover the patterned structures 108. In step 606, a solubility modifier 117 (e.g., an acid) of the overcoat film 112 may be diffused into the outer periphery of the patterned structures 108 to form modified portions 118. In step 606, the overcoat film 112 may be selectively removed. In step 608, an overcoat film 120 may be deposited on the semiconductor wafer (semiconductor workpiece 100). The overcoat film 120 may fill the recesses 110 and cover the patterned structures 108.

[0173] In step 610, a development process may be performed using one or more suitable developers. The development process may remove a first portion of the overcoat film 120 to expose at least a portion of the periphery (modified portion 118) of the patterned structure 108 and may remove the periphery (modified portion 118) of the patterned structure 108 to define the patterned structure 123. The patterned structure 123 may include a remaining portion (unmodified portion 119) of the patterned structure 108 and a remaining portion 122 of the overcoat film 120 interspersed among the remaining portion (unmodified portion 119) of the patterned structure 108. The patterned structure 123 may define a recess 124, which may have a width smaller than that of the recess 110, thereby defining a narrow critical dimension that may be transferred to an underlying layer. In certain embodiments, the recess 124 has a width of 10 nanometers or less.

[0174] Methods 400, 500, and 600 may be combined with each other or with other methods and performed using the systems and devices described herein. While shown in a logical order, the arrangement and numbering of the steps of methods 400, 500, and 600 is not intended to be limiting. The steps of methods 400, 500, and 600 may be performed in any suitable order or concurrently with each other, as would be apparent to one of ordinary skill in the art.

[0175] 7-9 illustrate exemplary processing tools that may be used together or in combination to implement certain embodiments of the present disclosure.

[0176] 7 shows a block diagram of an exemplary lithography system 700, in accordance with certain embodiments. Lithography system 700 is merely one example of a lithography system that may be used in certain embodiments. In the illustrated example, lithography system 700 includes a track system 702 and a projection scanner 704. In certain embodiments, lithography system 700 is generally configured to perform patterning process 202.

[0177] The scanner 704 may be configured to perform the exposure phase of the photolithography process. In certain embodiments, the scanner 704 is a combination of an optical system and a mechanical system for scanning an optical image of a pattern printed on a photomask (e.g., pattern mask 230, 330) onto the surface of a wafer (e.g., semiconductor workpiece 100, 200, 300) coated with a resist (e.g., photoresist layer 209, 309). After scanning the pattern once, the scanner 704 may be operated to step to an adjacent location on the same wafer, where the scan is repeated to form another copy of the pattern. In this manner, the photoresist layer is exposed to multiple copies of the pattern arranged in a rectangular matrix on the surface of the wafer.

[0178] Track system 702 includes a series of process modules assembled to potentially sequentially perform processes for lithography processes before and after the exposure step performed by scanner 704. Track system 702 provides material processes such as coating a wafer with photoresist, baking the photoresist, and developing the photoresist after exposure. In the illustrated example, the process modules of track system 702 include spin-coating module 1206, spin-coating module 710, PEB module 712, and develop module 714 for developing the exposed photoresist. Spin-coating modules 706 and 710 include spin coaters, examples of which are described below with reference to FIG. 9 . Photoresist materials, chemical-containing layer materials, overcoat materials, and solvents are connected from a liquid supply system to the appropriate processing modules (e.g., spin-coating modules 706 and 710, develop module 714, etc.) via pipelines, filters, valves, and pumps.

[0179] In addition to the process modules, the track system 702 includes an imaging module 708 and may also include an inspection and metrology (IM) module.

[0180] Imaging module 708 may be an optical imaging module used to identify defects before exposing the resist to a radiation pattern in scanner 704. Photoresist-coated wafers are received from spin-coating module 706 and imaged in imaging module 708 using an imaging system including a light source and a camera. The light source is configured to illuminate the wafer, while the camera forms a photographic image of the surface. In certain embodiments, the imaging system of imaging module 708 includes a camera for imaging the wafer from various directions (e.g., from the top (photoresist-coated side), from the bottom (backside), and from the side (chamfered edge)). The camera may be coupled to a controller of the imaging system, which acquires images and transmits them to an inspection device for image analysis. The inspection device may identify defects using, for example, a processor of the inspection device configured to execute instructions stored in an electronic memory of the inspection device to perform appropriate image analysis. Defective wafers may be reworked or scrapped as necessary.

[0181] The IM module may receive the wafer after the photoresist layer has been exposed to an actinic radiation pattern in the scanner 704, the pattern transferred to the photoresist in the development module 714, and the exposed photoresist developed to form a patterned photoresist layer. The quality of the photoresist pattern is assessed in the IM module by inspecting and measuring various images of the photoresist pattern. The IM module may include, for example, a scanning electron microscope (SEM) for measuring critical dimensions of the photoresist pattern. A wafer may fail inspection if there are patterning defects or measurements are not within specified limits. Failed wafers may be discarded or, if possible, reworked by stripping the photoresist and repeating the photoresist patterning process.

[0182] Lithography system 700 may include a track system for moving wafers (e.g., semiconductor workpieces) from module to module of track system 702, from track system 702 to projection scanner 704 (which may be considered “off-track”), and from projection scanner 704 back to track system 702.

[0183] 8 shows a block diagram of an exemplary lithography system 800, in accordance with certain embodiments. Lithography system 800 is merely one example of a lithography system that may be used in certain embodiments of the present disclosure. In the illustrated example, lithography system 800 includes a track system 802 and a projection scanner 804. In certain embodiments, lithography system 800 is generally configured to perform patterning process 302. In general, lithography system 800 is similar to lithography system 700, except that lithography system 800 is configured to perform patterning process 302. The description of lithography system 700 is incorporated by reference.

[0184] Scanner 804 may be configured to perform the exposure phase of the photolithography process as described above with respect to scanner 704 .

[0185] Track system 802 includes a series of process modules assembled to potentially sequentially perform processes for lithography processes before and after the exposure step performed by scanner 804. Track system 802 provides material processes such as coating a wafer with photoresist, baking the photoresist, and developing the photoresist after exposure. In the illustrated example, the process modules of track system 802 include a spin-coating module 806 (e.g., for depositing photoresist layer 309), a spin-coating module 808 (e.g., for depositing chemical agent-containing layer 338), a pre-exposure bake module 810, a solvent clean module 812, a PEB module 814, and a develop module 816 for developing the exposed photoresist. Spin-coating modules 806 and 808 include spin coaters, examples of which are described below with reference to FIG. 9 . Photoresist materials, chemical-containing layer materials, overcoat materials, and solvents are connected from the liquid supply system via pipelines, filters, valves, and pumps to the appropriate processing modules (e.g., spin coating modules 806 and 808, development module 816, etc.) Although not shown, track system 802 may include imaging modules and IM modules similar to those described above.

[0186] Lithography system 800 may include a track system for moving wafers (e.g., semiconductor workpieces) from module to module of track system 802, from track system 802 to projection scanner 804 (which may be considered “off-track”), and from projection scanner 804 back to track system 802.

[0187] 9 illustrates an exemplary liquid-based spin-on deposition system 900, according to certain embodiments. For example, the liquid-based spin-on deposition system 900 can be used to process any of the described semiconductor workpieces to deposit a photoresist layer, a barrier layer, a photoresist formulation, an overcoat film, or any of the other suitable materials described in this disclosure. In certain embodiments, the spin-on deposition system 900 can be a semi-enclosed spin-on deposition system used to coat a substrate (wafer) with a desired layer. The semi-enclosed configuration can enable fume control and minimize exhaust emissions.

[0188] In the illustrated example, the spin-on deposition system 900 includes a process chamber 902 including a substrate holder 904 for supporting, heating, and rotating (spinning) a substrate 906 (which may include any of the semiconductor workpieces at an appropriate processing stage described in this disclosure), a rotation device 908 (e.g., a motor), and a liquid delivery nozzle 910 configured to supply a processing liquid 912 to an upper surface of the substrate 906. Liquid supply systems 914, 916, and 918 supply different processing liquids to the liquid delivery nozzle 910. For depositing photoresist, the different processing liquids may include, for example, a first reactant in a first liquid, a second reactant in a second liquid, and a rinse liquid. In certain embodiments, the spin-on deposition system 900 includes additional liquid delivery nozzles for providing different liquids to the substrate 906. An exemplary rotation speed can be between about 500 rpm and about 1500 rpm, e.g., 1000 rpm, during exposure of the upper surface of the substrate 906 to the processing liquid 912.

[0189] The spin-on deposition system 900 may include a controller 920 coupled to and capable of controlling the process chamber 902, liquid supply systems 914, 916, and 918, a liquid delivery nozzle 910, a rotation device 908, and a mechanism for heating the substrate holder 904. The substrate 906 may be under an inert atmosphere during film deposition. The spin-on deposition system 900 may be configured to process substrates 906 of any suitable size.

[0190] Particular embodiments may provide none, some, or all of the following technical advantages: Other advantages are described throughout this disclosure or will otherwise become apparent to those skilled in the art upon reading this disclosure.

[0191] Certain embodiments also improve feature fidelity for older lithography platforms, such as immersion lithography (e.g., 193 nanometer immersion lithography), i-line lithography, or other older lithography techniques that perform additional processing (e.g., anti-spacer double patterning lithography) to achieve sub-resolution features. Certain embodiments can achieve sub-EUV dimensions using 193 nanometer immersion and other older lithography techniques without additional ALD deposition and etching. Compared to other techniques, such as EUV or alternative spacer-based multi-patterning techniques, anti-spacer technology can be a lower-cost track-based approach to achieving sub-EUV dimensions. Because certain embodiments of the present disclosure improve anti-spacer technology, certain embodiments provide an improved, lower-cost track-based approach to achieving sub-EUV dimensions.

[0192] Certain embodiments reduce or eliminate wiggling / collapse in anti-spacer patterns. Certain embodiments improve anisotropic etch transfer critical dimensions by reducing shadowing effects from aspect ratios in combination with sidewall angles. Certain embodiments facilitate track-based resolution scaling by providing improved features that can be implemented on-track.

[0193] As another example, techniques involving depositing a photoresist layer at a reduced height to attempt to reduce the aspect ratio for subsequent pattern transfer can pose problems. During exposure, the height of the photoresist is optimized to take advantage of the full aerial image and photons to which the photoresist is exposed. Thinner, height-optimized photoresists may suffer patterning losses, including suboptimal profile, surface roughness, and the like. In contrast, certain embodiments maintain the photoresist height to achieve the desired patterning and reduce the height of the exposed resist, such as by diffusing an acid or another chemical agent into the planar resist to cause a solubility-modifying reaction either before or after exposure. In certain embodiments, process designers may attempt to achieve a desired level of diffusion and associated solubility modification, and thereby associated height reduction of the patterned structure, so that sufficient mask volume for pattern transfer is present within the patterned structure being formed. In certain embodiments, the height reduction achieves an aspect ratio (structure height to recess width) of 5:1 or less, such as 2:1.

[0194] As another example, the use of the chemical agent-containing layers disclosed herein can reduce the height of a photoresist layer with little or no change in the width (critical dimension) of features patterned from the resist layer (e.g., mandrels). For example, techniques that involve depositing a layer to trim the height of mandrel features after development are likely to reduce the feature size both vertically and laterally, undesirably destroying the target width of the features. In contrast, by applying a chemical agent-containing layer before development, certain embodiments can selectively trim a photoresist layer in the vertical (e.g., up and down) direction.

[0195] Although certain embodiments have been described as providing particular advantages over 193 nanometer immersion lithography techniques, i-line techniques, and other older lithography techniques, including the ability to provide improved sub-EUV critical dimensions, sub-10 nanometer critical dimensions, etc., the present disclosure may be implemented using any suitable lithography technique, including EUV techniques.

[0196] Furthermore, although this disclosure primarily describes embodiments using the disclosed techniques to pattern photoresist and / or layers underlying the photoresist, embodiments of the present disclosure may be used to pattern any suitable type of layer, for example, the present disclosure may be used to pattern films other than photoresist layers that may benefit from a top-down thinning process.

[0197]

[0030] Exemplary embodiments of the present disclosure are summarized here. Other embodiments may be understood from the claims of this application, as well as from the entire specification.

[0198] Example 1. A method includes depositing a photoresist layer on a semiconductor wafer to be patterned by photolithography, wherein the photoresist layer has a first height, and exposing the photoresist layer to an actinic radiation pattern to form exposed and unexposed regions in the photoresist layer. The method further includes depositing a chemical agent-containing layer on the photoresist layer and performing a post-exposure bake of the semiconductor wafer. The post-exposure bake modifies portions of the photoresist layer to form soluble portions of the photoresist layer for development. The soluble portions of the photoresist layer include the exposed regions and upper portions of the unexposed regions. The method further includes developing the photoresist layer to selectively remove the soluble portions, wherein remaining portions of the unexposed regions form a patterned structure on the semiconductor wafer and have a second height less than the first height.

[0199] Example 2. The method of Example 1, wherein the post-exposure bake causes a first solubility modifier to diffuse from the chemical agent-containing layer to an upper portion of the unexposed areas of the photoresist layer, causing the first solubility modifier to dissolve in development, and a second solubility modifier to be activated by actinic radiation in the exposed areas of the photoresist layer, causing the exposed areas of the photoresist layer to dissolve in development, to modify portions of the photoresist layer to form soluble portions of the photoresist layer for development.

[0200] Example 3. The method of Example 1 or 2, wherein the post-exposure bake diffuses the first solubility modifier from the chemical agent-containing layer to a target depth into an upper portion of the unexposed area of ​​the photoresist layer, the target depth corresponding to a difference between the first height and the second height, and one or more of the type of chemical agent in the chemical agent-containing layer, the concentration of the chemical agent, and the thickness of the chemical agent-containing layer are selected such that the post-exposure bake diffuses the first solubility modifier from the chemical agent-containing layer to the target depth into an upper portion of the unexposed area of ​​the photoresist layer.

[0201] Example 4. The method of any one of Examples 1-3, wherein the first solubility-modifying agent and the second solubility-modifying agent comprise an acid, and the photoresist layer comprises an acid-reactive material.

[0202] Example 5. The method of any one of Examples 1-4, wherein the chemical agent-containing layer, as deposited, comprises a polymer and a first solubility modifier or a chemical agent-generating component for generating a first solubility modifier.

[0203] Example 6. The method of any one of Examples 1-5, wherein prior to the post-exposure bake, the exposed portion of the photoresist layer comprises a second solubility-modifying agent, and the second solubility-modifying agent is generated in response to actinic radiation.

[0204] Example 7. The method of any one of Examples 1-6, wherein depositing the chemical agent-containing layer on the photoresist layer includes depositing the chemical agent-containing material by spin-coating the chemical agent-containing material on the photoresist layer.

[0205] Example 8. The method of any one of Examples 1-7, wherein the semiconductor wafer further comprises a topcoat formed on the photoresist layer prior to depositing the chemical agent-containing layer on the photoresist layer, such that the topcoat is between the photoresist layer and the chemical agent-containing layer, wherein the topcoat functions as a diffusion barrier.

[0206] Example 9. The method of any one of Examples 1-8, wherein the lithographic technique for exposing the photoresist layer to the actinic radiation pattern comprises one or more of an immersion lithography technique or i-line lithography.

[0207] Example 10. The method of any one of Examples 1-9, further comprising forming sub-resolution features in an underlying layer of the semiconductor wafer using the patterned structure of the semiconductor wafer having the second height.

[0208] Example 11. A method includes depositing a photoresist layer on a semiconductor wafer to be patterned by photolithography, wherein the photoresist layer has a first height. The method further includes depositing a chemical agent-containing layer on the photoresist layer and performing a pre-exposure bake of the semiconductor wafer. The pre-exposure bake diffuses a first solubility-modifying agent from the chemical agent-containing layer into a first portion of the photoresist layer, such that the first portion of the photoresist layer is disposed between the chemical agent-containing layer and a second portion of the photoresist layer. The method further includes selectively removing the chemical agent-containing layer and exposing the second portion of the photoresist layer to a pattern of actinic radiation through the first portion of the photoresist layer to form exposed and unexposed regions in the second portion of the photoresist layer. The method further includes performing a post-exposure bake of the semiconductor wafer, where the post-exposure bake modifies exposed areas of the second portion of the photoresist layer so that they are soluble in development, and developing the photoresist layer to selectively remove the first portion of the photoresist layer and the exposed areas of the second portion of the photoresist layer modified by the post-exposure bake, wherein the remaining portions of the unexposed areas of the photoresist layer form a patterned structure of the semiconductor wafer and have a second height that is less than the first height of the photoresist layer.

[0209] Example 12. The method of Example 11, wherein performing a post-exposure bake causes a first solubility modifier to diffuse into a first portion of the photoresist layer, causing the first portion of the photoresist layer to dissolve in development, and wherein the post-exposure bake causes a second solubility modifier activated by actinic radiation in the exposed areas of the second portion of the photoresist layer to modify the exposed areas of the second portion of the photoresist layer to dissolve in development.

[0210] Example 13. The method of Example 11 or 12, wherein the pre-exposure bake diffuses the first solubility modifier from the chemical agent-containing layer into the first portion of the photoresist layer to a target depth, the target depth corresponds to a difference between the first height and the second height, and one or more of the type of chemical agent in the chemical agent-containing layer, the concentration of the chemical agent, and the thickness of the chemical agent-containing layer are selected such that the pre-exposure bake diffuses the first solubility modifier from the chemical agent-containing layer into the first portion of the photoresist layer to the target depth.

[0211] Example 14. The method of any one of Examples 11-13, wherein the first solubility-modifying agent and the second solubility-modifying agent comprise an acid, and the photoresist layer comprises an acid-reactive material.

[0212] Example 15. The method of any one of Examples 11-14, wherein the chemical agent-containing layer, as deposited, comprises a polymer and a first solubility modifier or a chemical agent-generating component for generating a first solubility modifier.

[0213] Example 16. The method of any one of Examples 11 and 13-15, wherein performing a pre-exposure bake causes a first solubility modifier to diffuse from the chemical agent-containing layer into a first portion of the photoresist layer, causing the first solubility modifier to diffuse into the first portion of the photoresist layer and render the first portion of the photoresist layer dissolvable upon development, and wherein a post-exposure bake causes a second solubility modifier activated by actinic radiation in the exposed areas of the second portion of the photoresist layer to modify the exposed areas of the second portion of the photoresist layer to render the exposed areas of the second portion of the photoresist layer dissolvable upon development.

[0214] Example 17. The method of any one of Examples 11-16, wherein prior to the post-exposure bake, the exposed portion of the photoresist layer comprises a second solubility-modifying agent, and the second solubility-modifying agent is generated in response to actinic radiation.

[0215] Example 18. The method of any one of Examples 11-17, wherein depositing the chemical agent-containing layer on the photoresist layer includes depositing the chemical agent-containing material by spin-coating the chemical agent-containing material on the photoresist layer.

[0216] Example 19. The method of any one of Examples 11-18, wherein the semiconductor wafer further comprises a topcoat formed on the photoresist layer prior to depositing the chemical agent-containing layer on the photoresist layer, such that the topcoat is between the photoresist layer and the chemical agent-containing layer, wherein the topcoat functions as a diffusion barrier.

[0217] Example 20. The method of any one of Examples 11-19, wherein the lithographic technique for exposing the photoresist layer to the actinic radiation pattern comprises one or more of an immersion lithography technique or i-line lithography.

[0218] Example 21. The method of any one of Examples 11-20, further comprising forming sub-resolution features in an underlying layer of the semiconductor wafer using the patterned structure of the semiconductor wafer having the second height.

[0219] Example 22. The method of any one of Examples 11-21, wherein the first portion of the photoresist layer is relatively transparent to the actinic radiation of the actinic radiation pattern.

[0220] Example 23. A method includes forming a first patterned structure on a semiconductor wafer, the first patterned structure defining a first recess and having a first height. Forming the first patterned structure includes depositing a photoresist layer on the photolithographically patterned semiconductor wafer, the photoresist layer having a second height greater than the first height, depositing a trimming layer on the photoresist layer, reducing the second height of the photoresist layer to the first height using a first solubility modifier diffused into the photoresist layer from the trimming layer before developing the photoresist layer, exposing the photoresist layer to an actinic radiation pattern, and developing the photoresist layer, wherein remaining portions of the photoresist layer form micro-fabricated structures defining the recess. The method further includes depositing a first overcoat film on the semiconductor wafer, where the first overcoat film fills the first recess and covers the first patterned structure, diffusing a second solubility modifier of the first overcoat film into an outer periphery of the first patterned structure, and selectively removing the first overcoat film. The method further includes depositing a second overcoat film on the semiconductor wafer, where the second overcoat film fills the first recess and covers the first patterned structure, and performing a development process that removes a first portion of the second overcoat film to expose the outer periphery of the first patterned structure and removes the outer periphery of the first patterned structure to define a second patterned structure. The second patterned structure includes remaining portions of the first patterned structure and second portions of the second overcoat film interspersed among the remaining portions of the first patterned structure, and the second patterned structure defines a second recess.

[0221] Example 24. The method of example 23, wherein the second recess has a width of 10 nm or less.

[0222] Example 25. The method of Example 23 or 24, wherein the first solubility modifier and the second solubility modifier comprise an acid.

[0223] In the preceding description, specific details have been set forth, such as the particular geometry of the processing system and descriptions of the various components and processes used therein. However, it should be understood that the techniques described herein may be practiced in other embodiments that deviate from these specific details, and that such details are for purposes of explanation and not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numerical values, materials, and configurations have been set forth to provide a thorough understanding. However, embodiments may be practiced without such specific details. Components having substantially the same functional structure may be designated by like reference numerals, and redundant description may be omitted.

[0224] The order of description of the different steps described herein is shown for clarity. In general, these steps can be performed in any suitable order. Also, although different features, techniques, configurations, etc. herein may be referred to in different places in this disclosure, it is understood that each concept can be performed independently of each other or in combination with each other. Thus, the present disclosure can be implemented and viewed in a variety of ways.

[0225] As used herein, "substrate," "target substrate," "structure," or "device" generally refers to an object to be processed according to the present disclosure and may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate, structure, or device is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or not, but is intended to include such layers or base structures, and any combination of layers and / or base structures. While the specification may refer to particular types of substrates, structures, or devices, this is for illustrative purposes only.

[0226] Although the present disclosure describes certain process steps as occurring in a particular order, the present disclosure contemplates that the process steps may be performed in any suitable order. While the present disclosure has been described with reference to exemplary embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present disclosure, will be apparent to those skilled in the art upon reference to the description. It is therefore intended that the appended claims cover any and all such modifications or embodiments.

Claims

1. depositing a photoresist layer on a semiconductor wafer to be photolithographically patterned, the photoresist layer having a first height; exposing the photoresist layer to a pattern of actinic radiation to form exposed and unexposed areas of the photoresist layer; depositing a chemical agent-containing layer over the photoresist layer; performing a post-exposure bake of the semiconductor wafer, the post-exposure bake modifying portions of the photoresist layer to form soluble portions of the photoresist layer for development, the soluble portions of the photoresist layer including the exposed regions of the photoresist layer and portions above the unexposed regions of the photoresist layer; developing the photoresist layer to selectively remove the soluble portions of the photoresist layer, wherein remaining portions of the unexposed areas of the photoresist layer form patterned features of the semiconductor wafer and have a second height that is less than the first height of the photoresist layer; A method comprising:

2. the post-exposure bake to modify the portions of the photoresist layer to form the soluble portions of the photoresist layer for development; allowing a first solubility modifier to diffuse from the chemical agent-containing layer to the upper portion of the unexposed areas of the photoresist layer, such that the first solubility modifier dissolves the upper portion of the unexposed areas of the photoresist layer upon development; 10. The method of claim 1, wherein a second solubility-modifying agent is activated in the exposed areas of the photoresist layer by the actinic radiation to cause the exposed areas of the photoresist layer to dissolve upon development.

3. the post-exposure bake diffuses the first solubility-modifying agent from the chemical agent-containing layer into the upper portion of the unexposed area of ​​the photoresist layer to a target depth, the target depth corresponding to a difference between the first height and the second height; 3. The method of claim 2, wherein one or more of a type of chemical agent, a concentration of chemical agent, and a thickness of the chemical agent-containing layer are selected such that the post-exposure bake diffuses the first solubility-modifying agent from the chemical agent-containing layer to the upper portion of the unexposed areas of the photoresist layer to the target depth.

4. the first solubility modifier and the second solubility modifier comprise an acid; The method of claim 2 , wherein the photoresist layer comprises an acid-reactive material.

5. The chemical agent-containing layer, as deposited, A polymer, the first solubility modifier or a chemical agent generating component for generating the first solubility modifier; The method of claim 4, comprising:

6. 3. The method of claim 2, wherein prior to the post-exposure bake, the exposed portion of the photoresist layer comprises the second solubility modifier, the second solubility modifier being generated in response to the actinic radiation.

7. 10. The method of claim 1, wherein depositing the chemical agent-containing layer on the photoresist layer comprises depositing the chemical agent-containing material by spin-coating the chemical agent-containing material on the photoresist layer.

8. a lithographic technique for exposing the photoresist layer to the pattern of actinic radiation, immersion lithography techniques, or i-line lithography The method of claim 1 , comprising one or more of:

9. 10. The method of claim 8, further comprising forming sub-resolution features in an underlying layer of the semiconductor wafer using the patterned structures of the semiconductor wafer having the second height.

10. depositing a photoresist layer on a semiconductor wafer to be photolithographically patterned, the photoresist layer having a first height; depositing a chemical agent-containing layer over the photoresist layer; performing a pre-exposure bake of the semiconductor wafer, the pre-exposure bake causing a first solubility-modifying agent to diffuse from the chemical agent-containing layer into a first portion of the photoresist layer, the first portion of the photoresist layer being disposed between the chemical agent-containing layer and a second portion of the photoresist layer; selectively removing the chemical agent-containing layer; exposing the second portion of the photoresist layer to a pattern of actinic radiation through the first portion of the photoresist layer to form exposed and unexposed regions in the second portion of the photoresist layer; performing a post-exposure bake of the semiconductor wafer, the post-exposure bake modifying the exposed areas of the second portion of the photoresist layer to make them dissolvable in development; developing the photoresist layer to selectively remove the first portion of the photoresist layer modified by the post-exposure bake and the exposed portions of the second portion of the photoresist layer, wherein remaining portions of the unexposed areas of the photoresist layer form patterned features of the semiconductor wafer and have a second height that is less than the first height of the photoresist layer; A method comprising:

11. performing the post-exposure bake causes the first solubility-modifying agent to diffuse into the first portion of the photoresist layer and cause the first portion of the photoresist layer to dissolve upon development; 11. The method of claim 10, wherein the post-exposure bake activates a second solubility-modifying agent in the exposed areas of the second portion of the photoresist layer by the actinic radiation to modify the exposed areas of the second portion of the photoresist layer to dissolve in development.

12. the pre-exposure bake diffuses the first solubility-modifying agent from the chemical agent-containing layer into the first portion of the photoresist layer to a target depth, the target depth corresponding to a difference between the first height and the second height; 12. The method of claim 11 , wherein one or more of a type of chemical agent, a concentration of chemical agent, and a thickness of the chemical agent-containing layer of the chemical agent-containing layer are selected such that the pre-exposure bake diffuses the first solubility-modifying agent from the chemical agent-containing layer into the first portion of the photoresist layer to the target depth.

13. the first solubility modifier and the second solubility modifier comprise an acid; the photoresist layer comprises an acid-reactive material; The chemical agent-containing layer, as deposited, A polymer, the first solubility modifier or a chemical agent generating component for generating the first solubility modifier; The method of claim 11 , comprising:

14. performing the pre-exposure bake causes the first solubility modifier to diffuse from the chemical agent-containing layer into the first portion of the photoresist layer and causes the first solubility modifier that has diffused into the first portion of the photoresist layer to dissolve the first portion of the photoresist layer upon development; 11. The method of claim 10, wherein the post-exposure bake activates a second solubility-modifying agent in the exposed areas of the second portion of the photoresist layer by the actinic radiation to modify the exposed areas of the second portion of the photoresist layer to dissolve in development.

15. a lithographic technique for exposing the photoresist layer to the pattern of actinic radiation, immersion lithography techniques, or i-line lithography The method of claim 10, comprising one or more of:

16. 16. The method of claim 15, further comprising forming sub-resolution features in an underlying layer of the semiconductor wafer using the patterned structures of the semiconductor wafer having the second height.

17. 11. The method of claim 10, wherein the first portion of the photoresist layer is relatively transparent to the actinic radiation of the actinic radiation pattern.

18. forming a first patterned structure on a semiconductor wafer, the first patterned structure defining a first recess and having a first height; depositing a photoresist layer on a semiconductor wafer to be photolithographically patterned, the photoresist layer having a second height greater than the first height; depositing a trimming layer on the photoresist layer; reducing the second height of the photoresist layer to the first height using a first solubility-modifying agent diffused into the photoresist layer from the trimming layer prior to developing the photoresist layer; exposing the photoresist layer to a pattern of actinic radiation; developing the photoresist layer, wherein remaining portions of the photoresist layer form micro-fabricated structures defining recesses; forming a depositing a first overcoat film on the semiconductor wafer, the first overcoat film filling the first recess and covering the first patterned structure; diffusing the second solubility-modifying agent of the first overcoat film into the periphery of the first patterned structure; selectively removing the first overcoat film; depositing a second overcoat film on the semiconductor wafer, the second overcoat film filling the first recess and covering the first patterned structure; performing a development process that removes a first portion of the second overcoat film to expose the periphery of the first patterned structure and removes the periphery of the first patterned structure to define a second patterned structure, the second patterned structure including a remaining portion of the first patterned structure and a second portion of the second overcoat film interspersed among the remaining portion of the first patterned structure, the second patterned structure defining a second recess; A method comprising:

19. 20. The method of claim 18, wherein the second recess has a width of 10 nanometers or less.

20. 20. The method of claim 18, wherein the first solubility modifier and the second solubility modifier comprise an acid.

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