Semiconductor Interconnect Bridge Packaging

Abstract

[0003] Embodiments of the present disclosure include techniques for a package and method for semiconductor dies. An interconnect bridge includes a first conductor that electrically connects two or more semiconductor dies. The interconnect bridge includes a second conductor between opposing surfaces. A substrate of the interconnect bridge is removed to expose conductors of an interconnect layer that are electrically coupled to connections to the first and second semiconductor dies in areas where the semiconductor dies and the interface bridge overlap.

Description

[Technical Field]

[0001] The present disclosure relates generally to semiconductor packaging, and more particularly to power delivery in semiconductor packaging. [Background technology]

[0002] Semiconductor devices are typically fabricated from silicon. Thin slices of silicon (wafers) are processed to create various electrical circuits on the wafer's top layers. A single wafer typically has many identical circuits formed in an array on the wafer. The array of circuits may be cut to produce individual chips (integrated circuit chips, or IC chips). The chips are then packaged. The package houses one or more chips and provides electrical connections to the internal IC within the package. Summary of the Invention

[0003] It is often advantageous to house many ICs in a single package. Some IC packages contain internal circuitry to electrically connect the ICs internally. However, in some applications, the internal connection circuitry interferes with the conductors between the external package connections and the internal package connections. This is particularly important for power delivery. If the power delivery conductors are forced to extend their wiring to accommodate the internal connection circuitry, the longer wiring can reduce the overall efficiency of the circuit and cause other problems.

[0004] The embodiments described herein advantageously provide semiconductor packaging techniques that reduce the impact of interconnect circuitry between multiple ICs within a package. [Brief explanation of the drawings]

[0005] [Figure 1A] FIG. 1 illustrates a semiconductor package according to one embodiment. [Figure 1B] FIG. 1B illustrates the interconnect bridge of FIG. 1A according to one embodiment. [Figure 2]1 illustrates a semiconductor packaging method according to an embodiment. [Figure 3] 1 illustrates a semiconductor packaging method according to an embodiment. [Figure 4A] 1 illustrates an exemplary semiconductor packaging method and package according to one embodiment. [Figure 4B] 1 illustrates an exemplary semiconductor packaging method and package according to one embodiment. [Figure 5A] 1 illustrates another exemplary semiconductor packaging method and package according to one embodiment. [Figure 5B] 1 illustrates another exemplary semiconductor packaging method and package according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] Techniques for storing and retrieving data in memory are described herein. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of some embodiments. Various embodiments as defined by the claims may include some or all of the features in these examples, alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

[0007] 1A illustrates a semiconductor package 100 according to one embodiment. FIG. 1B illustrates further aspects of the semiconductor package 100 according to one embodiment. The semiconductor package 100 includes semiconductor dies 110 and 111 (as used herein, "die" is singular and refers to a single chip, and "dies" is plural and refers to multiple chips) configured on a redistribution layer (RDL) 120. In this example, the semiconductor dies 110 and 111 reside on a surface formed by the RDL 120. In this example, the RDL 120 extends under both the semiconductor dies 110 and 111, although in other embodiments, for example, individual RDLs may be formed under each semiconductor die.

[0008] Features and advantages of the present disclosure include an interconnect bridge 130 configured between semiconductor dies to establish an electrical connection between the semiconductor dies. The interconnect bridge 130 overlaps portions of the semiconductor dies 110 and 111, as indicated at 131 and 132. The interconnect bridge 130 includes conductors configured to electrically couple the semiconductor dies 110 and 111, for example, via the redistribution layer 120. The interconnect bridge 130 further includes conductors configured to electrically couple connections on the bottom surface of the interconnect bridge (e.g., the surface opposite the surface adjacent the RDL layer) to connections on the top surface of the interconnect bridge (e.g., adjacent the RDL layer) and to connections on the semiconductor dies 110 and 111 in the region where the interconnect bridge overlaps the semiconductor dies. Thus, signals and / or power may be more directly exchanged between the semiconductor dies without detouring through the interconnect bridge, which advantageously reduces the length of such connections.

[0009] For example, semiconductor dies 110 and 111 include multiple connections 112a-n and 113a-m, respectively, for transmitting and receiving electrical signals or power. RDL 120 includes connections (e.g., connection 122) on a surface between RDL 120 and semiconductor dies 110 and 111 that are coupled to semiconductor die connections 112a-n and 113a-m. RDL 120 further includes connections (e.g., connection 121) on a surface between RDL 120 and interconnect bridge 130 that are coupled to connections on interconnect bridge 130. RDL connections on opposite surfaces are electrically coupled to each other. However, the locations of the connections on opposite surfaces may be different. For example, the locations of RDL connections coupled to semiconductor connections may be at locations on the RDL / interconnect bridge surface that are different from the locations of the connections on the RDL / semiconductor die surface. Relocating the connection locations allows, for example, flexible matching of the top connection locations to the connection locations of structures on the opposite surface of the RDL. In various embodiments, different RDL structures may be used for the RDL 120. In some embodiments, a fabricated RDL including metallization and silicon dioxide (herein "oxide") may be used. For example, the RDL may include copper conductors separated by silicon dioxide. Such a structure may be fabricated using, for example, a dual damascene process. In other embodiments, a fabricated RDL, such as an organic RDL including polyimide, may be used. In some exemplary embodiments, the organic RDL may include, for example, copper and polyimide.

[0010] In this example, interconnect bridge 130 includes a connection portion (e.g., connection 133) coupled to a bottom connection portion of RDL 120 and a connection portion (e.g., connection 134) on the opposite surface for connecting to, for example, a circuit board. As described above, interconnect bridge 130 includes two different types of conductors (also known as conductive traces). Conductor 135 (shown in FIG. 1B ) is configured to electrically couple connections 112a-n of semiconductor die 110 to connections 113a-m of semiconductor die 111 through RDL 120. Conductor 136 is configured to electrically couple one or more particular connections on the surface of the interconnect bridge opposite RDL 120 (e.g., connection 134 on the bottom surface of the bridge) to one or more connections of the interconnect bridge on the opposite surface adjacent RDL 120 (e.g., connection 133 on the top surface of the bridge) and to one or more connections of semiconductor die 110 and / or 111 in the region where the interconnect bridge overlaps the semiconductor die.

[0011] As shown in Figures 1A and 1B, the connections on the underside of the bridge may be bonded to solder bumps, such as solder bump 160, which may be used to establish a connection to, for example, a printed circuit board.

[0012] In this example, the bottom surface of the interconnect bridge extends below semiconductor dies 110 and 111 and includes molding compound 103, as is well known to those skilled in the art. In the above example, two semiconductor dies are shown, however, in other embodiments, more semiconductor dies may be coupled together using interconnect bridges using the techniques described herein.

[0013] In some exemplary embodiments, the conductors 135 between the semiconductor dies are interface signal conductors, and the conductors 136a-b between the semiconductor dies and the underside of the interconnect bridge are power conductors. In some embodiments, the power conductors include thicker conductive traces or multiple conductive traces arranged in parallel to carry more current with less resistance. Furthermore, in some embodiments, the conductors 136a-b extend substantially vertically from solder bumps (e.g., solder bumps 160) on one or more bottom connections of the interconnect bridge to one or more bottom connections of the redistribution layer. Restricting horizontal movement along the surface to within the overlap region can advantageously shorten the length of the conductors, thereby reducing, for example, resistive voltage drop and heat loss.

[0014] In some embodiments, the interconnect bridge 130 is substrateless. For example, a silicon bridge die may include a substrate (e.g., Pyrex glass or silicon) and a metallization layer. The substrate is removed to create a substrateless interconnect layer (e.g., copper and silicon dioxide or copper and polyimide conductors between multiple dies or between a die and the underside of the interconnect bridge).

[0015] In some embodiments, additional conductors may be configured vertically to electrically couple to the semiconductor die in areas where interconnect bridge 130 does not overlap the semiconductor die. For example, conductors 153-155 are configured outside the area where interconnect bridge 130 overlaps the semiconductor die. Conductors 153-155 are configured to extend vertically (e.g., through molding compound) from the same plane as the bottom connections (e.g., connection 134) of the interconnect bridge to RDL 120. RDL 120 is electrically coupled to the connections of the semiconductor die. As shown in FIGS. 1A and 1B, these additional connections (e.g., connections 153-155) may be electrically coupled to the circuit board via solder bumps (e.g., solder bump 160).

[0016] FIG. 2 illustrates a semiconductor packaging method according to one embodiment. At 201, a redistribution layer (RDL) is formed. In various embodiments, the RDL may be formed on a surface including on an interconnect bridge or on a semiconductor die, as described in more detail below. At 202, connections on another structure (e.g., the interconnect bridge or the semiconductor die) that are not below the RDL are bonded to the other surface of the RDL. Thus, if the RDL is formed on the interconnect bridge, the semiconductor die is bonded to the RDL on the opposite surface. Alternatively, if the RDL is formed on the semiconductor die, the interconnect bridge is bonded to the RDL on the opposite surface. At 203, the substrate of the interconnect bridge is removed, creating a substrateless interconnect bridge with exposed connections. For example, the exposed connections extend substantially vertically through the interconnect bridge, through the RDL, and to connections (e.g., power connections) on the semiconductor die. The exposed connections of the interconnect bridges may be electrically coupled to the circuit board using, for example, solder bumps, as described in more detail below.

[0017] FIG. 3 illustrates a semiconductor packaging method according to one embodiment. 301a-b illustrate alternative starting conditions. In 301a, an interconnect bridge including interconnect layer 390 and substrate 391 forms a planar surface. Similarly, in 301b, semiconductor dies 110 and 111 form a planar surface. In 302a-b, an RDL 399 is formed on this surface. The RDL includes an RDL surface 392 including multiple connections and an RDL surface 393 including multiple connections. A particular connection on RDL surface 392 is electrically coupled to a particular connection on RDL surface 393. In some cases, one RDL connection on RDL surface 392 is connected to one RDL connection on RDL surface 393. However, in other cases, multiple RDLs are coupled together (e.g., for higher current carrying capacity). As shown in FIG. 3, the connections on the RDL layer surface 392 are electrically coupled to connections on either the interconnect bridge (302a) or the semiconductor die (302b).

[0018] At 303a-b, the other of the interconnect bridge or semiconductor die is bonded to the RDL. The connections on the RDL are aligned with the semiconductor die connections or the interconnect bridge connections. In some embodiments, solder bumps (not shown) may be used. Accordingly, the connections on the other of the interconnect bridge or semiconductor die are bonded to the connections on the top RDL surface.

[0019] At 304, the substrate 391 of the interconnect bridge is removed to expose the interconnect layer 390. A surface 395 includes the interconnect bridge. Accordingly, at 305, solder bumps may be formed, for example, to electrically couple the connections on surface 395 to a circuit board.

[0020] 4A-4B illustrate an exemplary semiconductor packaging method and package according to one embodiment. Method 400 can begin in step 401 with a carrier 420, such as a silicon or glass (e.g., Pyrex® glass by Corning, Inc.) substrate. In 402, two semiconductor dies (e.g., system-on-chip, "SoC") 421a-b are attached to the carrier using, for example, a die attach film. The SoC includes connections (e.g., contacts) as shown at 422. A molding compound 423 is formed around the SoC and polished to expose connections 422. In 403, a redistribution layer 424 is formed on the SoC. In this example, redistribution layer (RDL) 424 includes bottom connections that contact the connections of the SOC and top connections that are electrically coupled to the bottom connections. The bottom and top connections of the RDL may be at different locations on the bottom and top RDL surfaces, for example, to move the contact points from the SOC contact points on the bottom RDL surface to other locations on the top RDL surface. At 404, conductive pillars (e.g., copper (Cu) pillars 426) are formed on some of the top RDL surface connections. As will be further described below, pillars are not formed on the top RDL surface connections where the silicon bridge die will be connected (e.g., in the area where the bridge die and the SoC overlap). At 405, a silicon bridge die 427 is flip-chip attached to the top RDL surface. Flip-chip attachment refers to attaching the structure upside down, as shown at 405. The bridge die 427 may include a substrate 429 (e.g., 50-110 μm of Si or glass) and an interconnect layer 430 (e.g., the interconnect layer may include multiple metallization layers at 2 μm / layer). The bridge interconnect layer may include a first conductor configured to electrically couple a connection portion of SOC421a to a connection portion of SOC421b via RDL424, and a second conductor configured to electrically couple the connections of the interconnect bridge on opposing sides of the interconnect layer to contact the SOCs in the region where the interconnect bridge overlaps the first and second semiconductor dies.

[0021] The method proceeds from A in FIG. 4A to A in FIG. 4B. At 406, the structure is background to remove the silicon bridge die substrate and molding compound. In this example, grinding exposes connections on the top surface of the bridge die interconnect layer 430. The connections on the top surface of layer 430 are electrically coupled to connections on the bottom surface of layer 430 and are further coupled to the SOC connections in the overlapping regions via the RDL layer. The connections on the top surface are in the same plane (on the same surface) as the connections to the exposed, ground-away pillars 426. At 407, solder bumps (e.g., solder bumps 431) may be formed on the pillar connections and the connections on the top surface of interconnect layer 430. The solder bumps may be, for example, C4 solder bumps as known to those skilled in the art. At 408, the carrier 420 is removed, and the individual integrated circuits (ICs) may be singulated (cut into individual ICs including SOCs coupled to each other via the bridge die interconnect layer). At 409, the IC may be mounted on a circuit board, such as, for example, a printed circuit board (PCB) or a flexible circuit board (FCB).

[0022] 5A-5B illustrate another exemplary semiconductor packaging method and package according to one embodiment. Method 500 can begin with a carrier 520 in step 501. In 502, conductive pillars 521 (e.g., copper) are formed. A polyimide layer 522, for example, may be formed on the surface of carrier 501 and etched in areas where pillars 521 may be formed. In 503, a bridge die 523 is attached to the surface of the carrier (and / or polyimide layer). In 504, a molding compound is formed and ground away to expose connections to the pillars and top connections 525 to the bridge die. A redistribution layer (RDL) 524 is formed such that connections on the bottom surface of the RDL contact the top connections to the pillars and connections 525 on an interconnect layer 526. Connections 525 may include, for example, contacts to the interconnect layer for connecting the RDL. At 505, solder bumps (eg, C4 microbumps 528) are formed on the top surface connections of the RDL 524 to attach two semiconductor dies (SOCs) 527a and 527b.

[0023] The method proceeds from A in FIG. 5A to A in FIG. 5B. At 506, molding compound 259 is formed around the SOC and planarized (e.g., back-grinded) to form a surface. The SOC may or may not be exposed in various embodiments. At 507, carrier 520 is removed. Carrier 520 may be removed, for example, by mechanical grinding and finished with etching or chemical-mechanical polishing (CMP). Accordingly, as shown at 507, the substrate of the bridge die is removed to expose the underside of the interconnect layer. The pillars are exposed, for example, at the same surface as the connections on the underside of the interconnect layer. Further, at 507, a new carrier 530 is formed above the SoC. At 508, solder bumps are formed on the pillars and their connections coupled to the connections of the SoC via the RDL in areas not overlapping the bridge die interconnect layer. Further, solder bumps are formed on the underside connections to the interconnect layer in the area where they overlap the bridge die interconnect layer and are coupled to the connections of the SoC via the RDL. As described above, in some embodiments, power connections may be coupled to power input connections of the SoC, for example, via connections on the underside of the bridge die interconnect layer in the area where the bridge die and SoC overlap. Further, individual multi-chip ICs may be singulated into individual IC structures. At 509, the multi-chip ICs may be bonded to a circuit substrate. Further examples Each of the following non-limiting features in the following examples may stand alone by itself or may be combined in various permutations or combinations with one or more of the other features in the following examples.

[0024] In one embodiment, the present disclosure includes a semiconductor package comprising: a first semiconductor die including a plurality of connections; a second semiconductor die including a plurality of connections; a redistribution layer including top connections and bottom connections coupled to the first and second semiconductor dies, wherein one or more particular top connections are electrically coupled to one or more particular bottom connections; an interconnect bridge overlapping a portion of the first and second semiconductor dies and including top connections and bottom connections coupled to the bottom connections of the redistribution layer, the interconnect bridge comprising: a first plurality of conductors configured to electrically couple the plurality of connections of the first semiconductor die to the plurality of connections of the second semiconductor die through the redistribution layer; and a second plurality of conductors configured to electrically couple the one or more particular bottom connections of the interconnect bridge to the one or more top connections of the interconnect bridge and to the one or more connections of the first and second semiconductor dies in a region where the interconnect bridge overlaps the first and second semiconductor dies.

[0025] In one embodiment, the interconnect bridge is substrateless. In one embodiment, the interconnect bridge is a metallization layer of a silicon bridge die.

[0026] In one embodiment, the redistribution layer is an organic redistribution layer comprising polyimide. In one embodiment, the redistribution layer is a fabricated redistribution layer comprising silicon dioxide. In one embodiment, the redistribution layer comprises copper conductors.

[0027] In one embodiment, the first plurality of conductors are interface signal conductors and the second plurality of conductors are power conductors. In one embodiment, the second plurality of conductors extend substantially vertically from the first solder bumps on the one or more bottom connections of the interconnect bridge to the one or more bottom connections of the redistribution layer.

[0028] In one embodiment, the plurality of connections of the first and second semiconductor dies are coupled to solder bumps, and the top connections of the redistribution layer are coupled to the connections of the first and second semiconductor dies via the solder bumps.

[0029] In one embodiment, the package further comprises a third plurality of conductors electrically coupled to one or more connections of the first and second semiconductor dies arranged vertically in an area where the interconnect bridge does not overlap the first or second semiconductor dies.

[0030] In one embodiment, the bottom connections of the interconnect bridge are in the same plane as the connections to the third plurality of conductors. In one embodiment, the top and bottom connections of the redistribution layer are at different locations.

[0031] In one embodiment, the package further comprises a circuit substrate comprising a plurality of connections electrically coupled to the bottom connections of the interconnect bridge and a third plurality of connections to the conductors coupled to the connections of the first and second semiconductor dies in areas where the interconnect bridge does not overlap the first or second semiconductor dies.

[0032] In one embodiment, the connections of the circuit board are electrically coupled to the bottom connections of the interconnect bridge and to the connections to the third plurality of conductors via solder bumps. In another embodiment, the present disclosure provides a semiconductor device comprising: a first semiconductor die including a plurality of connections; a second semiconductor die including a plurality of connections; a redistribution layer including top connections and bottom connections coupled to the first and second semiconductor dies via first solder bumps, wherein one or more particular top connections are electrically coupled to one or more particular bottom connections; and an interconnect bridge overlapping a portion of the first and second semiconductor dies and including top connections and bottom connections coupled to the bottom connections of the redistribution layer, electrically coupling the plurality of connections of the first semiconductor die to the plurality of connections of the second semiconductor die via the solder bumps and the redistribution layer. and a second plurality of conductors configured to electrically couple one or more particular bottom connections of the interconnect bridge to one or more top connections of the interconnect bridge and to one or more connections of the first and second semiconductor dies via the first solder bumps in a region where the interconnect bridge overlaps the first and second semiconductor dies; a copper pillar formed outside the region where the interconnect bridge overlaps the first and second semiconductor dies; and a semiconductor package comprising: an interconnect bridge including a first plurality of conductors configured to electrically couple one or more particular bottom connections of the interconnect bridge to one or more top connections of the interconnect bridge and to one or more connections of the first and second semiconductor dies via the first solder bumps.

[0033] In another embodiment, the present disclosure provides a semiconductor device including a first semiconductor die including a plurality of connections; a second semiconductor die including a plurality of connections; a redistribution layer including top connections and bottom connections in contact with the connections to the first and second semiconductor dies, wherein one or more particular top connections are electrically coupled to one or more particular bottom connections; and an interconnect bridge overlapping a portion of the first and second semiconductor dies, the interconnect bridge including the top connections and bottom connections coupled to the bottom connections of the redistribution layer via first solder bumps, electrically connecting the plurality of connections of the first semiconductor die to the plurality of connections of the second semiconductor die via the redistribution layer. and a second plurality of conductors configured to electrically couple one or more particular bottom connections of the interconnect bridge to one or more top connections of the interconnect bridge and to one or more connections of the first and second semiconductor dies in a region where the interconnect bridge overlaps the first and second semiconductor dies; a copper pillar formed outside the region where the interconnect bridge overlaps the first and second semiconductor dies; and a semiconductor package comprising: a copper pillar formed outside the region where the interconnect bridge overlaps the first and second semiconductor dies; and a plurality of second solder bumps connected to the copper pillar and the bottom connections of the interconnect bridge.

[0034] In one embodiment, the first solder bump is a C4 solder microbump. In one embodiment, the package further comprises a circuit board coupled to the plurality of second solder bumps.

[0035] In another embodiment, the present disclosure provides a method for fabricating a semiconductor device, comprising: forming a redistribution layer on a first surface, the redistribution layer including a first redistribution layer surface including a plurality of connections and a second redistribution layer surface including a plurality of connections, wherein one or more particular connections on the first redistribution layer surface are electrically coupled to one or more particular connections on the second redistribution layer surface, and at least a portion of the plurality of connections on the first redistribution layer surface are electrically coupled to a plurality of connections of one of an interconnect bridge or a plurality of semiconductor dies; bonding the plurality of connections of the other of the interconnect bridge or the plurality of semiconductor dies to at least a portion of the plurality of connections on the second redistribution layer surface; and bonding the interconnect layer to at least a portion of the plurality of connections on the second redistribution layer surface. removing a substrate of the interconnect bridge to expose an interconnect layer comprising: a first plurality of conductors configured to electrically couple a plurality of connections of a first semiconductor die of the plurality of semiconductor dies to a plurality of connections of a second semiconductor die of the plurality of semiconductor dies via a redistribution layer; and a second plurality of conductors configured to electrically couple one or more particular connections on a first surface of the interconnect layer to one or more connections on a second exposed surface of the interconnect layer and to one or more connections of the first and second semiconductor dies in an area where the interconnect bridge overlaps the first and second semiconductor dies.

[0036] In one embodiment, the first surface includes an interconnect bridge, and the joining step includes forming solder bumps between a plurality of connections on the first redistribution layer surface and a plurality of connections on the plurality of semiconductor dies.

[0037] In one embodiment, the first surface includes a plurality of semiconductor dies, and the bonding step includes bonding a plurality of connections on the first redistribution layer surface to a plurality of connections on the plurality of semiconductor dies.

[0038] In one embodiment, the method further includes forming a solder bump on the second surface that includes the exposed interconnect layer. In one embodiment, the method further includes joining a plurality of circuit board connections on the first surface of the circuit board to solder bumps on the second surface including the exposed interconnect layer to electrically couple one or more connections on the second surface including the exposed interconnect layer to the plurality of connections of the circuit board.

[0039] In one embodiment, the second surface including the exposed interconnect layer further includes a plurality of connections to a third plurality of conductors electrically coupled to the connections of the first and second semiconductor dies in areas where the interconnect bridge does not overlap the first or second semiconductor dies, and the step of joining the plurality of circuit board connections on the first surface of the circuit board to solder bumps on the second surface including the exposed interconnect layer further includes joining the second plurality of circuit board connections to the third plurality of conductors.

[0040] In one embodiment, the interconnect layer is a metallization layer of a silicon bridge die. In one embodiment, the redistribution layer is an organic redistribution layer comprising polyimide.

[0041] In one embodiment, the redistribution layer is a fabricated redistribution layer comprising silicon dioxide. In one embodiment, the redistribution layer comprises copper conductors. In one embodiment, the first plurality of conductors are interface signal conductors and the second plurality of conductors are power conductors.

[0042] In one embodiment, the second plurality of conductors are power conductors that extend at least partially vertically between a second surface of the interconnect bridge that includes the exposed interconnect layer and one or more portions of the plurality of connections on the second redistribution layer surface.

[0043] In one embodiment, the plurality of connections on the first redistribution layer surface are at a different location along the horizontal axis than the plurality of connections on the second redistribution layer surface. In another embodiment, the present disclosure provides a semiconductor device manufacturing method comprising the steps of: attaching a first semiconductor die and a second semiconductor die to a first carrier; forming a molding compound around the first and second semiconductor dies; grinding the molding compound to form a first surface including a plurality of exposed connections to the first and second semiconductor dies; forming a redistribution layer on the first surface, the redistribution layer including a first redistribution layer surface including a plurality of connections and a second redistribution layer surface including a plurality of connections, wherein one or more particular connections on the first redistribution layer surface are electrically coupled to one or more particular connections on the second redistribution layer surface, and at least a portion of the plurality of connections on the first redistribution layer surface are electrically coupled to the exposed connections of the first and second semiconductor dies; bonding the plurality of connections of an interconnect bridge to at least a portion of the plurality of connections on the second redistribution layer surface; and grinding the molding compound to form a second semiconductor die outside of an overlapping area of ​​the interconnect bridge and the first and second semiconductor dies. forming a molding compound on the interconnect bridge and the copper pillars; removing a substrate of the interconnect bridge to expose the connections to the interconnect layer and to the copper pillars, the interconnect layer comprising: a first plurality of conductors configured to electrically couple a plurality of connections of the first semiconductor die to a plurality of connections of the second semiconductor die through the redistribution layer; and a second plurality of conductors configured to electrically couple one or more particular connections on the first surface of the interconnect layer to one or more exposed connections on the second surface of the interconnect layer and to one or more connections of the first and second semiconductor dies in an area where the interconnect bridge overlaps the first and second semiconductor dies; forming solder bumps on the exposed connections of the interconnect layer and the exposed connections of the pillars; and removing the carrier.

[0044] In one embodiment, the method further includes attaching the solder bumps to a circuit board. In one embodiment, prior to said removal of the substrate of the interconnect bridge, a plurality of copper pillars extend vertically above the interconnect layer of the interconnect bridge.

[0045] In another embodiment, the present disclosure provides a semiconductor device comprising: forming a plurality of copper pillars on a surface of a carrier over a first region; attaching an interconnect bridge to the carrier; forming a molding compound around the interconnect bridge and the pillars; grinding the molding compound to form a first surface including a plurality of exposed connections to the interconnect bridge and the pillars; forming a redistribution layer on the first surface, the redistribution layer including a first redistribution layer surface including a plurality of connections and a second redistribution layer surface including a plurality of connections, one or more particular connections on the first redistribution layer surface being electrically coupled to one or more connections on the second redistribution layer surface, and at least a portion of the plurality of connections on the first redistribution layer surface being electrically coupled to the exposed connections of the interconnect bridge and the pillars; and bonding the plurality of connections of the first and second semiconductor dies to at least a portion of the plurality of connections on the second redistribution layer surface. forming a molding compound over the first and second semiconductor dies; removing a substrate of the interconnect bridge to expose connections to the interconnect layer and to expose connections to the copper pillars, the interconnect layer comprising: a first plurality of conductors configured to electrically couple a plurality of connections of the first semiconductor die to a plurality of connections of the second semiconductor die via a redistribution layer; and a second plurality of conductors configured to electrically couple one or more particular connections on the first surface of the interconnect layer to one or more exposed connections on the second surface of the interconnect layer and to one or more connections of the first and second semiconductor dies in an area where the interconnect bridge overlaps the first and second semiconductor dies; forming solder bumps on the exposed connections of the interconnect layer and the exposed connections of the pillars; and removing the carrier.

[0046] In one embodiment, the method further includes attaching the solder bumps to a circuit board. In one embodiment, prior to said grinding, a plurality of copper pillars extend vertically above the interconnect layer of the interconnect bridge.

[0047] The above description illustrates various embodiments, along with examples of how aspects of some embodiments may be implemented. The above examples and embodiments should not be considered the only embodiments, but are presented to illustrate the flexibility and advantages of some embodiments as defined by the following claims. Based on the above disclosure and the following claims, other configurations, embodiments, implementations, and equivalents may be employed without departing from the scope of the invention as defined by the claims.

Claims

1. a first semiconductor die including a plurality of connections; a second semiconductor die including a plurality of connections; a redistribution layer including top connections and bottom connections coupled to the first and second semiconductor dies, wherein one or more particular top connections are electrically coupled to one or more particular bottom connections; an interconnect bridge overlapping a portion of the first and second semiconductor dies, the interconnect bridge including a top connection coupled to the bottom connection of the redistribution layer and a bottom connection; a first plurality of conductors configured to electrically couple the plurality of connections of the first semiconductor die and the plurality of connections of the second semiconductor die through the redistribution layer; a second plurality of conductors configured to electrically couple one or more particular bottom connections of the interconnect bridge to one or more top connections of the interconnect bridge and to one or more connections of the first and second semiconductor dies in a region where the interconnect bridge overlaps the first and second semiconductor dies; and interconnection bridges including 1. A semiconductor package comprising:

2. 10. The semiconductor package of claim 1, wherein the interconnect bridge is substrateless.

3. 10. The semiconductor package of claim 1, wherein the interconnect bridge is a metallization layer of a silicon bridge die.

4. 2. The semiconductor package according to claim 1, wherein the redistribution layer is an organic redistribution layer containing polyimide.

5. 10. The semiconductor package of claim 1, wherein the redistribution layer is a fabricated redistribution layer comprising silicon dioxide.

6. The semiconductor package of claim 1 , wherein the redistribution layer comprises a copper conductor.

7. 2. The semiconductor package of claim 1, wherein the first plurality of conductors are interface signal conductors and the second plurality of conductors are power conductors.

8. 2. The semiconductor package of claim 1, wherein the second plurality of conductors extend substantially vertically from first solder bumps on one or more bottom connections of the interconnect bridge to one or more bottom connections of the redistribution layer.

9. 2. The semiconductor package of claim 1, wherein the plurality of connection portions of the first and second semiconductor dies are coupled to solder bumps, and the top connection portions of the redistribution layer are coupled to the first and second semiconductor die connection portions via the solder bumps.

10. 10. The semiconductor package of claim 1, further comprising a third plurality of conductors arranged vertically in an area where the interconnect bridge does not overlap the first or second semiconductor die and electrically coupled to one or more connection portions of the first and second semiconductor die.

11. 11. The semiconductor package of claim 10, wherein the bottom connections of the interconnect bridge are in the same plane as connections to the third plurality of conductors.

12. 2. The semiconductor package according to claim 1, wherein the upper connection portion and the lower connection portion of the redistribution layer are located at different positions.

13. 10. The semiconductor package of claim 1, further comprising a circuit board, the circuit board including a plurality of connections electrically coupled to the bottom connection portions of the interconnect bridge, and the connections to the third plurality of conductors coupled to the connection portions of the first and second semiconductor dies in areas where the interconnect bridge does not overlap the first or second semiconductor dies.

14. 14. The semiconductor package of claim 13, wherein the circuit board connection is electrically coupled to the bottom connection of the interconnect bridge and to the connection to the third plurality of conductors via solder bumps.

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