Buried Metal Signal Rails for Memory Arrays

Abstract

The IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. The device also includes a plurality of shunt transistors in the same layer. The device also includes a buried metal signal rail disposed between the array of memory cells and the plurality of shunt transistors in a buried layer buried in the substrate below the transistors. The device also includes a single-layer via in the same layer as the transistors, electrically connecting the memory cell transistors to the shunt transistors through the buried metal signal rail.

Description

[Technical Field]

[0001] The present invention relates to the fields of electrical, electronic, and computer technology, and more particularly to the fabrication of integrated circuit memory devices. [Background technology]

[0002] It is well known that integrated circuit memory devices incorporate arrays of memory cells that are addressed by word and bit lines (metal traces and vias) through which voltages / currents can be applied for writing and reading individual cells. Generally, the bit lines connect from the memory cell transistors (in the front-end layer) up through multi-level metal vias to the back-end layer, and then back down through additional levels of vias to connect to sense amplifiers also formed in the front-end layer. In the operation of conventional IC memory devices, due in part to the layout of the bit lines, significant I 2 R loss and latency occurs. Summary of the Invention

[0003] The principles of the present invention provide techniques for buried metal signal rails for memory arrays.

[0004] In one embodiment, an exemplary integrated circuit memory device comprises a substrate and an array of memory cells disposed on the substrate. Each memory cell has at least one memory cell transistor disposed in a first layer of the device adjacent to a top surface of the substrate. The device also comprises a plurality of shunt transistors, each disposed in the first layer. The device also comprises a buried metal signal rail disposed between the array of memory cells and the plurality of shunt transistors in a buried layer of the device buried in the substrate below the first layer. The device also comprises a first single-layer via disposed in the first layer, electrically connecting one of the memory cell transistors to the buried metal signal rail; and a second single-layer via disposed in the first layer, electrically connecting the buried metal signal rail to one of the plurality of shunt transistors.

[0005] According to another aspect, an exemplary method for fabricating an integrated circuit memory device is provided. The method includes forming a memory cell transistor and a shunt transistor in a first layer of the device, the first layer being adjacent to a substrate at an upper surface of the substrate. The method also includes forming a buried metal signal rail in a buried layer of the device buried in the substrate between the memory cell transistor and the shunt transistor; and forming a bit line connecting the memory cell transistor to the shunt transistor via the buried metal signal rail, whereby the bit line is contained entirely within the first layer and the buried layer.

[0006] According to another aspect, in an integrated circuit memory device, a method includes transmitting a signal from a memory cell transistor disposed in a first layer of the device, the first layer adjacent a top surface of a substrate of the device, through a first single-layer via disposed in the first layer to a buried metal signal rail disposed in a buried layer buried in the substrate of the device.

[0007] In view of the above, the techniques of the present invention can provide substantial beneficial technical effects. For example, one or more embodiments may provide one or more of the following:

[0008] The significant resistance reduction (~50-60%) of both the vias / metal stacks and lines improves read and write operations, thereby enabling larger memory book sizes.

[0009] Two of the four vias in the memory unit cell have been eliminated, resulting in a reduction of ~0.56μm 2 This saves the footprint of a unit cell, allowing for a significant cell reduction.

[0010] The upper metal stack wire level is made available for purposes other than memory access.

[0011] Heterogeneous Integration of Backplane Power Networks: Backplane power networks do not necessarily require heterogeneous integration, but backplane power is expected to offer very attractive benefits for heterogeneously integrated systems.

[0012] Some embodiments may not have these potential advantages, and these potential advantages are not necessarily required for all embodiments. These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 shows a schematic diagram of an integrated circuit memory device according to the prior art;

[0014] [Figure 2] 1 shows a schematic diagram of a memory cell and a shunt transistor connected by a bit line including a multi-layer via according to the prior art;

[0015] [Figure 3] 1 illustrates, in a schematic diagram, an integrated circuit memory device incorporating buried metal routing, according to an exemplary embodiment;

[0016] [Figure 4] 1 illustrates a schematic diagram of a memory cell and a shunt transistor connected by a buried metal signal rail, according to an exemplary embodiment.

[0017] [Figure 5A] 5A-5C are schematic diagrams illustrating steps in a method for fabricating the integrated circuit memory device shown in FIGS. 3 and 4, according to an exemplary embodiment. [Figure 5B] 5A-5C are schematic diagrams illustrating steps in a method for fabricating the integrated circuit memory device shown in FIGS. 3 and 4, according to an exemplary embodiment.

[0018] [Figure 6] The advantages of the exemplary embodiments over the prior art are presented in tabular form. DETAILED DESCRIPTION OF THE INVENTION

[0019] FIG. 1 shows a schematic diagram of a prior art integrated circuit memory device 100. The device 100 includes memory arrays 102, 104 and a sense amplifier array 106. Each of the memory arrays 102, 104 includes a plurality of memory cells 108, and the sense amplifier array 106 includes a plurality of sense amplifiers 110. The columns of the memory arrays 102, 104 are electrically connected to the sense amplifier array 106 by bit lines 112. Word lines 114 are electrically connected to the rows of the memory arrays 102, 104. As will be appreciated by those skilled in the art, each memory cell 108 can be addressed by its combination of word line and bit line. A column driver provides a source voltage VSS or a drain voltage VDD to the memory cell. A signal FEED_BLH is provided through the sense amplifier array 106 to the bit line 112, which provides a signal to both subsections or segments of the overall arrays 102, 104.

[0020] FIG. 2 shows a schematic diagram of a portion of a memory cell 108 and a sense amplifier 110 connected by a bit line 112 including multi-layer vias 202, 204, according to the prior art. The specific metal layers that make up the multi-layer vias, e.g., M1, M2, M3, M4, M5, M6, M7, and M8, are familiar to those skilled in the art and will not be described in further detail. In one or more embodiments, the memory cell 108 and the portion of the sense amplifier 110 each include fin-type field-effect transistors (FinFETs) 206, with the bit line 112 connecting these transistors. In one or more embodiments, the memory cell 108 includes a memory module 208, such as a phase-change memory, a magnetoresistive memory, or a resistive memory.

[0021] In one or more embodiments, the memory 208 is a phase change memory module that includes a bottom electrode 220, a heating element 222, an optional metal level 224, and a phase change material 226 (e.g., a chalcogenide material), with a top electrode designated M4.

[0022] The memory module options are not limited to resistive memory; embodiments of the present invention relate specifically to structures for communication between memory cells 108 and the sense amplifier 110 portion of the sense amplifier, but are equally applicable to static random-access memory (SRAM) or dynamic random-access memory (DRAM). In one or more embodiments, memory cells 108 (as well as multi-layer vias 202, 204) include multi-layer intermediate metal 210.

[0023] 3 illustrates, in schematic form, an integrated circuit memory device 300 incorporating buried metal routing 304, according to an exemplary embodiment. The device 300 includes memory arrays 102, 104 and a sense amplifier array 106. Each of the memory arrays 102, 104 includes a plurality of memory cells 108, and the sense amplifier array 106 includes a plurality of sense amplifiers 110. The columns of the memory arrays 102, 104 are electrically connected to the sense amplifier array 106 by bit lines 302 implemented on the buried metal signal rails 304. Word lines 114 are electrically connected to the rows of the memory arrays 102, 104. As will be appreciated by those skilled in the art, each memory cell 108 can be addressed by its combination of word lines and bit lines.

[0024] Signal rails may be distinguished from power rails in that signal rails are connected to a signal source that provides a time-varying signal, while power rails are connected to a power supply or ground. A signal path connects the source of one device with the gate of another, while power rails are connected to a wide-area power distribution network (or "power grid"), which in turn connects many devices. Note that power rails can carry DC and also have time-dependent currents; for example, if a portion of a logic block is "power-gated," then power is temporarily blocked to that segment of the chip. Thus, power rails can generally carry both DC and time-dependent currents.

[0025] FIG. 4 shows a schematic diagram of a portion of a memory cell 108 and a sense amplifier 110 connected by a bit line 302 including a buried metal signal rail 304 and single-layer vias 402, 404, according to an example embodiment. In one or more embodiments, the vias 402, 404 are formed from the top surface of the chip and typically have a size in the range of 5-25 nm, for example. They may be formed from metals such as Co, Ru, W, Mo, or others capable of withstanding the high thermal budget (up to 1000 K) of device processing. The height of these vias may be in the range of 20-100 nm, for example. In one or more embodiments, the memory cell 108 and a portion of the sense amplifier 110 each include a FinFET (Fin Field Effect Transistor) 206. In one or more embodiments, the memory cell 108 includes a memory module 208, such as a phase-change memory, a magnetoresistive memory, or a resistive memory. The memory module options are not limited to resistive memory. 4 also includes a buried metal power rail 410 electrically connected to one of the transistors 206 in the sense amplifier 110. In one or more embodiments, the buried metal power rail 410 is adjacent to the buried metal signal rail 304.

[0026] 5A and 5B illustrate, in schematic form, selected stages of a method 500 for fabricating the integrated circuit memory device shown in FIGS. 3 and 4. At 502, a starting substrate, e.g., silicon, is obtained. At 504, fins 206 are patterned and an interlayer dielectric (e.g., an oxide such as SiO, not separately labeled) is deposited around them in a manner known to those skilled in the art. At 506, buried metal signal rails 304 and buried metal power rails 410 are formed. Each of the buried rails has a liner and also has a conductive filler (not separately labeled), as is well known to those skilled in the art.

[0027] The fabrication of semiconductor devices involves various stages of a device patterning process. For example, the fabrication of a semiconductor chip may begin with multiple device patterns, generated, for example, by computer-aided design (CAD), followed by replicating these device patterns in a substrate. The replication process may involve the use of various exposure techniques and various subtractive (etching) and / or additive (deposition) material processing procedures.

[0028] As an exemplary subtractive process, in a photolithography process, a layer of photoresist material may first be applied onto a substrate and then selectively exposed according to one or more predetermined device patterns. Portions of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beam, X-rays, etc.) may undergo some change in their solubility in a particular solution. The photoresist may then be developed in a developer solution, thereby removing the non-irradiated portions (in negative resist) or the irradiated portions (in positive resist) of the resist layer to create a photoresist pattern or photomask. The photoresist pattern or photomask may then be copied or transferred to the substrate below the photoresist pattern.

[0029] Various structures described herein, such as source / drain structures, may be epitaxially grown. As used herein, "epitaxy" or "epitaxial growth" refers to a process in which a layer of single-crystal or large-grained polycrystalline material is formed on an existing material with similar crystalline properties. One characteristic of epitaxy is that the process reproduces the crystalline structure of the existing substrate or seed layer (including any defects therein) in the epitaxially grown material. Epitaxial growth can include heteroepitaxy (i.e., growing a material having a different composition than the underlying layer) or homoepitaxy (i.e., growing a material having the same composition as the underlying layer). Heteroepitaxy can introduce strain into the epitaxially grown material, as its crystalline structure may bend to match that of the underlying layer. In certain applications, such strain may be desirable. In an epitaxial deposition process, chemical reactants provided by source gases are controlled and system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with enough energy to move around the surface and orient themselves to match the crystalline arrangement of atoms at the deposition surface. Thus, the epitaxial semiconductor material may have the same crystalline properties as the deposition surface on which it is formed. For example, epitaxial semiconductor material deposited on a {100} crystalline surface may be {100} oriented. In some embodiments, the epitaxial growth and / or deposition process may be selective for formation on semiconductor surfaces and may not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0030] A number of different precursors may be used for the epitaxial deposition of in-situ doped semiconductor materials. In some embodiments, a gas source for depositing the epitaxially formed in-situ doped semiconductor material may include silicon (Si) deposited from silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, disilane, and combinations thereof. In another example, when the in-situ doped semiconductor material includes germanium, the germanium gas source may be selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Examples of other epitaxial growth processes that can be used to grow the semiconductor layers described herein include rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE).

[0031] "In situ" means that the dopant that determines the conductivity type of the doped layer is introduced during the process step that forms the doped layer, e.g., epitaxial deposition. The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), where the growing semiconductor material (crystal on layer) has substantially the same crystalline properties as the semiconductor material on the deposition surface (seed material). In an epitaxial deposition process, chemical reactants provided by source gases are controlled and system parameters are set so that the depositing atoms arrive at the deposition surface of a semiconductor substrate with sufficient energy to move around the surface, thereby orienting themselves to the crystalline arrangement of the atoms on the deposition surface. Thus, the epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed.

[0032] At 508, front-end and middle-of-line processes are completed. The front-end processes form transistors, diodes, or other active elements, while the middle-of-line processes form conductive traces and vias that interconnect the active elements. The elements added at stage 508 include transistor devices (including source, drain, channel, gate, etc.) and "middle-of-line" electrical connections between the transistors and the interconnects in the back-end of the line (BEOL). These connections include gate connections and source / drain connections. These electrical connections can be buried in an oxide material (such as SiO2 or the like) and can include a dielectric cap (SiN, as an example) thereon. At 510, front-end processes are completed for the back-end layers (BEOL). Stage 510 includes the formation of all BEOL metal levels. To form a single metal level, a low-k dielectric is deposited and then etched to form openings. These openings are filled with metal (e.g., Cu), followed by chemical-mechanical polishing (CMP) to remove excess metal. The whole is then capped with a dielectric cap material (e.g., SiN). This process is repeated to form each subsequent metal level on top of the previous metal level. The chip can have, for example, 10-20 metal levels in total, with increasing dimensions from the bottom to the top metal level. At 512, the front side of the wafer is coated in preparation for backside processing. In one or more embodiments, the wafer may be coated with a thick oxide or nitride-based material to protect the front side of the wafer during subsequent processing. At 514, the wafer is flipped over.

[0033] At 516, the wafer is thinned. Those skilled in the art utilize a variety of techniques for removing material at various stages in fabricating semiconductor structures. As used herein, these processes are collectively referred to as "etching." For example, etching includes wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE) techniques, all of which are well-known techniques for removing selected materials when forming semiconductor structures. Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid and hydrogen peroxide. The techniques and applications of etching are well understood by those skilled in the art, and therefore, a more detailed description of such processes will not be presented herein.

[0034] Another mode of material removal is chemical mechanical planarization (CMP), which may be utilized to thin the wafer in step 516 in one or more embodiments.

[0035] At 518, nano-silicon through-vias (TSVs) 519 are formed to the buried metal power rails 410. To form the nano-TSVs, an etch and fill process, such as a "Bosch etch," may be used to form openings that are then filled with a metal such as copper. At 520, a backside metal process is completed that connects the buried metal power rails 410 with backside power rails 521. Step 520 may be performed similarly to step 510, for example, except that it is now performed on the backside of the wafer rather than the frontside. The same steps described above (dielectric deposition, etch, metal fill, CMP, dielectric cap) may be used to form several levels of interconnect wiring.

[0036] The steps shown in FIG. 5 are not necessarily the only steps in method 500, and method 500 may include additional detailed and intermediate steps that would be understood by one of ordinary skill in the art in view of this disclosure.

[0037] 6 shows in tabular form the advantages of exemplary embodiments over the prior art. Notably, selected embodiments of the inventive structure reduce bit line resistance by 53% to 62% over the prior art. These percentage improvements may not be present in all embodiments.

[0038] Given the foregoing discussion, it will be understood that, in general, an exemplary integrated circuit memory device includes a substrate (Si in FIG. 4 ); an array of memory cells (e.g., 108) disposed in the substrate, with each memory cell including at least one memory cell transistor 206 disposed in a first layer of the device adjacent the top surface of the substrate. This first layer is typically formed by front-end (FEOL) processing, e.g., in steps 504 and 508 of FIG. 5A . The device also includes a plurality of shunt transistors, e.g., 110, each disposed in the first layer. The device also includes a buried metal signal rail 304 disposed between the array of memory cells and the plurality of shunt transistors in a buried layer of the device buried in the substrate below the first layer. The device also includes a first single-layer via 402 disposed in the first layer, electrically connecting one of the memory cell transistors to the buried metal signal rail; and a second single-layer via 404 disposed in the first layer, electrically connecting the buried metal signal rail to one of the plurality of shunt transistors.

[0039] In one or more embodiments, at least one of the memory cells includes a resistive memory element disposed in a second layer of the device adjacent to the top surface of the first layer, i.e., the top surface of the first layer opposite the substrate. In one or more embodiments, this second layer may be formed as part of a middle-of-line (MOL) process, i.e., step 508 of FIG. 5A.

[0040] In one or more embodiments, at least one of the memory cell transistors is a fin field effect transistor (FinFET). In one or more embodiments, at least one of the shunt transistors is a fin field effect transistor (FinFET).

[0041] In one or more embodiments, the device also includes a second array of memory cells (e.g., 102 and 104 in FIG. 3) and a second buried metal signal rail (e.g., BL0 and BL1 in FIG. 3), and the plurality of shunt transistors, the buried metal signal rail, and the second buried metal signal rail form a bit line bus interconnecting the array of memory cells and the second array of memory cells.

[0042] In one or more embodiments, the device also includes a buried metal power rail 410 that is adjacent to the buried metal signal rail in the buried layer and adjacent to one of the multiple shunt transistors in the first layer.

[0043] In one or more embodiments, the device also includes a backside via 521 that is electrically connected to a buried metal power rail and extends from the buried layer to the bottom surface of the substrate, where the bottom surface of the substrate is on the side opposite the first layer.

[0044] According to another aspect, an exemplary method 500 is provided for fabricating an integrated circuit memory device. The method includes forming memory cell transistors and shunt transistors in a first layer of the device, at 504 and 508, where the first layer is adjacent to a substrate at an upper surface of the substrate. The method also includes forming a buried metal signal rail in a buried layer of the device buried in the substrate between the memory cell transistors and the shunt transistor, at 506; and forming a bit line connecting the memory cell transistor to the shunt transistor via the buried metal signal rail, whereby the bit line is contained entirely within the first layer and the buried layer.

[0045] In one or more embodiments, forming the bit line includes forming a first single-layer via that electrically connects the memory cell transistor to the buried metal signal rail; and forming a second single-layer via from the buried metal signal rail to the shunt transistor.

[0046] Some embodiments of the method also include, at 506, forming a buried metal power rail adjacent to the buried metal signal rail and adjacent to the shunt transistor.

[0047] One or more embodiments also include, at 518, forming a backside via that is electrically connected to the buried metal power rail.

[0048] In one or more embodiments, forming at least one of the memory cell transistors comprises forming a FinFET. In one or more embodiments, forming at least one of the shunt transistors comprises forming a FinFET.

[0049] According to another aspect, in an integrated circuit memory device, a method includes: The method includes transmitting a signal from a memory cell transistor disposed in a first layer of the device, where the first layer is adjacent to a top surface of a substrate of the device, through a first single-layer via disposed in the first layer to a buried metal signal rail disposed in a buried layer buried in the substrate of the device. In one or more embodiments, the method also includes transmitting the signal from the buried metal signal rail through a second single-layer via to a shunt transistor of the sense amplifier, where the shunt transistor is also disposed in the first layer.

[0050] While the overall fabrication method and structures formed thereby are novel, certain individual processing steps required to implement the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tools. These techniques and tools will be familiar to those skilled in the relevant art, given the teachings herein. Furthermore, one or more of the processing steps and tools used to fabricate semiconductor devices are also described in numerous readily available publications, including, for example, James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001, and PH Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, both of which are incorporated herein by reference. While several individual processing steps are described herein, it is emphasized that these steps are merely exemplary and that several equally suitable alternatives may be familiar to those skilled in the art where applicable.

[0051] It should be understood that the various layers and / or regions illustrated in the accompanying figures are not necessarily drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for ease of illustration. This does not imply that the semiconductor layers not explicitly shown are omitted in the actual integrated circuit device.

[0052] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles, practical applications, or technical improvements of the embodiments over art found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. An integrated circuit memory device comprising: substrate; an array of memory cells disposed on the substrate, each memory cell having at least one memory cell transistor disposed in a first layer of the integrated circuit memory device adjacent a top surface of the substrate; a plurality of shunt transistors each disposed on the first layer; a buried metal signal rail disposed between the array of memory cells and the plurality of shunt transistors in a buried layer of the integrated circuit memory device buried in the substrate below the first layer; a first single-layer via disposed in the first layer, electrically connecting one of the memory cell transistors to the buried metal signal rail; and a second single-layer via disposed in the first layer, electrically connecting the buried metal signal rail to one of the plurality of shunt transistors; 1. An integrated circuit memory device comprising:

2. 2. The integrated circuit memory device of claim 1, wherein at least one of the memory cells has a resistive memory element disposed in a second layer of the integrated circuit memory device adjacent to a top surface of the first layer, the top surface of the first layer being on the opposite side from the substrate.

3. 10. The integrated circuit memory device of claim 1, wherein at least one of the memory cell transistors is a fin field effect transistor (FinFET).

4. 10. The integrated circuit memory device of claim 1, wherein at least one of the plurality of shunt transistors is a fin field effect transistor (FinFET).

5. 10. The integrated circuit memory device of claim 1, further comprising a second array of memory cells and a second buried metal signal rail, wherein said plurality of shunt transistors, said buried metal signal rail, and said second buried metal signal rail comprise a bit line bus interconnecting said array of memory cells with said second array of memory cells.

6. 2. The integrated circuit memory device of claim 1 further comprising a buried metal power rail adjacent to said buried metal signal rail in said buried layer and adjacent to one of said plurality of shunt transistors in said first layer.

7. 7. The integrated circuit memory device of claim 6, further comprising a backside via electrically connected to the buried metal power rail and extending from the buried layer to a bottom surface of the substrate, wherein the bottom surface of the substrate is on the opposite side from the first layer.

8. 1. A method for fabricating an integrated circuit memory device, comprising: forming a memory cell transistor and a shunt transistor in a first layer of the integrated circuit memory device, the first layer being adjacent to the substrate at a top surface of the substrate; forming a buried metal signal rail in a buried layer of the integrated circuit memory device buried in the substrate between the memory cell transistor and the shunt transistor; and forming a bit line connecting said memory cell transistor to said shunt transistor through said buried metal signal rail, said bit line being entirely contained within said first layer and said buried layer; A method for providing the above.

9. forming the bit lines forming a first single-level via electrically connecting the memory cell transistor to the buried metal signal rail; and forming a second single layer via from the buried metal signal rail to the shunt transistor; 9. The method of claim 8, comprising:

10. forming a buried metal power rail adjacent to said buried metal signal rail and adjacent to said shunt transistor; The method of claim 8 further comprising:

11. forming a backside via electrically connected to the buried metal power rail; The method of claim 10 further comprising:

12. 9. The method of claim 8, wherein forming at least one of the memory cell transistors comprises forming a FinFET.

13. The method of claim 8 , wherein forming at least one of the shunt transistors comprises forming a FinFET.

14. In an integrated circuit memory device, transmitting a signal from a memory cell transistor disposed in a first layer of the integrated circuit memory device, the first layer being adjacent to a top surface of a substrate of the integrated circuit memory device, through a first single-layer via disposed in the first layer to a buried metal signal rail disposed in a buried layer buried in the substrate of the integrated circuit memory device. A method for providing the above.

15. 15. The method of claim 14, further comprising transmitting the signal from the buried metal signal rail through a second single-layer via to a shunt transistor of a sense amplifier, wherein the shunt transistor is also located in the first layer.

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