Ferroelectric memory device erasure

Abstract

A non-volatile memory (NVM) structure is provided that includes a proximity or local heater configured to generate Joule heating to increase the temperature of a ferroelectric material layer of a ferroelectric memory device above the Curie temperature of the ferroelectric material layer, the Joule heating being triggered when tampering in the NVM structure is detected, and the Joule heating can result in memory erasure.

Description

[Background technology]

[0001] This application relates to ferroelectric memory devices, and more particularly to erasing memory from ferroelectric memory devices using heaters.

[0002] Ferroelectric memory devices are considered a promising technology for electronic memory storage. In ferroelectric memory devices, information is based on polarization in a ferroelectric layer that can be switched based on an electric field and becomes non-ferroelectric when the temperature of the ferroelectric layer is raised above the Curie temperature. Ferroelectric memory devices are a non-volatile type of memory, and therefore, stored data can be stolen by unauthorized physical access to the memory. Such unauthorized access can compromise the security of the data by extracting encryption keys from the memory. Summary of the Invention

[0003] A non-volatile memory (NVM) structure is provided that includes a proximity or local heater configured to generate Joule heating to increase the temperature of a ferroelectric material layer of a ferroelectric memory device above the Curie temperature of the ferroelectric material layer, the Joule heating being triggered when tampering in the NVM structure is detected, and the Joule heating can result in memory erasure.

[0004] In one aspect of the present application, an NVM structure is provided that includes a proximity heater. In one embodiment, the NVM structure includes at least one ferroelectric memory device including a ferroelectric material layer and a proximity heater disposed adjacent to the at least one ferroelectric memory device. When triggered, the proximity heater is configured to generate Joule heating and increase the temperature of the ferroelectric material layer above the Curie temperature of the ferroelectric material layer.

[0005] In some embodiments of the present application, the proximity heater is spaced from at least one ferroelectric memory device and is embedded in a thermally conductive and electrically insulating dielectric material layer, examples of which include AlN, BN, or diamond-like carbon.

[0006] In some embodiments of the present application, at least one ferroelectric memory device is a ferroelectric field effect transistor (FeFET) including a source region, a drain region, and a gate electrode, in such embodiments, the gate electrode of the FeFET is disposed on top of the ferroelectric material layer.

[0007] In some embodiments of the present application, at least one ferroelectric memory device is a one-transistor, one-capacitor ferroelectric random access memory (1T1C FeRAM). In such embodiments, a ferroelectric material layer of the 1T1C FeRAM is located between a bottom electrode and a top electrode.

[0008] In some embodiments of the present application, at least one ferroelectric memory device is a ferroelectric tunnel junction (FeTJ) device. In such embodiments, a ferroelectric material layer of the FeTJ device is disposed between a first metal layer and a second metal layer. In such embodiments, a first junction formed between the first metal layer and the ferroelectric material layer has a higher energy barrier height than a second junction formed between the second metal layer and the ferroelectric material layer. In yet other embodiments, the first junction formed between the first metal layer and the ferroelectric material layer has a lower energy barrier height than a second junction formed between the second metal layer and the ferroelectric material layer.

[0009] In some embodiments of the present application, the proximity heater is disposed between the upper and lower electrodes.

[0010] In some embodiments of the present application, the proximity heater is spaced from the at least one ferroelectric memory device by a distance of 1 nm to 40 nm, which distance is sufficient to facilitate Joule heating of the ferroelectric material layer when an event triggers the need for such necessary Joule heating.

[0011] In some embodiments of the present application, the at least one ferroelectric memory device includes a plurality of ferroelectric memory devices (i.e., FeFET, IT1C FeRAM, or FeTJ), and each ferroelectric memory device of the plurality of ferroelectric memory devices includes a ferroelectric material layer. In such embodiments, a proximity heater is disposed between each of the ferroelectric memory devices.

[0012] In some embodiments of the present application, the proximity heater is connected to a processor, where the processor notifies the proximity heater to activate when a trigger event occurs. When activated, the proximity heater causes sufficient Joule heating of the ferroelectric material layer so that memory erasure can occur. The processor may include a notification unit or a tamper detection unit.

[0013] In another embodiment, an NVM structure includes a key storage region including at least one first ferroelectric field effect transistor (FeFET), the at least one first FeFET including a source region, a drain region, a ferroelectric material layer, and a local heater, where the local heater in the key storage region is disposed on top of the ferroelectric material layer. The NVM structure of this embodiment also includes a memory region disposed adjacent to the key storage region, the memory region including at least one second FeFET, the at least one second FeFET including a source region, a drain region, a ferroelectric material layer, a U-shaped local heater, and a gate electrode, where the U-shaped local heater in the memory region is disposed on top of the ferroelectric material layer and is present along sidewalls and a bottom wall of the gate electrode of the at least one second FeFET.

[0014] In some embodiments of the present application, there is an inter-layer dielectric (ILD) material layer that separates the key storage area and the memory area from each other.

[0015] In some embodiments of the present application, the U-shaped local heater has a top surface that is coplanar with the top surface of the gate electrode present in the memory region.

[0016] In some embodiments of the present application, a local heater in the key storage region is configured to generate Joule heating and increase the temperature of the ferroelectric material layer of the at least one first FeFET above the Curie temperature of the ferroelectric material layer of the at least one first FeFET such that at least the secret cryptographic key is erased. In some embodiments, erasure of the secret cryptographic key is sufficient and no data erasure is required in the memory region.

[0017] In some embodiments of the present application, the local heater in the memory region is also configured to generate Joule heating and increase the temperature of the ferroelectric material layer of the at least one second FeFET above the Curie temperature of the ferroelectric material layer of the at least one second FeFET so that data is erased in the memory region. This embodiment, which includes erasing data in the memory region, adds further security protection to the overall system.

[0018] In some embodiments of the present application, the NVM structure further comprises a first spacer and a second spacer present in the key storage area, wherein the second spacer is disposed along a sidewall of the local heater of the at least one first FeFET and generally on top of the ferroelectric material layer of the at least one first FeFET, and the first spacer is disposed along a sidewall of the second spacer and along a sidewall of the ferroelectric material layer of the at least one first FeFET.

[0019] In some embodiments of the present application, the NVM structure further comprises spacers in the memory region, wherein the spacers in the memory region are present along sidewalls of the U-shaped local heater of the at least one second FeFET and along sidewalls of the ferroelectric material layer of the at least one second FeFET.

[0020] In some embodiments of the present application, the local heater of at least one first FeFET is connected to a processor, where the processor notifies the local heater of the at least one first FeFET to activate when a trigger event occurs. In some embodiments, the U-shaped local heater of at least one second FeFET is also connected to the processor, such that the U-shaped local heater activates when the processor notifies the U-shaped local heater that a trigger event has occurred. This embodiment adds additional security and need not be used in all cases. Thus, in some embodiments of the present application, the local heater of the at least one second FeFET is not connected to the processor, so that data is maintained in its domain. The processor may include a notification unit or a tamper detection unit. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a cross-sectional view of a first exemplary NVM structure according to an embodiment of the present application, the first exemplary NVM structure including a ferroelectric memory device region including an FeFET and a heater located in the ferroelectric memory device region and adjacent to the FeFET.

[0022] [Figure 2] FIG. 2 is a cross-sectional view of an alternative ferroelectric memory device that can replace the FeFET shown in FIG. 1 . In this embodiment, the alternative ferroelectric memory device is a one-transistor, one-capacitor ferroelectric random access memory (1T1C FeRAM), which is intended to be used in FIG. 1 in place of the FeFET.

[0023] [Figure 3] FIG. 2 is a cross-sectional view of yet another alternative ferroelectric memory device that can replace the FeFET shown in FIG. 1; in this embodiment, the alternative ferroelectric memory device is a ferroelectric tunnel junction device, which is intended to be used in FIG. 1 in place of the FeFET.

[0024] [Figure 4] FIG. 1 is a cross-sectional view of a second exemplary NVM structure according to another embodiment of the present application, the second exemplary structure including a key storage region and an adjacent memory region, both regions including FeFETs with built-in (i.e., localized) heaters.

[0025] [Figure 5A] FIG. 5 is a top view of the exemplary NVM structure shown in FIG. 4, illustrating that the local heater in the key memory region is surrounded by a second spacer.

[0026] [Figure 5B] FIG. 5 is a top view of the exemplary NVM structure shown in FIG. 4, illustrating that the local heater in the memory region surrounds the gate electrode.

[0027] [Figure 6] 5 is a diagram illustrating a memory erasure system for use with the second exemplary structure as shown in FIG. 4. DETAILED DESCRIPTION OF THE INVENTION

[0028] The present application will now be described in more detail by reference to the following discussion and the drawings that accompany this application. It should be noted that the drawings herein are provided for illustrative purposes only, and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0029] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, it will be understood by those skilled in the art that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0030] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that the element can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it will be understood that the element can be directly below or directly underneath the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0031] Referring first to FIG. 1 , a first exemplary NVM structure according to an embodiment of the present application is illustrated, and the first exemplary NVM structure includes a ferroelectric memory device region 100 including a FeFET as a ferroelectric memory device, and a heater 26 disposed proximate to the ferroelectric memory device present in the ferroelectric memory device region 100. In this embodiment, the heater 26 may be referred to as a proximity heater because it is disposed adjacent to the ferroelectric memory device region 100. As an example, two ferroelectric memory device regions 100 each including a ferroelectric memory device (e.g., the FeFET illustrated in FIG. 1 ) are described and illustrated. Although two ferroelectric memory device regions 100 are described and illustrated, the present application contemplates a structure having a single ferroelectric memory device region 100 or having more than two ferroelectric memory device regions 100. Each ferroelectric memory device region 100 includes a ferroelectric memory device.

[0032] In FIG. 1 , the ferroelectric memory device is a FeFET that includes a source region (e.g., one of the source / drain regions 14 depicted in the leftmost FeFET shown in FIG. 1 ), a drain region (e.g., another source / drain region 14 depicted in the leftmost FeFET shown in FIG. 1 ), a ferroelectric material layer 16, and a gate electrode 18. In some embodiments, a thin interfacial layer (IL) may be included between the ferroelectric material layer 16 and the top surface of the FET's channel, which is disposed in the semiconductor material layer 12. In a silicon-based FET, the IL may be composed of silicon dioxide (SiO 2 ). In FIG. 1 , the gate electrode 18 is disposed on top of the ferroelectric material layer 16. Within the ferroelectric memory device region 100, source / drain contact structures 22 are present on the source / drain regions 14, and spacers 20 are present along the sidewalls of both the gate electrode 18 and the ferroelectric material layer 16. In this embodiment, spacers 20 are also disposed on the source / drain regions 14 and are between the source / drain contact structures 22 and the material stack consisting of the gate electrode 18 and the ferroelectric material layer 16. As shown in Figure 1, the source / drain regions 14 are disposed in a semiconductor material layer 12 disposed on a substrate 10. The semiconductor material layer 12 includes the FeFET's channel, which extends from one of the FeFET's source / drain regions 14 to the other of the FeFET's source / drain regions 14, with the channel region being disposed below each ferroelectric material layer 16 shown in Figure 1.

[0033] In some embodiments, substrate 10 may comprise a semiconductor material having semiconducting properties. Examples of semiconductor materials that may be used to provide substrate 10 include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloy, silicon germanium carbide (SiGeC) alloy, germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors. In some embodiments (not shown), substrate 10 is a semiconductor-on-insulator (SOI) substrate that includes a buried dielectric material layer, such as a buried silicon oxide layer and / or a buried boron nitride layer, that separates a first semiconductor substrate material layer from a second semiconductor substrate material layer. In other embodiments, substrate 10 is a bulk semiconductor substrate composed entirely of at least one of the semiconductor materials mentioned above. In other embodiments, substrate 10 may be composed of a material that provides mechanical support and / or thermal conduction for active device layers (including ferroelectric memory and interconnects). Examples of such materials include, but are not limited to, glass, sapphire (Al2O3), or mica.

[0034] The semiconductor material layer 12, which includes the channel region, may be composed of one of the semiconductor materials mentioned above for the substrate 10. In some embodiments, the semiconductor material layer 12 represents the processed top semiconductor material layer of the substrate 10.

[0035] Each source / drain region 14 is composed of a semiconductor material and a dopant. As used herein, a "source / drain or S / D" region can be either a source region or a drain region, depending on subsequent wiring and the application of voltages during operation of the ferroelectric memory device. As is known, a source / drain region 14 is disposed on each side of a gate structure including a ferroelectric material layer 14 and a gate electrode 18. The semiconductor material providing the source / drain regions 14 can include one of the semiconductor materials mentioned above for the substrate 10. The semiconductor material providing the source / drain regions 14 can be compositionally identical to or compositionally different from the semiconductor material providing the semiconductor material layer 12. The dopant present in the source / drain regions 14 can be either a p-type dopant or an n-type dopant. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a valence electron defect. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. "N-type" refers to the addition of impurities that provide free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, or impurities, include, but are not limited to, antimony, arsenic, and phosphorus. In one example, the source / drain regions 14 are 4×10 20 atoms / cm 3 ~3×10 21 atoms / cm 3 The source / drain regions 14 may have a dopant concentration of 0.015 to 0.015. The source / drain regions 14 may be formed by introducing dopants into the semiconductor material layer 12 by ion implantation, or alternatively, by first forming source / drain trenches in the semiconductor material layer 12 and then filling the source / drain trenches with semiconductor material. Filling the source / drain trenches involves an epitaxial growth process in which dopants may or may not be present during the epitaxial growth. When dopants are not present during the epitaxial growth process, dopants may be added to the epitaxially grown semiconductor material by ion implantation or any other suitable dopant introduction technique.

[0036] The ferroelectric material layer 16 is composed of a material exhibiting ferroelectricity (i.e., a ferroelectric material). Ferroelectricity is the ability of a material to have spontaneous electric polarization. This polarization can be reversed by the application of an external electric field in the opposite direction. All ferroelectric materials exhibit the piezoelectric effect. An example of a ferroelectric material that can be employed as the ferroelectric material layer 16 is Hf (x) Zr (1-x) O2, (HZO), where 0 < x < 1. In one example, the HZO ferroelectric material used is Hf 0.5 Zr 0.5 O2 composition. Other examples of ferroelectric materials that can be employed as the ferroelectric material layer 16 are BaTaO2, Ba2Bi4Ti5O 15 , Pb2Bi4Ti5O 15 , BaBi4Ti4O 15 , SrBi2Ta2O3, BaTiO3, PbZrO3, PbTiO3, Bi 1-x Nd x Ti3O 12 , Bi4Ti3O 12 or Bi 1-x La x Ti3O 12 including, but not limited to, these. The ferroelectric material layer 16 is formed by the deposition of a layer of the ferroelectric material. The deposition includes, but is not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or sputtering. The ferroelectric material layer 16 typically has a thickness of 1 nm to 20 nm; however, other thicknesses are envisioned and can be used as the thickness of the ferroelectric material layer 16.

[0037] The gate electrode 18 is made of tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (Al), lead (Pb), platinum (Pt), tin (Sn), silver (Ag), or gold (Au), tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC XThe ferroelectric material may comprise a conductive metal-containing material, including, but not limited to, titanium carbide (TiC), titanium aluminum carbide, tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO), cobalt silicide, or nickel silicide. In some embodiments, a work function metal (WFM) layer may be employed as the conductive metal-containing material providing the gate electrode or as an isolation layer disposed between the ferroelectric material layer and the gate electrode. The WFM layer may be used to set the threshold voltage of the FeFET to a desired value. In some embodiments, the WFM layer may be selected to produce an n-type threshold voltage shift. "N-type threshold voltage shift," as used herein, refers to a shift in the effective work function of the work function metal-containing material toward the conduction band of silicon in the silicon-containing material. In one embodiment, the work function of the n-type work function metal is in the range of 4.1 eV to 4.3 eV. Examples of such materials that can produce an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM layer can be selected to produce a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9 eV to 5.2 eV. As used herein, "threshold voltage" refers to the lowest achievable gate voltage that activates a semiconductor device, e.g., a transistor, by making the device's channel conductive. The term "p-type threshold voltage shift," as used herein, refers to a shift in the effective work function of a work function metal-containing material toward the valence band of silicon in the silicon-containing material. Examples of such materials that can produce a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof.

[0038] The spacers 20 include any dielectric spacer material such as silicon oxide, silicon nitride, SiBCN, SiOCN, or SiOC, etc. The spacers 20 may be formed by deposition followed by a spacer etch.

[0039] The source / drain contact structures 22 are composed of at least one contact conductor material, such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof. The contact conductor material may be formed by any suitable deposition method, such as CVD, PVD, atomic layer deposition (ALD), or plating. The source / drain contact structures 22 may include one or more contact liners (not shown) formed along the sidewalls of the contact openings used in forming the source / drain contact structures 22. In one or more embodiments, the contact liners (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. In one or more embodiments in which a contact liner is present, the contact liner (not shown) may include a silicide liner, such as Ti, Ni, NiPt, or the like, and a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. In any embodiment, the contact liner may be formed using a conformal deposition process, including PVD, CVD, or ALD. The formed contact liner may have a thickness ranging from 1 nm to 8 nm, although lesser and greater thicknesses may also be employed.

[0040] The proximity heater 26 is composed of any resistive material, such as TiN, TaN, carbon, hydrogen-doped carbon, or a combination thereof, such as a TiN / TaN / TiN stack. The resistive material providing the proximity heater 26 may be formed by a deposition process, such as CVD, PECVD, ALD, PVD, sputtering, or plating. In the present application, the proximity heater 26 may be located to the left and right of the ferroelectric memory device region 100, as shown in FIG. 1 , and may be located in and out of the plane of the drawing paper containing FIG. 1 . The proximity heater 26 is spaced from the ferroelectric memory device within the ferroelectric device region 100 by a distance of 1 nm to 40 nm (in some embodiments, a distance of 1 nm to 10 nm is more typical). The distance provided herein is sufficient to promote Joule heating of the ferroelectric material layer 16 when an event triggers the need for such Joule heating. Joule heating is employed to increase the temperature of the ferroelectric material layer 16 above the Curie temperature of the ferroelectric material layer. Above the Curie temperature, the ferroelectric memory layer 16 loses its memory capability, thus providing a means for erasing the memory of the ferroelectric memory device. Not all ferroelectric memory devices in a series (or plurality) of ferroelectric memory devices need to have their data erased. Instead, only those ferroelectric memory devices for which a trigger event is detected may have their data erased. As explained below, the dielectric material layer 24 may be selected to be a good thermal conductor (while also being a good electrical insulator). Due to good thermal coupling, such a material allows for more efficient heating, even when the distance between the proximity heater 26 and the ferroelectric material layer 16 is greater.

[0041] A trigger event may be used to activate a memory wipe. A trigger event may be any occurrence that results in the activation of a particular protocol. As used herein, a trigger event refers to a threshold that may be met to activate a memory wipe. A trigger event may include, for example, reaching the end of a subscription (e.g., the threshold is a date), receiving a manual command to delete (e.g., the threshold is a set input value), identifying a tamper attempt (e.g., the threshold is recognition of attempted unauthorized access), or other similar occurrences. An expiration trigger may be tied to an external system (e.g., a remote subscription calendar), an internal system (e.g., a date and / or time entered into a calendar on a local device), or some combination thereof. A tamper attempt may be identified by multiple means, including, for example, removing a memory module from a rack without providing the proper access code, attempting to bypass a device enclosure, or other recognition of unauthorized tampering with a device.

[0042] Tampering may involve reverse engineering the contents of memory selections, such as reverse engineering the contents of a cryptographic key. Many physical reverse engineering techniques require access to the chip structure through imaging (e.g., electron beam from scanning electron microscopy, focused ion beam, x-ray, etc.), thus generating radiation (e.g., photocurrent, laser beam induced current, electron beam induced current, etc.). Some embodiments of the present application may utilize this principle, using solar cells to convert radiation from a tamper attempt into a current that triggers a tamper response (e.g., to power a heater) to erase data.

[0043] Tampering may involve unauthorized physical access (e.g., removing a computer board from a computer without authorization or opening a box containing a computer chip). Tampering may include unauthorized access of a secure room. In some embodiments, sensors may be used to detect intrusion; such sensors may include, for example, sensors for light, temperature, humidity, pressure, similar detectors, or some combination thereof.

[0044] Tampering can include inducing disturbances (e.g., inversions) to cause devices to perform unauthorized operations through electrical probing and delayering to extract secret keys. Attempts to tamper typically deploy a wide range of techniques to discover specific circuits and structures; these techniques usually involve imaging or radiation to induce electrical currents and disturbances. Some embodiments of the present application can also redirect energy from radiation or current to activate anti-tamper devices and erase target memories and / or memory containing cryptographic keys for the target memories. For example, solar cells can automatically capture and redirect energy from a tamper attempt to power the operation of proximity heater 26.

[0045] 1, the proximity heater 26 is spaced from at least one ferroelectric memory device within the ferroelectric memory device region 100 and is embedded in a thermally conductive and electrically insulating dielectric material layer 24. Examples of such materials that may be used as the dielectric material layer 24 include, but are not limited to, aluminum nitride (AlN), boron nitride (BN), or diamond-like carbon. The dielectric material layer 24 may be formed by a deposition process including, for example, CVD, PECVD, or ALD.

[0046] As illustrated in FIG. 1 , the proximity heater 26 is positioned between a bottom electrode 28 and a top electrode 29. The bottom electrode 28 and the top electrode 29 are composed of any electrode material, such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, Cu, W, WN, or any combination thereof. The electrode materials providing the bottom and top electrodes 28, 29 can be deposited by CVD, PECVD, ALD, sputtering, or plating. In FIG. 1 , arrows indicate the direction of current flow from the bottom electrode 28 through the proximity heater 26 to the top electrode 28. In some embodiments of the present application, the circuitry connecting the proximity heater 26 can be electrically isolated from the circuitry connecting the ferroelectric memory device region 100. This provides an additional layer of security to prevent activation of the proximity heater 26 by utilizing the circuitry in the ferroelectric memory device region 100.

[0047] The FeFET illustrated in ferroelectric memory device region 100 may be formed utilizing any well-known FeFET formation techniques. After forming the FeFET, a dielectric material layer 24 is formed laterally adjacent to the FeFET, and then dielectric material layer 24 may be processed to include bottom electrode 28, proximity heater 26, and top electrode 29. These elements / components are formed by forming various trenches / openings in dielectric material layer 24 and then filling the various trenches / openings with appropriate materials to provide bottom electrode 28, proximity heater 26, and top electrode 29 in dielectric material layer 24.

[0048] In the present embodiment (which will become more apparent from the description herein below), the proximity heater 26 is connected to a processor, which may include a notification unit, a tamper detection unit, or other device that can activate the proximity heater 26 (or local heaters 26L and / or 26R in the embodiment shown in FIG. 4). The processor may also activate the heater as a result of a trigger event. In the present application, the processor is connected to the heater so that when a trigger event is detected, the heater is activated, raising the temperature of the ferroelectric memory layer 16 above the Curie temperature so that data erasure can occur. It is important to note that the processor referred to above is not the CPU that reads and writes to the memory module. The CPU is completely isolated from the circuitry that operates the proximity heater. This ensures that malicious code that may be running on the CPU cannot be used to erase memory. Therefore, the tamper detection unit is electrically isolated from the CPU circuitry.

[0049] Referring now to FIG. 2, an alternative ferroelectric memory device that can be used in place of the FeFET shown in FIG. 1 is illustrated. Note that the ferroelectric memory device shown in FIG. 2 can be inserted into ferroelectric memory device region 100 and used in place of the FeFET shown in FIG. 1; the proximity heater 26 of FIG. 1 is disposed laterally adjacent to the ferroelectric memory device shown in FIG. 2 in such an embodiment. In this embodiment, the alternative ferroelectric memory device is a 1T1C FeRAM. The 1T1C FeRAM includes one FET including a gate dielectric material layer and a gate electrode layer; the gate dielectric material layer and gate electrode layer are not separately shown in FIG. 2. The FET is disposed on a semiconductor material layer 12. Source / drain regions 14 are disposed in the footprint of the FET and / or on each side of the FET, and an insulating structure 11 is disposed within the semiconductor material layer 12. The 1T1C FeRAM further includes a capacitor 32 / 16 / 34 including a bottom electrode 33, a ferroelectric material layer 16, and a top electrode 34. As shown, the 1T1C FeRAM further includes source / drain contact structures 22 integrated into first dielectric material layer 24A; the FET is also integrated into this first dielectric material layer 24A. The 1T1C FeRAM further includes a second dielectric material layer 24B having integrated therein a first metal line M1 and a first metal via V1, a third dielectric material layer 24C having integrated therein a second metal line M2 and a second metal via V2, and a fourth dielectric material layer 24D incorporating capacitors 32 / 26 / 34 and a third metal line M3 that contacts the top electrodes 34 of capacitors 32 / 16 / 34.

[0050] The first semiconductor material layer 12, source / drain regions 14, gate electrode material, source / drain contact structures 22, and ferroelectric material layer 16 used to provide the 1T1C FeRAM are the same as those mentioned above for providing the FeFET shown in FIG. 1. The first dielectric material layer 24A, second dielectric material layer 24B, third dielectric material layer 24C, and fourth dielectric material layer 24D of the 1T1C FeRAM comprise one of the dielectric materials mentioned above for dielectric material layer 24. The bottom electrode 32 and top electrode 24 of the capacitor comprise one of the electrode materials mentioned above for forming the bottom electrode 28 and top electrode 29 in FIG. 1. In embodiments, the proximity heater 26 (and the bottom and top electrodes 28, 29) can be formed in a dielectric material stack consisting of the first, second, third, and fourth dielectric material layers, and a separate dielectric material layer 24 need not be used.

[0051] The gate dielectric material layer of a FET is composed of a gate dielectric material such as, for example, silicon oxide or a dielectric material having a dielectric constant greater than 4.0 (such a dielectric material may be referred to as a high-k gate dielectric material). All dielectric constants referred to herein are measured in vacuum unless otherwise specified. Illustrative examples of high-k gate dielectric materials include, for example, hafnium dioxide (HfO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium dioxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium silicon oxynitride (ZrSiO). x N y ), tantalum oxide (TaO xHigh-k gate dielectric materials may include metal oxides such as titanium oxide (TiO), barium strontium titanium oxide (BaOSrTi), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YbO), aluminum oxide (AlO), lead tantalum scandium oxide (Pb(Sc,Ta)O), and / or lead zinc niobate (Pb(Zn,Nb)O), or combinations thereof. The high-k gate dielectric material may further include dopants such as lanthanum (La), aluminum (Al), and / or magnesium (Mg).

[0052] Isolation structure 11 may be a trench isolation structure composed of a trench dielectric material such as silicon oxide. Alternatively, isolation structure 11 may be a thermal isolation structure formed using a thermal oxidation process. Isolation structure 11 may have a top surface that is disposed below, flush with, or above the top surface of semiconductor material layer 12.

[0053] Each of the first, second, and third metal lines M1, M2, and M3 and each of the first and second metal vias V1 and V2 are composed of a conductive interconnect metal or a conductive interconnect metal alloy. Examples of conductive interconnect metals include, but are not limited to, Cu, Al, Co, or W, while examples of conductive interconnect metal alloys include, but are not limited to, Cu-Al alloys.

[0054] The 1T1C FeFRAM shown in FIG. 2 can be formed using any known 1T1C FeRAM processing technique. For example, a FET can be formed on semiconductor material layer 12, followed by insulating structure 11 and source / drain regions 14 formed using techniques known in the art. After forming the FET, the various dielectric material layers in the embedded wiring are formed using conventional interconnect wiring formation processes. A capacitor is formed on third dielectric material layer 24C before forming fourth dielectric material layer 24D. Proximity heater 26 (and lower and upper electrodes 28, 29) can be formed in any one of the dielectric material layers of the 1T1C FeRAM.

[0055] Referring now to FIG. 3, yet another alternative ferroelectric memory device is illustrated in place of the FeFET shown in FIG. 1. Note that the ferroelectric memory device shown in FIG. 3 can be inserted into the ferroelectric memory device region 100 and used in place of the FeFET; the proximity heater 26 of FIG. 1 is disposed laterally adjacent to the ferroelectric memory device shown in FIG. 3 in such an embodiment. In this embodiment, the alternative ferroelectric memory device is a ferroelectric tunnel junction or FeTJ device. In this embodiment, the ferroelectric material layer 16 of the FeTJ device is disposed between a first metal layer M1 and a second metal layer M2. In this embodiment, M1 can be, for example, Pt, Co, Ti, TiN, Ta, TaN, W, PtO, Ir, or IrO, while M2 can be, for example, Pt, Co, Ti, TiN, Ta, TaN, W, PtO, Ir, or IrO, or a semiconductor material. In such an embodiment, the first junction formed between the first metal layer M1 and the ferroelectric material layer 16 has a higher energy barrier height than the second junction formed between the second metal layer M2 and the ferroelectric material layer 16. In yet another embodiment, the first junction formed between the first metal layer M1 and the ferroelectric material layer 16 has a lower energy barrier height than the second junction formed between the second metal layer M2 and the ferroelectric material layer 16. The FeTJ device shown in FIG. 3 can be formed using techniques well known to those skilled in the art.

[0056] Referring now to FIG. 4, a second exemplary NVM structure according to another embodiment of the present application is illustrated. The second exemplary NVM structure includes a key storage region 102 and an adjacent memory region 104, both of which include FeFETs with built-in heaters (or localized heaters 27L, 27R). Note that within the key storage region 102, there is at least one first FeFET residing on the semiconductor material layer 12. The at least one first FeFET includes a source region (one of the source / drain regions 14 in the key memory device region 102), a drain region (another source / drain region 14 shown in the key memory device region 102), a ferroelectric material layer 16, and a localized heater 27L. In this embodiment, the localized heater 27L in the key storage region 102 is entirely disposed on top of the ferroelectric material layer 16. The local heater 27L in the key storage area 102 is configured to generate Joule heating and increase the temperature of the ferroelectric material layer 16 of the at least one first FeFET above the Curie temperature of the ferroelectric material layer 16 of the at least one first FeFET so that at least the secret cryptographic key is erased.

[0057] The first FeFET further includes a first spacer S1, a second spacer S2, and a source / drain contact structure 22. As shown in FIG. 4, the second spacer S2 is disposed along the sidewall of the local heater 27L of the at least one first FeFET and is present on top of the ferroelectric material layer 16 of the at least one first FeFET, and the first spacer S1 is disposed along the sidewall of the second spacer S2 and along the sidewall of the ferroelectric material layer 16 of the at least one first FeFET. The first spacer S1 is in contact with a portion of the source / drain region 14. As further shown, the source / drain contact structure 22 is disposed laterally adjacent to the first spacer S1 and along its sidewall; the source / drain contact structure 22 is in contact with another portion of the source / drain region 14. In this embodiment, the source / drain contact structures 22, the first spacers S1, the second spacers S2, and the local heater 27L each have a top surface that is coplanar with one another and with the top surface of the ILD material layer 50.

[0058] In the memory region 104 located adjacent to the key storage region 102, there is at least one second FeFET located on a semiconductor material layer 12; the semiconductor material layers 12 in both the key storage region 102 and the memory region 104 are located on the substrate 10. The at least one second FeFET includes a source region (one of the source / drain regions 14 in the memory region 104), a drain region (another source / drain region 14 present in the memory region 104), a ferroelectric material layer 16, a U-shaped local heater 27R, and a gate electrode 18. In this embodiment, the U-shaped local heater 27R in the memory region 104 is located on top of the ferroelectric material layer 16 and is present along the sidewalls and bottom wall of the gate electrode 18 of the at least one second FeFET. In this embodiment, the U-shaped local heater 27R has a top surface that is coplanar with the top surface of the gate electrode 18 present in the memory region 104. The U-shaped local heater 27R in the memory region 104 is configured to generate Joule heating and increase the temperature of the ferroelectric material layer 16 of the at least one second FeFET above the Curie temperature of the ferroelectric material layer 16 of the at least one second FeFET so that data is erased in the memory region 104. In some embodiments, the U-shaped local heater 27R is not connected to any processor, so that data in the memory region 104 can be maintained. In a preferred embodiment, erasing the data in the memory region 104 is not necessary because it is sufficient to erase the encryption key present in the key storage region 102. In a highly secure system, it may be necessary to erase memory in both the key storage region 102 and the memory region 104. In that case, the U-shaped heater 27R is connected to the processor so that the temperature in the ferroelectric memory layer 16 present in the memory region 104 can be raised above the Curie temperature.

[0059] The second FeFET further includes a spacer (i.e., a first spacer S1). The spacer (i.e., a first spacer S1) in the memory region 104 exists along the sidewall of the U-shaped local heater 27R of the at least one second FeFET and along the sidewall of the ferroelectric material layer 16 of the at least one second FeFET.

[0060] In this embodiment, substrate 10, semiconductor material layer 12, source / drain regions 14, ferroelectric material layer 16, gate electrode 18, and source / drain contact structures 22 comprise the materials mentioned above for the same components / elements used to provide those mentioned above for the FeFET shown in Figure 1. Local heaters 27L and 27R comprise one of the materials mentioned above for proximity heater 26. First and second spacers comprise one of the spacer dielectric materials mentioned above for spacer 20.

[0061] The ILD material layer 50 may include a dielectric material such as silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As used throughout this application, the term "low-k" refers to a dielectric material having a dielectric constant below 4.0. The ILD material layer 40 may be formed by a deposition and subsequent planarization process.

[0062] An exemplary NVM structure may be formed by first forming a first FeFET and a second FeFET in any order using techniques known to those skilled in the art. An ILD material layer 50 is then formed as described above.

[0063] 5A, a top view of the exemplary NVM structure shown in FIG. 4 is provided, showing the local heater 27L in the key memory region 102 surrounded by the second spacer S2, while FIG. 5B is a top view of the exemplary NVM structure shown in FIG. 4, showing the local heater 27R in the memory region 104 surrounding the gate electrode 18. Note that the coplanar first spacer S1, source / drain contact structures 22, and ILD material layer 50 are not shown for clarity.

[0064] Referring now to FIG. 6, a memory system 600 with erasure capabilities according to an embodiment of the present application is illustrated, which may be used with the exemplary NVM structure shown in FIG. 4 . Memory system 600 may include one or more package integrity sensors 602 and one or more environmental sensors 601. Package integrity sensor 602 may be capable of detecting physical tampering with the device, such as by identifying an attempt to bypass the device enclosure. Environmental sensor 601 may be capable of detecting changes to the device's environment, such as removal of the device from a memory rack, by detecting changes in speed, rotational movement, stability, ambient temperature, and / or ambient humidity. In some embodiments, an authorization code may be used to identify authorized access, such as authorized maintenance that may require bypass of the device enclosure and / or removal from a particular environment.

[0065] The emergency power supply 604 may provide energy to the package integrity sensor 602 and / or the environmental sensor 601. The emergency power supply 604 may also directly or indirectly provide power to the tamper detector 606 (i.e., processor). The tamper detector 606 may be, for example, a notification device (e.g., utilizing an input command), a tamper detection unit (e.g., an anti-tamper device), a unit for identifying a specific event (e.g., a subscription expiration), a combination thereof, or any other unit that may be used to identify a trigger event. The tamper detector 606 may communicate with the package integrity sensor 602 and the environmental sensor 601 such that the tamper detector 606 receives information from the package integrity sensor 602 and the environmental sensor 601.

[0066] Some embodiments of the present application include a tamper prevention device for detecting physical tampering and for providing tamper response through data erasure. Erasing a memory cluster in the key storage area 102 erases any data, including encryption keys (i.e., Key 1 and / or Key 2 and / or Key N) stored in the memory cluster present in the key storage area 102. Erasing the encryption keys stored in the memory clusters of the key storage area 102 prevents the encryption module 608 from using the encryption keys to decrypt data. In some embodiments, such memory clusters in the key storage area 102 may be implemented using ferroelectric memory devices (such as the first FeFET shown in FIG. 4) and local heaters 27R, as described with reference to FIG. 4; for example, the processor (i.e., the tamper detector 606) may activate at least one of the local heaters 27L incorporated in the ferroelectric memory devices to erase data contained in the memory clusters in the key storage area 102. The processor may also be used to heat a U-shaped local heater 27R in the memory area 104 (this is not depicted in FIG. 6, but could easily be achieved by wiring a tamper detector 606 (or other similar processor) to the U-shaped local heater 27R).

[0067] In some embodiments (not shown), a proximity heater 26 used with a ferroelectric memory device shown in Figures 1, 2, or 3 may abut a thermal coupling material, which may be thermally conductive, to facilitate efficient thermal energy transfer from the proximity heater to such a ferroelectric memory device. In such embodiments, the thermal coupling material may be electronically insulating to prevent electronic pulses from passing between the proximity heater and the ferroelectric memory device shown in Figures 1, 2, or 3.

[0068] 6, the ferroelectric memories may be in contact with the encryption module 608. The ferroelectric memories may act as encryption keys for the encryption module 608. For example, they may store encryption keys for the encryption module 608. For example, data written to the storage memory 610 may be encrypted as it is written to the storage memory 610. Similarly, encrypted data read from the storage memory 610 may be decrypted as it is fetched from the memory. In such an embodiment, both encryption and decryption may be based on one or more encryption keys stored in the ferroelectric memory.

[0069] The encryption module 608 may communicate with a memory storage module 610. The storage memory 610 may be any type of memory (e.g., PCM, dynamic random access memory (DRAM), flash, etc.) or any combination thereof. In embodiments, the memory area 104 may be used as the storage memory 610. The encryption module 608 may also communicate with a data source. The encryption module 608 may, for example, receive data from a data source, encrypt the data, and store the encrypted data in the storage memory 610.

[0070] A memory system according to the present application may be accessible only locally (e.g., physical access on-site), only virtually (e.g., via a local area connection or an internet connection), or some combination thereof. In some embodiments, a local-only connection may be preferred to prevent any virtual access that may enable unauthorized remote access. In some embodiments, a virtual connection may be preferred to enable remote access, such as via a specifically authorized remote machine that may communicate with memory system 600 via end-to-end encryption to enable triggering an erase of memory system 600 based on a non-local event.

[0071] While the present application has been particularly shown and described in connection with its preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. at least one ferroelectric memory device including a layer of ferroelectric material; and a proximity heater disposed adjacent to the at least one ferroelectric memory device, the proximity heater configured to generate Joule heating and increase a temperature of the ferroelectric material layer above a Curie temperature of the ferroelectric material layer; A non-volatile memory (NVM) structure comprising:

2. 10. The NVM structure of claim 1, wherein the proximity heater is spaced from the at least one ferroelectric memory device and embedded in a thermally conductive and electrically insulating dielectric material layer.

3. 2. The NVM structure of claim 1, wherein the at least one ferroelectric memory device is a ferroelectric field effect transistor (FeFET) including a source region, a drain region, and a gate electrode, the gate electrode being disposed on top of the ferroelectric material layer.

4. 2. The NVM structure of claim 1, wherein the at least one ferroelectric memory device is a one-transistor, one-capacitor ferroelectric random access memory (1T1C FeRAM), and the ferroelectric material layer is located between a first electrode and a second electrode.

5. 10. The NVM structure of claim 1, wherein the at least one ferroelectric memory device is a ferroelectric tunnel junction device, and the ferroelectric material layer is disposed between a first metal layer and a second metal layer.

6. The NVM structure of claim 1 , wherein the proximity heater is disposed between a bottom electrode and a top electrode.

7. 10. The NVM structure of claim 1, wherein the proximity heater is spaced from the at least one ferroelectric memory device by a distance between 1 nm and 40 nm.

8. 2. The NVM structure of claim 1, wherein the at least one ferroelectric memory device comprises a plurality of ferroelectric memory devices, each ferroelectric memory device of the plurality of ferroelectric memory devices including at least the layer of ferroelectric material.

9. 2. The NVM structure of claim 1, wherein the proximity heater is connected to a processor, wherein the processor signals the proximity heater to activate when a trigger event occurs.

10. The NVM structure of claim 9 , wherein the processor includes a notification unit or a tamper detection unit.

11. a key storage area including at least one first ferroelectric field effect transistor (FeFET), the at least one first FeFET including a source region, a drain region, a ferroelectric material layer, and a local heater, wherein the local heater in the key storage area is disposed on top of the ferroelectric material layer; and a memory region disposed adjacent to the key storage region, the memory region including at least one second FeFET, the at least one second FeFET including a source region, a drain region, a ferroelectric material layer, a U-shaped local heater, and a gate electrode, wherein the U-shaped local heater in the memory region is disposed on top of the ferroelectric material layer and is present along sidewalls and a bottom wall of the gate electrode of the at least one second FeFET; A non-volatile memory (NVM) structure comprising:

12. 12. The NVM structure of claim 11, further comprising an inter-layer dielectric material (ILD) layer separating the key storage area and the memory area.

13. 12. The NVM structure of claim 11, wherein the U-shaped local heater has a top surface that is coplanar with a top surface of the gate electrode present in the memory region.

14. 12. The NVM structure of claim 11, wherein the local heater in the key storage area is configured to generate Joule heating to increase a temperature of the ferroelectric material layer of the at least one first FeFET above a Curie temperature of the ferroelectric material layer of the at least one first FeFET such that at least a secret cryptographic key is erased.

15. 15. The NVM structure of claim 14, wherein the local heater in the memory region is configured to generate Joule heating and increase a temperature of the ferroelectric material layer of the at least one second FeFET above a Curie temperature of the ferroelectric material layer of the at least one second FeFET such that data is erased in the memory region.

16. 12. The NVM structure of claim 11, further comprising: a first spacer and a second spacer present in the key storage area, wherein the second spacer is disposed along a sidewall of the local heater of the at least one first FeFET and generally on top of the ferroelectric material layer of the at least one first FeFET, and the first spacer is disposed along a sidewall of the second spacer and along a sidewall of the ferroelectric material layer of the at least one first FeFET.

17. 12. The NVM structure of claim 11, further comprising spacers in the memory region, wherein the spacers in the memory region are present along sidewalls of the U-shaped local heater of the at least one second FeFET and along sidewalls of the ferroelectric material layer of the at least one second FeFET.

18. 12. The NVM structure of claim 11, wherein the local heater of the at least one first FeFET is connected to a processor, wherein the processor signals the local heater of the at least one first FeFET to activate when a trigger event occurs.

19. 20. The NVM structure of claim 18, wherein the U-shaped local heater of the at least one second FeFET is connected to the processor, wherein the processor also notifies the U-shaped local heater of the at least one second FeFET to activate when the trigger event occurs.

20. The NVM structure of claim 18 , wherein the processor includes a notification unit or a tamper detection unit.

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