Package with substrate having dielectric layers of different materials

Abstract

The package includes a substrate and an integrated device coupled to the substrate. The substrate includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects disposed within the first, second, and third dielectric layers. The second dielectric layer is disposed between the first and third dielectric layers. The second dielectric layer includes a different material than the first and third dielectric layers.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to and the benefit of non-provisional patent application Ser. No. 17 / 951,601, filed with the United States Patent and Trademark Office on September 23, 2022, the entire contents of which are incorporated herein as if fully set forth below in their entirety, and for all applicable purposes. [Background technology]

[0002] Field Various features relate to a package having a substrate and an integrated device.

[0003] background A package may include a substrate and an integrated device. These components are coupled together to provide a package capable of performing various functions. The performance of the package and its components may depend on how these components are coupled together. There is a continuing need to have packages that include more compact form factors with improved connections so that the packages can be implemented into smaller devices and provide improved performance. Summary of the Invention

[0004] Various features relate to a package having a substrate and an integrated device.

[0005] One embodiment provides a package comprising a substrate and an integrated device coupled to the substrate. The substrate includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects disposed within the first, second, and third dielectric layers. The second dielectric layer is disposed between the first and third dielectric layers. The second dielectric layer comprises a different material than the first and third dielectric layers.

[0006] Another embodiment provides a substrate comprising a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects disposed within the first, second, and third dielectric layers, the second dielectric layer being disposed between the first and third dielectric layers, the second dielectric layer comprising a different material than the first and third dielectric layers.

[0007] Another embodiment provides a method for manufacturing a package. The method includes providing a substrate including a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects disposed within the first, second, and third dielectric layers. The second dielectric layer is disposed between the first and third dielectric layers. The second dielectric layer comprises a different material than the first and third dielectric layers. The method includes bonding an integrated device to the substrate.

[0008] Various features, properties, and advantages may become apparent from the following detailed description when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief explanation of the drawings]

[0009] [Figure 1] 1 shows a cross-sectional side view of a substrate. [Figure 2] 1 shows a cross-sectional side view of a package including a substrate, an integrated device, and a passive device. [Figure 3] 1 shows a plan view of a substrate. [Figure 4] 1 shows an enlarged cross-sectional side view of an integrated device bonded to a substrate. [Figure 5A] 1 illustrates an exemplary sequence for manufacturing a substrate having different dielectric layers. [Figure 5B] 1 illustrates an exemplary sequence for manufacturing a substrate having different dielectric layers. [Figure 5C] 1 illustrates an exemplary sequence for manufacturing a substrate having different dielectric layers. [Figure 5D]1 illustrates an exemplary sequence for manufacturing a substrate having different dielectric layers. [Figure 6] 1 shows an exemplary flow diagram of a method for manufacturing a package comprising substrates with different dielectric layers. [Figure 7] 1 illustrates an exemplary sequence for manufacturing a package comprising a substrate, an integrated device, and a passive device. [Figure 8] 1 shows an exemplary flow diagram of a method for manufacturing a package comprising a substrate, an integrated device, and a passive device. [Figure 9] Various electronic devices are illustrated that may incorporate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following description, specific details are set forth to provide a thorough understanding of various aspects of the present disclosure. However, those skilled in the art will understand that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0011] The present disclosure describes a package including a substrate and an integrated device coupled to the substrate. The substrate includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects disposed within the first, second, and third dielectric layers. The second dielectric layer is disposed between the first and third dielectric layers. The second dielectric layer includes a different material from the first and third dielectric layers. In some implementations, the second dielectric layer does not include a glass material, and the first and / or third dielectric layers include a glass material. In some implementations, the first and / or third dielectric layers include a prepreg. The use of dielectric layers having different materials for different layers can help provide interconnects with smaller spacing and / or smaller pitch, potentially enabling higher interconnect density and shorter electrical paths for current and / or signals, which can lead to improved performance for integrated devices and packages.

[0012] Exemplary Package Comprising an Integrated Device and a Substrate Including Dielectric Layers with Different Materials 1 shows a cross-sectional side view of a substrate 102. The substrate 102 may be an embedded trace substrate (ETS). The substrate 102 may be a coreless substrate that does not include a core layer. The substrate 102 includes a dielectric layer 120, a dielectric layer 130, a dielectric layer 140, a plurality of interconnects 122, a solder resist layer 150, and a solder resist layer 160.

[0013] The dielectric layer 120 can be a first dielectric layer. The dielectric layer 130 can be a second dielectric layer. The dielectric layer 140 can be a third dielectric layer. The dielectric layer 120 is bonded to a first surface of the dielectric layer 130. The dielectric layer 140 is bonded to a second surface of the dielectric layer 130. The dielectric layer 130 can be disposed between the dielectric layer 120 and the dielectric layer 140. The dielectric layer 130 can include one or more materials different from the materials of the dielectric layer 120 and the dielectric layer 140. In some implementations, the dielectric layer 130 (e.g., the second dielectric layer) does not include a glass material. In some implementations, the dielectric layer 120 (e.g., the first dielectric layer) and / or the dielectric layer 140 (e.g., the third dielectric layer) include a glass material. In some implementations, the dielectric layer 120 and / or the dielectric layer 140 include a prepreg. A solder resist layer 150 may be disposed on (e.g., above) the surface of dielectric layer 120. A solder resist layer 160 may be disposed on (e.g., below) the surface of dielectric layer 140.

[0014] The plurality of interconnects 122 can be disposed within at least dielectric layer 120, dielectric layer 130, and dielectric layer 140. Some interconnects from the plurality of interconnects 122 can be disposed within and / or on the surfaces of dielectric layer 120, dielectric layer 130, and dielectric layer 140. The plurality of interconnects 122 includes interconnect 122aa, interconnect 122ab, interconnect 122ac, interconnect 122ad, interconnect 122ae, interconnect 122af, interconnect 122ag, interconnect 122ba, interconnect 122bb, interconnect 122bc, interconnect 122bd, interconnect 122be, interconnect 122bf, and interconnect 122bg. Interconnector 122aa, interconnector 122ab, interconnector 122ac, interconnector 122ad, interconnector 122ae, interconnector 122af, and / or interconnector 122ag may define a first row of interconnectors 105a. Interconnector 122aa is coupled to interconnector 122ab. Interconnector 122ab is coupled to interconnector 122ac. Interconnector 122ac is coupled to interconnector 122ad. Interconnector 122ad is coupled to interconnector 122ae. Interconnector 122ae is coupled to interconnector 122af. Interconnector 122af is coupled to interconnector 122ag. Interconnector 122ba, interconnector 122bb, interconnector 122bc, interconnector 122bd, interconnector 122be, interconnector 122bf, and / or interconnector 122bg may define a second column of interconnectors 105b. Interconnector 122ba is coupled to interconnector 122bb. Interconnector 122bb is coupled to interconnector 122bc. Interconnector 122bc is coupled to interconnector 122bd. Interconnector 122bd is coupled to interconnector 122be. Interconnector 122be is coupled to interconnector 122bf. Interconnector 122bf is coupled to interconnector 122bg. The first column of interconnectors 105a and the second column of interconnectors 105b may be part of multiple columns of interconnectors 105.

[0015] An integrated device (not shown) can be coupled to the substrate 102 via a plurality of pillar interconnects 104 and a plurality of solder interconnects 106. The plurality of pillar interconnects 104 includes pillar interconnect 104a and pillar interconnect 104b. The plurality of solder interconnects 106 includes solder interconnect 106a and solder interconnect 106b.

[0016] Pillar interconnect 104a is coupled to first row of interconnects 105a via solder interconnect 106a. Pillar interconnect 104b is coupled to second row of interconnects 105b via solder interconnect 106b. A plurality of solder interconnects 190 are coupled to substrate 102. A plurality of solder interconnects 190 are coupled to a plurality of interconnects 122. For example, a plurality of solder interconnects 190 are coupled to first row of interconnects 105a and second row of interconnects 105b. In one embodiment, solder interconnect 190a is coupled to first row of interconnects 105a and second solder interconnect 190b is coupled to second row of interconnects 105b.

[0017] As shown in FIG. 1, the multiple pillar interconnects 104 are ID Similarly, the plurality of solder interconnects 106 may have an integrated device bump pitch of P IDS The plurality of solder interconnects 190 may include adjacent solder interconnects (e.g., 106a, 106b) that may have an integrated device bump solder pitch of P IPDS In some implementations, the pitch between adjacent rows of interconnects (e.g., 105a, 105b) may be P CIIn some implementations, the pitch between adjacent rows of interconnects (e.g., 105a, 105b) is approximately the same as the pitch between adjacent solder interconnects (e.g., 106a, 106b) that are coupled to the adjacent rows of interconnects (e.g., 105a, 105b). In some implementations, the pitch between adjacent rows of interconnects (e.g., 105a, 105b) is approximately the same as the pitch between adjacent pillar interconnects (e.g., 104a, 104b) that are coupled to the adjacent rows of interconnects (e.g., 105a, 105b) via adjacent solder interconnects (e.g., 106a, 106b). In some implementations, the pitch between adjacent rows of interconnects (e.g., 105a, 105b) is approximately the same as the pitch between adjacent solder interconnects (e.g., 190a, 190b) coupled to the adjacent rows of interconnects (e.g., 105a, 105b).

[0018] In some implementations, a pair of pad interconnects on a particular metal layer (e.g., M1, M2, M3, M4) from the first row of interconnects 105a and the second row of interconnects 105b may have approximately the same pitch as another pair of pad interconnects on another metal layer (e.g., M1, M2, M3, M4) from the first row of interconnects 105a and the second row of interconnects 105b. For example, in some implementations, the pitch between interconnects 122aa and 122ba is approximately the same as the pitch between interconnects 122ac and 122bc. In some implementations, the pitch between interconnects 122aa and 122ba is approximately the same as the pitch between interconnects 122ae and 122be. In some implementations, the pitch between interconnects 122aa and 122ba is approximately the same as the pitch between interconnects 122ag and 122bg.

[0019] In some implementations, a pair of via interconnects between two particular metal layers from the first row of interconnects 105 a and the second row of interconnects 105 b may have approximately the same pitch as another pair of via interconnects between two other metal layers from the first row of interconnects 105 a and the second row of interconnects 105 b. For example, in some implementations, the pitch between interconnects 122 ab and 122 bb is approximately the same as the pitch between interconnects 122 ab and 122 bb. In some implementations, the pitch between interconnects 122 ab and 122 bb is approximately the same as the pitch between interconnects 122 af and 122 bf.

[0020] In some implementations, pairs of pad interconnects on a particular metal layer from the first row of interconnects 105a and the second row of interconnects 105b may have approximately the same pitch as pairs of via interconnects between two metal layers from the first row of interconnects 105a and the second row of interconnects 105b. For example, in some implementations, the pitch between interconnects 122aa and 122ba is approximately the same as the pitch between interconnects 122ab and 122bb. In some implementations, the pitch between interconnects 122ac and 122bc is approximately the same as the pitch between interconnects 122ad and 122bd. In some implementations, the pitch between interconnects 122ae and 122be is approximately the same as the pitch between interconnects 122af and 122bf.

[0021] The use of dielectric layers having different materials for different layers helps to provide interconnects with smaller spacing and / or smaller pitch, allowing for higher density interconnects and shorter electrical paths for current and / or signals, which may lead to improved performance for integrated devices and packages. Furthermore, the use of different dielectric materials between two other dielectric layers does not significantly affect the overall warpage of the substrate, thereby providing a substrate with highly reliable interconnects.

[0022] In some implementations, the pad interconnects (e.g., 122aa, 122ac, 122ae, 122ag, 122ba, 122bc, 122be, 122bg) from the first row of interconnects 105a and / or the second row of interconnects 105b may each have a minimum width and / or minimum diameter of approximately 90 micrometers. In some implementations, the first dielectric layer 120 may have a minimum thickness (T1) of approximately 20 micrometers. In some implementations, the second dielectric layer 130 may have a minimum thickness (T2) of approximately 15 micrometers. In some implementations, the third dielectric layer 140 may have a minimum thickness (T3) of approximately 20 micrometers. Therefore, in some implementations, the thickness (T2) of the second dielectric layer 130 can be thinner than the thickness (T1) of the first dielectric layer 120 and / or the thickness (T3) of the third dielectric layer 140.

[0023] In some implementations, the via interconnects (e.g., 122ab, 122af, 122bb, 122bf) from the first row of interconnects 105a and / or the second row of interconnects 105b disposed in the first dielectric layer 120 and / or the third dielectric layer 140 may each have a minimum width and / or minimum diameter of about 60 micrometers at its widest portion. In some implementations, the via interconnects (e.g., 122ad, 122bd) from the first row of interconnects 105a and / or the second row of interconnects 105b disposed in the second dielectric layer 130 may each have a minimum width and / or minimum diameter of about 50 micrometers at its widest portion. In some implementations, the above configurations using different dielectric layers between the two dielectric layers may allow pairs of interconnects on the same metal layer from adjacent rows of interconnects to be spaced apart with similar or the same spacing (S I ) is useful for defining the

[0024] In some implementations, the first row of interconnects 105a is configured to provide an electrical path for power between the integrated device and a passive device. In some implementations, the second row of interconnects 105b is configured to provide an electrical path for ground between the integrated device and a passive device. The passive devices may include capacitors (e.g., discrete inductors). The passive devices may include decoupling capacitors configured to be coupled to a power source and / or a power distribution network.

[0025] 1 illustrates a substrate including four metal layers. However, other implementations may include substrates with five or more metal layers. Furthermore, other substrates may include other dielectric layers similar to second dielectric layer 130. For example, in some implementations, a substrate may include five metal layers, having a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer, where the second and third dielectric layers are similar to second dielectric layer 130 and the first and fourth dielectric layers are similar to first dielectric layer 120.

[0026] 2 shows a package 200 including a substrate 102, an integrated device 202, a passive device 205, a passive device 207, and a passive device 209. The integrated device 202 is coupled to a first surface (e.g., a top surface) of the substrate 102 via a plurality of pillar interconnects 104 and a plurality of solder interconnects 106. The passive device 205 is coupled to a second surface (e.g., a bottom surface) of the substrate 102 via a plurality of solder interconnects 250. The passive device 207 is coupled to the second surface (e.g., a bottom surface) of the substrate 102 via a plurality of solder interconnects 270. The passive device 209 is coupled to the second surface (e.g., a bottom surface) of the substrate 102 via a plurality of solder interconnects 290. In some implementations, at least a portion of passive device 205, at least a portion of passive device 207, and / or at least a portion of passive device 209 may vertically overlap integrated device 202.

[0027] Substrate 102 includes multiple rows of interconnects 222. Multiple rows of interconnects 222 are a portion of multiple interconnects 122 of substrate 102. Multiple rows of interconnects 222 may be configured and / or arranged in a similar manner as first row of interconnects 105a and / or second row of interconnects 105b.

[0028] Integrated device 202 is configured to be electrically coupled to passive device 205 via an electrical pathway (e.g., for power) that includes pillar interconnects from the plurality of pillar interconnects 104, solder interconnects from the plurality of solder interconnects 106, row 222a of interconnects, and solder interconnects from the plurality of solder interconnects 250. Integrated device 202 is configured to be electrically coupled to passive device 205 via an electrical pathway (e.g., for ground) that includes pillar interconnects from the plurality of pillar interconnects 104, solder interconnects from the plurality of solder interconnects 106, row 222b of interconnects, and solder interconnects from the plurality of solder interconnects 250.

[0029] Integrated device 202 is configured to be electrically coupled to passive device 207 via an electrical pathway (e.g., for power) that includes pillar interconnects from the plurality of pillar interconnects 104, solder interconnects from the plurality of solder interconnects 106, row 222c of interconnects, and solder interconnects from the plurality of solder interconnects 270. Integrated device 202 is configured to be electrically coupled to passive device 207 via an electrical pathway (e.g., for ground) that includes pillar interconnects from the plurality of pillar interconnects 104, solder interconnects from the plurality of solder interconnects 106, at least row 222d of interconnects, and solder interconnects from the plurality of solder interconnects 270.

[0030] Integrated device 202 is configured to be electrically coupled to passive device 209 via an electrical path (e.g., for power) that includes pillar interconnects from the plurality of pillar interconnects 104, solder interconnects from the plurality of solder interconnects 106, row 222e of interconnects, and solder interconnects from the plurality of solder interconnects 290. Integrated device 202 is configured to be electrically coupled to passive device 207 via an electrical path (e.g., for ground) that includes pillar interconnects from the plurality of pillar interconnects 104, solder interconnects from the plurality of solder interconnects 106, row 222f of interconnects, and solder interconnects from the plurality of solder interconnects 290. In some implementations, integrated device 202, passive device 205, passive device 207, and passive device 209 are configured to be electrically coupled to a power distribution network.

[0031] FIG. 3 illustrates a plan view of the substrate 102. As illustrated in FIG. 3, the substrate 102 includes a first dielectric layer 120, a plurality of interconnects 302, and a plurality of interconnects 304. The plurality of interconnects 302 and the plurality of interconnects 304 are disposed in a region 300 of the substrate 102 that vertically overlaps an integrated device (e.g., 202). The plurality of interconnects 302 and the plurality of interconnects 304 may be disposed on a first metal layer (e.g., M1) of the substrate 102. The pitch and / or spacing of the plurality of interconnects 302 is greater than the pitch and / or spacing of the plurality of interconnects 304. The plurality of interconnects 302 may include interconnects that are part of multiple rows of interconnects (e.g., 105, 222) as described at least in FIGS. 1 and 2. The plurality of interconnects and / or the plurality of interconnects 304 may be part of the plurality of interconnects 122.

[0032] 4 shows an expanded view of how an integrated device can be bonded to a substrate. The integrated device 202 can be bonded to the substrate 102 via a plurality of pillar interconnects and a plurality of solder interconnects. The integrated device 202 and the substrate 102 can be part of a package 200. The integrated device 202 includes a die portion 402, a plurality of pillar interconnects 104, and a plurality of solder interconnects 106. The plurality of pillar interconnects 104 are bonded to the die portion 402. The plurality of solder interconnects 106 are bonded to the plurality of pillar interconnects 104. The integrated device 202 can include a flip chip.

[0033] The die portion 402 includes a die substrate 420, an interconnect portion 422, a passivation layer 405, a passivation layer 408, a plurality of pads 407, a passivation layer 408, and a plurality of under-bump metallization interconnects 409. The die substrate 420 may include silicon (Si). A plurality of cells (e.g., logic cells) and / or a plurality of transistors (not shown) may be formed in and / or on the die substrate 420. Different implementations may use different types of transistors, such as field effect transistors (FETs), planar FETs, finFETs, and gate-all-around FETs. In some implementations, a front end of line (FEOL) process may be used to form the plurality of cells (e.g., logic cells) and / or transistors in and / or on the die substrate 420. The interconnect portion 422 is disposed on and coupled to the die substrate 420. Interconnect portion 422 can be coupled to multiple cells and / or transistors disposed in and / or on die substrate 420. Interconnect portion 422 (e.g., die interconnect portion) can include multiple die interconnects (not shown) coupled to multiple cells and / or transistors. In some implementations, interconnect portion 422 can be fabricated using back end of line (BEOL) processes.

[0034] A passivation layer 405 is disposed on and bonded to the interconnect portion 422. The passivation layer 405 may be a hard passivation layer. A passivation layer 408 is disposed on the passivation layer 405. The passivation layer 408 may include a polymer passivation layer. A plurality of pads 407 are disposed on the interconnect portion 422. The plurality of pads 407 may be bonded to die interconnects of the interconnect portion 422. In some implementations, the passivation layer 405, the passivation layer 408, and / or the plurality of pads 407 may be considered part of the interconnect portion 422. In some implementations, back-end (BEOL) processes may be used to fabricate the passivation layer 405, the passivation layer 408, and the plurality of pads 407. A plurality of under-bump metallization interconnects 409 are bonded to the plurality of pads 407. The plurality of under bump metallization interconnects 409 can be disposed on the plurality of pads 407. In some implementations, there can be additional interconnects between the plurality of pads 407 and the plurality of under bump metallization interconnects 409. For example, there can be metallization interconnects between the plurality of pads 407 and the plurality of under bump metallization interconnects 409. Examples of metallization interconnects include rewiring interconnects. In some implementations, the plurality of under bump metallization interconnects 409 can be coupled to the plurality of pads 407 via metallization interconnects (e.g., rewiring interconnects).

[0035] A plurality of pillar interconnects 104 may be coupled to the die portion 402. The plurality of pillar interconnects 104 may be coupled to a plurality of under bump metallization interconnects 409. The plurality of pillar interconnects 104 may be coupled to the die portion 402 via a plurality of under bump metallization interconnects 409. The plurality of pillar interconnects 104 may be a means for pillar interconnection. The plurality of under bump metallization interconnects 409 may be a means for under bump metallization interconnection.

[0036] The plurality of pads 407 includes a first pad 407a and a second pad 407b. The plurality of underbump metallization interconnects 409 includes a first underbump metallization interconnect 409a and a second underbump metallization interconnect 409b. The plurality of pillar interconnects 104 includes a first pillar interconnect 104a and a second pillar interconnect 104b. The plurality of solder interconnects 106 includes a first solder interconnect 106a and a second solder interconnect 106b.

[0037] The first underbump metallization interconnect 409a is coupled to the first pad 407a. The first pillar interconnect 104a is coupled to the first underbump metallization interconnect 409a. The first solder interconnect 106a is coupled to the first pillar interconnect 104a. Note that in some implementations, the first pillar interconnect 104a is coupled to the first underbump metallization interconnect 409a via at least one metallization interconnect. That is, at least one metallization interconnect (e.g., a rewiring interconnect) can be disposed between the first pillar interconnect 104a and the first underbump metallization interconnect 409a.

[0038] The second under bump metallization interconnect 409b is coupled to the second pad 407b. The second pillar interconnect 104b is coupled to the second under bump metallization interconnect 409b. The second solder interconnect 106b is coupled to the second pillar interconnect 104b. Note that in some implementations, the second pillar interconnect 104b is coupled to the second under bump metallization interconnect 409b via at least one metallization interconnect. That is, at least one metallization interconnect (e.g., a rewiring interconnect) can be disposed between the second pillar interconnect 104b and the second under bump metallization interconnect 409b.

[0039] The integrated device 202 is coupled to the substrate 102 via a plurality of solder interconnects 106 and a plurality of pillar interconnects 104. For example, solder interconnect 106a can be directly coupled to interconnect 122aa and pillar interconnect 104a. In some implementations, solder interconnect 106b can be directly coupled to interconnect 122ba and pillar interconnect 104b.

[0040] The integrated device (e.g., 202) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 02) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device. In some implementations, an integrated device may be a chiplet. Chiplets may be manufactured using processes that result in better yields compared to other processes used to manufacture other types of integrated devices, which may lower the overall cost of manufacturing the chiplet. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several chiplets may be used to perform the functions of one or more chips (e.g., one or more integrated devices). Thus, for example, a single integrated device may be divided into several chiplets.As described above, using several chiplets that perform several functions can reduce the overall cost of a package compared to using a single chip to perform all of the package's functions. In some implementations, one or more of the chiplets and / or one or more of the integrated devices (e.g., 202) described in this disclosure can be fabricated using the same technology node or two or more different technology nodes. For example, an integrated device (e.g., 202) can be fabricated using a first technology node, and a chiplet can be fabricated using a second technology node that is less advanced than the first technology node. In such examples, the integrated device (e.g., 202) can include components (e.g., interconnects, transistors) having a first minimum size, and the chiplet can include components (e.g., interconnects, transistors) having a second minimum size, where the second minimum size is larger than the first minimum size. In some implementations, one integrated device and another integrated device in a package can be fabricated using the same technology node or different technology nodes. In some implementations, one chiplet and another chiplet in a package can be manufactured using the same technology node or different technology nodes.

[0041] Exemplary Sequence for Fabricating a Substrate In some implementations, manufacturing a substrate includes several processes. Figures 5A-5D show an example sequence for preparing or manufacturing a substrate. In some implementations, the sequence of Figures 5A-5D can be used to prepare or manufacture substrate 102. However, the processes of Figures 5A-5D can also be used to manufacture any of the substrates described in this disclosure.

[0042] 5A-5D, one or more steps may be combined to simplify and / or clarify the sequence for preparing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure.

[0043] 5A, Stage 1 shows a state after a core layer 501 is prepared. The core layer 501 may include a seed layer 503 disposed on a first surface of the core layer 501 and a seed layer 505 disposed on a second surface of the core layer 501. The core layer 501 may be a dielectric. The core layer 501 may be a carrier.

[0044] Stage 2 depicts the state after interconnects have been formed in and on the surfaces of core layer 501, seed layer 503, and / or seed layer 505. A plurality of interconnects 502 may be formed on (e.g., above) a first surface of core layer 501 and / or on seed layer 503. Seed layer 503 may be part of the plurality of interconnects 502. A plurality of interconnects 512 may be formed on (e.g., below) a second surface of core layer 501 and / or on seed layer 505. Seed layer 505 may be part of the plurality of interconnects 512. Masking, plating, and / or etching processes may be used to form the plurality of interconnects 502 and / or the plurality of interconnects 512.

[0045] Stage 3 shows the state after a dielectric layer 520 has been formed on (e.g., above) the first surface of the core layer 501, the seed layer 503, and / or the plurality of interconnects 502. Stage 4 also shows the state after a dielectric layer 530 has been formed on (e.g., below) the second surface of the core layer 501, the seed layer 505, and / or the plurality of interconnects 512. Deposition and / or lamination processes can be used to form the dielectric layer 520 and the dielectric layer 530. The dielectric layer 520 and the dielectric layer 530 can be different from the core layer 501.

[0046] Stage 4 shows the state after multiple cavities 521 have been formed in dielectric layer 520 and multiple cavities 531 have been formed in dielectric layer 530. Multiple cavities 521 and multiple cavities 531 can be formed using a photolithography process (e.g., exposure and development) and / or a laser process (e.g., laser ablation). Multiple cavities 521 and multiple cavities 531 can be formed using a masking process, an exposure process, and / or a development process.

[0047] Stage 5 depicts the state after interconnects have been formed in and on the surfaces of dielectric layer 520 and dielectric layer 530. A plurality of interconnects 522 may be formed on (e.g., above) the first surface and the plurality of cavities 521 of dielectric layer 520. A plurality of interconnects 532 may be formed on (e.g., below) the second surface and the plurality of cavities 531 of dielectric layer 530. Masking, plating, and / or etching processes may be used to form the plurality of interconnects 522 and / or the plurality of interconnects 532.

[0048] 5B , stage 6 depicts the state after dielectric layer 540 has been formed over (e.g., above) the first surface of dielectric layer 520 and the plurality of interconnects 522. Stage 7 also depicts the state after dielectric layer 550 has been formed over (e.g., below) the second surface of dielectric layer 530 and the plurality of interconnects 532. Deposition and / or lamination processes can be used to form dielectric layer 540 and dielectric layer 550. Dielectric layer 540 and / or dielectric layer 550 can be a different dielectric material than the dielectric material from dielectric layer 520 and / or dielectric layer 530.

[0049] Stage 7 shows the state after multiple cavities 541 have been formed in dielectric layer 540 and multiple cavities 551 have been formed in dielectric layer 550. Multiple cavities 541 and multiple cavities 551 can be formed using a photolithography process (e.g., exposure and development) and / or a laser process (e.g., laser ablation). Multiple cavities 541 and multiple cavities 551 can be formed using a masking process, an exposure process, and / or a development process.

[0050] Stage 8 shows the state after interconnects have been formed in and on the surfaces of dielectric layer 540 and dielectric layer 550. A plurality of interconnects 542 can be formed on (e.g., above) the first surface of dielectric layer 540 and on the plurality of cavities 541. A plurality of interconnects 552 can be formed on (e.g., below) the second surface of dielectric layer 550 and on the plurality of cavities 551. Masking, plating, and / or etching processes can be used to form the plurality of interconnects 542 and / or the plurality of interconnects 552.

[0051] 5C , stage 9 depicts the state after a dielectric layer 560 has been formed over (e.g., above) the first surface of the dielectric layer 540 and the plurality of interconnects 542. Stage 9 also depicts the state after a dielectric layer 570 has been formed over (e.g., below) the second surface of the dielectric layer 550 and the plurality of interconnects 552. Deposition and / or lamination processes can be used to form the dielectric layers 560 and 570. The dielectric layers 560 and / or 570 can be of a different dielectric material than the dielectric layers 540 and / or 550. The dielectric layers 560 and / or 570 can be of a similar dielectric material to the dielectric layers 520 and / or 530.

[0052] Stage 10 shows the state after multiple cavities 561 have been formed in dielectric layer 560 and multiple cavities 571 have been formed in dielectric layer 570. Multiple cavities 561 and multiple cavities 571 can be formed using a photolithography process (e.g., exposure and development) and / or a laser process (e.g., laser ablation). Multiple cavities 561 and multiple cavities 571 can be formed using a masking process, an exposure process, and / or a development process.

[0053] Stage 11 shows the state after interconnects have been formed in and on the surfaces of dielectric layer 560 and dielectric layer 570. A plurality of interconnects 562 can be formed on (e.g., above) the first surface and the plurality of cavities 561 of dielectric layer 560. A plurality of interconnects 572 can be formed on (e.g., below) the second surface and the plurality of cavities 571 of dielectric layer 570. A masking process, a plating process, and / or an etching process can be used to form the plurality of interconnects 562 and / or the plurality of interconnects 572. Stage 11 can show substrate 590a and substrate 590b being bonded to core layer 501.

[0054] 5D , stage 12 depicts the state after substrate 590b has been removed from core layer 501. A portion of seed layer 505 may also be removed. Substrate 590a may also be removed from core layer 501 in a similar manner. Substrate 590b may correspond to substrate 102, including dielectric layer 120, dielectric layer 130, and dielectric layer 140. For example, first dielectric layer 120 may be dielectric layer 530, second dielectric layer 130 may be dielectric layer 550, and third dielectric layer 140 may be dielectric layer 570. Plurality of interconnects 122 may correspond to plural interconnects 532, plural interconnects 552, and / or plural interconnects 572.

[0055] Similarly, substrate 590a may correspond to substrate 102, including dielectric layer 120, dielectric layer 130, and dielectric layer 140. For example, first dielectric layer 120 may be dielectric layer 520, second dielectric layer 130 may be dielectric layer 540, and third dielectric layer 140 may be dielectric layer 560. Plurality of interconnects 122 may correspond to plural interconnects 522, plural interconnects 542, and / or plural interconnects 562.

[0056] Stage 13 shows the state after the formation of solder resist layer 150 and solder resist layer 160. Solder resist layer 150 and solder resist layer 160 can be formed using a lamination and / or deposition process.

[0057] It should be noted that additional dielectric layers and / or additional interconnects may be formed by repeating some of the processes described above.

[0058] Different implementations may use different processes to form the metal layers and / or interconnects. In some implementations, the metal layers may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process.

[0059] 1 is an exemplary flow diagram of a method for manufacturing a substrate; In some implementations, manufacturing a substrate includes several processes. Figure 6 shows an example flow diagram of a method 600 for preparing or manufacturing a substrate. In some implementations, the method 600 of Figure 6 can be used to prepare or manufacture the substrate 102 described in this disclosure. However, the method 600 can also be used to prepare or manufacture any of the substrates described in this disclosure.

[0060] 6 may combine one or more processes to simplify and / or clarify the method for preparing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure.

[0061] The method includes (at 605) preparing a core layer and at least one seed layer. As shown in FIG. 5A, step 1 illustrates the state after the core layer 501 is prepared. The core layer 501 may include a seed layer 503 disposed on a first surface of the core layer 501 and a seed layer 505 disposed on a second surface of the core layer 501. The core layer 501 may be a dielectric. The core layer 501 may be a carrier.

[0062] The method forms and patterns (at 610) a plurality of interconnects on (e.g., above, below) the core layer and / or at least one seed layer. Stage 2 of FIG. 5A shows the state after interconnects have been formed in and on the surfaces of the core layer 501, the seed layer 503, and / or the seed layer 505. A plurality of interconnects 502 can be formed on (e.g., above) a first surface of the core layer 501 and / or on (e.g., below) the seed layer 503. The seed layer 503 can be part of the plurality of interconnects 502. A plurality of interconnects 512 can be formed on (e.g., below) a second surface of the core layer 501 and / or on (e.g., below) the seed layer 505. The seed layer 505 can be part of the plurality of interconnects 512. A masking process, a plating process, and / or an etching process can be used to form the plurality of interconnects 502 and / or the plurality of interconnects 512.

[0063] The method forms (at 615) at least one dielectric layer over (e.g., above, below) the plurality of interconnects, the core layer, and / or the seed layer. Stage 3 of FIG. 5A illustrates the state after a dielectric layer 520 has been formed over (e.g., above) the first surface of the core layer 501, the seed layer 503, and / or the plurality of interconnects 502. Stage 3 also illustrates the state after a dielectric layer 530 has been formed over (e.g., below) the second surface of the core layer 501, the seed layer 505, and / or the plurality of interconnects 512. Deposition and / or lamination processes can be used to form the dielectric layer 520 and the dielectric layer 530. The dielectric layer 520 and the dielectric layer 530 can be different from the core layer 501.

[0064] The method forms (at 620) a plurality of interconnects in and on at least one dielectric layer (e.g., a first dielectric layer). Forming the plurality of interconnects may include forming a plurality of cavities in the at least one dielectric layer (e.g., the first dielectric layer) and performing a plating process. Stage 4 of FIG. 5A illustrates a state after a plurality of cavities 521 have been formed in dielectric layer 520 and a plurality of cavities 531 have been formed in dielectric layer 530. The plurality of cavities 521 and the plurality of cavities 531 may be formed using a photolithography process (e.g., exposure and development) and / or a laser process (e.g., laser ablation). A masking process, an exposure process, and / or a development process may be used to form the plurality of cavities 521 and the plurality of cavities 531. Note that in some implementations, forming the cavities in the dielectric layer may be considered part of forming the dielectric layer.

[0065] 5A shows the state after interconnects have been formed in and on the surfaces of dielectric layer 520 and dielectric layer 530. A plurality of interconnects 522 may be formed on (e.g., above) a first surface of dielectric layer 520 and on (e.g., above) the plurality of cavities 521. A plurality of interconnects 532 may be formed on (e.g., below) a second surface of dielectric layer 530 and on (e.g., below) the plurality of cavities 531. A masking process, a plating process, and / or an etching process may be used to form the plurality of interconnects 522 and / or the plurality of interconnects 532.

[0066] The method forms (at 625) at least one dielectric layer on (e.g., above, below) a dielectric layer (e.g., a first dielectric layer). This dielectric layer can be a second dielectric layer formed on the first dielectric layer. The second dielectric layer can be a different material from that of the first dielectric layer. As shown in FIG. 5B , step 6 illustrates the state after dielectric layer 540 has been formed on (e.g., above) the first surface of dielectric layer 520 and the plurality of interconnects 522. Step 7 also illustrates the state after dielectric layer 550 has been formed on (e.g., below) the second surface of dielectric layer 530 and the plurality of interconnects 532. Deposition and / or lamination processes can be used to form dielectric layer 540 and dielectric layer 550. Dielectric layer 540 and / or dielectric layer 550 can be a different dielectric material from dielectric layer 520 and / or dielectric layer 530.

[0067] The method forms (at 630) a plurality of interconnects in and on at least one dielectric layer (e.g., a second dielectric layer). Forming the plurality of interconnects may include forming a plurality of cavities in at least one dielectric layer (e.g., a second dielectric layer) and performing a plating process. Stage 7 of FIG. 5B illustrates the state after a plurality of cavities 541 have been formed in dielectric layer 540 and a plurality of cavities 551 have been formed in dielectric layer 550. The plurality of cavities 541 and the plurality of cavities 551 may be formed using a photolithography process (e.g., exposure and development) and / or a laser process (e.g., laser ablation). A masking process, an exposure process, and / or a development process may be used to form the plurality of cavities 541 and the plurality of cavities 551. Note that in some implementations, forming the cavities in the dielectric layer may be considered part of forming the dielectric layer.

[0068] 5B shows the state after interconnects have been formed in and on the surfaces of dielectric layer 540 and dielectric layer 550. A plurality of interconnects 542 may be formed on (e.g., above) the first surface of dielectric layer 540 and on the plurality of cavities 541. A plurality of interconnects 552 may be formed on (e.g., below) the second surface of dielectric layer 550 and on the plurality of cavities 551. Masking, plating, and / or etching processes may be used to form the plurality of interconnects 542 and / or the plurality of interconnects 552.

[0069] The method forms (at 630) at least one dielectric layer on (e.g., above, below) a dielectric layer (e.g., a second dielectric layer). This dielectric layer can be a third dielectric layer formed on the second dielectric layer. The third dielectric layer can be a different material from the second dielectric layer. The third dielectric layer can be the same or a similar material as the first dielectric layer. As shown in FIG. 5C , stage 9 illustrates the state after dielectric layer 560 has been formed on (e.g., above) the first surface of dielectric layer 540 and the plurality of interconnects 542. Stage 9 also illustrates the state after dielectric layer 570 has been formed on (e.g., below) the second surface of dielectric layer 550 and the plurality of interconnects 552. Deposition and / or lamination processes can be used to form dielectric layer 560 and dielectric layer 570. Dielectric layer 560 and / or dielectric layer 570 can be a different dielectric material than dielectric layer 540 and / or dielectric layer 550. Dielectric layer 560 and / or dielectric layer 570 can be a dielectric material similar to the dielectric material of dielectric layer 520 and / or dielectric layer 530 .

[0070] The method includes (at 640) forming a plurality of interconnects in and on at least one dielectric layer (e.g., a third dielectric layer). Forming the plurality of interconnects may include forming a plurality of cavities in the at least one dielectric layer (e.g., the third dielectric layer) and performing a plating process. Stage 10 of FIG. 5C illustrates a state after a plurality of cavities 561 have been formed in dielectric layer 560 and a plurality of cavities 571 have been formed in dielectric layer 570. The plurality of cavities 561 and the plurality of cavities 571 may be formed using a photolithography process (e.g., exposure and development) and / or a laser process (e.g., laser ablation). A masking process, an exposure process, and / or a development process may be used to form the plurality of cavities 561 and the plurality of cavities 571. Note that in some implementations, forming the cavities in the dielectric layer may be considered part of forming the dielectric layer.

[0071] 5C shows the state after interconnects have been formed in and on the surfaces of dielectric layer 560 and dielectric layer 570. A plurality of interconnects 562 can be formed on (e.g., above) the first surface of dielectric layer 560 and on the plurality of cavities 561. A plurality of interconnects 572 can be formed on (e.g., below) the second surface of dielectric layer 570 and on the plurality of cavities 571. Masking, plating, and / or etching processes can be used to form the plurality of interconnects 562 and / or the plurality of interconnects 572. Stage 11 can show substrate 590a and substrate 590b being bonded to core layer 501.

[0072] The method separates (at 645) the core layer from the dielectric layer. In some implementations, portions of the seed layer may also be removed. Stage 12 of FIG. 5D shows the state after substrate 590b has been removed from core layer 501. A portion of seed layer 505 may also be removed. Substrate 590a may also be removed from core layer 501 in a similar manner. Substrate 590b may correspond to substrate 102, including dielectric layer 120, dielectric layer 130, and dielectric layer 140. For example, first dielectric layer 120 may be dielectric layer 530, second dielectric layer 130 may be dielectric layer 550, and third dielectric layer 140 may be dielectric layer 570. Multiple interconnects 122 may correspond to multiple interconnects 532, multiple interconnects 552, and / or multiple interconnects 572.

[0073] Similarly, substrate 590a may correspond to substrate 102, including dielectric layer 120, dielectric layer 130, and dielectric layer 140. For example, first dielectric layer 120 may be dielectric layer 520, second dielectric layer 130 may be dielectric layer 540, and third dielectric layer 140 may be dielectric layer 560. Plurality of interconnects 122 may correspond to plural interconnects 522, plural interconnects 542, and / or plural interconnects 562.

[0074] In some implementations, the method may also form one or more solder resist layers on the one or more dielectric layers. Stage 13 of Figure 5D shows the state after solder resist layer 150 and solder resist layer 160 have been formed. Lamination and / or deposition processes may be used to form solder resist layer 150 and solder resist layer 160. It should be noted that the above method may be used to manufacture substrates with more metal layers and more dielectric layers.

[0075] Different implementations may use different processes to form the metal layers and / or interconnects. In some implementations, the metal layers may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process.

[0076] Exemplary Sequence for Manufacturing a Package Comprising a Substrate, an Integrated Device, and a Passive Device In some implementations, manufacturing a package includes several processes. Figure 7 shows an example sequence for preparing or manufacturing a package including a substrate. In some implementations, the sequence of Figure 7 can be used to prepare or manufacture package 200 of Figure 2. However, the process of Figure 7 can also be used to manufacture any of the packages described in this disclosure.

[0077] 7 may be combined with one or more steps to simplify and / or clarify the sequence for preparing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure.

[0078] As shown in FIG. 7, stage 1 illustrates the state after the substrate 102 is prepared. The substrate 102 includes a first dielectric layer 120, a second dielectric layer 130, a third dielectric layer 140, a solder resist layer 150, a solder resist layer 160, and a plurality of interconnects 122. The second dielectric layer 130 may include a dielectric material different from the dielectric materials of the first dielectric layer 120 and / or the third dielectric layer 140. The second dielectric layer 130 may not include a glass material. In some implementations, the dielectric layer 130 may include Ajinomoto Build-Up Film (ABF). The first dielectric layer 120 and / or the third dielectric layer 140 may include a glass material. FIGS. 5A-5D illustrate an example of manufacturing a substrate.

[0079] Stage 2 shows the state after the integrated device 202 has been bonded to the first surface of the substrate 102 via the pillar interconnects 104 and the solder interconnects 106. A solder reflow process can be used to bond the integrated device 202 to the substrate 102. Figure 4 shows one example of how the integrated device 202 can be bonded to the substrate 102.

[0080] Stage 2 also shows the state after at least one passive device (e.g., 205, 207, 209) has been coupled to the second surface of the substrate 102 via a plurality of solder interconnects (e.g., 250, 270, 290). A solder reflow process can be used to couple the at least one passive device to the substrate 102.

[0081] Stage 3 shows the state after an encapsulation layer 208 has been provided (e.g., formed) on the substrate 102. The encapsulation layer 208 can encapsulate the integrated device 202. The encapsulation layer 208 can include a mold, a resin, and / or an epoxy. The encapsulation layer 208 can be formed using a compression molding process, a transfer molding process, or a liquid molding process. The encapsulation layer 208 can be photo-etchable. The encapsulation layer 208 can be a means for encapsulation.

[0082] Stage 4 shows the state after the plurality of solder interconnects 450 have been bonded to the second surface of the substrate 102 via a solder reflow process. The plurality of solder interconnects 450 may be bonded to the plurality of interconnects 122.

[0083] 1 is an exemplary flow diagram of a method for manufacturing a package comprising a substrate, an integrated device, and a passive device; In some implementations, manufacturing a package includes several processes. Figure 8 shows an example flow diagram of a method 800 for preparing or manufacturing a package comprising a substrate. In some implementations, the method 800 of Figure 8 can be used to prepare or manufacture the package 200 of Figure 2 described in this disclosure. However, the method 800 can also be used to prepare or manufacture any of the packages described in this disclosure.

[0084] 8 may combine one or more processes to simplify and / or clarify the method for preparing or manufacturing the package. In some implementations, the order of the processes may be changed or modified.

[0085] The method provides (at 1205) a substrate (e.g., 102). The substrate 102 may be provided by a supplier or may be manufactured. Different implementations may use different processes to manufacture the substrate 102. Examples of processes that may be used to manufacture the substrate include a semi-additive process (SAP) and a modified semi-additive process (mSAP). The substrate 102 includes a first dielectric layer 120, a second dielectric layer 130, a third dielectric layer 140, a solder resist layer 150, a solder resist layer 160, and a plurality of interconnects 122. The second dielectric layer 130 may include a different dielectric material than the first dielectric layer 120 and / or the third dielectric layer 140. The second dielectric layer 130 may not include a glass material. The first dielectric layer 120 and / or the third dielectric layer 140 may include a glass material. Figures 5A-5D show an example of manufacturing a substrate. Stage 1 of Figure 7 shows an example of a substrate being prepared.

[0086] The method may (at 810) couple an integrated device to a first surface of the substrate and may couple at least one passive device to a second surface of the substrate. Stage 2 of Figure 7 shows the state after the integrated device 202 has been coupled to the first surface of the substrate 102 via the pillar interconnects 104 and the solder interconnects 106. A solder reflow process may be used to couple the integrated device 202 to the substrate 102. Figure 4 shows one example of how the integrated device 202 may be coupled to the substrate 102.

[0087] Stage 2 also shows the state after at least one passive device (e.g., 205, 207, 209) has been coupled to the second surface of the substrate 102 via a plurality of solder interconnects (e.g., 250, 270, 290). A solder reflow process can be used to couple the at least one passive device to the substrate 102.

[0088] The method forms (at 815) an encapsulation over the substrate and the integrated device. The encapsulation layer can be bonded to the substrate and the integrated device. Step 3 of FIG. 7 shows the state after the encapsulation layer 208 is provided (e.g., formed) over the substrate 102. The encapsulation layer 208 can encapsulate the integrated device 202. The encapsulation layer 208 can include a mold, a resin, and / or an epoxy. The encapsulation layer 208 can be formed using a compression molding process, a transfer molding process, or a liquid molding process. The encapsulation layer 208 can be photo-etchable. The encapsulation layer 208 can be a means for encapsulation.

[0089] The method couples (at 820) a plurality of solder interconnects to the second surface of the substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 450 to the substrate 102.

[0090] The packages (e.g., 200) described in this disclosure can be manufactured one by one, or can be manufactured integrally as part of one or more wafers and then singulated into individual packages.

[0091] Exemplary Electronic Devices FIG. 9 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 902, a laptop computer device 904, a fixed location terminal device 906, a wearable device 908, or an autonomous vehicle 910 may include a device 900 as described herein. The device 900 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 902, 904, 906, and 908 and the vehicle 910 illustrated in FIG. 9 are merely examples. Other electronic devices may also feature device 900, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, eyeglasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0092] One or more of the components, processes, features, and / or functions shown in Figures 1-4, 5A-5D, and / or 6-9 may be rearranged and / or combined into a single component, process, feature, or function, or may be embodied as several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that Figures 1-4, 5A-5D, and / or 6-9, and their corresponding descriptions in this disclosure, are not limited to dies and / or ICs. In some implementations, devices and / or integrated devices may be manufactured, fabricated, prepared, and / or produced using Figures 1-4, 5A-5D, and / or 6-9, and their corresponding descriptions in this disclosure. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0093] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0094] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as preferred or advantageous over other aspects of the present disclosure. Likewise, the term “aspects” does not require that all aspects of the present disclosure include the discussed feature, advantage, or mode of operation. The term “coupled” is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, objects A and C can still be considered coupled to each other even though they are not in direct physical contact with each other. Object A, which is coupled to object B, may also be coupled to at least a portion of object B. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electric current (e.g., a signal, a power source, a ground) can propagate between the two objects. Two objects that are electrically coupled may or may not propagate an electric current between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may also be a first component, a second component, a third component, or a fourth component. The terms “encapsulate,” “encapsulating,” and / or any derivatives mean that an object may partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary.A component disposed on top may be disposed on top of a component disposed on bottom. A top component may also be considered a bottom component, and vice versa. As described in this disclosure, a first component disposed “over” a second component may mean that the first component is disposed above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be disposed on (e.g., above) a first surface of the second component, and a third component may be disposed on (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being disposed on top of another component, the term “over” as used herein can be used to refer to a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but not in direct contact with the second component, (2) that the first component is present on the second component (e.g., on the surface of the second component), and / or (3) that the first component is present within the second component (e.g., embedded within the second component). A first component that is disposed "in" a second component can be partially disposed within the second component or completely disposed within the second component. A value that is approximately X to XX can mean a value between X and XX, inclusive of X and XX. The value between X and XX can be discrete or continuous. As used in this disclosure, the term "about 'value X'" or "approximately value X" means within a 10 percent range of "value X." For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0095] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, the interconnects may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process.

[0096] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0097] In the following, further examples are described to facilitate understanding of the present disclosure.

[0098] Aspect 1: A package comprising a substrate including a first dielectric layer, a second dielectric layer, and a third dielectric layer. The second dielectric layer is disposed between the first dielectric layer and the third dielectric layer. The second dielectric layer comprises a different material than the first dielectric layer and the third dielectric layer. The substrate includes a plurality of interconnects disposed within the first dielectric layer, the second dielectric layer, and the third dielectric layer. The package includes an integrated device coupled to the substrate.

[0099] Aspect 2: The package of aspect 1, wherein the second dielectric layer does not include a glass material, and the first dielectric layer and / or the third dielectric layer include a glass material.

[0100] Aspect 3: The package of Aspects 1 and 2, wherein the first dielectric layer and / or the third dielectric layer comprises a prepreg.

[0101] Embodiment 4: The package of Embodiments 1-3, wherein the first dielectric layer has a first thickness and the second dielectric layer has a second thickness that is less than the first thickness.

[0102] Aspect 5: The package of Aspect 4, wherein the plurality of interconnects includes: a first via interconnect disposed in a first dielectric layer, the first via interconnect having a first via thickness; and a second via interconnect disposed in a second dielectric layer, the second via interconnect having a second via thickness that is smaller than the first via thickness.

[0103] Embodiment 6: The package of Embodiments 1-5, wherein the integrated device is coupled to the first surface of the substrate via a plurality of pillar interconnects and a plurality of solder interconnects.

[0104] Embodiment 7: The package of embodiment 6, further comprising an integrated passive device coupled to the second surface of the substrate, the integrated passive device being coupled to two adjacent interconnects from the plurality of interconnects.

[0105] Aspect 8: The package of aspect 7, wherein the plurality of pillar interconnects includes two adjacent pillar interconnects having a minimum pillar interconnect pitch, and the two adjacent interconnects have a minimum pitch approximately the same as the minimum pillar interconnect pitch.

[0106] Aspect 9: The package of aspects 7 and 8, wherein the plurality of interconnects includes a first plurality of interconnects arranged in a first row of interconnects extending vertically throughout the entire substrate, and a second plurality of interconnects arranged in a second row of interconnects extending vertically throughout the entire substrate, wherein the first row of interconnects is configured to provide a first electrical path between the integrated device and the integrated passive device, and wherein the second row of interconnects is configured to provide a second electrical path between the integrated device and the integrated passive device.

[0107] Embodiment 10: The package of embodiment 9, wherein the first row of interconnects is configured to be coupled to a power source and the second row of interconnects is configured to be coupled to ground.

[0108] Aspect 11: The package of aspects 9 and 10, wherein the first row of interconnects is adjacent to the second row of interconnects, and the first row of interconnects and the second row of interconnects have a minimum pitch.

[0109] Embodiment 12: The package of any one of embodiments 1 to 11, wherein the substrate is a coreless substrate that does not include a core layer.

[0110] Aspect 13: A substrate comprising: a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects disposed within the first, second, and third dielectric layers. The second dielectric layer is disposed between the first and third dielectric layers. The second dielectric layer comprises a different material than the first and third dielectric layers.

[0111] Embodiment 14: The substrate of embodiment 13, wherein the second dielectric layer does not comprise a glass material, and the first dielectric layer and / or the third dielectric layer comprises a glass material.

[0112] Embodiment 15: The substrate of embodiments 13 and 14, wherein the first dielectric layer and / or the third dielectric layer comprises a prepreg.

[0113] Embodiment 16: The substrate of any of embodiments 13-15, wherein the first dielectric layer has a first thickness and the second dielectric layer has a second thickness that is less than the first thickness.

[0114] Embodiment 17: A substrate of embodiments 13 to 16, wherein the plurality of interconnectors includes a first row of interconnectors and a second row of interconnectors, the first row of interconnectors being adjacent to the second row of interconnectors, and the first row of interconnectors and the second row of interconnectors having a minimum pitch.

[0115] Embodiment 18: The substrate of embodiment 17, wherein each pair of interconnects from the first row of interconnects and the second row of interconnects comprises the same minimum pitch.

[0116] Embodiment 19: The substrate of any one of embodiments 13 to 18, wherein the substrate is a coreless substrate that does not include a core layer.

[0117] Aspect 20: The package of aspects 13-19, wherein the substrate is implemented within a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device within an autonomous vehicle.

[0118] Aspect 21: A method for manufacturing a package. The method includes providing a substrate comprising a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects disposed within the first, second, and third dielectric layers. The second dielectric layer is disposed between the first and third dielectric layers. The second dielectric layer comprises a different material than the first and third dielectric layers. The method includes bonding an integrated device to the substrate.

[0119] Embodiment 22: The method of embodiment 21, wherein the second dielectric layer does not comprise a glass material, and the first dielectric layer and / or the third dielectric layer comprises a glass material.

[0120] Embodiment 23: The method of embodiments 21 and 22, wherein the first dielectric layer and / or the third dielectric layer comprises a prepreg.

[0121] Embodiment 24: The method of any one of embodiments 21-23, wherein the first dielectric layer has a first thickness and the second dielectric layer has a second thickness that is less than the first thickness.

[0122] Example 25: The method of example 24, wherein the plurality of interconnects includes a first via interconnect disposed in a first dielectric layer, the first via interconnect having a first via thickness, and a second via interconnect disposed in a second dielectric layer, the second via interconnect having a second via thickness that is smaller than the first via thickness.

[0123] Various features of the present disclosure described herein can be implemented in a variety of systems without departing from the present disclosure. It should be noted that the above-described aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and is not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package, A substrate, a first dielectric layer; a second dielectric layer; and a third dielectric layer; the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer; the second dielectric layer comprises a material different from the first dielectric layer and the third dielectric layer; a substrate having a plurality of interconnects disposed within the first dielectric layer, the second dielectric layer, and the third dielectric layer; an integrated device coupled to the substrate; A package comprising:

2. the second dielectric layer does not include a glass material; the first dielectric layer and / or the third dielectric layer comprises a glass material; The package of claim 1.

3. The package of claim 1 , wherein the first dielectric layer and / or the third dielectric layer comprises a prepreg.

4. the first dielectric layer has a first thickness; the second dielectric layer having a second thickness less than the first thickness; The package of claim 1.

5. the plurality of interconnectors a first via interconnect disposed within the first dielectric layer, the first via interconnect having a first via thickness; a second via interconnect disposed within the second dielectric layer, the second via interconnect having a second via thickness less than the first via thickness.

6. The package of claim 1 , wherein the integrated device is coupled to the first surface of the substrate via a plurality of pillar interconnects and a plurality of solder interconnects.

7. 7. The package of claim 6, further comprising an integrated passive device coupled to a second surface of the substrate, the integrated passive device being coupled to two adjacent interconnects from the plurality of interconnects.

8. the plurality of pillar interconnects includes two adjacent pillar interconnects having a minimum pillar interconnect pitch; the two adjacent interconnects have a minimum pitch that is approximately the same as the minimum pillar interconnect pitch; The package of claim 7.

9. the plurality of interconnectors a first plurality of interconnects arranged in a first row of interconnects extending vertically through the entire substrate; a second plurality of interconnects arranged in a second row of interconnects extending vertically through the entire substrate; a first row of the interconnects configured to provide a first electrical path between the integrated device and the integrated passive device; The package of claim 7 , wherein the second row of interconnects is configured to provide a second electrical path between the integrated device and the integrated passive device.

10. a first row of the interconnectors configured to be coupled to a power source; a second row of the interconnectors configured to be coupled to ground; 10. The package of claim 9.

11. a first row of the interconnectors adjacent to a second row of the interconnectors; the first row of interconnects and the second row of interconnects have a minimum pitch; 10. The package of claim 9.

12. The package of claim 1 , wherein the substrate is a coreless substrate that does not include a core layer.

13. A substrate, a first dielectric layer; a second dielectric layer; and a third dielectric layer; the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer; the second dielectric layer comprises a material different from the first dielectric layer and the third dielectric layer; A substrate, wherein a plurality of interconnects are disposed within the first dielectric layer, the second dielectric layer, and the third dielectric layer.

14. the second dielectric layer does not include a glass material; the first dielectric layer and / or the third dielectric layer comprises a glass material; The substrate of claim 13.

15. The substrate of claim 13 , wherein the first dielectric layer and / or the third dielectric layer comprises a prepreg.

16. the first dielectric layer has a first thickness; the second dielectric layer having a second thickness less than the first thickness; The substrate of claim 13.

17. the plurality of interconnects includes a first row of interconnects and a second row of interconnects; a first row of the interconnectors adjacent to a second row of the interconnectors; the first row of interconnects and the second row of interconnects have a minimum pitch; The substrate of claim 13.

18. 20. The substrate of claim 17, wherein each pair of interconnects from the first row of interconnects and the second row of interconnects comprises the same minimum pitch.

19. The substrate of claim 13 , wherein the substrate is a coreless substrate that does not include a core layer.

20. 14. The substrate of claim 13, wherein the substrate is implemented in a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an autonomous vehicle.

21. 1. A method for manufacturing a package, comprising: Providing a substrate, the substrate comprising: a first dielectric layer; a second dielectric layer; and a third dielectric layer; the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer; the second dielectric layer comprises a material different from the first dielectric layer and the third dielectric layer; providing a substrate having a plurality of interconnects disposed within the first dielectric layer, the second dielectric layer, and the third dielectric layer; and bonding an integrated device to the substrate.

22. the second dielectric layer does not include a glass material; the first dielectric layer and / or the third dielectric layer comprises a glass material; 22. The method of claim 21.

23. 22. The method of claim 21, wherein the first dielectric layer and / or the third dielectric layer comprises a prepreg.

24. the first dielectric layer has a first thickness; the second dielectric layer having a second thickness less than the first thickness; 22. The method of claim 21.

25. the plurality of interconnectors a first via interconnect disposed within the first dielectric layer, the first via interconnect having a first via thickness; a second via interconnect disposed in the second dielectric layer, the second via interconnect having a second via thickness less than the first via thickness.

Images