Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes an insulating layer, a pad portion arranged on the insulating layer, a conductive metal portion arranged on the pad portion, a protective layer arranged on the conductive metal portion, and a bonding portion electrically connected to the conductive metal portion by penetrating at least a portion of the protective layer, wherein the pad portion includes a first portion inclined so that its horizontal width increases along a vertical direction from an upper surface of the pad portion to a lower surface of the insulating layer, and a second portion extending from the first portion and having a slope different from the slope of the first portion, and the conductive metal portion is arranged to cover at least a portion of a side surface of the first portion.

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor package, and more particularly to a circuit board having bonding portions with uniform heights and a semiconductor package including the same. [Background technology]

[0002] As the performance of electrical and electronic products continues to improve, technologies for arranging more semiconductor elements on a semiconductor package substrate with limited size are being proposed and researched. However, because a typical semiconductor package is designed to mount only one semiconductor element, there is a limit to how much performance can be achieved.

[0003] Recently, semiconductor packages have been developed that use multiple substrates to arrange multiple semiconductor elements. These semiconductor packages have a structure in which multiple semiconductor elements are connected to each other horizontally and / or vertically on a circuit board. This has the advantages of efficiently using the mounting area of ​​the semiconductor elements and enabling high-speed signal transmission through short signal transmission paths between the semiconductor elements.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IOT), autonomous vehicles, and high-performance servers are becoming more highly integrated, and the number of semiconductor elements and / or the size of each semiconductor element are increasing, or the functional parts of the semiconductor element are being divided, expanding the concept to semiconductor chiplets.

[0005] As a result, intercommunication between semiconductor devices and / or semiconductor chiplets has become important, and as a result, there is a trend to place an interposer between a semiconductor device and a semiconductor package substrate connected to a main board of an electronic device.

[0006] The interposer may function as a redistribution layer that gradually increases the width of a circuit pattern from the semiconductor device toward the semiconductor package in order to facilitate intercommunication between semiconductor devices and / or semiconductor chiplets or to interconnect the semiconductor device and a semiconductor package substrate, thereby facilitating electrical signal transmission between the semiconductor device and a semiconductor package substrate having a circuit pattern that is relatively larger than the circuit pattern of the semiconductor device.

[0007] Recently, as the functionality of semiconductor devices has increased and their performance has improved, the number of I / O terminals provided on semiconductor devices has also increased. As a result, the width and / or pitch of I / O terminals provided on semiconductor devices has become finer. In the process of connecting I / O terminals of semiconductor devices using a bonding material such as solder, electrical shorts may occur due to contact between multiple bonding materials. Therefore, as the density of terminals on semiconductor devices increases, fine bonding processes such as thermal compression bonding (TC bonding) can be used to reduce the amount of bonding material used. In addition, when performing a fine bonding process, the interposer and / or semiconductor package substrate may have a bonding portion to improve alignment with the terminals of the semiconductor device. The bonding portion may have a protruding bonding portion on the interposer and / or semiconductor package substrate, thereby reducing the volume of the bonding material and improving alignment with the terminals of the semiconductor device.

[0008] In this case, process deviations in the plating process for forming the bonding parts and / or differences in the horizontal width and / or area of ​​the bottom surfaces of the bonding parts may cause differences in the current applied during the plating process, which may result in changes in the plating process speed. Therefore, height deviations may occur between the bonding parts. If height deviations occur between the bonding parts, the semiconductor device may not be stably mounted, and the reliability of the electrical connection between the semiconductor device and the circuit board may be reduced. Summary of the Invention [Problem to be solved by the invention]

[0009] The embodiments provide a circuit board in which the adhesion between the insulating layer and the electrode portion is improved, and a semiconductor package including the same.

[0010] Furthermore, the examples provide a circuit board and a semiconductor package in which a uniform centerline average surface roughness Ra is imparted to the interface between the insulating layer and the electrode portion.

[0011] Furthermore, the embodiments provide a circuit board with improved electrical reliability and a semiconductor package including the same.

[0012] Further, the present invention provides a circuit board and a semiconductor package including the same, in which the chemical copper plating layer of the electrode portion and the reinforcing member in the insulating layer do not come into contact with each other.

[0013] Furthermore, the embodiments provide a circuit board in which height deviation between a plurality of bonding portions is minimized, and a semiconductor package including the same.

[0014] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0015] A circuit board according to an embodiment includes an insulating layer, a pad portion arranged on the insulating layer, a conductive metal portion arranged on the pad portion, a protective layer arranged on the conductive metal portion, and a bonding portion electrically connected to the conductive metal portion by penetrating at least a portion of the protective layer, wherein the pad portion includes a first portion inclined so that its horizontal width increases along a vertical direction from an upper surface of the pad portion to a lower surface of the insulating layer, and a second portion extending from the first portion and having a slope different from the slope of the first portion, and the conductive metal portion is arranged to cover at least a portion of a side surface of the first portion.

[0016] The bonding portion also includes a protrusion disposed on the protective layer, and a through portion extending from the protrusion and penetrating at least a portion of the protective layer to be electrically connected to the conductive metal portion.

[0017] The insulating layer includes a reinforcing member, and at least a part of a side surface of the first portion of the pad does not overlap the reinforcing member of the insulating layer along the horizontal direction.

[0018] A recess is provided in the upper surface of the insulating layer, and the first portion of the pad is disposed within the recess.

[0019] The conductive metal portion includes a metal material different from a metal material of at least one of the pad portion and the bonding portion.

[0020] The side surface of the first portion of the pad has a curved surface.

[0021] Furthermore, the through portion does not overlap the curved surface along the direction perpendicular to the curved surface.

[0022] The horizontal width of the protrusion is smaller than the width of the second portion of the pad.

[0023] The conductive metal portion also includes a contact portion that contacts the upper surface of the first portion of the pad portion, and an extension portion that extends from the contact portion and does not overlap the upper surface of the first portion along a direction perpendicular to the contact portion.

[0024] The extension overlaps the curved surface along a direction perpendicular to the curved surface.

[0025] The extension is bent from the contact portion toward the upper surface of the insulating layer and overlaps the side surface of the first portion of the pad in the horizontal direction.

[0026] The extension portion also includes a top surface, an inner surface facing the side of the first portion of the pad portion, an outer surface opposite the inner surface, and a bottom surface between the inner surface and the outer surface, and the top surface and the outer surface of the extension portion contact the protective layer.

[0027] Additionally, the bottom surface of the extension does not contact the side surface of the first portion of the pad portion.

[0028] Additionally, the bottom surface of the extension contacts the protective layer.

[0029] Additionally, the inner side surface of the extension portion contacts the side surface of the first portion of the pad portion.

[0030] Also, at least a part of the inner surface of the extension portion is in contact with the protective layer without being in contact with the side surface of the first portion of the pad portion.

[0031] Furthermore, the extension does not overlap the side surface of the first portion of the pad in the horizontal direction.

[0032] Additionally, the bottom surface of the extension portion contacts the side surface of the first portion of the pad portion.

[0033] Furthermore, the width of the through portion is smaller than the horizontal width of the conductive metal portion.

[0034] The width of the through portion is smaller than the width of the upper surface of the first portion of the pad portion.

[0035] The vertical length of the through portion is greater than the vertical length of the pad portion.

[0036] Furthermore, the vertical length of the through portion is smaller than the vertical length of the pad portion.

[0037] The circuit board further includes a connecting circuit pattern portion that overlaps the second portion of the pad portion in the horizontal direction but does not overlap the pad portion in the vertical direction, and the connecting circuit pattern portion does not overlap the second portion of the pad portion in the horizontal direction.

[0038] The insulating layer also includes a first layer including a reinforcing member and a second layer provided on the first layer and not including a reinforcing member, and at least a portion of the pad portion overlaps horizontally with the second layer.

[0039] Further, a recess is provided in the upper surface of the insulating layer, and the first and second portions of the pad are disposed within the recess.

[0040] The conductive metal portion also includes a first region disposed on the pad portion, and a second region extending from the first region to between a side surface of the first portion of the pad portion and an inner wall of the recess.

[0041] Moreover, the second region of the conductive metal portion overlaps in the horizontal direction with at least a portion of each of the first layer, the second layer, and the pad portion.

[0042] The recess includes a first part provided in the first layer of the insulating layer, and a second part provided in the second layer of the insulating layer and connected to the first part.

[0043] The upper surface of the pad portion is located lower than the upper surface of the second layer of the insulating layer.

[0044] Furthermore, a side surface of the first portion of the pad overlaps with an inner wall of the recess in the horizontal direction and is spaced apart from the inner wall of the recess.

[0045] Furthermore, the side surface of the second portion of the pad contacts the inner wall of the recess.

[0046] The conductive metal portion is provided between a side surface of the first portion of the pad portion and an inner wall of the recess.

[0047] The conductive metal portion includes a portion that protrudes above the second layer of the insulating layer, and at least a portion of the protruding portion of the conductive metal portion contacts an upper surface of the second layer of the insulating layer.

[0048] The reinforcing member is a filler contained in an organic resin, and the second insulating layer is a pure resin layer that does not contain a filler.

[0049] In addition, a first surface roughness is imparted to the upper surface of the second layer of the insulating layer, and a second surface roughness different from the first surface roughness is imparted to the interface between the first layer and the second layer of the insulating layer.

[0050] The interface is provided with a second surface roughness corresponding to the particle size of the filler contained in the first layer of the insulating layer.

[0051] The first surface roughness is a center line average surface roughness Ra in the range of 0.2 μm to 1.5 μm.

[0052] Additionally, the inner wall of the recess has a third surface roughness that is smaller than the first surface roughness.

[0053] Furthermore, the deviation of the centerline average surface roughness for each line on the top surface of the second layer of the insulating layer is smaller than the deviation of the centerline average surface roughness for each line on the interface between the first layer and the second layer.

[0054] The first layer of the insulating layer contains fillers with particle sizes different from each other, and the center line average surface roughness of the upper surface of the second layer is smaller than the average particle size of the fillers. [Effects of the Invention]

[0055] The circuit board of the embodiment can minimize height deviations between a plurality of bonding portions connected with a coupling member. Specifically, the circuit board of the embodiment can include a pad portion. The pad portion can include a first portion embedded in an insulating layer and a second portion disposed on the first portion and protruding above the insulating layer. The circuit board can also include a connecting circuit pattern portion corresponding to traces that overlap horizontally with the first portions of the pad portions. In this case, the second portions of the pad portions can serve as a seed layer for forming the first portions of the pad portions and the connecting circuit pattern portion by electroplating.

[0056] Specifically, in conventional circuit boards, the copper foil layer used as a seed layer is entirely removed. This increases the thickness of the bonding portion provided on the pad portion. This can result in height variations between the horizontally spaced bonding portions in conventional circuit boards. Therefore, when bonding a semiconductor device to the bonding portion, the semiconductor device may not be stably positioned on the bonding portion and may be bonded in a tilted state in a specific direction due to the height differences between the bonding portions. In contrast, in the embodiment, a portion of the copper foil layer used as a seed layer where the bonding portion is to be disposed may not be removed. This allows the pad portion to have a second portion, which is the portion of the unremoved copper foil layer. In this case, the upper surface of the second portion of the pad portion may refer to the upper surface of the copper foil layer initially disposed on the carrier member during the substrate manufacturing process. Therefore, the upper surface of the second portion of the pad portion may be flat. Furthermore, the upper surfaces of the second portions of the multiple pad portions may be coplanar with each other. Therefore, in the embodiment, by disposing the bonding part on the second portion of the pad part, the plurality of bonding parts can be formed with a uniform thickness and / or height. Furthermore, in the embodiment, the thickness of the bonding part can be reduced by the thickness of the second portion of the pad part. As a result, the embodiment can solve the problem of thickness deviation between the plurality of bonding parts increasing in proportion to the thickness of the bonding part. As a result, the embodiment can minimize height deviation between the plurality of bonding parts. Therefore, the embodiment can stably dispose semiconductor devices on the plurality of bonding parts. Furthermore, in the embodiment, the thickness of the bonding part can be increased by the thickness of the second portion of the pad part compared to the thickness of a conventional bonding part. Furthermore, in the embodiment, by forming the bonding part using the pad part having a uniform height, the thickness deviation between the plurality of bonding parts can be minimized even when the thickness of the bonding part is increased.

[0057] As a result, the embodiment can ensure a bonding part height that can stably bond a semiconductor device, thereby improving the overall physical and / or electrical characteristics of the semiconductor package, thereby facilitating smooth operation of the semiconductor device, and further facilitating smooth operation of servers and electronic products.

[0058] In addition, the bonding portion may include a through portion penetrating at least a portion of the protective layer from the upper surface thereof, and a bonding portion disposed on the through portion and protruding above the protective layer. The second portion of the pad portion may include a curved side surface. The through portion of the bonding portion may vertically overlap the curved side surface of the pad portion. Therefore, in the embodiment, when forming the through portion of the bonding portion, the through portion may be disposed biased to one side on the pad portion. As a result, the embodiment may increase the spacing between adjacent through portions and between adjacent bonding portions. In the embodiment, increasing the spacing between the bonding portions may increase the amount of bonding material disposed on the bonding portion, thereby improving the bonding strength between the semiconductor device and the substrate.

[0059] In addition, the conductive metal portion of the bonding portion may include a contact portion that overlaps a top surface of the pad portion in a vertical direction and an extension portion that overlaps a side surface of the pad portion having a curvature in a vertical direction. The extension portion may be bent from the contact portion in a bending direction corresponding to the curvature of the side surface of the pad portion. In this manner, the embodiment may increase the contact area between the protective layer and the pad portion using the extension portion, thereby improving the bonding strength between the protective layer and the pad portion.

[0060] In addition, at least a portion of the inner surface of the extension of the conductive metal portion may not contact the side of the pad portion. Thus, a certain gap may be provided between the side of the pad portion and the inner surface of the extension. The protective layer may be provided by filling the gap. The gap may function as an anchor that improves bonding strength with the protective layer. Thus, the embodiment may improve adhesion between the insulating layer and the protective layer and between the protective layer and the bonding portion.

[0061] In another embodiment, the insulating layer may include a first layer including a reinforcing member and a second layer on the first layer. The first layer of the insulating layer may include a reinforcing member such as a filler, while the second layer may not include a reinforcing member, e.g., a pure resin layer. This allows the embodiment to improve the electrical characteristics of the electrode portion while ensuring adhesion between the insulating layer and the circuit layer. Specifically, the insulating layer of the comparative example includes only the first layer, which is entirely covered with a reinforcing member, resulting in a problem of the reinforcing member in contact with the circuit layer. When the circuit layer contacts the filler, adhesion at the contact point decreases, and the physical properties of the reinforcing member increase transmission loss of signals transmitted through the circuit layer, resulting in degraded electrical characteristics. Furthermore, reducing the content of the reinforcing member in the insulating layer to address this issue may reduce the rigidity of the circuit board. A reduced rigidity of the circuit board may result in a reliability issue, such as significant warping in a specific direction.

[0062] Therefore, in the embodiment, the insulating layer is divided into a first layer and a second layer, thereby ensuring adhesion between the electrode portion and the insulating layer and improving the electrical characteristics of the electrode portion. To this end, the first insulating layer may be made of an organic material including a reinforcing member. This allows the first layer to ensure the rigidity of the insulating layer and enable the electrode portion to be stably disposed on the insulating layer. The second insulating layer may be provided on the first insulating layer. The second insulating layer may not include a reinforcing member, and the electrode portion may be disposed on the second insulating layer. For example, the electrode portion may be in contact with the second insulating layer. In this case, the second insulating layer may not include a reinforcing member, and therefore the electrode portion may not be in contact with the reinforcing member. Therefore, the embodiment may improve adhesion between the electrode portion and the insulating layer. Furthermore, the embodiment may improve the electrical characteristics of the electrode portion.

[0063] In addition, the electrode portion of the embodiment includes a lower wiring electrode, and the lower wiring electrode may include a first metal layer of a chemical copper plating layer. In this case, the insulating layer may include a third layer below the first layer, and the third insulating layer may not include a reinforcing member. The lower surface of the third layer may be provided with a certain level of centerline average surface roughness Ra. As a result, the embodiment may improve the adhesion between the first metal layer of the lower wiring electrode and the insulating layer. In this case, the first metal layer of the embodiment does not contact the first insulating layer. That is, the first metal layer does not contact the reinforcing member provided on the first insulating layer. Through this, the embodiment may solve the problem of the reinforcing member reducing the adhesion between the first metal layer and the insulating layer. Furthermore, the embodiment may prevent the reinforcing member from increasing transmission loss of signals passing through the first metal layer. Through this, the embodiment may improve the physical reliability and electrical reliability of the circuit board.

[0064] In addition, in some embodiments, the insulating layer may include a first layer and a second layer, thereby providing a uniform surface roughness to the upper surface of the second layer. As a result, the conductive metal portions and / or bonding portions may have a uniform thickness. Specifically, in some embodiments, the conductive metal portions and / or bonding portions may be disposed on the second layer of the insulating layer, which has a uniform surface roughness, thereby providing a uniform thickness to the conductive metal portions and / or bonding portions that are horizontally spaced apart from one another. As a result, the embodiments may provide a stable bond between the semiconductor device and the conductive metal portions and / or bonding portions. Therefore, the embodiments may improve the operational characteristics of the semiconductor device and products including the semiconductor device. [Brief explanation of the drawings]

[0065] [Figure 1a] 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 1b] FIG. 10 is a cross-sectional view showing a semiconductor package according to a second embodiment. [Figure 1c] FIG. 10 is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 1d] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. [Figure 1e] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fifth embodiment. [Figure 1f] FIG. 10 is a cross-sectional view showing a semiconductor package according to a sixth embodiment. [Figure 1g] FIG. 13 is a cross-sectional view showing a semiconductor package according to a seventh embodiment. [Figure 2] FIG. 1 is a cross-sectional view showing a circuit board according to a first embodiment. [Figure 3] 3 is a plan view of a first electrode provided on the uppermost side of the first insulating layer of FIG. 2. FIG. [Figure 4-5] 3 is an enlarged view of a partial area of ​​the circuit board provided in FIG. 2. FIG. [Figure 6] 3 is an enlarged view showing a first modified example of the circuit board of FIG. 2. FIG. [Figure 7] 3 is an enlarged view showing a second modified example of the circuit board of FIG. 2. FIG. [Figure 8] 2. FIG. 4 is an enlarged view showing a third modified example of the circuit board of FIG. [Figure 9] 2. FIG. 6 is an enlarged view showing a fourth modified example of the circuit board of FIG. [Figure 10] 2. FIG. 9 is an enlarged view showing a fifth modified example of the circuit board of FIG. [Figure 11] 2. FIG. 9 is an enlarged view showing a sixth modified example of the circuit board of FIG. [Figure 12-23] 3A to 3C are cross-sectional views showing a method for manufacturing the circuit board shown in FIG. 2 in the order of steps. [Figure 24] FIG. 10 is a cross-sectional view showing a circuit board according to a second embodiment. [Figure 25] 25 is an optical microscope photograph showing the interface of an insulating layer provided on the circuit board of the embodiment of FIG. 24. [Figure 26] FIG. 25 is a cross-sectional view showing a state before a conductive metal portion is disposed in one region of FIG. 24. [Figure 27] FIG. 27 is a diagram showing the state after the conductive metal part is placed in FIG. 26. [Figure 28] 25 is a diagram showing a detailed layer structure of a lower wiring electrode in the circuit board of FIG. 24. FIG. [Figure 29] FIG. 10 is a cross-sectional view showing a circuit board according to a third embodiment. [Figure 30] FIG. 10 is a cross-sectional view showing a circuit board according to a fourth embodiment. [Figure 31] FIG. 10 is a cross-sectional view showing a circuit board according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0066] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0067] However, the technical concept of the present invention is not limited to the described embodiments, but may be embodied in various different forms, and one or more of the components of the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0068] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as meanings commonly understood by those of ordinary skill in the art to which the present invention belongs, and commonly used terms such as predefined terms may be interpreted in light of the contextual meaning of the relevant art. Furthermore, the terms used in the embodiments of the present invention are intended to describe the embodiments and do not limit the present invention.

[0069] In this specification, unless otherwise stated in the phrase, the singular can also include the plural, and when referring to "A and (and) at least one (or more) of B and C," it can include one or more of all possible combinations of A, B, and C. Furthermore, terms such as first, second, A, B, (a), (b), etc. can be used to describe components of the present invention.

[0070] Such terms are used merely to distinguish a component from other components, and are not intended to limit the essence, order, or sequence of the components. When a component is described as being "coupled," "coupled," or "connected" to another component, it can include not only a case where the component is directly coupled, coupled, or connected to the other component, but also a case where the component is "coupled," "coupled," or "connected" by another component between the component and the other component.

[0071] Furthermore, when it is stated that something is formed or placed "above or below" each component, "above" or "below" not only refers to the case where two components are in direct contact with each other, but also includes the case where one or more other components are formed or placed between the two components. Furthermore, when it is expressed as "above" or "below," it can mean not only the upward direction based on one component, but also the downward direction.

[0072] -Electronic Devices-

[0073] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments can be applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various semiconductor elements may be mounted in the semiconductor package.

[0074] The semiconductor device may include active and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0075] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and other memory chips.

[0076] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0077] The electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0078] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package according to the embodiment may have various package structures including the circuit board described below.

[0079] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, and Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0080] Referring to FIG. 1 a, the semiconductor package of the first embodiment may include a first circuit board 10 , a second circuit board 20 , and a semiconductor device 30 .

[0081] The first circuit board 10 may refer to a semiconductor package substrate.

[0082] For example, the first circuit board 10 may provide a space to which at least one external circuit board is coupled. The external circuit board may refer to the second circuit board 20 coupled on the first circuit board 10. The external circuit board may also refer to a main board included in an electronic device coupled to the lower part of the first circuit board 10.

[0083] Although not shown in the drawings, the first circuit board 10 may provide a space in which at least one semiconductor element is mounted.

[0084] The first circuit board 10 can include at least one insulating layer, a circuit pattern layer disposed on the at least one insulating layer, and a through electrode that penetrates the at least one insulating layer.

[0085] A second circuit board 20 may be disposed on the first circuit board 10 .

[0086] The second circuit board 20 may be an interposer. For example, the second circuit board 20 may provide a space in which at least one semiconductor element is mounted. The second circuit board 20 may be connected to at least one semiconductor element 30. For example, the second circuit board 20 may provide a space in which a first semiconductor element 31 and a second semiconductor element 32 are mounted. The second circuit board 20 may electrically connect the first semiconductor element 31 and the second semiconductor element 32, and may also electrically connect the first and second semiconductor elements 31 and 32 to the first circuit board 10. That is, the second circuit board 20 may function as a horizontal connection between multiple semiconductor elements and a vertical connection between the semiconductor element and a package substrate.

[0087] 1a illustrates two semiconductor elements 31 and 32 disposed on the second circuit board 20, but is not limited to this. For example, one semiconductor element may be disposed on the second circuit board 20, or alternatively, three or more semiconductor elements may be disposed on the second circuit board 20.

[0088] The second circuit board 20 can be disposed between at least one or more semiconductor elements 30 and the first circuit board 10 .

[0089] In one embodiment, the second circuit board 20 may be an active interposer that functions as a semiconductor device. When the second circuit board 20 functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first circuit board 10 and may have the functions of multiple logic chips. Having the functions of a logic chip may mean having the functions of both active and passive devices. Unlike passive devices, active devices do not need to have linear current-voltage characteristics. An active interposer may have the functions of an active device. Furthermore, the active interposer may perform the functions of a logic chip while also transmitting signals between the first circuit board 10 and a second logic chip disposed thereon.

[0090] According to another embodiment, the second circuit board 20 may be a passive interposer. For example, the second circuit board 20 may function as a signal relay between the semiconductor device 30 and the first circuit board 10 and may have passive element functions such as a resistor, capacitor, or inductor. For example, the number of terminals on the semiconductor device 30 is gradually increasing due to factors such as 5G, the Internet of Things (IOT), improved image quality, and increased communication speed. That is, the number of terminals provided on the semiconductor device 30 is increasing, and as a result, the width of the terminals and the spacing between the terminals are decreasing. In this case, the first circuit board 10 may be connected to a main board of an electronic device. Therefore, in order to ensure that the electrodes provided on the first circuit board 10 have the width and spacing required to be connected to the semiconductor device 30 and the main board, respectively, the thickness of the first circuit board 10 would increase or the layer structure of the first circuit board 10 would become complex. Therefore, in the first embodiment, the second circuit board 20 is disposed on the first circuit board 10 and the semiconductor device 30. The second circuit board 20 may include electrodes having fine widths and intervals corresponding to the terminals of the semiconductor element 30 .

[0091] The semiconductor package includes a first coupling member 41 disposed between the first circuit board 10 and the second circuit board 20. The first coupling member 41 couples the second circuit board 20 to the first circuit board 10 and electrically connects them.

[0092] The semiconductor package may include a second coupling member 42 disposed between the second circuit board 20 and the semiconductor element 30. The second coupling member 42 may couple the semiconductor element 30 onto the second circuit board 20 and electrically connect them together.

[0093] The semiconductor package includes a third coupling member 43 disposed on the lower surface of the first circuit board 10. The third coupling member 43 couples the first circuit board 10 to the main board and electrically connects them.

[0094] In this case, the first coupling member 41, the second coupling member 42, and the third coupling member 43 can electrically connect the multiple components using at least one bonding method of wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first coupling member 41, the second coupling member 42, and the third coupling member 43 have the function of electrically connecting the multiple components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as the electrically connected part, rather than the solder or wire.

[0095] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material containing at least one of Sn, Ag, and Cu. The inter-metal direct bonding method may refer to directly bonding multiple components through recrystallization by applying heat and pressure between the multiple components without using solder, wire, conductive adhesive, or other materials. The inter-metal direct bonding method may refer to a bonding method using a second bonding member 42. In this case, the second bonding member 42 may refer to a metal layer formed between the multiple components through recrystallization.

[0096] Specifically, the first connecting member 41, the second connecting member 42, and the third connecting member 43 can connect multiple components to each other using a TC (Terminal Compression) bonding method. The TC bonding method may refer to a method of directly bonding multiple components by applying heat and pressure to the first connecting member 41, the second connecting member 42, and the third connecting member 43.

[0097] In this case, bonding portions may be disposed on the electrodes on which the first coupling member 41, the second coupling member 42, and the third coupling member 43 are disposed in at least one of the first circuit board 10 and the second circuit board 20. The bonding portions may protrude outward from the first circuit board 10 or the second circuit board 20.

[0098] The bonding portion may be referred to as a bump, a post, or a pillar. Preferably, the bonding portion may refer to an electrode of the second circuit board 20 on which a second coupling member 42 for coupling to the semiconductor device 30 is disposed. That is, as the pitch of the terminals of the semiconductor device 30 becomes finer, short circuits may occur between the second coupling members 42, which are respectively connected to the terminals of the semiconductor device 30 by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second coupling members 42. In addition, the bonding portion may be included in the electrode of the second circuit board 20 on which the second coupling member 42 is disposed to ensure compatibility, diffusion strength, and diffusion prevention strength that prevents intermetallic compounds (IMCs) formed between the conductive adhesive such as solder and the bonding portion from diffusing into the interposer and / or circuit board.

[0099] Referring to FIG. 1B, the semiconductor package of the second embodiment may differ from the semiconductor package of the first embodiment in that a connecting member 21 is disposed on a second circuit board 20. Recently, as the number of signals that semiconductor devices must process increases, the size of semiconductor devices tends to increase. However, this increase in the area of ​​semiconductor devices reduces the yield of semiconductor devices. Therefore, there is a trend to divide the pattern size or functional portion of a semiconductor device, arrange chiplets on a circuit board, and embed a connecting member 21, which functions to electrically connect them, within the circuit board. However, the connecting member 21 is not limited to this and may also connect a semiconductor device to a semiconductor device having another function, such as a memory. For example, the connecting member 21 may include a redistribution layer. The connecting member 21 may function to electrically connect multiple semiconductor devices horizontally. For example, since the area required for a semiconductor device is generally too large, the connecting member 21 may include a redistribution layer. Since there is a large difference between the width of the circuit pattern of a semiconductor package and that of a semiconductor device, a buffer for the circuit pattern is required for electrical connection. The buffering function may mean having an intermediate size between the width of the circuit pattern of the semiconductor package and the width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0100] In one embodiment, the connecting member 21 may include a silicon material, and may include a silicon circuit substrate and a redistribution layer disposed on the silicon circuit substrate.

[0101] In other embodiments, the connecting member 21 may include an organic material, for example, the connecting member 21 may include an organic circuit board that includes an organic material instead of a silicon circuit board.

[0102] The connecting member 21 may be embedded in the second circuit board 20, but is not limited to this. For example, the connecting member 21 may be arranged to have a protruding structure on the second circuit board 20. Furthermore, the second circuit board 20 may include a cavity, and the connecting member 21 may be arranged in the cavity of the second circuit board 20. The connecting member 21 may horizontally connect between multiple semiconductor elements arranged on the second circuit board 20.

[0103] 1c, the semiconductor package of the third embodiment may include a second circuit board 20 and a semiconductor device 30. In this regard, the semiconductor package of the third embodiment has a structure in which the first circuit board 10 is removed compared to the semiconductor package of the second embodiment.

[0104] That is, the second circuit board 20 of the third embodiment can function as both an interposer and a package substrate.

[0105] The first coupling member 41 disposed on the underside of the second circuit board 20 can couple the second circuit board 20 to the main board of the electronic device.

[0106] Referring to FIG. 1 d, the semiconductor package of the fourth embodiment may include a first circuit board 10 and a semiconductor device 30 .

[0107] In this case, the semiconductor package of the fourth embodiment has a structure in which the second circuit board 20 is removed, as compared with the semiconductor package of the second embodiment.

[0108] That is, the first circuit board 10 of the fourth embodiment can function as a package substrate and also as a connection between the semiconductor devices 30 and the main board. To this end, the first circuit board 10 can include a connecting member 11 for connecting between the plurality of semiconductor devices. The connecting member 11 can be a silicon bridge or an organic bridge for connecting between the plurality of semiconductor devices.

[0109] Referring to FIG. 1e, the semiconductor package of the fifth embodiment further includes a third semiconductor element 33 compared to the semiconductor package of the fourth embodiment.

[0110] For this purpose, a fourth coupling member 44 may be disposed on the lower surface of the first circuit board 10. A third semiconductor element 33 may be disposed on the fourth coupling member 44. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor elements are mounted on both the upper and lower sides.

[0111] In this case, the third semiconductor element 33 may have a structure in which it is disposed on the lower surface of the second circuit board 20 in the semiconductor package of FIG. 1c.

[0112] Referring to FIG. 1f, the semiconductor package of the sixth embodiment includes a first circuit board 10.

[0113] A first semiconductor element 31 may be disposed on the first circuit board 10. To this end, a first coupling member 41 may be disposed between the first circuit board 10 and the first semiconductor element 31.

[0114] The first circuit board 10 may also include a conductive coupling part 45. The conductive coupling part 45 may further protrude from the first circuit board 10 toward the second semiconductor device 32. The conductive coupling part 45 may be referred to as a bump, or alternatively as a post. The conductive coupling part 45 may be disposed in a protruding structure on an electrode disposed on the top side of the first circuit board 10.

[0115] The second semiconductor element 32 may be disposed on the conductive coupling part 45. At this time, the second semiconductor element 32 may be connected to the first circuit board 10 via the conductive coupling part 45. In addition, a second coupling member 42 may be disposed on the first semiconductor element 31 and the second semiconductor element 32.

[0116] As a result, the second semiconductor element 32 can be electrically connected to the first semiconductor element 31 via the second coupling member 42 .

[0117] That is, the second semiconductor element 32 may be connected to the first circuit board 10 through the conductive coupling portion 45 and also connected to the first semiconductor element 31 through the second coupling member 42 .

[0118] At this time, the second semiconductor element 32 may be supplied with a power signal and / or power via the conductive coupling member 45. In addition, the second semiconductor element 32 may transmit and receive communication signals to and from the first semiconductor element 31 via the second coupling member 42.

[0119] The semiconductor package of the sixth embodiment supplies a power signal and / or power to the second semiconductor element 32 via the conductive coupling portion 45, thereby providing sufficient power to drive the second semiconductor element 32 and enabling smooth control of power supply operation.

[0120] As a result, the embodiment can improve the driving characteristics of the second semiconductor device 32. That is, the embodiment can solve the problem of insufficient power provided to the second semiconductor device 32. Furthermore, the embodiment allows at least one of the power signal, power, and communication signal of the second semiconductor device 32 to be provided via different paths via the conductive coupling part 45 and the second coupling member 42. As a result, the embodiment can solve the problem of loss of the communication signal due to the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0121] Meanwhile, in the sixth embodiment, the second semiconductor device 32 may be arranged on the first circuit board 10 in a package-on-package (POP) structure in which a plurality of package circuit boards are stacked. For example, the second semiconductor device 32 may be a memory package including a memory chip. The memory package may be coupled to the conductive coupling part 45. In this case, the memory package may not be connected to the first semiconductor device 31.

[0122] Meanwhile, the semiconductor package in the sixth embodiment may include a molding member 46. The molding member 46 may be disposed between the first circuit board 10 and the second semiconductor element 32. For example, the molding member 46 may mold the first coupling member 41, the second coupling member 42, the first semiconductor element 31, and the conductive coupling portion 45.

[0123] 1g, the semiconductor package of the seventh embodiment may include a first circuit board 10, a first coupling member 41, a semiconductor device 30, and a third coupling member 43. The semiconductor package of the seventh embodiment differs from the semiconductor package of the fourth embodiment in that the connecting member 11 is removed and the first circuit board 10 includes multiple substrate layers.

[0124] The first circuit board 10 may include multiple substrate layers, such as a first circuit board layer 10A corresponding to a package substrate and a second circuit board layer 10B corresponding to a connecting member.

[0125] In other words, the semiconductor package of the seventh embodiment may include a first circuit board layer 10A and a second circuit board layer 10B in which the first circuit board 10 (package substrate) and the second circuit board 20 (interposer) shown in FIG. 1A are integrally formed. The material of the insulating layer of the second circuit board layer 10B may be different from the material of the insulating layer of the first circuit board layer 10A. For example, the material of the insulating layer of the second circuit board layer 10B may include a photo-curable material. For example, the second circuit board layer 10B may be a PID (Photo Imageable Dielectric). Furthermore, the second circuit board layer 10B may include a photo-curable material, thereby enabling miniaturization of electrodes. Therefore, in the seventh embodiment, the second circuit board layer 10B may be formed by sequentially stacking insulating layers of a photo-curable material on the first circuit board layer 10A and then forming miniaturized electrodes on the insulating layers of the photo-curable material. Thus, the second circuit board layer 10B may have a function of a rewiring layer including miniaturized electrodes and a function of connecting the plurality of semiconductor elements 31 and 32 horizontally.

[0126] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals, the same or corresponding components are denoted by the same reference numerals, and redundant description thereof will be omitted.

[0127] 2a is a cross-sectional view showing a circuit board according to the first embodiment, FIG. 3 is a plan view of a first electrode provided on the top side of the insulating layer of FIG. 2, FIGS. 4 and 5 are enlarged views of a partial area of ​​the circuit board provided in FIG. 2, FIG. 6 is an enlarged view showing a first modified example of the circuit board of FIG. 2, FIG. 7 is an enlarged view showing a second modified example of the circuit board of FIG. 2, FIG. 8 is an enlarged view showing a third modified example of the circuit board of FIG. 2, FIG. 9 is an enlarged view showing a fourth modified example of the circuit board of FIG. 2, FIG. 10 is an enlarged view showing a fifth modified example of the circuit board of FIG. 2, and FIG. 11 is an enlarged view showing a sixth modified example of the circuit board of FIG. 2.

[0128] The substrate of the embodiment will be specifically described below with reference to FIGS.

[0129] 2a, the circuit board 100 may include an insulating substrate 110. Specifically, the insulating substrate 110 may refer to a layer including an insulating material among the components of the circuit board 100, and may include, for example, an insulating layer 111, a first protective layer 112, and a second protective layer 113.

[0130] The insulating layer 111 may be a layer provided for interlayer insulation between the wiring electrode 120 and the via electrode 130. The first protective layer 112 may be an upper protective layer disposed on the insulating layer 111, and the second protective layer 113 may be a lower protective layer disposed below the insulating layer 111. The first protective layer 112 and the second protective layer 113 may include a different material from the insulating layer 111, and may include a solder resist, for example.

[0131] The insulating layer 111 may have a structure in which multiple layers are stacked in the vertical direction. For example, as shown in FIG. 2, the circuit board 100 may have a two-layer structure based on the number of insulating layers 111, but is not limited to this. The circuit board 100 of one embodiment may have less than two layers based on the number of insulating layers 111. The circuit board 100 of another embodiment may have three or more layers based on the number of insulating layers 111. Preferably, the circuit board 100 of the embodiment may have five or more, seven or more, or nine or more layers based on the number of insulating layers 111.

[0132] When the insulating layer 111 has a multi-layer structure, the multiple insulating layers 111 may contain the same insulating material, but are not limited to this. For example, at least one of the multiple insulating layers 111 may contain an insulating material different from at least the other layers.

[0133] The insulating layer 111 is disposed for vertical insulation between wiring electrodes, which will be described later. Exemplarily, a thermosetting insulating material containing an inorganic filler in a resin may be used as the insulating layer 111, and one example is Ajinomoto Build-up Film (ABF) from Ajinomoto Co., Inc. However, the embodiment is not limited thereto, and a photo-curable insulating material, photo-imageable dielectric resin (PID), for forming a fine pattern may be used.

[0134] A first protective layer 112 may be disposed on the upper surface of the insulating layer 111, and a second protective layer 113 may be disposed on the lower surface of the insulating layer 111.

[0135] The first protective layer 112 can protect the upper surface of the wiring electrode 120 and / or the insulating layer 111 (described later) from external moisture and contaminants. Furthermore, when a semiconductor device is disposed on the circuit board 100 using a material such as solder, the first protective layer 112 functions to prevent short circuits between the solder due to its low wettability with the solder. The first protective layer 112 can be made of a photo-curable insulating material, e.g., solder resist. However, the embodiment is not limited thereto, and the first protective layer 112 can be made of a thermosetting insulating material, which is the same insulating material as the insulating layer 111. The first protective layer 112 can be made of the same insulating material as the insulating layer 111, and can be provided, for example, as Ajinomoto Build-up Film (ABF) from Ajinomoto Co.

[0136] The circuit board 100 may include an electrode portion 150 .

[0137] The electrode portion 150 may be disposed on the insulating substrate 110. For example, the electrode portion 150 may penetrate the insulating substrate 110. For example, a portion of the electrode portion 150 may be disposed within the insulating substrate 110, and at least a remaining portion may protrude above or below the surface of the insulating substrate 110.

[0138] The electrode section 150 may include multiple electrodes depending on their positions or functions.

[0139] For example, the electrode unit 150 may include a wiring electrode 120 and a via electrode 130. The wiring electrode 120 may be disposed on the surface of the insulating layer 111. For example, the wiring electrode 120 may be disposed on the upper surface and / or lower surface of the insulating layer 111. For example, when the insulating layer 111 includes a first insulating layer and a second insulating layer, the wiring electrode 120 may include a first wiring layer disposed on the upper surface of the first insulating layer, a second wiring layer provided between the first insulating layer and the second insulating layer, and a third wiring layer disposed on the lower surface of the second insulating layer.

[0140] The via electrodes 130 can connect the wiring electrodes 120 arranged on different layers along the vertical direction of the circuit board 100. For example, if the insulating layer 111 has a three-layer structure, the via electrodes 130 can be spaced apart from each other along the vertical direction and arranged on each of the insulating layers 111 of the three-layer structure.

[0141] Any one of the plurality of wiring electrodes 120 arranged on different layers may have an ETS (Embedded Trace Substrate) structure. For example, the wiring electrode 120 arranged on the uppermost side of the circuit board 100 may have the ETS structure. Here, the wiring electrode 120 having the ETS structure may mean that at least a portion of the uppermost wiring electrode 120 has an embedded structure embedded in the insulating layer 111. That is, the embedded structure may mean that at least a portion of the wiring electrode 120 overlaps the insulating layer 111 in the horizontal direction. For example, the embedded structure may mean that the lower surface and / or the upper surface of the wiring electrode 120 is located closer to the lower surface of the insulating layer 111 than the upper surface of the insulating layer 111. Furthermore, the embedded structure may mean that the lower surface and / or the upper surface of the wiring electrode 120 is located closer to the lower surface of the second protective layer 113 located below the insulating layer 111 than the upper surface of the insulating layer 111.

[0142] The ETS structure is advantageous for miniaturization compared to wiring electrodes having a general protruding structure. Therefore, the embodiment allows wiring electrodes to be formed according to the size and pitch of terminals provided on a semiconductor device. This allows the embodiment to improve circuit integration. Furthermore, the embodiment allows the embodiment to minimize the transmission distance of signals transmitted through a semiconductor device, thereby minimizing signal transmission loss.

[0143] In particular, the wiring electrode 120 may include a pad portion 120P and a connecting circuit pattern portion 120T depending on the position and / or function.

[0144] The pad portion 120P may refer to a wiring electrode that is vertically overlapped with the bonding portion 140 among the wiring electrodes 120 arranged on the uppermost side of the circuit board 100. For example, the pad portion 120P may refer to a wiring electrode that is in direct contact with the bonding portion 140.

[0145] The connecting circuit pattern portion 120T may refer to the remaining electrodes of the wiring electrode 120 excluding the pad portions 120P. For example, the connecting circuit pattern portion 120T may refer to electrodes electrically connecting the plurality of pad portions 120P. For example, the connecting circuit pattern portion 120T may refer to traces connecting the plurality of pad portions 120P.

[0146] The pad portion 120P may be divided into a plurality of parts. For example, the pad portion 120P may include a first portion 121 that overlaps the connecting circuit pattern portion 120T in the horizontal direction. The first portion 121 of the pad portion 120P may be embedded in the insulating layer 111. For example, the side surfaces of the first portion 121 of the pad portion 120P may be covered with the insulating layer 111. The pad portion 120P may include a second portion 122 provided on the first portion 121. The second portion 122 of the pad portion 120P may refer to a portion of the entire area of ​​the pad portion 120P that is disposed on the insulating layer 111.

[0147] In this case, the first portion 121 and the second portion 122 of the pad portion 120P may be formed through a plurality of separate processes. For example, the second portion 122 of the pad portion 120P may be a copper foil layer. For example, the second portion 122 of the pad portion 120P may be a seed layer for electroplating the first portion 121 of the pad portion 120P and the connecting circuit pattern portion 120T. That is, the first portion 121 of the pad portion 120P and the connecting circuit pattern portion 120T may be electroplated layers formed by electroplating using the second portion 122 of the pad portion 120P as a seed layer.

[0148] In this case, the conventional circuit board entirely removes the copper foil layer used as a seed layer. This increases the thickness of the bonding part provided on the electrode in the conventional circuit board. As a result, the conventional circuit board may have a difference in height between the bonding parts spaced apart in the horizontal direction. Therefore, when bonding a semiconductor device to the bonding part, the conventional circuit board may bond the semiconductor device in a tilted state in a specific direction due to the difference in height between the bonding parts.

[0149] In contrast, in the embodiment, a portion of the copper foil layer used as a seed layer where the bonding portion 140 is to be disposed may not be removed. The unremoved portion of the copper foil layer may constitute the second portion 122 of the pad portion 120P. The upper surface of the second portion 122 of the pad portion 120P may refer to the upper surface of the copper foil layer that is first disposed on the carrier member during the substrate manufacturing process. As a result, the upper surface of the second portion 122 of the pad portion 120P may be flat. Furthermore, the upper surfaces of the second portions 122 of the multiple pad portions 120P may be located on the same plane. Therefore, in the embodiment, the bonding portion 140 may be disposed on the second portion 122 of the pad portion 120P, thereby forming the multiple bonding portions 140 with a uniform thickness. Furthermore, in the embodiment, the thickness of the bonding portion 140 may be reduced by the thickness of the second portion 122 of the pad portion 120P. As a result, the embodiment may solve the problem of thickness deviation increasing in proportion to the thickness of the bonding portion 140. As a result, the embodiment can minimize height deviations between the plurality of bonding parts 140. Therefore, the embodiment can stably place semiconductor devices on the plurality of bonding parts 140. Furthermore, the embodiment can increase the thickness of the bonding part 140 by the thickness of the second part 122 of the pad part 120P compared to the thickness of a conventional bonding part. As a result, the embodiment can ensure a height of the bonding part that can stably bond the semiconductor device, thereby improving the overall physical and / or electrical characteristics of the semiconductor package. This can facilitate smooth operation of the semiconductor device, and further facilitate smooth operation of servers and electronic products.

[0150] The first portion 121 and the second portion 122 of the pad portion 120P may include the same metal material. As a result, it may be difficult to distinguish the interface between the first portion 121 and the second portion 122 of the pad portion 120P. Therefore, the first portion 121 and the second portion 122 of the pad portion 120P may have a structure in which they are integrally formed. However, the embodiment is not limited thereto. If it is possible to distinguish the interface between the first portion 121 and the second portion 122 of the pad portion 120P, the pad portion 120P may have a two-layer structure including the first portion 121 and the second portion 122.

[0151] The pad portion 120P may include a region whose width varies in the vertical direction. The pad portion 120P may include a region whose width increases from the upper surface to the lower surface. Specifically, the first portion 121 and the second portion 122 of the pad portion 120P may have different vertical cross-sectional shapes. The first portion 121 of the pad portion 120P may be formed by an electrolytic plating process. The second portion 122 of the pad portion 120P may be formed by an etching process. For example, the second portion 122 of the pad portion 120P may be formed by a dry etching and / or wet etching process. Although it may be difficult to distinguish the interface between the first portion 121 and the second portion 122 of the pad portion 120P, such distinction may be possible based on the shape of the side surface of the pad portion 120P. For example, the pad portion 120P may include a side surface 122S having a curvature and / or slope along the vertical direction formed by etching. The curvature-provided side surface 122S may also be provided on the second portion 122. The side surface of the first portion 121 may not have a curvature. Thus, in this embodiment, the first portion 121 and the second portion 122 of the pad portion 120P may be distinguished from each other by the side surface 122S having a curvature. Here, having a curvature may mean having a slope in which the width changes (e.g., increases or decreases) along the vertical direction, and not having a curvature may mean that there is almost no change in width along the vertical direction.

[0152] The pad portion 120P may include a first side surface adjacent to the lower surface and having a first slope. The first side surface may refer to a side surface of the first portion 121 of the pad portion 120P. The first slope of the first side surface may be perpendicular to the upper surface of the pad portion 120P. For example, the interior angle between the first side surface and the upper surface of the pad portion 120P may be in the range of 85 to 95 degrees. The pad portion 120P may also include a second side surface 122S adjacent to the upper surface and having a second slope different from the first slope. The second side surface may refer to the side surface 122S of the second portion 122 of the pad portion 120P. The second side surface 122S may be a curved surface having a specific curvature and / or slope along the vertical direction. The second side surface 122S may have a curvature corresponding to the etching process conditions of the copper foil layer used to electrolytically plate the first portion 121 of the pad portion 120P. The pad portion 120P may have a width different from that of the connecting circuit pattern portion 120T. The width may refer to the horizontal distance perpendicular to the vertical direction of the circuit board 100. Preferably, the width of the pad unit 120P may refer to the horizontal distance in the region having the widest width among the entire vertical region of the pad unit 120P. And, the width of the connecting circuit pattern unit 120T may refer to the horizontal distance in the region having the widest width among the entire vertical region of the connecting circuit pattern unit 120T.

[0153] The width of the pad portion 120P may refer to the width of the first portion 121 of the pad portion 120P. For example, the width of the pad portion 120P may refer to the width of the lower surface of the pad portion 120P.

[0154] Furthermore, the planar shape of the pad portion 120P may be circular. In another embodiment, the planar shape of the pad portion 120P may be elliptical. If the planar shape of the pad portion 120P is circular, the width of the pad portion 120P may refer to the diameter of the pad portion 120P. If the planar shape of the pad portion 120P is elliptical, the width of the pad portion 120P may refer to the diameter of the pad portion 120P in the major axis direction.

[0155] Referring to FIG. 3, the width W1 of the pad portion 120P may range from 40 μm to 70 μm. Preferably, the width W1 of the pad portion 120P may range from 42 μm to 68 μm. More preferably, the width W1 of the pad portion 120P may range from 45 μm to 65 μm. If the width W1 of the pad portion 120P is less than 40 μm, the electrical connectivity with the chip mounted on the circuit board may be reduced. If the width W1 of the pad portion 120P is less than 40 μm, the allowable current of the signal transmitted through the pad portion 120P may be reduced. If the allowable current is reduced, the signal transmission characteristics may be degraded. If the width W1 of the pad portion 120P exceeds 70 μm, it may be difficult to arrange all the pad portions, each connected to a terminal of a semiconductor device, within a limited space. If the width W1 of the pad portion 120P exceeds 70 μm, the volume of the circuit board and the volume of the semiconductor package may increase.

[0156] Meanwhile, the width W2 of the connecting circuit pattern portion 120T may be in the range of 2 μm to 20 μm. Preferably, the width W2 of the connecting circuit pattern portion 120T may be in the range of 2.2 μm to 18 μm. More preferably, the width W2 of the connecting circuit pattern portion 120T may be in the range of 2.5 μm to 15 μm.

[0157] If the width W2 of the connecting circuit pattern portion 120T is less than 2 μm, the signal resistance of the connecting circuit pattern portion 120T increases, which may hinder proper communication with a chip mounted on the circuit board. Furthermore, if the width W2 of the connecting circuit pattern portion 120T is less than 2 μm, not only is it difficult to implement, but the connecting circuit pattern portion 120T may easily break during the manufacturing process, resulting in reliability issues. Furthermore, if the width W2 of the connecting circuit pattern portion 120T exceeds 20 μm, it may be difficult to arrange all of the connecting circuit pattern portions 120T connected to the pad portions 120P within a limited space. If the width W2 of the connecting circuit pattern portion 120T exceeds 20 μm, the volume of the circuit board and semiconductor package may increase, making it difficult to achieve a thinner board.

[0158] The electrode portion 150 may include a bonding portion 140. The bonding portion 140 may be disposed on the wiring electrode 120. Preferably, the bonding portion 140 may be disposed on the pad portion 120P of the wiring electrode 120.

[0159] The bonding portion 140 may include a conductive metal portion 141 disposed on the pad portion 120P and a bonding portion 142 disposed on the conductive metal portion 141.

[0160] The conductive metal portion 141 may be disposed on the pad portion 120P. The conductive metal portion 141 may be disposed on the second portion 122 of the pad portion 120P. The conductive metal portion 141 may include a metal material different from the metal material constituting the pad portion 120P. For example, the conductive metal portion 141 may include a first metal material constituting the pad portion 120P and a second metal material that can be selectively etched. In this case, the fact that the first metal material and the second metal material can be selectively etched may mean that the second metal material is not etched when an etching process is performed using an etchant that can etch the first metal material.

[0161] Referring to FIG. 4, the width of the conductive metal portion 141 may be greater than the width W3 of the upper surface of the pad portion 120P. The width of the conductive metal portion 141 may refer to the horizontal distance from the left end to the right end of the conductive metal portion 141. The width of the conductive metal portion 141 may refer to the length of the upper surface of the conductive metal portion 141. The width of the conductive metal portion 141 may be in the range of 110% to 180% of the width W3 of the upper surface of the pad portion 120P. Preferably, the width of the conductive metal portion 141 may be in the range of 112% to 170% of the width W3 of the upper surface of the pad portion 120P. More preferably, the width of the conductive metal portion 141 may be in the range of 115% to 150% of the width W3 of the upper surface of the pad portion 120P. If the width of the conductive metal portion 141 is less than 110% of the width W3 of the upper surface of the pad portion 120P, the processability of forming the second portion 122 of the pad portion 120P by an etching process may be reduced. For example, if the width of the conductive metal portion 141 is less than 110% of the width W3 of the top surface of the pad portion 120P, the pad portion 120P may not have a uniform thickness, and the effect achieved by the structure of this embodiment may be insufficient. For example, if the width of the conductive metal portion 141 is less than 110% of the width W3 of the top surface of the pad portion 120P, the width W3 of the top surface of the pad portion 120P may be excessively small. If the width W3 of the top surface of the pad portion 120P is excessively small, the vertical cross section of the second portion 122 of the pad portion 120P may have a nearly triangular shape, which may prevent the junction portion 142 of the bonding portion 140 from being stably disposed on the pad portion 120P. Furthermore, if the width of the conductive metal portion 141 exceeds 180% of the width W3 of the top surface of the pad portion 120P, the width of the region of the conductive metal portion 141 that does not vertically overlap the top surface of the pad portion 120P may increase. Furthermore, if the width of the area of ​​the conductive metal portion 141 that does not vertically overlap the top surface of the pad portion 120P increases, the conductive metal portion 141 may come into contact with the connecting circuit pattern portion 120T adjacent to the pad portion 120P or other pad portions, which may cause an electrical short circuit problem.Furthermore, if the width of the conductive metal portion 141 exceeds 180% of the width W3 of the top surface of the pad portion 120P, a problem may occur in that a portion of the second portion 122 of the pad portion 120P that does not vertically overlap with the first portion 121 of the pad portion 120P is not removed by etching. As a result, since at least a portion of the second portion 122 is not etched, an electrical short circuit problem may occur due to electrical connection between the adjacent pad portion 120P and the connecting circuit pattern portion 120T or between adjacent pad portions.

[0162] The conductive metal portion 141 may be divided into a plurality of parts. The conductive metal portion 141 may include a contact portion 141-1 that contacts the upper surface of the pad portion 120P. The contact portion 141-1 of the conductive metal portion 141 may be vertically overlapped with the upper surface of the pad portion 120P. This allows the bonding portion 142 to be stably bonded to the conductive metal portion 141 in this embodiment. Specifically, the conductive metal portion 141 may include a metal material that increases the bonding strength between the pad portion 120P and the bonding portion 142. This may solve the problem of the bonding portion 142 peeling off from the pad portion 120P.

[0163] The conductive metal portion 141 may include an extension portion 141-2 extending outward from the contact portion 141-1 of the pad portion 120P. The extension portion 141-2 of the conductive metal portion 141 may not overlap the upper surface of the pad portion 120P in the vertical direction. The extension portion 141-2 of the conductive metal portion 141 may overlap the side surface 122S of the pad portion 120P in the vertical direction. Preferably, the extension portion 141-2 of the conductive metal portion 141 may overlap the curved side surface 122S of the pad portion 120P in the vertical direction. Because the side surface 122S of the pad portion 120P has a curvature, the area of ​​the upper surface of the pad portion 120P can be reduced according to the curvature. In this case, the extension portion 141-2 of the conductive metal portion 141 overlaps the curved side surface 122S in the vertical direction, thereby increasing the contact area with the joint portion 142. As a result, the embodiment can further improve the bonding strength between the bonding portion 142 and the pad portion 120P.

[0164] In this case, the extension 141-2 of the conductive metal part 141 may be bent with a curvature corresponding to the curvature of the side surface 122S of the pad part 120P. As a result, the extension 141-2 may minimize the difference in width between the upper surface and the lower surface of the second part 122 of the pad part 120P. As a result, the embodiment may prevent a reduction in signal characteristics caused by the difference in width between the upper surface and the lower surface of the second part 122. As a result, the embodiment may further improve the operational reliability of the semiconductor package.

[0165] Therefore, the extension portion 141-2 of the conductive metal portion 141 may be provided to surround the periphery of the side surface 122S of the pad portion 120P. For example, the extension portion 141-2 may include an inner side surface 141-2S1 facing the side surface 122S of the pad portion 120P and an outer side surface 141-2S2 opposite the inner side surface 141-2S1. The extension portion 141-2 may also include a bottom surface 141-2L between the inner side surface 141-2S1 and the outer side surface 141-2S2. As a result, the embodiment may solve the problem of the extension portion 141-2 of the conductive metal portion 141 being separated from the contact portion 141-1. Furthermore, the embodiment may prevent the extension portion 141-2 of the conductive metal portion 141 from contacting another electrode portion adjacent to the extension portion 141-2 even if the extension portion 141-2 of the conductive metal portion 141 is separated from the contact portion 141-1. As a result, the embodiment may further improve the electrical reliability of the semiconductor package.

[0166] At this time, the inner surface 141-2S1 of the extension portion 141-2 can come into contact with the side surface 122S of the pad portion 120P having a curve. For example, the entire area of ​​the inner surface 141-2S1 can come into contact with the side surface 122S of the pad portion 120P.

[0167] In addition, the outer surface 141-2S2 of the extension portion 141-2 may be covered with the first protective layer 112. For example, the outer surface 141-2S2 of the extension portion 141-2 may be in direct contact with the first protective layer 112. The bottom surface 141-2L of the extension portion 141-2 may not be in contact with the side surface 122S of the pad portion 120P. For example, the bottom surface 141-2L of the extension portion 141-2 may be in contact with the first protective layer 112. In the first embodiment, the outer surface 141-2S2 and the bottom surface 141-2L of the extension portion 141-2 of the conductive metal portion 141 may be in contact with the first protective layer 112, and the inner surface 141-2S1 of the extension portion 141-2 may be in contact with the side surface 122S of the pad portion 120P having a curvature. As a result, the extension portion 141-2 of the conductive metal portion 141 can increase the contact area between the electrode portion 150 and the first protective layer 112, thereby improving the adhesion between the electrode portion 150 and the first protective layer 112.

[0168] The bonding portion 140 may include a joint portion 142 disposed on the conductive metal portion 141. The joint portion 142 may include a through portion 142-1 disposed on the conductive metal portion 141 and a protrusion portion 142-2 disposed on the through portion 142-1. Therefore, the bonding portion 140 may have a structure in which the conductive metal portion 141, the through portion 142-1, and the protrusion portion 142-2 are stacked along the vertical direction.

[0169] The through portion 142-1 can penetrate at least a portion of the first protective layer 112. For example, the second portion 122 of the pad portion 120P, the conductive metal portion 141, and the through portion 142-1 can be a through electrode that penetrates the first protective layer 112. The through portion 142-1 can be a part of the through electrode that penetrates the first protective layer 112.

[0170] The width W4 of the through portion 142-1 may be smaller than the width of the conductive metal portion 141. In this case, the width of the conductive metal portion 141 may refer to the horizontal length including the contact portion 141-1 and the extension portion 141-2 of the conductive metal portion 141. The contact portion 141-1 of the conductive metal portion 141 may refer to a portion that vertically overlaps the upper surface of the pad portion 120P, and the extension portion 141-2 of the conductive metal portion 141 may refer to a portion that does not vertically overlap the upper surface of the pad portion 120P but vertically overlaps the curved side surface 122S. This allows the boundary between the contact portion 141-1 and the extension portion 141-2 of the conductive metal portion 141 to be distinguished.

[0171] The width W4 of the through portion 142-1 may be smaller than the width of the contact portion 141-1 of the conductive metal portion 141. If the width W4 of the through portion 142-1 is larger than the width of the conductive metal portion 141, a height deviation may occur between the multiple bonding portions 142. For example, if the width W4 of the through portion 142-1 is larger than the width of the conductive metal portion 141, a thickness deviation and / or a height deviation may increase between the multiple bonding portions spaced apart from each other, which may result in a decrease in bonding strength with the semiconductor device. Furthermore, if the width W4 of the through portion 142-1 is larger than the width of the conductive metal portion 141, the distance between the multiple adjacent through portions decreases, which may increase signal interference between them and result in an increase in signal transmission loss.

[0172] The width W4 of the through portion 142-1 may be smaller than the width W3 above the pad portion 120P. For example, the width W4 of the through portion 142-1 may be smaller than the width W3 of the top surface of the second portion 122 of the pad portion 120P. If the width W4 of the through portion 142-1 is larger than the width W3 above the pad portion 120P, the height deviation of the bonding portion 142 may increase. For example, if the width W4 of the through portion 142-1 is larger than the width W3 above the pad portion 120P, the thickness deviation and / or height deviation between the spaced-apart bonding portions may increase, which may result in a decrease in bonding strength with the semiconductor device. Furthermore, if the width W4 of the through portion 142-1 is larger than the width W3 above the pad portion 120P, the spacing between adjacent through portions may decrease, which may increase signal interference between them and result in an increase in signal transmission loss.

[0173] The bonding portion 142 may include a protrusion 142-2 disposed on the through portion 142-1. The through portion 142-1 and the protrusion 142-2 may be integrally formed. The through portion 142-1 may refer to a region that horizontally overlaps the first protective layer 112, and the protrusion 142-2 may refer to a region that does not horizontally overlap the first protective layer 112. For example, the protrusion 142-2 may refer to a portion that protrudes above the upper surface of the first protective layer 112. The protrusion 142-2 may refer to a portion that is bonded with a conductive adhesive such as solder. A width W5 of the protrusion 142-2 may be smaller than a width W1 of the lower surface of the pad portion 120P. Specifically, the width W5 of the protrusion 142-2 may be smaller than a width W1 of the lower surface of the first portion 121 of the pad portion 120P. If the width W5 of the protrusion 142-2 is greater than the width W1 of the bottom surface of the pad portion 120P, the spacing between the spaced apart bonding portions may become smaller. If the spacing between the bonding portions becomes smaller, the solders disposed on the adjacent bonding portions may be connected to each other, which may cause an electrical short circuit problem.

[0174] According to the embodiment of FIG. 5, the vertical length H1 of the pad portion 120P of the embodiment may be different from the vertical length H2 of the through portion 142-1. In one embodiment, the vertical length H1 of the pad portion 120P may be greater than the vertical length H2 of the through portion 142-1. That is, in the embodiment, the pad portion 120P includes the second portion 122, so that the vertical length H2 of the through portion 142-1 can be reduced by the vertical length of the second portion 122. As a result, in the embodiment, the vertical length H2 of the through portion 142-1 can be made smaller than the vertical length H1 of the pad portion 120P. Furthermore, because the vertical length H2 of the through portion 142-1 is smaller than the vertical length H1 of the pad portion 120P, the vertical lengths of the multiple bonding portions can be made uniform.

[0175] According to the embodiment of FIG. 6, the vertical length H1 of the pad portion 120P of the embodiment may be different from the vertical length H2' of the through portion 142-1A of the joint portion 142.

[0176] In one embodiment, the vertical length H1 of the pad portion 120P may be smaller than the vertical length H2' of the through portion 142-1A. That is, in this embodiment, the pad portion 120P includes the second portion 122, thereby improving the flatness of the upper surface of the pad portion 120P. Therefore, in this embodiment, even if the through portion 142-1A has a vertical length H2' that is larger than the vertical length H1 of the pad portion 120P, the vertical lengths of the bonding portions can be made uniform. That is, in this embodiment, the pad portion 120P includes the second portion 122, thereby minimizing the height deviation between the bonding portions 142 even if the vertical length H2' of the through portion 142-1A increases.

[0177] The wiring electrode 120, the via electrode 130, and the joint 142 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The wiring electrode 120, the via electrode 130, and the joint 142 may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the wiring electrode 120, the via electrode 130, and the joint 142 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0178] The conductive metal portion 141 may include a metal material different from that of the wiring electrode 120, the via electrode 130, and the bonding portion 142. Preferably, the conductive metal portion 141 of the electrode portion 150 may include a metal material different from that of the wiring electrode 120. For example, the conductive metal portion 141 may include a metal material different from that of the wiring electrode 120, such as nickel (Ni), palladium (Pd), gold (Au), or titanium (Ti). For example, the second portion 122 of the pad portion 120P of the electrode portion 150 may include copper, and may be etched using an etchant such as H2SO4 in the etching process. The conductive metal portion 141 may include a metal material that is not etched by an etchant such as H2SO4. If the conductive metal portion 141 includes nickel, the adhesion between the pad portion 120P and the bonding portion 142 may be improved, thereby increasing the bonding strength between the pad portion 120P and the bonding portion 142.

[0179] The via electrodes 130 of the electrode unit 150 may be formed by filling through-holes formed in the insulating substrate 110 with a conductive material. The through-holes may be formed by any one of mechanical, laser, and chemical processing. When the through-holes are formed by mechanical processing, methods such as milling, drilling, and routing may be used. When the through-holes are formed by laser processing, UV or CO2 laser methods may be used. When the through-holes are formed by chemical processing, chemicals including aminosilanes, ketones, etc. may be used.

[0180] The following describes the structures of other embodiments, focusing on the structure of the substrate described above. Detailed descriptions of the substrates of the following embodiments that are substantially the same as those of the substrate described above will be omitted.

[0181] Meanwhile, referring to FIG. 7, the substrate may have a different structure of the bonding portion 140B compared to the previous embodiment.

[0182] That is, the bonding portion 140 in the previous embodiment includes the conductive metal portion 141 and the bonding portion 142, and the through portion 142-1 does not overlap the curved side surface 122S of the pad portion 120P in the vertical direction. That is, the through portion 142-1 in the previous embodiment entirely overlaps the upper surface of the pad portion 120P in the vertical direction.

[0183] In another embodiment, the bonding portion 140 may include a conductive metal portion 141 and a joint portion 142B. The conductive metal portion 141 may include a contact portion 141-1 and an extension portion 141-2. The joint portion 142B may include a penetration portion 142-1B and a protrusion portion 142-2.

[0184] In this case, the through portion 142-1B may be disposed offset to one side on the conductive metal portion 141. For example, the horizontal central axis of the through portion 142-1B may be offset from the horizontal central axis of the conductive metal portion 141. This is because the conductive metal portion 141 includes a contact portion 141-1 and an extension portion 141-2, and the width of the conductive metal portion 141 is greater than the width of the upper surface of the pad portion 120P due to the extension portion 141-2.

[0185] Therefore, in the embodiment, when forming the through portion 142-1B, the through portion 142-1B may be arranged biased to one side on the pad portion 120P. As a result, the through portion 142-1B may include a portion that vertically overlaps with the curved side surface 122S of the pad portion 120P. For example, the through portion 142-1B may include a first portion that vertically overlaps with the top surface of the pad portion 120P and a second portion that vertically overlaps with the curved side surface 122S of the pad portion 120P.

[0186] As a result, the embodiment can increase the spacing between adjacent through holes 142-1B and between adjacent bonding portions 142B. In addition, the embodiment can increase the amount of conductive adhesive disposed on the bonding portions 142B by increasing the spacing between the bonding portions 142B, thereby improving the bonding strength between the semiconductor element and the substrate.

[0187] 8, an embodiment may include a bonding portion 140C. The bonding portion 140C may include a conductive metal portion 141C and a joint portion 142.

[0188] The conductive metal portion 141C may include a contact portion 141-1 that vertically overlaps the upper surface of the pad portion 120P. The conductive metal portion 141C may also include an extension portion 141-2C that bends downward and extends from the contact portion 141-1. In this case, the inner surface of the extension portion 141-2 of the previous embodiment may be in overall contact with the curved side surface 122S of the pad portion 120P.

[0189] Alternatively, the inner surface of the extension portion 141-2C may partially contact the curved side surface 122S of the pad portion 120P. For example, the extension portion 141-2C may be bent in a bending direction corresponding to the curvature of the side surface 122S of the pad portion 120P. However, the curvature of the inner surface of the extension portion 141-2C may be different from the curvature of the side surface 122S of the pad portion 120P. Therefore, the inner surface of the extension portion 141-2C may include a first portion that contacts the curved side surface 122S of the pad portion 120P and a second portion that is spaced apart from the side surface 122S of the pad portion 120P. A certain space may be provided between the second portion of the inner surface of the extension portion 141-2C and the side surface 122S of the pad portion 120P. In this case, the first protective layer 112 may be provided to fill the space. In this case, the separation space can function as an anchor that improves the bonding strength with the first protective layer 112. As a result, the embodiment can increase the adhesion strength between the insulating layer 111 and the first protective layer 112 and the adhesion strength between the first protective layer 112 and the bonding portion 140C.

[0190] On the other hand, in this modified example, the inner surface of the extension portion 141-2C may include only the second portion. For example, the inner surface of the extension portion 141-2C may not be in contact with the curved side surface 122S of the pad portion 120P entirely. For example, the inner surface of the extension portion 141-2C may be in contact with the first protective layer 112 entirely.

[0191] According to the embodiment of FIG. 9, the embodiment may include a bonding portion 140D. The bonding portion 140D may include a conductive metal portion 141D and a joint portion 142. The conductive metal portion 141D may include a contact portion 141-1 that vertically overlaps the upper surface of the pad portion 120P. The conductive metal portion 141D may also include an extension portion 141-2D that bends downward and extends from the contact portion 141-1. The inner surface of the extension portion 141-2D may not generally contact the curved side surface 122S of the pad portion 120P. For example, the extension portion 141-2D may be bent in a bending direction different from the curvature of the side surface 122S of the pad portion 120P. However, the curvature of the inner surface of the extension portion 141-2D may be different from the curvature of the side surface 122S of the pad portion 120P. Therefore, the inner surface of the extension 141-2C does not need to contact the side surface 122S of the pad portion 120P, which has a curve. In this case, the bottom surface of the extension 141-2D also does not need to contact the side surface 122S of the pad portion 120P. For example, the inner surface, outer surface, and bottom surface of the extension 141-2D can all be in contact with the first protective layer 112.

[0192] 10, the embodiment may include a bonding portion 140E. The bonding portion 140E may include a conductive metal portion 141E and a bonding portion 142.

[0193] The conductive metal portion 141E may include a contact portion 141-1 that vertically overlaps the upper surface of the pad portion 120P. The conductive metal portion 141E may also include an extension portion 141-2E that bends downward and extends from the contact portion 141-1. The inner surface of the extension portion 141-2E may not generally contact the curved side surface 122S of the pad portion 120P. For example, the extension portion 141-2E may be bent in a bending direction different from the curvature of the side surface 122S of the pad portion 120P. However, the curvature of the inner surface of the extension portion 141-2E may be different from the curvature of the side surface 122S of the pad portion 120P. Therefore, the inner surface of the extension portion 141-2E may not generally contact the curved side surface 122S of the pad portion 120P. In addition, the bottom surface of the extension 141-2E can come into contact with the curved side surface 122S of the pad portion 120P. That is, depending on the horizontal length of the extension 141-2E, the bottom surface corresponding to the end of the extension 141-2E can come into contact with the side surface 122S of the pad portion 120P.

[0194] 11, the embodiment may include a bonding portion 140F. The bonding portion 140F may include a conductive metal portion 141F and a bonding portion 142.

[0195] The conductive metal portion 141F may include a contact portion 141-1 that vertically overlaps the upper surface of the pad portion 120P. The conductive metal portion 141F may also include an extension portion 141-2F that bends downward and extends from the contact portion 141-1. The extension portion 141-2F may not overlap the side surface 122S of the pad portion 120P in the horizontal direction. For example, the extension portion 141-2F may extend horizontally rather than downward from the contact portion 141-1. That is, the extension portion 141-2F may overlap the side surface 122S of the pad portion 120P vertically but not horizontally.

[0196] The circuit board according to the above-described exemplary embodiment can minimize height deviations between a plurality of bonding portions connected to a coupling member. Specifically, the circuit board according to the exemplary embodiment can include a pad portion. The pad portion can include a first portion embedded in an insulating layer and a second portion disposed on the first portion and protruding above the insulating layer. The circuit board can also include a connecting circuit pattern portion corresponding to traces that overlap horizontally with the first portions of the pad portions. In this case, the second portions of the pad portions can serve as a seed layer for forming the first portions of the pad portions and the connecting circuit pattern portion by electroplating.

[0197] Specifically, in conventional circuit boards, the copper foil layer used as a seed layer is entirely removed. This increases the thickness of the bonding portion provided on the pad portion. This can result in height variations between the horizontally spaced bonding portions in conventional circuit boards. Therefore, when bonding a semiconductor device to the bonding portion, the semiconductor device may not be stably positioned on the bonding portion and may be bonded in a tilted state in a specific direction due to the height differences between the bonding portions. In contrast, in the embodiment, a portion of the copper foil layer used as a seed layer where the bonding portion is to be disposed may not be removed. This allows the pad portion to have a second portion, which is the portion of the unremoved copper foil layer. In this case, the upper surface of the second portion of the pad portion may refer to the upper surface of the copper foil layer initially disposed on the carrier member during the substrate manufacturing process. Therefore, the upper surface of the second portion of the pad portion may be flat. Furthermore, the upper surfaces of the second portions of the multiple pad portions may be coplanar with each other. Therefore, in the embodiment, by disposing the bonding part on the second portion of the pad part, the plurality of bonding parts can be formed with a uniform thickness and / or height. Furthermore, in the embodiment, the thickness of the bonding part can be reduced by the thickness of the second portion of the pad part. As a result, the embodiment can solve the problem of thickness deviation between the plurality of bonding parts increasing in proportion to the thickness of the bonding part. As a result, the embodiment can minimize height deviation between the plurality of bonding parts. Therefore, the embodiment can stably dispose semiconductor devices on the plurality of bonding parts. Furthermore, in the embodiment, the thickness of the bonding part can be increased by the thickness of the second portion of the pad part compared to the thickness of a conventional bonding part. Furthermore, in the embodiment, by forming the bonding part using the pad part having a uniform height, the thickness deviation between the plurality of bonding parts can be minimized even when the thickness of the bonding part is increased.

[0198] As a result, the embodiment can ensure a bonding part height that can stably bond a semiconductor device, thereby improving the overall physical and / or electrical characteristics of the semiconductor package, thereby facilitating smooth operation of the semiconductor device, and further facilitating smooth operation of servers and electronic products.

[0199] In addition, the bonding portion may include a through portion penetrating at least a portion of the protective layer from the upper surface thereof, and a bonding portion disposed on the through portion and protruding above the protective layer. The second portion of the pad portion may include a curved side surface. The through portion of the bonding portion may vertically overlap the curved side surface of the pad portion. Therefore, in the embodiment, when forming the through portion of the bonding portion, the through portion may be disposed biased to one side on the pad portion. As a result, the embodiment may increase the spacing between adjacent through portions and between adjacent bonding portions. In the embodiment, increasing the spacing between the bonding portions may increase the amount of bonding material disposed on the bonding portion, thereby improving the bonding strength between the semiconductor device and the substrate.

[0200] In addition, the conductive metal portion of the bonding portion may include a contact portion that overlaps a top surface of the pad portion in a vertical direction and an extension portion that overlaps a side surface of the pad portion having a curvature in a vertical direction. The extension portion may be bent from the contact portion in a bending direction corresponding to the curvature of the side surface of the pad portion. In this manner, the embodiment may increase the contact area between the protective layer and the pad portion using the extension portion, thereby improving the bonding strength between the protective layer and the pad portion.

[0201] In addition, at least a portion of the inner surface of the extension of the conductive metal portion may not contact the side of the pad portion. Thus, a certain gap may be provided between the side of the pad portion and the inner surface of the extension. The protective layer may be provided by filling the gap. The gap may function as an anchor that improves bonding strength with the protective layer. Thus, the embodiment may improve adhesion between the insulating layer and the protective layer and between the protective layer and the bonding portion.

[0202] 12 to 23 are cross-sectional views showing the manufacturing method of the circuit board shown in FIG. 2 in the order of steps.

[0203] Referring to FIG. 12 , an embodiment may provide a carrier board. For example, an embodiment may provide a carrier board including a carrier insulating layer CB1 and a metal layer CB2 disposed on at least one side of the carrier insulating layer CB1. In this case, the metal layer CB2 may be disposed on only one of the first and second sides of the carrier insulating layer CB1, or may be disposed on both sides. For example, the metal layer CB2 may be disposed on only one side of the carrier insulating layer CB1, thereby allowing a circuit board manufacturing process to be performed on only one side. In another embodiment, the metal layer CB2 may be disposed on both sides of the carrier insulating layer CB1, thereby allowing a process to simultaneously manufacture multiple circuit boards on both sides of the carrier board.

[0204] The metal layer CB2 may be formed by electroless plating on the carrier insulating layer CB1. Alternatively, the carrier insulating layer CB1 and the metal layer CB2 may be CCL (Copper Clad Laminate). That is, the metal layer CB2 may be a copper foil layer. For example, the metal layer CB2 may be copper foil. For example, the metal layer CB2 may be an electroless plating layer formed on the carrier insulating layer CB1. That is, the metal layer CB2 may be the first metal layer formed in the manufacturing process of the circuit board. The metal layer CB2 may constitute the second portion 122 of the pad portion 120P of the wiring electrode 120. The metal layer CB2 may be a seed layer for electroplating the first portion 121 of the pad portion 120P and the connecting circuit pattern portion 120T. The metal layer CB2 may have a certain thickness. The metal layer CB2 may be composed of one layer or at least two or more layers. This may ensure the thickness of the second portion 122 of the pad portion 120P. When the metal layer CB2 is composed of two or more layers, one of the layers may be a copper foil layer and the other layer may be an electroless plated layer.

[0205] 13, in an embodiment, a process of forming the wiring electrode 120 below the metal layer CB2 may be performed. Preferably, in an embodiment, a process of forming the first portion 121 of the pad portion 120P and the connecting circuit pattern portion 120T by performing electrolytic plating using the metal layer CB2 as a seed layer may be performed. To this end, a mask M1 including open regions corresponding to regions where the first portion 121 of the pad portion 120P and the connecting circuit pattern portion 120T will be disposed may be disposed below the metal layer CB2.

[0206] In this embodiment, a curing process of heat-treating the mask M1 may be further performed before the electroplating process of the first portion 121 of the pad portion 120P and the connecting circuit pattern portion 120T. For example, in the embodiment, a process of curing the mask M1 may be performed after the exposing and developing process of the mask M1. The curing of the mask M1 may include curing using ultraviolet light and curing using infrared light. For example, in the embodiment, the mask M1 may be cured using ultraviolet light in a range of 5 mV to 100 mV. Alternatively, in the embodiment, the mask M1 may be thermally cured by infrared light. As described above, in the embodiment, the bonding strength between the metal layer CB2 and the mask M1 may be improved by further performing a process of curing the mask M1. As a result, in the embodiment, the first portion 121 of the pad portion 120P and the connecting circuit pattern portion 120T may be miniaturized due to the improved bonding strength between the mask M1 and the metal layer CB2.

[0207] Next, referring to FIG. 14 , the mask M1 may be removed in an embodiment. Then, the embodiment may perform a process of pretreating the first portion 121 of the pad portion 120P and the connecting circuit pattern portion 120T. For example, the embodiment may perform a process of imparting a certain level of surface roughness to the surfaces of the first portion 121 of the pad portion 120P and the connecting circuit pattern portion 120T. For example, the embodiment may cause each of the side and bottom surfaces of the first portion 121 of the pad portion 120P and the connecting circuit pattern portion 120T to have a 10-point average surface roughness Rz in the range of 0.01 μm to 0.5 μm. Then, the embodiment may form the insulating layer 111 under the metal layer CB2.

[0208] 15, the embodiment may perform a step of forming through holes TH in the insulating layer 111. The through holes TH may be formed by laser processing, but is not limited to this.

[0209] Next, referring to FIG. 16, in the embodiment, a step of forming the wiring electrode 120 and the via electrode 130 on the insulating layer 111 can be performed.

[0210] 17 , an embodiment may perform a step of laminating an additional build-up layer below the insulating layer 111. For example, an embodiment may perform a step of laminating a second layer of insulating layer 111 below the first layer of insulating layer 111. Thereafter, an embodiment may perform a step of forming wiring electrodes 120 and via electrodes 130 on the second layer of insulating layer 111 by repeating the steps of FIGS. 15 and 16 .

[0211] 18, in an embodiment, a step of removing the carrier board from the circuit board manufactured as described above can be performed. For example, in an embodiment, a step of separating the carrier insulating layer CB1 and the metal layer CB2 from each other can be performed. As a result, the metal layer CB2 included in the carrier board remains on the outermost side of the circuit board of the embodiment.

[0212] 19, in this embodiment, a process of forming a conductive metal portion 141 on an upper surface of the metal layer CB2 may be performed. The conductive metal portion 141 may be disposed in a region of the metal layer CB2 of the carrier board that vertically overlaps with the wiring electrode 120 of the pad portion 120P. In this case, the conductive metal portion 141 may be formed of a metal material that is selectively etchable with respect to the metal layer CB2 of the carrier board.

[0213] 20, in this embodiment, a process may be performed in which the metal layer CB2 of the carrier board is etched using the conductive metal portion 141 to form the second portion 122 of the pad portion 120P. At this time, depending on the etching characteristics, the side of the second portion 122 may include a curved side. Furthermore, due to the etching of the second portion 122, at least a portion of the conductive metal portion 141 may not vertically overlap the top surface of the second portion 122. That is, the conductive metal portion 141 may include a contact portion 141-1 and an extension portion 141-2. The extension portion 141-2 may entirely contact the side of the second portion 122 of the pad portion 120P, which has a curvature depending on the etching characteristics. However, the shape is not limited thereto, and the extension portion 141-2 may have any one of the shapes shown in FIGS. 8 to 11.

[0214] Next, referring to FIG. 21, in an embodiment, a step of forming a first protective layer 112 and a second protective layer 113 on the upper and lower surfaces of the insulating layer 111, respectively, may be performed.

[0215] 22, the embodiment may perform a step of forming an opening 112TH in the first protective layer 112, the opening 112TH being vertically overlapping with the contact portion 141-1 of the conductive metal portion 141. Also, the embodiment may perform a step of forming at least one opening 113TH in the second protective layer 113.

[0216] 23 , in an embodiment, a step of forming a bonding portion 142 in the opening 112TH of the first protective layer 112 may be performed. At this time, the bonding portion 142 may include a through portion 142-1 filling the opening 112TH of the first protective layer 112 and a protruding portion 142-2 disposed on the first protective layer 112.

[0217] 24 is a cross-sectional view showing a circuit board according to a second embodiment, FIG. 25 is an optical microscope photograph showing the interface of an insulating layer provided on the circuit board according to the embodiment of FIG. 24, FIG. 26 is a cross-sectional view showing the state before a conductive metal portion is placed in one area of ​​FIG. 24, FIG. 27 is a diagram showing the state after the conductive metal portion has been placed in FIG. 26, FIG. 28 is a diagram showing the detailed layer structure of the lower wiring electrode in the circuit board of FIG. 24, FIG. 29 is a cross-sectional view showing a circuit board according to a third embodiment, FIG. 30 is a cross-sectional view showing a circuit board according to a fourth embodiment, and FIG. 31 is a cross-sectional view showing a circuit board according to a fifth embodiment.

[0218] The circuit board according to the embodiment will be specifically described below with reference to FIGS.

[0219] 24 , the circuit board 1000 may include an insulating layer 1110, an electrode unit 1120, a first protective layer 1130, and a second protective layer 1140. The electrode unit 1120 may include a first wiring electrode 1121, a second wiring electrode 1122, and a via electrode 1123. The first wiring electrode 1121 may refer to an electrode disposed on the lower surface of one insulating layer, and the second wiring electrode 1122 may refer to an electrode disposed on the upper surface of the one insulating layer. In addition, the electrode unit 1120 may include a conductive metal unit 1124 disposed on the second wiring electrode 1122. For convenience of explanation, the circuit board 1000 in FIG. 24 shows a single insulating layer 1110, and the insulating layer 1110 may have a stacked structure of multiple layers along the vertical direction. In this case, the first wiring electrode 1121 may refer to an electrode arranged on the underside of the lowest insulating layer among the plurality of insulating layers, and the second wiring electrode 1122 may refer to an electrode arranged on the upper surface of the highest insulating layer among the plurality of insulating layers.

[0220] The insulating layer 1110 may include multiple layers based on one via electrode 1123. For example, the insulating layer 1110 may include a first layer 1111 and a second layer 1112. The first layer 1111 and the second layer 1112 of the insulating layer 1110 may include different insulating materials. For example, the first layer 1111 of the insulating layer 1110 may include a reinforcing member. The reinforcing member may refer to a filler. That is, the reinforcing member may refer to an inorganic filler and may have a different meaning from glass fiber material that may extend along the horizontal direction of the insulating layer 1110. The first layer 1111 of the insulating layer 1110 may include an organic material containing a filler. For example, the first layer 1111 of the insulating layer 1110 may use ABF (Ajinomoto Build-up Film), a product sold by Ajinomoto Co., Inc., or PID (Photo Imageable Dielectric resin). The second layer 1112 of the insulating layer 1110 may be disposed on the first layer 1111 of the insulating layer 1110. The second layer 1112 of the insulating layer 1110 may be disposed on the first layer 1111 while having a smaller thickness than the first layer 1111. For example, the second layer 1112 of the insulating layer 1110 may include an insulating material that is different from the insulating material provided in the first layer 1111. Preferably, the second layer 1112 of the insulating layer 1110 may not include a reinforcing member. For example, the second layer 1112 of the insulating layer 1110 may include a pure polymer.

[0221] For example, the insulating layer in the comparative example included only the first layer. In this case, if the insulating layer includes only the first layer, the physical and electrical reliability of the circuit board may be reduced. Specifically, the first layer of the insulating layer may include a reinforcing member. When electrodes are disposed on the insulating layer, a surface treatment may be performed to ensure adhesion between the electrodes and the first layer of the insulating layer. The surface treatment may involve etching the surface of the first layer of the insulating layer. When etching the surface of the first layer of the insulating layer, the filler contained within the first layer of the insulating layer may be exposed to the outside. The exposed filler may act as a factor that reduces the electrical and physical reliability of the circuit board. For example, when a seed layer is formed on the first layer of the insulating layer by chemical copper plating, the seed layer may come into contact with the resin and filler of the first layer of the insulating layer. Depending on the characteristics of the seed layer, the adhesion between the seed layer and the filler may be reduced. That is, if the contact area between the seed layer and the filler increases or if the contact area between the seed layer and the resin decreases, the adhesion between the seed layer and the insulating layer may decrease. This may result in changes in capacitance, resistance, inductance, etc., resulting in changes in leakage current and substrate impedance, and reduced electrical reliability. To address this issue, the filler content in the insulating layer may be reduced. However, if the filler content is reduced, the rigidity of the substrate may decrease accordingly. Furthermore, if the rigidity of the substrate decreases, the substrate may warp significantly in a specific direction, resulting in reliability issues. Furthermore, if the electrode portion comes into contact with the filler, the physical properties of the filler may increase transmission loss of signals transmitted through the electrode portion, thereby degrading electrical characteristics.

[0222] Therefore, the embodiment may improve the electrical characteristics of the electrode unit 1120 while ensuring adhesion between the insulating layer 1110 and the electrode unit 1120. To this end, the insulating layer 1110 may include a first layer 1111 and a second layer 1112 on the first layer 1111. The first layer 1111 of the insulating layer 1110 may be made of an organic material including a reinforcing member. For example, the reinforcing member may be a filler. Thus, the first layer 1111 may ensure the rigidity of the insulating layer 1110 while enabling the electrode unit 1120 to be stably disposed on the insulating layer 1110. The second layer 1112 of the insulating layer 1110 may be provided on the first layer 1111 of the insulating layer 1110. The second layer 1112 of the insulating layer 1110 may not include a reinforcing member. At least a portion of the electrode unit 1120 may be disposed on the second layer 1112 of the insulating layer 1110. For example, at least a portion of the electrode portion 1120 may be in contact with the second layer 1112 of the insulating layer 1110. In this case, the second layer 1112 of the insulating layer 1110 may not be provided with a reinforcing member. As a result, the electrode portion 1120 may not be in contact with the reinforcing member. Therefore, the embodiment can improve the adhesion between the electrode portion 1120 and the insulating layer 1110. Furthermore, the embodiment can improve the electrical characteristics of the electrode portion 1120.

[0223] A third layer 1113 may be provided below the first layer 1111 of the insulating layer 1110. The third layer 1113 may include the same material as the second layer 1112. The third layer 1113 may include an organic material without a reinforcing member. The third layer 1113 may be a pure polymer without a reinforcing member. In this case, the third layer 1113 of the insulating layer 1110 may include the same insulating material as the second layer 1112, and may thus also be referred to as the "second layer." For example, if the substrate has a multi-layer structure, one of the multiple insulating layers may include the first layer 1111, the second layer 1112, and the third layer 1113 of the insulating layer 1110. For example, if the substrate has a multi-layer structure, one of the multiple insulating layers may include the first layer 1111 and the second layer 1112 of the insulating layer 1110. For example, if the substrate has a multi-layer structure, one of the multiple insulating layers may include the first layer 1111 and the third layer 1113 of the insulating layer 1110 .

[0224] The first layer 1111 of the insulating layer 1110 may have a thickness in the range of 20 μm to 40 μm. Preferably, the first layer 1111 of the insulating layer 1110 may have a thickness in the range of 22 μm to 38 μm. More preferably, the first layer 1111 of the insulating layer 1110 may have a thickness in the range of 25 μm to 35 μm. If the thickness of the first layer 1111 is less than 20 μm, the rigidity of the circuit board 1000 may decrease. If the thickness of the first layer 1111 is less than 20 μm, the electrode portion 1120 may not be stably positioned, which may reduce the electrical reliability of the board. If the thickness of the first layer 1111 of the insulating layer 1110 exceeds 40 μm, the overall thickness of the circuit board 1000 may increase, which may increase the thickness of the semiconductor package. Furthermore, if the thickness of the first layer 1111 of the insulating layer 1110 exceeds 40 μm, it may be difficult to miniaturize the electrode portion 1120 of the circuit board 1000.

[0225] The second layer 1112 of the insulating layer 1110 may have a thickness smaller than the first layer 1111. For example, the second layer 1112 of the insulating layer 1110 may have a thickness in the range of 1 μm to 5 μm. Preferably, the second layer 1112 of the insulating layer 1110 may have a thickness in the range of 1.2 μm to 4 μm. More preferably, the second layer 1112 of the insulating layer 1110 may have a thickness in the range of 1.5 μm to 3 μm. Preferably, the thickness of the second layer 1112 of the insulating layer 1110 may be in the range of 2% to 25% of the thickness of the first layer 1111 of the insulating layer 1110. Preferably, the thickness of the second layer 1112 of the insulating layer 1110 may be in the range of 3% to 18% of the thickness of the first layer 1111 of the insulating layer 1110. More preferably, the thickness of the second layer 1112 of the insulating layer 1110 can be in the range of 4% to 12% of the thickness of the first layer 1111 of the insulating layer 1110. If the thickness of the second layer 1112 of the insulating layer 1110 is less than 1 μm or less than 2% of the thickness of the first layer 1111, it may be difficult to impart a uniform centerline average surface roughness Ra to the upper surface of the second layer 1112 of the insulating layer 1110. If the thickness of the second layer 1112 of the insulating layer 1110 is less than 1 μm or less than 2% of the thickness of the first layer 1111, the filler provided in the first layer 1111 of the insulating layer 1110 may be exposed on the second layer 1112. As a result, the electrode portion 1120 and the filler in the first layer 1111 may come into contact with each other, resulting in a decrease in adhesion or a decrease in the electrical properties of the electrode portion 1120. Also, if the thickness of the second layer 1112 of the insulating layer 1110 is greater than 5 μm or greater than 25% of the thickness of the first layer 1111, the thickness of the insulating layer 1110 increases, which can increase the thickness of the circuit board.

[0226] Here, the thickness may correspond to the distance of each layer of the insulating layer 1110 in the substrate vertical direction. That is, the thickness may refer to the length from the top surface to the bottom surface of the circuit board 1000 or from the bottom surface to the top surface, or may refer to the length in the substrate vertical direction. Here, the top surface may refer to the highest position in the vertical direction of each component, and the bottom surface may refer to the lowest position in the vertical direction of each component. These positions may be referred to oppositely.

[0227] The first layer 1111 of the insulating layer 1110 includes a filler, and the second layer 1112 of the insulating layer 1110 does not include a filler, which may enable differentiation of the interface between the first layer 1111 and the second layer 1112. Specifically, the refractive index of the filler may be higher than that of a typical epoxy or acrylic resin. This may result in a difference in refractive index, which may enable differentiation of the interface between the first layer 1111, which includes the filler, and the second layer 1112, which does not include the filler. For example, as shown in FIG. 25, when an image is captured by reflecting and refracting electrons, the image colors of the first layer 1111 and the second layer 1112 of the insulating layer 1110 may appear different, which may enable differentiation of the interface.

[0228] The first layer 1111 of the insulating layer 1110 may include a certain level or more of filler. For example, the first layer 1111 of the insulating layer 1110 may include a resin 1111P and a reinforcing member 1111F. The reinforcing member 1111F may refer to a filler. The reinforcing member 1111F may be included in the first layer 1111 at a certain content or more. The content of the reinforcing member 1111F in the first layer 1111 of the insulating layer 1110 may be in the range of 60% to 85% by weight. If the content of the reinforcing member 1111F in the first layer 1111 of the insulating layer 1110 is less than 60% by weight, the rigidity of the insulating layer 1110 may be reduced. If the content of the reinforcing member 1111F in the first layer 1111 of the insulating layer 1110 exceeds 85% by weight, the signal transmission characteristics of the via electrodes 1123 penetrating the first layer 1111 may be reduced.

[0229] In this case, conventionally, when more than 60% by weight of reinforcing member 1111F was placed in the first layer 1111 of insulating layer 1110, reinforcing member 1111F was exposed on the upper or lower side of insulating layer 1110, causing electrode portion 1120 and reinforcing member 1111F to come into contact with each other.

[0230] In contrast, in the embodiment, the insulating layer 1110 includes the second layer 1112 on the first layer 1111, which solves the problem of contact between the electrode unit 1120 and the filler even if the filler content in the first layer 1111 is increased. Therefore, the embodiment can improve the rigidity of the circuit board 1000 and, thereby, the electrical characteristics of the electrode unit 1120.

[0231] The surface of the insulating layer 1110 can be imparted with a certain level of center line average surface roughness Ra. For example, the insulating layer 1110 can include an interface 1112B between the first layer 1111 and the second layer 1112. The insulating layer 1110 can also include an upper surface 1112U of the second layer 1112. The center line average surface roughness Ra of the interface 1112B can be different from the center line average surface roughness Ra of the upper surface 1112U. The deviation of the center line average surface roughness Ra value from line to line at the interface 1112B can be greater than the deviation of the center line average surface roughness Ra from line to line at the upper surface 1112U.

[0232] That is, in this embodiment, a uniform centerline average surface roughness Ra can be imparted to the second layer 1112 of the insulating layer 1110 without any deviation. This is because a metal layer (not shown) with a certain level of surface roughness is attached to the second layer 1112 of the insulating layer 1110, and the surface roughness of the metal layer is transferred to the second layer 1112 of the insulating layer 1110. As a result, a uniform centerline average surface roughness Ra can be imparted to the upper surface 1112U of the second layer 1112 of the insulating layer 1110. However, the interface 1112B between the first layer 1111 and the second layer 1112 of the insulating layer 1110 can be imparted with the centerline average surface roughness Ra by the reinforcing members 1111F included in the first layer 1111. In this case, the particle diameters of the reinforcing members 1111F provided in the first layer 1111 of the insulating layer 1110 can be different from each other. That is, fillers having various particle sizes may be disposed in the first layer 1111 of the insulating layer 1110. As a result, the centerline average surface roughness Ra of the interface 1112B between the first layer 1111 and the second layer 1112 of the insulating layer 1110 may have deviations from line to line.

[0233] The centerline average surface roughness Ra of the upper surface 1112U of the second layer 1112 can be in the range of 0.2 μm to 1.5 μm. Preferably, the centerline average surface roughness Ra of the upper surface 1112U of the second layer 1112 can be in the range of 0.25 μm to 1.3 μm. More preferably, the centerline average surface roughness Ra of the upper surface 1112U of the second layer 1112 can be in the range of 0.3 μm to 1.25 μm. If the centerline average surface roughness Ra of the upper surface 1112U of the second layer 1112 is less than 0.2 μm, the adhesion between the electrode portion 1120 and the upper surface 1112U of the second layer 1112 may not be ensured, which may result in a physical reliability problem such as peeling of the electrode portion 1120 from the insulating layer 1110. If the centerline average surface roughness Ra of the upper surface 1112U of the second layer 1112 exceeds 1.5 μm, the transmission loss of a signal transmitted through the electrode unit 1120 may increase. For example, as the frequency of a transmitted signal increases, the signal flows more along the surface of the electrode unit 1120, a phenomenon known as a skin effect. In this case, if the centerline average surface roughness Ra of the upper surface 1112U of the second layer 1112 exceeds 1.5 μm, the length of the surface may be increased, thereby increasing the transmission distance of the signal transmitted along the surface. Furthermore, as the signal transmission distance increases, signal transmission loss may increase. This may make it difficult to ensure smooth operation of semiconductor devices, servers, or electronic products. In other words, the centerline average surface roughness Ra of the upper surface 1112U of the second layer 1112 may be directly related to the reliability of servers or electronic products, and may provide technical interoperability or functional integrity.

[0234] The center line average surface roughness Ra of the upper surface 1112U of the second layer 1112 may be smaller than the particle size of the filler of the reinforcing member 1111F provided in the first layer 1111. Preferably, the particle size of the filler may have various sizes. In this case, the average particle size of the filler may be larger than the center line average surface roughness Ra of the upper surface 1112U of the second layer 1112. This can ensure adhesion between the electrode unit 1120 arranged on the upper surface 1112U of the second layer 1112 and the insulating layer 1110, while reducing transmission loss of signals flowing through the electrode unit 1120 and improving signal characteristics.

[0235] The lower surface of the third layer 1113 of the insulating layer 1110 may have a centerline average surface roughness Ra corresponding to the centerline average surface roughness Ra of the upper surface 1112U of the second layer 1112.

[0236] Here, the center line average surface roughness Ra can be expressed by the height of the irregularities. For example, a first irregularity may be provided at the interface between the first layer 1111 and the second layer 1112 of the insulating layer 1110. A second irregularity may be provided on the upper surface of the second layer 1112 of the insulating layer 1110. The height of the first irregularity may be different from the height of the second irregularity. Furthermore, the deviation in the height of the first irregularity may be greater than the deviation in the height of the second irregularity. Preferably, the height of the second irregularity may be uniform.

[0237] 26, the insulating layer 1110 may include a recess 1110R in which at least a portion of the electrode unit 1120 is disposed. The recess 1110R may be recessed from the upper surface toward the lower surface of the insulating layer 1110. The recess 1110R may be a space in which the second wiring electrode 1122 of the electrode unit 1120 is disposed.

[0238] The recess 1110R may be provided in the first layer 1111 and the second layer 1112 of the insulating layer 1110. In this case, the recess 1110R may penetrate the second layer 1112 of the insulating layer 1110 but not the first layer 1111. For example, the recess 1110R may include a first part 1111R provided in the first layer 1111 of the insulating layer 1110 and a second part 1112R connected to the first part 1111R and provided in the second layer 1112. The first part 1111R may be provided in the form of a groove that does not penetrate the first layer 1111 of the insulating layer 1110. The second part 1112R may be provided in the form of a through-hole that penetrates the second layer 1112 of the insulating layer 1110.

[0239] The first wiring electrode 1121 and the second wiring electrode 1122 may have different vertical cross-sectional shapes. For example, the second wiring electrode 1122 may be provided on the uppermost side of the circuit board 1000 and function as an electrode to which an interposer or a semiconductor device is connected. The second wiring electrode 1122 may refer to the wiring electrode 120 of the circuit board described with reference to FIG. 2. A conductive metal portion 1124 may be disposed on the second wiring electrode 1122. In this case, the conductive metal portion 1124 in the second embodiment may be formed by a different method than the conductive metal portion in the first embodiment, and thus may have a different structure from the conductive metal portion in the first embodiment. In this case, an etching process may be performed on the conductive metal portion 1124 to improve the bonding strength between the second wiring electrode 1122 and the conductive metal portion 1124. As a result, the recess 1110R of the insulating layer 1110 may include a portion filled with the second wiring electrode 1122 and a portion filled with the conductive metal portion 1124.

[0240] The second wiring electrode 1122 may include multiple outer surfaces. The second wiring electrode 1122 may include an upper surface 1122U, side surfaces 1122S, and a lower surface. The upper surface and the lower surface of the second wiring electrode 1122 may have different widths. For example, the upper surface of the second wiring electrode 1122 may have a width smaller than that of the lower surface of the second wiring electrode 1122. This may be because a portion of the upper surface and side surfaces of the second wiring electrode 1122 are etched and removed during an etching process of the second wiring electrode 1122 to increase the contact area with the conductive metal portion 1124. The upper surface 1122U of the second wiring electrode 1122 may not contact the insulating layer 1110. The upper surface 1122U of the second wiring electrode 1122 may not contact the first layer 1111 and the second layer 1112 of the insulating layer 1110. The upper surface 1122U of the second wiring electrode 1122 may be located lower than the upper surface of the insulating layer 1110. Preferably, the upper surface 1122U of the second wiring electrode 1122 may be located lower than the upper surface 1112U of the second layer 1112 of the insulating layer 1110. For example, the upper surface 1122U of the second wiring electrode 1122 may be located lower than the uppermost second protrusions and recesses among the second protrusions and recesses provided on the upper surface 1112U of the second layer 1112. The side surface 1122S of the second wiring electrode 1122 may include a plurality of slopes.

[0241] The side surface 1122S of the second wiring electrode 1122 is adjacent to the upper surface 1122U of the second wiring electrode 1122 and may include a first slope 1122S1 that increases in width toward the lower surface of the second wiring electrode 1122. The side surface 1122S of the second wiring electrode 1122 is adjacent to the lower surface of the second wiring electrode 1122 and may include a second slope 1122S2 that is different from the first slope 1122S1. The second slope of the side surface 1122S of the second wiring electrode 1122 may have a slope that changes in width toward the upper surface of the second wiring electrode 1122, but is not limited to this. The second slope 1122S2 of the side surface 1122S of the second wiring electrode 1122 does not have to overlap horizontally with the second layer 1112 of the insulating layer 1110. The second slope 1122S2 of the side surface 1122S of the second wiring electrode 1122 may contact the first layer 1111. For example, the second inclination 1122S2 of the side surface 1122S of the second wiring electrode 1122 can come into contact with the inner wall of the first part 1111R of the recess 1110R provided in the first layer 1111.

[0242] The first slope 1122S1 of the side surface 1122S of the second wiring electrode 1122 may include a first portion that horizontally overlaps the first layer 1111 and a second portion that horizontally overlaps the second layer 1112. The first slope 1122S1 of the side surface 1122S of the second wiring electrode 1122 may not contact the insulating layer 1110. For example, the first slope 1122S1 of the side surface 1122S of the second wiring electrode 1122 may be horizontally spaced apart from the inner wall of the first part 1111R of the recess 1111 provided in the first layer 1111 and the inner wall of the second part of the recess 1110R provided in the second layer 1112. The second wiring electrode 1122 may fill only a portion of the recess 1110R without filling the entire recess 1110R. This is because the manufacturing process of the second wiring electrode 1122 includes a process of surface treating the second wiring electrode 1122, and in the surface treatment process, a part of the outer surface of the second wiring electrode 1122 may be removed by etching. Therefore, the second wiring electrode 1122 may include a crevice spaced from the inner wall of the recess 1110R.

[0243] The conductive metal portion 1124 is disposed on the second wiring electrode 1122. Preferably, the second wiring electrode 1122 includes a pad portion, and the conductive metal portion 1124 is disposed on the pad portion. The conductive metal portion 1124 may contain a metal different from that of the second wiring electrode 1122. The conductive metal portion 1124 may contain a metal material for improving the adhesive strength between the second wiring electrode 1122 and the connection member. The conductive metal portion 1124 may also contain a metal material for improving the adhesive strength between the second wiring electrode 1122 and the bonding portion. For example, the conductive metal portion 1124 may contain nickel. When the conductive metal portion 1124 contains nickel, the adhesive strength between the second wiring electrode 1122 and the bonding portion can be improved. Furthermore, if electrical connection is subsequently made with the second wiring electrode 1122 via a material such as solder, the solder may diffuse into the second wiring electrode 1122, forming an inter-metallic compound, which can result in poor mechanical and electrical reliability. In particular, if the second wiring electrode 1122 is made of copper, the problem of the formation of an inter-metallic compound may be exacerbated. However, if nickel is used, the diffusion of solder can be prevented, preventing the formation of an inter-metallic compound, thereby improving the electrical and mechanical reliability of the semiconductor package. The conductive metal portion 1124 may include metals other than nickel. For example, the conductive metal portion 1124 may include gold. For example, the conductive metal portion 1124 may include palladium.

[0244] The conductive metal portion 1124 may protrude above the upper surface of the insulating layer 1110. For example, at least a portion of the conductive metal portion 1124 may be provided in the recess 1110R of the insulating layer 1110, and the remaining portion may protrude above the insulating layer 1110. Therefore, when the semiconductor package and the electronic element are subsequently bonded together through thermocompression (TC) bonding, there is an advantage in that the TC bonding can be performed smoothly while ensuring alignment and diffusion force.

[0245] The conductive metal portion 1124 may be provided to surround the second wiring electrode 1122 in the recess 1110R. For example, the first slope 1122S1 of the upper surface 1122U and the side surface 1122S of the second wiring electrode 1122 may not contact the insulating layer 1110. As a result, the conductive metal portion 1124 may include a portion disposed in the recess 1110R, and the portion disposed in the recess 1110R may be provided to cover the upper surface 1122U and the first slope 1122S1 of the side surface 1122S of the second wiring electrode 1122.

[0246] 27, the conductive metal portion 1124 may include a buried portion disposed in the recess 1110R. The buried portion of the conductive metal portion 1124 may include a portion in contact with the insulating layer 1110. The buried portion of the conductive metal portion 1124 may include a portion 1124S2 in contact with an inner wall of the first part 1111R of the recess 1110R and a portion 1124S3 in contact with an inner wall of the second part 1112R of the recess 1110R.

[0247] Furthermore, the embedded portion of the conductive metal portion 1124 may include a portion in contact with the second wiring electrode 1122. Specifically, the embedded portion of the conductive metal portion 1124 may include a portion 1124S4 in contact with the first slope 1122S1 of the upper surface 1122U of the second wiring electrode 1122.

[0248] Furthermore, the conductive metal portion 1124 may include a protruding portion that protrudes above the insulating layer 1110. The protruding portion of the conductive metal portion 1124 may include a portion that contacts the insulating layer 1110. Specifically, the protruding portion of the conductive metal portion 1124 may include a portion 1124S1 that contacts the upper surface 1112U of the second layer 1112 of the insulating layer 1110. That is, the protruding portion of the conductive metal portion 1124 may extend horizontally above the second wiring electrode 1122. Therefore, a portion of the protruding portion of the conductive metal portion 1124 may vertically overlap the second wiring electrode 1122, and the remaining portion may not vertically overlap the second wiring electrode 1122. Furthermore, the lower surface 1124S1 of the portion that does not vertically overlap the second wiring electrode 1122 may contact the upper surface 1112U of the second layer 1112 of the insulating layer 1110.

[0249] The conductive metal portion 1124 may include an upper surface 1124U that protrudes above the insulating layer 1110. The upper surface 1124U of the conductive metal portion 1124 may include a portion that is convex in a direction away from the upper surface of the insulating layer 1110. At least a portion of the conductive metal portion 1124 is provided within the recess 1110R of the insulating layer 1110. Therefore, the embodiment may increase the contact area between the conductive metal portion 1124 and the second wiring electrode 1122. As a result, the embodiment may improve the adhesion between the conductive metal portion 1124 and the second wiring electrode 1122. As a result, the embodiment may improve the physical reliability between the conductive metal portion 1124 and the second wiring electrode 1122. Furthermore, in the embodiment, since the conductive metal portion 1124 has a structure that surrounds the outer surface of the second wiring electrode 1122, signal transmission between the conductive metal portion 1124 and the second wiring electrode 1122 may be smooth, thereby improving electrical characteristics. Furthermore, the embodiment may uniformly distribute thicknesses of the horizontally spaced conductive metal portions 1124. Specifically, the conductive metal portions 1124 may be disposed on a second insulating layer. In this case, the second insulating layer may be a pure resin layer that does not include a reinforcing member such as a filler. This may provide a uniform surface roughness to the surface of the second insulating layer. The plurality of conductive metal portions may then be disposed on the second insulating layer to which the uniform surface roughness has been provided. This may result in the plurality of conductive metal portions having a uniform thickness. Furthermore, if bonding portions are further disposed on the conductive metal portions, the plurality of bonding portions may also have a uniform thickness. This may result in the embodiment stably bonding a semiconductor device to the conductive metal portions or the bonding portions. Therefore, the embodiment may enable the semiconductor device to operate stably and smoothly, thereby improving the operating characteristics of a server or electronic product.

[0250] 28, the first wiring electrode 1121 and the second wiring electrode 1122 may have different layer structures. The second wiring electrode 1122 may have a layer structure that does not include a seed layer. In contrast, the first wiring electrode 1121 may have a multi-layer structure that includes a seed layer.

[0251] For example, the first wiring electrode 1121 may include a first metal layer 1121-1 disposed below the third layer 1113 of the insulating layer 1110. The first metal layer 1121-1 may be an electroless plating layer. The first metal layer 1121-1 may be a chemical copper plating layer. The first wiring electrode 1121 may include a second metal layer 1121-2 disposed below the first metal layer 1121-1. The second metal layer 1121-2 may be an electrolytic plating layer formed by electrolytic plating using the first metal layer 1121-1 as a seed layer. In this case, a certain level of centerline average surface roughness Ra may be imparted to the lower surface of the third layer 1113 in contact with the first metal layer 1121-1. This embodiment may thereby improve adhesion between the first metal layer 1121-1 of the first wiring electrode 1121 and the insulating layer 1110. In this case, the first metal layer 1121-1 of the embodiment does not contact the first layer 1111 of the insulating layer 1110. That is, the first metal layer 1121-1 does not contact the reinforcing member 1111F provided on the first layer 1111 of the insulating layer 1110. As a result, the embodiment can solve the problem of the reinforcing member 1111F reducing the adhesion between the first metal layer 1121-1 and the insulating layer 1110. Furthermore, the embodiment can prevent the reinforcing member 1111F from increasing transmission loss of signals passing through the first metal layer 1121-1. As a result, the embodiment can improve the physical reliability and electrical reliability of the circuit board. This can ensure smooth operation of semiconductor devices, and further ensure smooth operation of servers and electronic products.

[0252] Furthermore, when the electrode unit 1120 includes a conductive metal unit 1124, the width of the conductive metal unit 1124 may be in the range of 40 μm to 70 μm. If the width of the conductive metal unit 1124 is smaller than 40 μm, the conductive metal unit 1124 may be too small and may collapse during thermocompression bonding. If the width of the conductive metal unit 1124 is larger than 70 μm, it may be difficult to accommodate the fine pitch of the terminals of the semiconductor element or the electrodes of the interposer.

[0253] Referring to FIG. 29, the electrode portion 1120 may further include a bonding portion 1125.

[0254] The bonding portion 1125 may protrude from the conductive metal portion 1124 in a direction away from the circuit board 1000. In this embodiment, the bonding portion 1125 is disposed on the upper side of the circuit board 1000, but is not limited thereto. For example, the bonding portion 1125 may also be disposed on the lower side of the circuit board 1000. In this case, the bonding portion 1125 may protrude above the upper surface of the first protective layer 1130. The conductive metal portion 1124 may be positioned lower than the upper surface of the first protective layer 1130. The bonding portion 1125 may be used to facilitate a fine bonding process.

[0255] 30, an electrode unit 1120 of a circuit board according to an embodiment may include a conductive metal portion 1124 having a structure that protrudes above an upper surface of a first protective layer 1130. For example, the upper surface of the conductive metal portion 1124 according to a second embodiment may be located lower than the upper surface of the first protective layer 1130. And, the upper surface of the conductive metal portion 1124 according to a third embodiment may be located lower than the upper surface of the first protective layer 1130, and a bonding portion 1125 may be disposed on the conductive metal portion 1124.

[0256] Alternatively, the conductive metal portion 1124 of the fourth embodiment may be provided by filling a portion of the recess 1110R and the opening of the first protective layer 1130. As a result, the conductive metal portion 1124 may have a structure that protrudes above the top surface of the first protective layer 1130.

[0257] Referring to FIG. 31, the circuit board of the embodiment can be a core board.

[0258] For example, the insulating layer of the circuit board may include a first insulating layer 1211 of the core layer. The first insulating layer 1211 may include a reinforcing member such as glass fiber. The insulating layer may include a second insulating layer 1212 provided on the first insulating layer 1211 and a third insulating layer 1213 provided below the first insulating layer 1211. The second insulating layer 1212 may have a structure in which multiple layers are stacked along the vertical direction. Exemplarily, the second insulating layer 1212 may be built up with multiple layers on the first insulating layer 1211, and each built-up layer may include the first layer 1111 and the second layer 1112 of the insulating layer 1110 described in FIG. 24. The third insulating layer 1213 may also have a structure corresponding to the second insulating layer 1212. The electrode portion 1220 may be disposed within the insulating layer. In this case, the electrode portion 1220 can be disposed in the second insulating layer 1212 and the third insulating layer 1213.

[0259] Each of the second insulating layer 1212 and the third insulating layer 1213 includes a first layer including a reinforcing member and a second layer not including a reinforcing member, as described above, and thereby can improve the electrical characteristics of the electrode part 1220 while ensuring adhesion to the electrode part 1220.

[0260] Meanwhile, when a semiconductor package having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect a semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical shorts between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it functions as a signal transmission device, it can solve noise problems. As a result, a circuit board having the above-described inventive features can maintain stable functionality in IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0261] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0262] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0263] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. an insulating layer; a pad portion disposed on the insulating layer; a conductive metal portion disposed on the pad portion; a protective layer disposed on the conductive metal portion; a bonding portion electrically connected to the conductive metal portion by penetrating at least a portion of the protective layer, the pad portion includes a first portion inclined so that its horizontal width increases along a vertical direction from an upper surface of the pad portion toward a lower surface of the insulating layer, and a second portion extending from the first portion and having a slope different from the slope of the first portion; The conductive metal portion is disposed to cover at least a portion of a side surface of the first portion.

2. 2. The circuit board according to claim 1, wherein the bonding portion includes a protrusion disposed on the protective layer and a through portion extending from the protrusion and penetrating at least a portion of the protective layer to be electrically connected to the conductive metal portion.

3. the insulating layer includes a reinforcing member; The circuit board according to claim 1 , wherein at least a part of a side surface of the first portion of the pad does not overlap the reinforcing member of the insulating layer along the horizontal direction.

4. a recess is provided in the upper surface of the insulating layer; The circuit board according to claim 1 , wherein the first portion of the pad portion is disposed within the recess.

5. The circuit board of claim 1 , wherein the conductive metal portion includes a metal material different from a metal material of at least one of the pad portion and the bonding portion.

6. The circuit board according to claim 2 , wherein the first portion of the pad has a curved side surface.

7. The circuit board according to claim 1 , wherein the through portion does not overlap the curved surface along a direction perpendicular to the curved surface.

8. The circuit board according to claim 7 , wherein a horizontal width of the protrusion is smaller than a width of the second portion of the pad.

9. 8. The circuit board according to claim 7, wherein the conductive metal portion includes a contact portion that contacts an upper surface of the first portion of the pad portion, and an extension portion that extends from the contact portion and does not overlap with the upper surface of the first portion along a direction perpendicular to the contact portion.

10. The circuit board according to claim 9 , wherein the extension overlaps the curved surface along a direction perpendicular to the curved surface.

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