Inter-line dielectric layer engineering for via void prevention

Abstract

Embodiments of the present disclosure provide methods for fabricating semiconductor devices with reduced via voids (e.g., gaps between a dielectric layer and a metal fill of a semiconductor device). One such technique includes forming a dielectric layer, where at least a portion of the dielectric layer includes a non-stoichiometric compound, forming one or more openings in the dielectric layer, filling the one or more openings with a metal, where the metal is disposed on a respective surface of the one or more openings, and exposing the dielectric layer and the metal disposed in the openings to an oxidizing atmosphere, where exposing the dielectric layer and the metal in the openings causes oxidation of the non-stoichiometric compound.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 409,657, filed September 23, 2022, and U.S. Provisional Patent Application No. 63 / 409,658, filed September 23, 2022, the contents of which are incorporated by reference in their entireties into this specification.

[0002] TECHNICAL FIELD

[0002] Embodiments of the present disclosure generally relate to methods for manufacturing semiconductor devices. [Background technology]

[0003] 2. Description of Related Art

[0003] Fabricating reliable features at and below 100 nm is one of the major technological challenges for the next generation of very large scale integration (VLSI) and ultra-large scale integration (ULSI) semiconductor devices. However, as the limits of circuit technology are pushed, shrinking dimensions in VLSI and ULSI technology are placing increasing demands on processing power. Forming reliable gate structures on substrates is critical to the success of VLSI and ULSI, and to the ongoing effort to increase circuit density and quality on individual substrates and dies.

[0004]

[0004] As the circuit density of next-generation devices increases, the widths of interconnects such as vias, trenches, contacts, gate structures, and other features, as well as the width of the dielectric material between these interconnects, are decreasing to dimensions of 45 nm and 32 nm and below, while the thickness of the dielectric layers remains essentially unchanged, resulting in an increase in the aspect ratio of the features. To enable the fabrication of next-generation devices and structures, three-dimensional (3D) stacking of semiconductor chips is often used to improve transistor performance. By arranging transistors in three dimensions instead of the traditional two dimensions, multiple transistors can be positioned closely together within an integrated circuit (IC). 3D stacking of semiconductor chips reduces wire length and keeps wiring delays low. In the fabrication of 3D stacked semiconductor chips, stair-like structures are often used, which allow multiple interconnect structures to be placed on top of them to form high-density vertical transistor devices.

[0005]

[0005] Conventional interconnect formation processes and interconnect designs result in high-resistivity structures due to the materials used in conventional component devices. In conventional methods, via filling is completed with a metal barrier, liner, and bulk-fill metal. The metal barrier and liner are used for reliability and gap-fill robustness. However, materials used for barrier and liner layers (e.g., titanium nitride (TiN) or tantalum nitride (TaN)) typically have high resistivity and can increase interconnect resistance when deposited at the via bottom. Interconnect resistance impacts the speed of the formed device as a result of power loss due to RC delay and IR drop. As design rules continue to shrink, reducing interconnect resistance has become an increasingly important priority. In particular, interconnect resistance significantly impacts overall resistance with short interconnect lines, smaller via dimensions (e.g., less than 40 nm), and multi-layer wiring with via stacks (i.e., higher resistance through the interconnect than through the line). Therefore, reducing interconnect resistance is becoming increasingly important to achieve chip performance.

[0006] Thus, there is a continuing need for improved methods of forming interconnections to reduce integrated circuit manufacturing costs, memory cell size, and power consumption, and to address the problems discussed above. Summary of the Invention

[0007]

[0007] One or more embodiments of the present disclosure are directed to a method for manufacturing a semiconductor device, the method including forming a dielectric layer, at least a portion of the dielectric layer comprising a nonstoichiometric compound, forming one or more openings in the dielectric layer, filling the one or more openings with a metal, the metal being disposed on a respective surface of the one or more openings, and exposing the dielectric layer and the metal disposed in the openings to an oxidizing atmosphere, wherein exposing the dielectric layer and the metal in the openings causes oxidation of the nonstoichiometric compound.

[0008]

[0008] One or more embodiments of the present disclosure are directed to a method for manufacturing a semiconductor device. The method includes exposing a patterned dielectric layer disposed on a substrate to an oxidizing atmosphere. The patterned dielectric layer includes a first dielectric layer having a plurality of openings, each having a metal layer disposed on a surface of the opening, the first dielectric layer including a non-stoichiometric compound. Exposing the patterned dielectric layer to the oxidizing atmosphere causes oxidation of the non-stoichiometric compound at the surface of the openings.

[0009] One or more embodiments of the present disclosure are directed to a method for manufacturing a semiconductor device, the method including forming a dielectric layer over a surface of a substrate, forming one or more openings in the dielectric layer, filling the one or more openings with a metal, the metal being disposed on a respective surface of the one or more openings, and implanting an oxygen-containing species into the dielectric layer to provide a dose of the oxygen-containing species to the one or more openings and the respective surface of the metal disposed thereon.

[0010]

[0010] One or more embodiments of the present disclosure are directed to a method for manufacturing a semiconductor device. The method includes implanting an oxygen-containing species into a patterned dielectric layer disposed over a substrate. The patterned dielectric layer includes a plurality of openings, each having a metal layer disposed on a surface of the opening, and implanting the oxygen-containing species into the dielectric layer provides a dose of the oxygen-containing species to a surface of each of the plurality of openings and the metal layer disposed thereon. After implanting the oxygen-containing species, the patterned dielectric layer is heated to oxidize a surface of each of the plurality of openings and the metal layer exposed to the dose of the oxygen-containing species.

[0011]

[0011] One or more embodiments of the present disclosure are directed to a semiconductor device comprising a substrate, a patterned dielectric layer disposed on the substrate, the patterned dielectric layer having a plurality of openings, a metal layer disposed on a surface of the plurality of openings, and a metal oxide layer at an interface between the metal layer and the surface of the plurality of openings.

[0012]

[0012] In order that the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the present disclosure, briefly summarized above, will be had by reference to embodiments. Some embodiments are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered to limit the scope of the present disclosure, which may also admit of other equally effective embodiments. [Brief explanation of the drawings]

[0013] [Figure 1]

[0013] FIG. 1 is a cross-sectional side view of an interconnect formed on a substrate in which one or more embodiments of the present disclosure may be implemented. [Figure 2]

[0014] 1 is a method for manufacturing a semiconductor device according to one or more embodiments of the present disclosure. [Figure 3]

[0015] 3 is a cross-sectional view of a portion of a semiconductor device formed using the method of FIG. 2 in accordance with one or more embodiments of the present disclosure. [Figure 4]

[0016] 1 is a multi-chamber processing system that can be used to implement one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0017] For ease of understanding, where possible, identical reference numerals have been used to designate identical elements common to the figures. It is envisioned that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0015]

[0018] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0016]

[0019] The term "substrate," as used herein and in the appended claims, refers to a surface or portion of a surface of a component upon which a process acts. Those skilled in the art will also understand that a reference to a substrate may refer to only a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, when reference is made to deposition on a substrate, it can refer to both a bare substrate and a substrate upon which one or more films or features have been deposited or formed.

[0017]

[0020] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates can be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps can be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayers as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0018]

[0021] FIG. 1 shows a cross-sectional side view of an interconnect formed in a substrate 110 and a dielectric layer 130, in which one or more embodiments of the present disclosure may be implemented.

[0019]

[0022] As shown, a first set of metal fill layers 120 may be formed on substrate 110. A dielectric layer 130 may be deposited over substrate 110 and metal fill layers 120, and a second set of metal fill layers 140 may be formed on dielectric layer 130. As shown, the second set of metal fill layers 140 may be aligned such that the second set of metal fill layers 140 are directly above and in contact with the first set of metal fill layers 120.

[0020]

[0023] In some embodiments, a selective metal fill layer may be used for intermediate line vias. For example, the second set of metal fill layers 140 may be a selective metal fill layer. The selective metal fill layer may be, for example, tungsten (W), aluminum (Al), molybdenum (Mo), cobalt (Co), titanium (Ti), tantalum (Ta), zirconium (Zr), platinum (Pt), zinc (Zn), hafnium (Hf), lead (Pb), nickel (Ni), iron (Fe), niobium (Ni), vanadium (V), or silicon (Si). In some embodiments, the selective metal fill layer includes a metal having a desired Pilling-Bedworth ratio, for example, a high Pilling-Bedworth ratio greater than 1. The selective metal fill layer may be referred to as a linerless fill layer because it does not require a conformal liner. Linerless fill layers generally have lower resistance than fill layers with liners and may be preferred for some devices. However, linerless fill layers can have adhesion problems with the surrounding dielectric, resulting in the presence of via voids (e.g., gaps) at the interface between the metal fill layer and the dielectric layer(s). These gaps can lead to defects in other areas of the circuit. For example, the gaps can cause yield defects in the formed circuit due to the diffusion and / or presence of residual wet etch chemicals, plasma etch chemicals, abrasive slurry components, and / or cleaning chemicals that attack the metal interconnect structure and / or underlying films during subsequent processing steps. Therefore, there is a need for a method to prevent or repair gaps at the interface between the metal fill layer and the dielectric layer.

[0021]

[0024] FIG. 2 illustrates a method of forming a semiconductor device according to one or more embodiments of the present disclosure.

[0022]

[0025] Method 200 may begin, in operation 210, by forming a dielectric layer (e.g., dielectric layer 130) over a surface of a substrate. In some embodiments, the dielectric material may be formed by depositing a stoichiometric dielectric film on the substrate. The process of forming the dielectric layer may be completed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or other useful deposition process. Method 200 may include, in operation 220, forming one or more openings in the dielectric layer. The one or more openings may be formed by etching one or more openings in the stoichiometric dielectric film.

[0023]

[0026] In operation 230, method 200 may include filling one or more openings with a metal (e.g., any of the metals described above), with the metal disposed on each surface of the one or more openings. Filling one or more openings with the metal may form a set of metal fill layers (e.g., second set of metal fill layers 140). The process of forming the metal fill layers may be completed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or any other useful deposition process. The deposition process performed during operation 230 is preferably a selective deposition process that does not form a layer of overfill material on the field regions of the substrate (i.e., the regions of the substrate surface between the openings) to avoid the need to perform a chemical mechanical polishing (CMP) process to remove the overfill layer. FIG. 1 illustrates the desirably formed metal layer without the overfill layer.

[0024]

[0027] However, in some embodiments, method 200 may optionally include removing overfill formed on or above the "field area" of the substrate during operation 230. In one example, the overfill removal process may include using a slurry-free chemical mechanical polishing (CMP) process. If overfill removal is performed, the substrate may need to be cleaned and dried.

[0025]

[0028] 3, the method 200 includes implanting an oxygen-containing species into the dielectric layer to provide a dose of the oxygen-containing species to the one or more openings and respective surfaces of a metal layer disposed therein (e.g., metal fill layer 140). The implantation process may cause a localized metal oxide layer to form (e.g., grow) on the exposed surface of the metal fill layer at an interface with the surface of the opening formed in the dielectric layer.

[0026]

[0029] In some embodiments, implanting the oxygen-containing species includes using a tilted beam implantation process. In some embodiments, implanting the oxygen-containing species includes annealing the dielectric layer 130 and the metal fill layer 140 to promote the formation of a metal oxide. Optionally, operation 240 may also include heating the patterned dielectric layer after implanting the oxygen-containing species to oxidize the surfaces of the one or more openings and the metal fill layer, respectively, that were exposed to the dose of oxygen-containing species. In one embodiment, the implantation process includes a hot tilted beam implantation process, which includes oxygen species in the beam. The implantation process may also be performed using thermion hot implant or other suitable means of oxidizing the dielectric layer.

[0027]

[0030] In one embodiment, the process of implanting oxygen-containing species into the dielectric layer 130 and the metal fill layer 140 may include implanting the oxygen-containing species while the substrate is maintained at a temperature between 20 and 500°C. In some embodiments, a dose of 10 to 10 may be implanted using an implant energy between 0.5 eV and 25 eV. The oxygen-containing species may be implanted at a tilt angle between 0 and 75 degrees. During implantation, the substrate may be rotated incrementally (e.g., 90 degrees, 180 degrees) to allow implantation of the oxygen-containing species into all exposed surfaces of the metal fill layer 140. The substrate may also be annealed at a temperature between 300 and 600°C for 5 to 120 seconds after performing the implantation process.

[0028]

[0031] In certain embodiments, by implanting oxygen-containing species into the dielectric layer and the metal fill layer, a metal oxide layer may grow on the exposed surfaces of the metal fill layer, thereby closing gaps formed between the metal fill layer and the dielectric layer due to poor adhesion between the metal fill layer and the dielectric layer.

[0029]

[0032] 3 illustrates cross-sectional views of dielectric layer 130 and metal fill layer 140 before and after operation 240 in method 200 of FIG. 2. In some embodiments, as shown, an intervening dielectric layer 310 may be disposed below dielectric layer 130. In some embodiments, intervening dielectric layer 310 may be considered part of dielectric layer 130. As shown, openings may be formed in both dielectric layer 130 and intervening dielectric layer 310, and metal fill layer 140 may be disposed on the surfaces of the openings in both dielectric layer 130 and intervening layer 310.

[0030]

[0033] The cross-sectional view to the left of the arrow in FIG. 3 illustrates the dielectric layer 130 and the metal fill layer 140 prior to operation 240 in FIG. 2 . As shown, a gap 320 exists between the metal fill layer 140 and the dielectric layer 130 due to adhesion issues. During operation 240, oxygen-containing species 330 are implanted into the dielectric layer to provide a dose of oxygen-containing species 330 to one or more openings disposed therein and to the respective surfaces of the metal fill layer 140. In some embodiments, implanting the oxygen-containing species 330 may include using a high-temperature oxygen gradient implant process, as illustrated. In some embodiments, the process of implanting the oxygen-containing species into the dielectric layer includes performing an ultra-shallow implant such that the depth of the implanted oxygen-containing species substantially reaches at least one of the surfaces of the one or more openings and the metal disposed thereon. Generally, it is desirable to perform the ultra-shallow implant process so that the implanted species does not significantly damage the surface of the metal fill layer 140 positioned adjacent to the surfaces of the openings. The dose of oxygen-containing species is 1×10 20 atoms / cm 2 It may exceed this.

[0031]

[0034] The cross-sectional view to the right of the arrow in FIG. 3 shows dielectric layer 130 and metal fill layer 140 after operation 240 in FIG. 2 (eg, dielectric layer 130 and metal fill layer 140 are implanted with oxygen-containing species 330).

[0032]

[0035] After trench patterning, filling, and CMP planarization, dielectric layer 130 and metal fill layer 140 may be implanted with an oxygen-containing compound (e.g., using hot ion implantation). As shown in the right cross-sectional view of FIG. 3, a metal oxide layer 340 has grown on the exposed surface of metal fill layer 140 as a result of the implantation process(es) performed during operation 240. In some embodiments, the implantation forms (e.g., grows) metal oxide layer 340 on the exposed surface of metal fill layer 140. Metal oxide layer 340 thereby closes gaps (e.g., gap 320) at the interface between metal fill layer 140 and dielectric layer 130. In one example, metal fill layer 140 may be tungsten, and metal oxide layer 340 may be a localized tungsten oxide (e.g., WOx, W2O3, WO5, etc.).

[0033]

[0036] In some embodiments, the metal fill layer 140 may be any suitable metal having a high Pilling-Bedworth ratio (e.g., a Pilling-Bedworth ratio greater than 1). It is believed that utilizing a metal layer with a high Pilling-Bedworth ratio may be used to ensure that the metal fill layer 140 forms a metal oxide layer 340 with sufficient volume expansion to fill gaps at the interface between the metal fill layer 140 and the dielectric layer 130. Such a metal may be, for example, tungsten (W), aluminum (Al), molybdenum (Mo), cobalt (Co), titanium (Ti), tantalum (Ta), zirconium (Zr), platinum (Pt), zinc (Zn), hafnium (Hf), lead (Pb), nickel (Ni), iron (Fe), niobium (Ni), vanadium (V), or silicon (Si).

[0034]

[0037] In some embodiments, at least the surface of the metal fill layer adjacent to the surface of the opening is exposed to a dose of implanted hydrogen species. The surface of the metal fill layer can then be subjected to a process to implant germanium. The hydrogen content can be increased by: 1) adding H2 gas during the process; 2) reducing the deposition temperature; 3) reducing the plasma power; or 4) reducing the oxidizer concentration. Typical hydrogen contents in films are within the range of 3% to 50%, and the benefits of increasing the hydrogen content are improved etch rate, reduced etch selectivity, reduced film stress, reduced density, and improved transparency.

[0035]

[0038] In some embodiments, the dielectric layer 130 and / or the metal fill layer 140 may be doped with heavy impurities (e.g., germanium (Ge) or argon (Ar)). Doping the dielectric layer 130 and / or the metal fill layer 140 with heavy impurities results in a mechanical volume expansion. Thus, the gap at the interface between the metal fill layer 140 and the dielectric layer 130 may be filled without a chemical reaction (e.g., without oxidation).

[0036]

[0039] The methods described herein may have beneficial applications beyond via void repair. For example, the methods described herein may also be utilized to induce compressive stress on or within various components (e.g., metal fill layer 140) of a formed IC device. The generated compressive stress may be used to modify the electrical conductivity and / or contact resistance of portions of interconnect structures within the formed IC device.

[0037]

[0040] 4 shows a multi-chamber processing system 400. The processing system 400 may include load lock chambers 402, 404, a robot 406, a transfer chamber 408, processing chambers 410, 412, 414, 416, 418, and 428, and a controller 420. The load lock chambers 402, 404 allow for the transfer of substrates (e.g., substrate 110, not shown) into and out of the processing system 400. The load lock chambers 402, 404 can pump down substrates introduced into the processing system 400 and maintain a vacuum seal. The robot 406 can transfer substrates between the load lock chambers 402, 404 and the processing chambers 410, 412, 414, 416, 418, and 428. The robot 406 can also transfer substrates between the load lock chambers 402, 404 and the transfer chamber 408.

[0038]

[0041] Each processing chamber 410, 412, 414, 416, 418, and 428 may be equipped to perform several substrate operations, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), dry etching, pre-cleaning, degassing, thermal treatment (e.g., annealing), orientation, or other substrate processes. Additionally, each processing chamber 410, 412, 414, 416, 418, and 428 may be equipped to deposit a dielectric barrier layer, deposit a dielectric layer, form one or more vias and / or trenches in the stack, perform one or more pre-cleaning processes, deposit a first metal material layer, and deposit a second metal material layer.

[0039]

[0042] The controller 420 may be configured to operate all aspects of the processing system 400, such as the method 200 disclosed in Figure 2. For example, the controller 420 may be configured to control a method of forming a dielectric layer (e.g., the dielectric layer 130) on a substrate, forming one or more openings in the dielectric layer, filling the one or more openings with a metal (e.g., the metal fill layer 140), and implanting an oxygen-containing species into the dielectric layer to provide a dose of the oxygen-containing species to a surface of each of the one or more openings and metal disposed therein.

[0040]

[0043] Each processing chamber 410, 412, 414, 416, 418, and 428 can rotate the substrate so that the sidewalls on each side of the metal fill can be treated with angled oxygen implants. For example, the substrate can be rotated in 90 or 180 degree increments.

[0041]

[0044] The controller 420 includes a programmable central processing unit (CPU) 422 operable with a memory 424 and mass storage device, an input control unit, and a display unit (not shown) (e.g., power supplies, clocks, cache, input / output (I / O) circuitry, and liners) coupled to various components of the processing system to facilitate control of substrate processing. The controller 420 also includes hardware for monitoring substrate processing through sensors in the processing system 400, including sensors that monitor the flow of precursors, process gases, and purge gases. Other sensors measuring system parameters such as substrate temperature and ambient chamber pressure may also provide information to the controller 420.

[0042]

[0045] To facilitate control of the above-described process chamber 400, the CPU 422 may be one of any form of general-purpose computer processor available in an industrial setting, such as a programmable logic controller (PLC), to control the various chambers and sub-processors. A memory 424 is coupled to the CPU 422 and may be non-transitory and comprise one or more of readily available memory, such as random access memory (RAM), read-only memory (ROM), a floppy disk drive, a hard disk, or any other form of local or remote digital storage. Support circuits 426 are coupled to the CPU 422 to support the processor in a conventional manner. Charged species generation, heating, and other processes are typically stored in the memory 424, typically as software routines. The software routines may also be stored and / or executed by a second CPU (not shown) located remotely from the hardware controlled by the CPU 422.

[0043]

[0046] The memory 424 is in the form of a computer-readable storage medium containing instructions that, when executed by the CPU 422, facilitate operation of the processing system 400. The instructions in the memory 424 are in the form of a program product, such as a program that implements the methods of the present disclosure. The program code may conform to any one of several different programming languages. In one example, the present disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The program(s) in the program product define the functions of the embodiments (including the methods described herein). Exemplary computer-readable storage media include, but are not limited to, (i) a non-writable storage medium in which information is permanently stored (e.g., a read-only memory device in a computer, such as a CD-ROM disk readable by a CD-ROM drive, a flash memory, a ROM chip, or any type of solid-state non-volatile semiconductor memory); and (ii) A writable storage medium (e.g., a floppy disk in a disk drive or hard disk drive, or any type of solid-state random access semiconductor memory) on which changeable information is stored. Such computer-readable storage medium, when bearing computer-readable instructions that direct the functions of the methods described herein, constitutes an embodiment of the present disclosure.

[0044]

[0047] The method 200 described above is not limited to being tied solely to the processing system 400. For example, one or more steps of the method 200 may be performed in a processing chamber external to the processing system 400.

[0048] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. 1. A method for manufacturing a semiconductor device, comprising: forming a dielectric layer, wherein at least a portion of the dielectric layer comprises a non-stoichiometric compound; forming one or more openings in the dielectric layer; filling the one or more openings with a metal, the metal being disposed on a surface of each of the one or more openings; exposing the dielectric layer and the metal disposed in the opening to an oxidizing atmosphere; wherein exposing the dielectric layer and metal causes oxidation of the non-stoichiometric compound.

2. The method of claim 1 , wherein the non-stoichiometric compound of the dielectric layer comprises silicon-rich silicon oxide.

3. The method of claim 1 , wherein exposing the dielectric layer and the metal disposed in the opening to an oxidizing atmosphere comprises annealing the non-stoichiometric compound in a low temperature oxidizing environment.

4. The method of claim 1 , wherein forming the dielectric layer comprises depositing a film comprising a non-stoichiometric silicon-containing compound.

5. forming the dielectric layer depositing a stoichiometric film in which the one or more openings are formed; depositing a liner within the opening; 2. The method of claim 1, wherein the liner comprises the non-stoichiometric compound.

6. The method of claim 1 , wherein exposing the dielectric layer and the metal disposed in the openings to an oxidizing atmosphere grows the dielectric layer on the surface of each of the one or more openings.

7. The method of claim 1 , wherein exposing the dielectric layer and the metal disposed in the openings to an oxidizing atmosphere causes the dielectric layer to expand at the surface of each of the one or more openings.

8. the one or more openings in the dielectric layer are formed in a surface of the dielectric layer; filling the one or more openings with the metal further comprises forming a layer of the metal on the surface of the dielectric layer; The method comprises: The method of claim 1 , further comprising removing the layer of the metal from the surface of the dielectric layer before exposing the dielectric layer and the metal disposed in the opening to an oxidizing atmosphere.

9. 1. A method for manufacturing a semiconductor device, comprising: exposing a patterned dielectric layer disposed on a substrate to an oxidizing atmosphere; the patterned dielectric layer comprising a first dielectric layer comprising a plurality of openings, each of the openings comprising a metal layer disposed on a surface of the opening; the first dielectric layer comprises a non-stoichiometric compound; The method, wherein exposing the patterned dielectric layer to an oxidizing atmosphere causes oxidation of the non-stoichiometric compound at the surface of the opening.

10. 10. The method of claim 9, wherein the non-stoichiometric compound of the first dielectric layer comprises silicon-rich silicon oxide.

11. 10. The method of claim 9, wherein exposing the patterned dielectric layer to an oxidizing atmosphere comprises annealing the non-stoichiometric compound in a low temperature oxidizing environment.

12. The method of claim 9 , wherein the first dielectric layer comprises a film including a non-stoichiometric silicon-containing compound.

13. the patterned dielectric layer is a stoichiometric membrane in which the opening is formed; a liner within one or more of said openings; 10. The method of claim 9, wherein the liner comprises the non-stoichiometric compound.

14. 10. The method of claim 9, wherein exposing the patterned dielectric layer to an oxidizing ambient causes the dielectric layer to grow on the surfaces of one or more of the openings.

15. 10. The method of claim 9, wherein exposing the patterned dielectric layer to an oxidizing ambient causes the dielectric layer to expand at the surface of one or more of the plurality of openings.

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