Stream processor, calculation method, chip and electronic device

Abstract

A stream processor, an operation method, a chip, and an electronic device are provided. The stream processor includes at least two types of arithmetic units and a master control unit, each of which is configured to perform one of the following operations: multiplication, addition, lookup table, and data migration. The master control unit is connected to each of the arithmetic units and configured to send operation instructions to the arithmetic units to cause the arithmetic units to perform corresponding arithmetic operations in response to the operation instructions.

Description

[Technical Field]

[0001] The present application belongs to the technical field of electronic circuits, and in particular to stream processors, computing methods, chips and electronic devices. [Background technology]

[0002] Depending on the network model, each computation task is different, making it difficult to process multiple computation tasks using a single computation module. For example, the softmax (softmax function) computation task is significantly different from the convolution computation task or matrix multiplication computation task, making it difficult to directly compute softmax using a convolution module or matrix multiplication module.

[0003] Currently, it is common to install a dedicated computing module for each network model or use a GPGPU (General-Purpose Graphics Processing Unit) with higher general-purpose computing power. However, dedicated computing modules are designed only for one specific network type and cannot compute other types of networks, so dedicated computing modules have low flexibility. Furthermore, when multiple network models need to be supported, computing modules corresponding to each network model must be merged and optimized, resulting in a significant increase in area. GPGPUs have extremely high general-purpose computing power, but occupy a relatively large area. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application provides a stream processor, a computing method, a chip, and an electronic device that can improve the problems of the low versatility of conventional dedicated computing modules and the relatively large area occupied by GPGPUs. [Means for solving the problem]

[0005] In a first aspect, the present application provides a stream processor, comprising at least two types of arithmetic units and a master control unit, each of the arithmetic units configured to perform one of a multiplication operation, an addition operation, a lookup table operation, and a data migration operation, and the master control unit is connected to each of the arithmetic units and configured to send an operation command to the arithmetic units to cause the arithmetic units to perform the corresponding arithmetic operation in response to the operation command.

[0006] In the embodiments of the present application, different computational units cooperate to realize different computational logics, thereby enabling processing of multiple different computational tasks. Therefore, the embodiments of the present application can support computational tasks of different network models with a single stream processor, providing greater versatility compared to dedicated computation modules. Furthermore, because a single stream processor can support computational tasks of different network models, it is unnecessary to install multiple stream processors, resulting in a smaller footprint compared to a GPGPU.

[0007] Each arithmetic unit is directly controlled by a master control unit within the stream processor, and instructions are sent directly by the master control unit to the specific arithmetic unit that performs the specified operation. This reduces the process of sending operation instructions to the GPGPU, eliminating the need to install a hardware unit in the GPGPU to send operation instructions, and therefore reducing the area occupied by the GPGPU.

[0008] In some possible embodiments of the technical solution according to the first aspect above, the number of arithmetic units of at least some types among the at least two types of arithmetic units is multiple, and the command receiving ends of the multiple arithmetic units of the same type are connected to each other and to the master control unit.

[0009] In the embodiment of the present application, the command receiving ends of a plurality of the same type of arithmetic units are connected to each other and to the master control unit, so that a plurality of the same type of arithmetic units can synchronously execute the same arithmetic operation, thereby allowing a plurality of the same type of arithmetic units to synchronously process a plurality of sets of data, thereby improving data processing efficiency.The master control unit can control a plurality of the same type of arithmetic units to synchronously process a plurality of sets of data by sending an operation command once, eliminating the need to send an operation command multiple times, reducing the number of command transmissions and improving data processing efficiency.

[0010] In some possible embodiments of the technical solution according to the first aspect, the stream processor further includes at least one data storage unit, and the plurality of same-type arithmetic units are connected to different data storage units, respectively.

[0011] In the embodiments of the present application, multiple arithmetic units of the same type are each connected to different data storage units, so that multiple arithmetic units of the same type do not acquire data from the same data storage unit in duplicate, i.e., do not acquire the same set of data in duplicate, thereby reducing the probability that the same set of data is processed multiple times in duplicate and reducing waste of arithmetic resources.

[0012] In some possible embodiments of the technical solution according to the first aspect above, the stream processor further includes a statistical calculation unit, which is connected to the master control unit and each of the data storage units, and is configured to perform a maximum value calculation or a sum calculation on target data in the data storage units in response to an operation command sent by the master control unit.

[0013] In the embodiment of the present application, a statistical calculation unit is connected to each of the data storage units, so that the statistical calculation unit can acquire target data from each of the data storage units and perform a process of calculating the maximum value or the sum of the target data. In this way, by installing the statistical calculation unit, it is not necessary to use a second type of calculation unit that performs addition calculations to calculate the sum multiple times, or to install an additional comparator to calculate the maximum value, thereby improving data processing efficiency.

[0014] In the technical solution according to the above first aspect, in some possible embodiments, the numbers of different types of arithmetic units are the same.

[0015] In the embodiments of the present application, since the number of different types of arithmetic units is the same, each data storage unit is connected to all arithmetic units, so that all arithmetic units connected to each data storage unit can process the same arithmetic task, and multiple sets of data can be processed synchronously by all arithmetic units connected to each data storage unit. Since the processing logic executed by the arithmetic units corresponding to each data memory is the same, the processing efficiency of multiple sets of data that require the execution of the same arithmetic logic can be improved.

[0016] In some possible embodiments of the technical solution according to the first aspect above, the at least two types of arithmetic units include a first type of arithmetic unit, a second type of arithmetic unit, a third type of arithmetic unit, and a fourth type of arithmetic unit, wherein the first type of arithmetic unit is an arithmetic unit that performs a multiplication operation, the second type of arithmetic unit is an arithmetic unit that performs an addition operation, the third type of arithmetic unit is an arithmetic unit that performs a lookup table operation, and the fourth type of arithmetic unit is an arithmetic unit that performs a shift operation.

[0017] In the embodiments of the present application, the first type of computing unit, the second type of computing unit, the third type of computing unit, and the fourth type of computing unit work together to realize the processing logic for a relatively large number of computing tasks, thereby increasing the application scenarios of the present invention.

[0018] In some possible embodiments of the technical solution according to the above first aspect, the stream processor further includes a table storage unit, the table storage unit is configured to store a function relationship table, the table storage unit is connected to each of the third type of arithmetic units, and the third type of arithmetic units are configured to perform lookup table operations on the function relationship table in the table storage unit in response to operation instructions sent by the master control unit.

[0019] In the embodiment of the present application, the table storage unit stores the function relationship table, and the third type of calculation unit can perform lookup table calculations on the function relationship table in the table storage unit, thereby reducing the amount of calculation for complex functions and improving the data processing efficiency of the present invention.

[0020] In some possible embodiments of the technical solution according to the above first aspect, the stream processor further includes an instruction storage unit, the instruction storage unit is connected to the master control unit and configured to store operation instructions, and the master control unit is further configured to obtain the operation instructions from the instruction storage unit.

[0021] In the embodiment of the present application, the operation instructions are stored in a command memory unit, so that there is no need to obtain the operation instructions from outside, and the present invention can be implemented independently, thereby broadening the scope of application of the present invention.

[0022] In a second aspect, the present application provides a computing method for use in the stream processor according to the first aspect and / or any one of the embodiments according to the first aspect, the computing method including the steps of: sending an operation instruction to the computing unit by the master control unit; and executing, by the computing unit, an operation corresponding to the computing unit in response to the operation instruction.

[0023] In a third aspect, the present application provides a chip, the chip comprising the stream processor according to the first aspect above and / or any one of the embodiments according to the first aspect above.

[0024] In a fourth aspect, the present application provides an electronic device, the electronic device comprising the chip according to the third aspect.

[0025] In order to more clearly explain the technical solutions of the embodiments of the present application, the drawings used in the embodiments will be briefly described below. The drawings described are only for illustrating some embodiments of the present application and are not intended to limit the scope. Those skilled in the art can obtain other related drawings based on these drawings without using inventive abilities. [Brief explanation of the drawings]

[0026] [Figure 1] 1 is a block diagram illustrating a configuration of a first type stream processor according to an embodiment of the present application. [Figure 2] FIG. 2 is a block diagram showing the configuration of an adder according to an embodiment of the present application. [Figure 3] FIG. 2 is a block diagram illustrating a configuration of a second type of stream processor according to an embodiment of the present application. [Figure 4] FIG. 10 is a block diagram illustrating a configuration of a third type of stream processor according to an embodiment of the present application. [Figure 5] FIG. 10 is a block diagram illustrating a configuration of a fourth type of stream processor according to an embodiment of the present application. [Figure 6]FIG. 10 is a block diagram showing the configuration of a fifth type stream processor according to an embodiment of the present application. [Figure 7] FIG. 10 is a block diagram showing the configuration of a sixth type stream processor according to an embodiment of the present application. [Figure 8] FIG. 10 is a block diagram showing the configuration of a seventh type stream processor according to an embodiment of the present application. [Figure 9] FIG. 10 is a block diagram showing the configuration of an eighth type stream processor according to an embodiment of the present application. [Figure 10] FIG. 10 is a block diagram showing the configuration of a ninth type stream processor according to an embodiment of the present application. [Figure 11] 1 is a schematic flow chart of a computational method according to an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0027] The terms "first," "second," "third," etc. are for descriptive purposes only and do not denote any ordering or relative importance stated or implied.

[0028] The technical solution of the present application will be described in detail below with reference to the drawings.

[0029] Figure 1 is a block diagram showing the configuration of a stream processor according to an embodiment of the present application. As shown in Figure 1, the stream processor includes at least two types of arithmetic units and a master control unit, and the master control unit is connected to each of the arithmetic units.

[0030] Each of the various types of arithmetic units of the at least two types of arithmetic units is configured to perform one of the following types of operations: a multiplication operation, an addition operation, a look-up table operation, and a data shift operation.

[0031] Optionally, the at least two types of arithmetic units include at least two types of arithmetic units from a first type of arithmetic unit, a second type of arithmetic unit, a third type of arithmetic unit and a fourth type of arithmetic unit.

[0032] The first type of arithmetic unit is an arithmetic unit that performs a multiplication operation, for example, the first type of arithmetic unit is an arithmetic unit that performs a multiplication operation, such as a multiplier.

[0033] The second type of arithmetic unit is an arithmetic unit that performs an addition operation, for example, an arithmetic unit of the second type is an arithmetic unit that performs an addition operation, such as an adder.

[0034] A subtraction operation in the conventional sense is essentially an operation of inverting one of the numbers and then adding it. That is, a subtraction operation is essentially an addition operation, and can be realized by a second-type arithmetic unit. For example, 3-1 can be regarded as the addition of 3 and -1. Therefore, by installing a corresponding inversion circuit within the second-type arithmetic unit, a subtraction operation can be realized by the second-type arithmetic unit. For example, as shown in FIG. 2, the inputs of one branch of an adder (In_1 shown in FIG. 2) are connected by a multiplexer, and the input of one branch of the multiplexer is the original data, and the input of the other branch of the multiplexer is an inversion circuit, and the input of the inversion circuit is the original data. In this way, when a subtraction operation is required, the inversion circuit is selected, and when an addition operation is required, the original data is selected.

[0035] The third type of arithmetic unit is an arithmetic unit that performs lookup table calculations. Lookup table calculations search for a dependent variable corresponding to an input independent variable from a predetermined function relationship table based on the input independent variable. For example, the function relationship table records the correspondence between A and B, and the third type of arithmetic unit can search the predetermined function relationship table based on A to obtain B.

[0036] The fourth type of arithmetic unit is an arithmetic unit that executes a migration operation, which is an operation to change the storage location of data in the data storage unit, for example, an operation to migrate and store data A from a first location to a second location in the storage area.

[0037] The master control unit is configured to send operation instructions to the arithmetic units to cause the arithmetic units to perform their corresponding arithmetic operations in response to the operation instructions.

[0038] The master control unit can be any circuit that can realize sending operation commands to the arithmetic units, and the specific circuit configuration of the master control unit is not limited here.

[0039] The different arithmetic units perform corresponding arithmetic operations, for example, a first type of arithmetic unit performs a multiplication operation, a second type of arithmetic unit performs an addition operation, a third type of arithmetic unit performs a lookup table operation, and a fourth type of arithmetic unit performs a shift operation.

[0040] The connection manner between the at least two computing units and the master control unit includes, but is not limited to, the following embodiments.

[0041] In the first embodiment, each computing unit is connected to a master control unit, respectively. For easy understanding, please refer to FIG.

[0042] Each operation command sent by the master control unit controls only one arithmetic unit to perform the corresponding arithmetic operation of the arithmetic unit.

[0043] In this way, the master control unit can independently control whether or not to execute each arithmetic unit, thereby enabling more flexible control of the arithmetic units, preventing unnecessary operations by the arithmetic units, and improving the efficiency of resource utilization within the stream processor.

[0044] In a second embodiment, the number of at least some of the at least two types of arithmetic units is multiple, and the command receiving ends of the multiple arithmetic units of the same type are connected to each other and to the master control unit. Since the command receiving ends of the multiple arithmetic units of the same type are connected to each other and to the master control unit, the multiple arithmetic units of the same type can synchronously perform the same arithmetic operation, thereby allowing the multiple arithmetic units of the same type to synchronously process multiple sets of data, thereby improving data processing efficiency.

[0045] For ease of understanding, as shown in Figure 4, in an example where the at least two types of arithmetic units include two first-type arithmetic units and one second-type arithmetic unit, the command receiving ends of the two first-type arithmetic units are connected to each other and connected to the master control unit, so that the master control unit can control the two first-type arithmetic units simultaneously to synchronously perform corresponding multiplication operations using one command. In this way, the master control unit can control multiple arithmetic units of the same type to synchronously perform the same arithmetic operation by sending one operation command, so that when multiple arithmetic units of the same type process data synchronously, there is no need to send operation commands multiple times, reducing the number of times commands are sent and improving data processing efficiency.

[0046] The above examples are for ease of understanding only and are not intended to limit the present application.

[0047] In a third embodiment, the number of at least some of the at least two types of arithmetic units is plural, and the instruction receiving ends of the same arithmetic units of a specified type are connected to each other and to the master control unit, and the other types of arithmetic units are respectively connected to the master control unit.

[0048] The designated type may be one type or multiple types, and the designated type is not limited to a specific type.

[0049] For ease of understanding, as shown in Figure 5, in an example where the at least two types of arithmetic units include two first type arithmetic units and three second type arithmetic units, the command receiving ends of the two first type arithmetic units are connected to each other and connected to the master control unit, so that the master control unit can simultaneously control the two first type arithmetic units to synchronously perform corresponding multiplication operations through one command. The three second type arithmetic units are respectively connected to the master control unit.

[0050] The above examples are for ease of understanding only and are not intended to limit the present application.

[0051] In the fourth embodiment, the computing units are divided into a plurality of computing unit groups, each of which includes at least two types of computing units, and the connection between each group of computing units and the master control unit is the same as that in the second embodiment.

[0052] The instruction receiving ends of the same type of arithmetic units in different arithmetic unit sets are not connected to each other.

[0053] Optionally, the types and numbers of arithmetic units included in each set of arithmetic units may be the same or different.

[0054] For ease of understanding, an example will be described in which there are three sets of arithmetic units, each of which includes two first-type arithmetic units and one second-type arithmetic unit, as shown in FIG.

[0055] For each set of computing units (the area surrounded by the dotted line in Figure 6), the command receiving terminals of two first-type computing units are connected to each other and to the master control unit, and the command receiving terminals of the first-type computing units in different sets of computing units are not connected. One second-type computing unit is connected to the master control unit.

[0056] The above examples are for ease of understanding only and are not intended to limit the present application.

[0057] In one embodiment, the stream processor further includes at least one data storage unit, and the number of at least some types of arithmetic units among the at least two types is plural, and the instruction receiving terminals of the plural arithmetic units of the same type are connected to each other, and the plural arithmetic units of the same type are respectively connected to different data storage units. Since the arithmetic units of the same type are respectively connected to different data storage units, it is possible to prevent the arithmetic units of the same type from acquiring the same set of data in duplicate and to prevent the same set of data from being processed multiple times.

[0058] The data storage units may be different areas of the same memory, or each data storage unit may be a single memory, which may be any medium capable of storing data, such as a portable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0059] Optionally, the results obtained by the operations of each arithmetic unit are stored in a data storage unit connected thereto.

[0060] For ease of understanding, as shown in FIG. 7, in an example where the at least two types of arithmetic units include a first type of arithmetic unit A, a first type of arithmetic unit B, a second type of arithmetic unit A, a data storage unit A, and a data storage unit B, the command receiving ends of the first type of arithmetic unit A and the first type of arithmetic unit B are connected to each other and to the master control unit, and the first type of arithmetic unit A is connected to the data storage unit A, and the first type of arithmetic unit B is connected to the data storage unit B.

[0061] The second type arithmetic unit A can be connected to either one of the data storage unit A or the data memory B. The example here is only for ease of understanding and is not intended to limit the present application.

[0062] Optionally, the data storage unit includes a scalar storage unit and a vector storage unit. In a specific implementation of the connection between the arithmetic unit and the data storage unit, the arithmetic unit is connected to each of the scalar storage unit and the vector storage unit of the data storage unit.

[0063] The scalar storage unit and the vector storage unit may be different areas in the same memory, or may be independent memories. The specific implementation method and principle of the memory here are the same as those of the memory described above, and for simplicity's sake, the description will be omitted here.

[0064] Optionally, there are different numbers of different types of arithmetic units, in which case some data stores are connected to each of the various types of arithmetic units and other data stores are connected to only some types of arithmetic units.

[0065] 8, when the at least two types of arithmetic units include a first type arithmetic unit and a second type arithmetic unit, the stream processor includes n first type arithmetic units and m second type arithmetic units, where n and m are positive integers and satisfy n>m. Correspondingly, the stream processor further includes n data storage units.

[0066] In this case, each data storage unit is connected to one first-type arithmetic unit. m data storage units are connected to one second-type arithmetic unit. The instruction receiving ends of the n first-type arithmetic units are connected to each other, and the instruction receiving ends of the m second-type arithmetic units are connected to each other. This example is merely for ease of understanding and does not limit the present application.

[0067] Optionally, the number of different types of arithmetic units is the same.

[0068] Since the number of different types of arithmetic units is the same, each data storage unit is connected to all arithmetic units, and as a result, the arithmetic tasks that can be processed by all arithmetic units connected to each data storage unit are the same, and multiple sets of data can be processed synchronously by all arithmetic units connected to each data storage unit.Since the processing logic executed by the arithmetic units corresponding to each data memory is the same, the processing efficiency of multiple sets of data that require the execution of the same arithmetic logic can be improved.

[0069] For example, as shown in Figure 9, if the at least two types of arithmetic units include a first type arithmetic unit and a second type arithmetic unit, the stream processor includes n first type arithmetic units and n second type arithmetic units, where n is a positive integer. Correspondingly, the stream processor further includes n data storage units.

[0070] In this case, each data storage unit is connected to one first-type arithmetic unit and one second-type arithmetic unit. The instruction receiving ends of the n first-type arithmetic units are connected to each other, and the instruction receiving ends of the n second-type arithmetic units are connected to each other. This example is for ease of understanding only and does not limit the present application.

[0071] Optionally, when the at least two types of arithmetic units include a first type arithmetic unit, a second type arithmetic unit, a third type arithmetic unit, and a fourth type arithmetic unit, each data storage unit is connected to one first type arithmetic unit, one second type arithmetic unit, one third type arithmetic unit, and one fourth type arithmetic unit.

[0072] Since the processing logic for most calculation tasks can be realized by multiplication operations, addition operations, lookup table operations, and transition operations, four types of calculation units connected to the same data storage unit can realize processing for one calculation task, and four types of calculation units connected to multiple data storage units can simultaneously realize processing for multiple sets of processing target data for the same calculation task, thereby improving data processing efficiency.

[0073] Optionally, in a third type of embodiment, the stream processor further comprises a statistics calculation unit, the statistics calculation unit being connected to the master control unit and each of the data stores.

[0074] The statistical calculation unit is configured to perform a maximum or sum calculation on the target data in the data store in response to an operation command sent by the master control unit.

[0075] Since the statistical calculation unit is connected to each of the data storage units, the statistical calculation unit can acquire target data from each of the data storage units and perform a process to find the maximum value or a process to find the sum of the target data. This eliminates the need to use a second type of calculation unit that performs addition calculations to find the sum multiple times to calculate the maximum value, thereby improving data processing efficiency.

[0076] The target data may be target data stored in advance in the data storage unit. In this case, the statistical calculation unit directly acquires the corresponding target data from each data storage unit, and performs a process of finding the maximum value or a cumulative addition process of finding the sum of all the acquired target data.

[0077] Alternatively, the target data may be the calculation results obtained after the calculation module performs the corresponding calculation operation and stored in the data storage unit, in which case the statistical calculation unit acquires the corresponding calculation results from each data storage unit and performs a process of finding the maximum value or a cumulative sum for all the acquired calculation results.

[0078] The processing results obtained by the statistical calculation unit executing the process of finding the maximum value or the cumulative addition process of finding the sum may be stored in each data storage unit or may be output directly to a third-party device.

[0079] The statistical calculation unit may be any circuit that can perform a process for finding a maximum value or a cumulative addition process for finding a sum, and the specific circuit configuration of the statistical calculation unit is not limited here.

[0080] In one embodiment, the stream processor further comprises a table storage unit configured to store the function relationship table.

[0081] A table storage unit is connected to each of the third type arithmetic units, and the third type arithmetic units are configured to perform lookup table operations on the function relationship table in the table storage unit in response to operation instructions sent by the master control unit.

[0082] Optionally, the function relationship table may be coordinate values ​​of a plurality of points within a predetermined range of independent variables of any one complex function (each coordinate value includes an independent variable and a dependent variable corresponding to the independent variable). When the third type of calculation unit performs the lookup table operation, the third type of calculation unit obtains a target independent variable or a target dependent variable, and searches the dependent variable corresponding to the target independent variable or the independent variable corresponding to the target dependent variable from the function relationship table.

[0083] Optionally, the table storage unit includes software configurable tables and function relationship tables pre-installed in the table storage unit.

[0084] By setting up a software configurable table, the corresponding function relationship table can be loaded into the software configurable table based on actual needs, and the lookup table operation can be realized by the configured software configurable table.

[0085] Since some functions are applicable to multiple computing tasks, the corresponding function relationship tables are pre-loaded into the table storage unit to improve computing efficiency. By providing the pre-loaded function relationship tables in the table storage unit, the time required to load the function relationship tables can be reduced, and since the pre-loaded function relationship tables in the table storage unit do not change, the memory footprint of the tables is very small.

[0086] For example, Tanh and sigmoid are activation functions commonly found in AI networks. To reduce the time required to load the table when looking up the tanh / sigmoid lookup table, one fixed sigmoid function relationship table and one fixed tanh function relationship table are stored in the table storage unit.

[0087] If the target independent variable or the target dependent variable exists in the function relationship table, the dependent variable corresponding to the target independent variable or the independent variable corresponding to the target dependent variable can be directly obtained.

[0088] If the target independent variable does not exist in the function relationship table, the third type calculation unit obtains two independent variables that are closest to the target independent variable from the function relationship table, and determines the average value of the dependent variables corresponding to these two independent variables as the dependent variable corresponding to the target independent variable.

[0089] Similarly, if the target dependent variable does not exist in the function relationship table, the third type calculation unit obtains two dependent variables that are closest to the target dependent variable from the function relationship table, and sets the average value of the independent variables corresponding to each of the two dependent variables as the independent variable corresponding to the target dependent variable.

[0090] Optionally, only one function relationship table may be stored in the table storage unit, or multiple different function relationship tables may be stored in the table storage unit.

[0091] The table storage unit may be any device having storage capabilities, for example, any type of storage medium, and the specific configuration of the table storage unit is not limited here.

[0092] Optionally, there are a plurality of table storage units, and each third type arithmetic unit is connected to one table storage unit.

[0093] The function relationship tables stored in different table storage units may be different or the same, or the function relationship tables stored in only some of the table storage units may be the same.

[0094] Optionally, when the command receiving ends of a plurality of third arithmetic units are connected to each other and to the master control unit, the function relationship tables stored in the table storage units connected to each of the plurality of third arithmetic units are the same.

[0095] In one embodiment, the stream processor further includes an instruction storage unit. The instruction storage unit is connected to the master control unit and configured to store operation instructions. The master control unit is further configured to obtain operation instructions from the instruction storage unit. By configuring the instruction storage unit to store operation instructions, there is no need to obtain operation instructions from outside, and the present invention can be implemented independently, thereby broadening the scope of application of the present invention.

[0096] Each operation command stored in the command storage unit may be an operation command corresponding to only one type of arithmetic unit. In this case, after the master control unit obtains the operation command, it directly transmits the operation command to the corresponding arithmetic unit.

[0097] Alternatively, each operation instruction stored in the instruction storage unit may be an operation instruction set corresponding to multiple types of arithmetic units, in which case the master control unit receives the operation instruction, divides the operation instruction according to the type of arithmetic unit, obtains multiple sub-operation instructions, and sends each sub-operation instruction to the corresponding arithmetic unit to synchronously control the multiple types of arithmetic units to perform operations.

[0098] In one embodiment, the stream processor can be set to two operation modes: an instruction mode and a shared mode.

[0099] When the stream processor is in the instruction mode, the master control unit is configured to control the arithmetic units to perform corresponding arithmetic operations according to the operation instructions stored in the instruction storage unit.

[0100] When a stream processor is in shared mode, it shares its arithmetic units with other processors, allowing the other processors to control the arithmetic units within the stream processor to perform arithmetic operations.

[0101] For easy understanding of the above-mentioned stream processor, description will be made with reference to Fig. 10, which is a block diagram showing the configuration of a stream processor according to an embodiment of the present application. The stream processor shown in Fig. 10 is merely one of several embodiments of the stream processor according to the embodiment of the present application, and is not intended to limit the present application.

[0102] The stream processor includes a master control unit, a statistical calculation unit, a table storage unit, an instruction storage unit, n first type calculation units, n second type calculation units, n third type calculation units, n fourth type calculation units, and n data storage units, where n is a positive integer.

[0103] The master control unit is connected to each of the arithmetic units, the statistical arithmetic unit and the command storage unit, and the command receiving ends of the same type of arithmetic units are connected to each other, and the same type of arithmetic units are connected to different data storage units.

[0104] Each of the n third-type arithmetic units is connected to the table storage unit, and the statistical arithmetic unit is further connected to each data storage unit.

[0105] The specific implementation methods and principles of the master control unit, statistical calculation unit, table storage unit, instruction storage unit, first type calculation unit, second type calculation unit, third type calculation unit, fourth type calculation unit and data storage unit have been made clear in the above explanation, and for the sake of brevity, redundant explanations will be omitted here.

[0106] In order to easily understand the specific operation process of the above stream processor, the following description will be given by taking the stream processor to perform a softmax calculation task as an example.

[0107] First, the master control unit controls the statistical calculation unit to calculate the maximum value of the received data, and stores the calculated target maximum value (hereinafter referred to as max) in each data storage unit.

[0108] Then, for each second-type arithmetic unit, the master control unit controls the second-type arithmetic unit to: i The calculation result (hereinafter referred to as A1) is stored in a data storage unit connected to the second type calculation unit. i is input data or data stored in advance in a data storage unit connected to the second type arithmetic unit.

[0109] The master control unit controls the third type arithmetic unit (connected to the same data storage unit) corresponding to the second type arithmetic unit to perform lookup table calculations, and retrieves the lookup table result (hereinafter referred to as B1) corresponding to A1. The table storage unit stores exp(x i -max) function relationship table is stored.

[0110] The master control unit controls the statistical calculation unit to perform cumulative summation for B1 in each data storage unit, i.e., sum(exp(x i -max)) and the obtained results (hereinafter referred to as C1) are stored in each data storage unit.

[0111] The master control unit controls the third type arithmetic unit to perform lookup table calculation to retrieve the lookup table result (hereinafter referred to as D1) corresponding to C1. The table storage unit stores 1 / sum(exp(x i -max)) function relationship table is stored.

[0112] The master control unit controls the first type of calculation unit as exp(x i -max)×(1 / sum(exp(x i -max))), i.e., B1 × D1, to obtain the output result and complete the calculation for softmax.

[0113] To easily understand the specific operation process of the above-mentioned stream processor, the following description will be given taking as an example the stream processor performing the calculation task of Instance Normalization.

[0114] First, the master control unit controls the first type of calculation unit, x ij 2 Control is performed to calculate x ij is the input data, and x ij represents the element in the i-th row and j-th column of the input data matrix, where i and j are both positive integers.

[0115] Then, the master control unit controls the statistical calculation unit to read x from each data storage unit. ij 2 and x ij and obtain all the x ij Based on sum(x ij ) and calculate all the obtained x ij 2 Based on sum(x ij 2 ) and the calculation results are stored in the data storage unit.

[0116] The master control unit controls the first type of calculation unit, x ij The average value μ i The mean value μ i is stored in the data storage unit. i =sum(x ij ) ÷ the number of elements, and the number of elements is sum(x ij ) obtained when calculating xij is the number of

[0117] Then, the master control unit controls the first type of calculation unit, μ i 2 That is, (sum(x ij ) ÷ number of elements) 2 The calculation result is stored in the data storage unit.

[0118] The master control unit controls the second type of calculation unit to calculate sum(x ij 2 )+μ i 2 The calculation result is stored in the data storage unit.

[0119] The master control unit controls the third type of calculation unit by 1 / √(σ i 2 +ε) and stores 1 / √(σ i 2 +ε) is stored in the function relationship table, and the calculation results are stored in the data storage unit. i 2 represents the variance. ε represents Epsilon, a very small positive floating point number (0.000001) that prevents the denominator of this equation from becoming 0.

[0120] The master control unit controls the second type of calculation unit, x ij -μ i The calculation result is stored in the data storage unit.

[0121] Finally, the master control unit controls the first type of arithmetic unit to calculate the final result of instance normalization. That is, the master control unit controls the first type of arithmetic unit to receive x from the data storage unit. ij -μ i and 1 / √(σ i 2 +ε), and then x ij -μi and 1 / √(σ i 2 +ε) to obtain the final result.

[0122] The above examples are for ease of understanding only and are not intended to limit the present application.

[0123] Based on the same technical idea, the present application further provides a calculation method, which is used in the above-mentioned stream processor. Hereinafter, the calculation method will be described with reference to FIG.

[0124] S100: The master control unit sends an operation command to the arithmetic unit.

[0125] S200: The arithmetic unit executes an arithmetic operation corresponding to the arithmetic unit in response to an operation instruction.

[0126] By repeatedly using the above-mentioned calculation method according to the calculation logic corresponding to the calculation task, different types of calculation units can be combined with each other to calculate different calculation tasks. The calculation logic corresponding to the calculation task is reflected by the issuing order of instructions, which may be, but is not limited to, predetermined by engineers.

[0127] The implementation principle and technical effects of the calculation method according to the embodiment of the present application are the same as those of the above-mentioned stream processor embodiment. For the sake of simplicity, for the parts not mentioned in the method embodiment, reference can be made to the corresponding contents in the above-mentioned stream processor embodiment.

[0128] Based on a similar technical idea, the present application further provides a chip, which includes the above-mentioned stream processor.

[0129] The chip may be a chip having data processing capabilities, such as a SOC (System on Chip) chip, an AI (Artificial Intelligence) chip, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or a GPGPU (General-purpose computing on graphics processing units).

[0130] The specific implementation method and principles of the stream processor have been made clear in the above explanation, and for the sake of simplicity, a redundant explanation will be omitted here.

[0131] In an alternative embodiment of the present application, one stream processor is implemented on one chip to perform different computational tasks.

[0132] In another alternative embodiment of the present application, multiple stream processors are implemented together on a single chip.

[0133] In this case, in one possible embodiment, each stream processor is independent and performs different computational tasks independently.

[0134] In another possible embodiment, an engineer or upper-level software divides a computing task into independent sub-computing tasks, and a higher-level dispatcher in the chip assigns different sub-computing tasks to stream processors for execution, or an engineer writes relevant instructions in the master control module in each stream processor based on the sub-computing tasks, thereby realizing cooperation between each stream processor and improving processing efficiency.

[0135] Based on a similar technical idea, the present application further provides an electronic device, which includes the above chip.

[0136] The electronic device may be a complete device such as a computer, mobile phone, or server, or may be an electronic device that is sold independently and installed in other devices, such as a CPU, a graphics board, or a controller.

[0137] The specific implementation method and principles of the chip have been made clear in the above description, and for the sake of brevity, a redundant description will be omitted here.

[0138] The technical features in the above embodiments can be freely combined to form new embodiments as long as there is no contradiction.

[0139] In the examples of this application, "plurality" means two or more.

[0140] "Connected" in the examples of this application means directly electrically connected or indirectly connected.

[0141] The above are only selectable examples of the present application and do not limit the present application. Those skilled in the art may find that the present application has various modifications and variations. As long as they do not deviate from the spirit and principle of the present application, any modifications, equivalent replacements, improvements, etc., fall within the scope of protection of the present application.

Claims

1. At least two types of computing units and a master control unit; each of the various arithmetic units is configured to perform one of the following operations: a multiplication operation, an addition operation, a lookup table operation, and a data transfer operation; The master control unit is connected to each of the arithmetic units and configured to send operation instructions to the arithmetic units to cause the arithmetic units to perform corresponding arithmetic operations in response to the operation instructions.

1. A stream processor comprising:

2. the number of arithmetic units of at least some types among the at least two types of arithmetic units is plural, The command receiving terminals of the same type of arithmetic units are connected to each other and to the master control unit.

2. The stream processor of claim 1.

3. the stream processor further comprises at least one data store; The plurality of arithmetic units of the same type are connected to different data storage units, respectively.

3. The stream processor of claim 2.

4. further comprising a statistical calculation unit; The statistical calculation unit is connected to the master control unit and to each of the data storage units, and is configured to execute a process of finding a maximum value or a process of finding a sum for target data in the data storage units in response to an operation command sent by the master control unit.

4. The stream processor of claim 3.

5. The number of different types of arithmetic units is the same 4. The stream processor of claim 3.

6. The at least two types of arithmetic units include a first type of arithmetic unit, a second type of arithmetic unit, a third type of arithmetic unit, and a fourth type of arithmetic unit, wherein the first type of arithmetic unit is an arithmetic unit that performs a multiplication operation, the second type of arithmetic unit is an arithmetic unit that performs an addition operation, the third type of arithmetic unit is an arithmetic unit that performs a lookup table operation, and the fourth type of arithmetic unit is an arithmetic unit that performs a shift operation.

6. The stream processor of claim 5.

7. the stream processor further comprising a table storage unit; the table storage unit is configured to store a function relationship table; The table storage unit is connected to each of the third-type arithmetic units, and the third-type arithmetic units are configured to perform lookup table operations on the function relationship table in the table storage unit in response to an operation command sent by the master control unit.

2. The stream processor of claim 1.

8. the stream processor further comprising an instruction storage unit; The instruction storage unit is connected to the master control unit and configured to store an operation instruction, and the master control unit is further configured to retrieve the operation instruction from the instruction storage unit.

2. The stream processor of claim 1.

9. A calculation method comprising: The stream processor according to any one of claims 1 to 8, wherein the calculation method is sending an operation command to the arithmetic unit by the master control unit; and executing, by the arithmetic unit, an arithmetic operation corresponding to the arithmetic unit in response to the operation instruction. A calculation method characterized by:

10. The stream processor according to any one of claims 1 to 8 is provided. A chip characterized by:

11. The chip according to claim 10 is provided. An electronic device characterized by:

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